From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2C47C47088 for ; Wed, 26 May 2021 23:50:17 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8832261157 for ; Wed, 26 May 2021 23:50:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8832261157 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 6507D82052; Thu, 27 May 2021 01:50:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 18AA182CAC; Thu, 27 May 2021 01:50:11 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 28F9A81DB3 for ; Thu, 27 May 2021 01:50:08 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D77D813A1; Wed, 26 May 2021 16:50:06 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1BA333F719; Wed, 26 May 2021 16:50:05 -0700 (PDT) Date: Thu, 27 May 2021 00:49:48 +0100 From: Andre Przywara To: Jagan Teki , Jernej =?UTF-8?B?xaBrcmFiZWM=?= , Icenowy Zheng Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: Re: [PATCH v2] sunxi: clock: H6/H616: Fix PLL clock factor encodings Message-ID: <20210527004948.0c2ef6b6@slackpad.fritz.box> In-Reply-To: <20210505125305.20564-1-andre.przywara@arm.com> References: <20210505125305.20564-1-andre.przywara@arm.com> Organization: Arm Ltd. X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean On Wed, 5 May 2021 13:53:05 +0100 Andre Przywara wrote: Hi, > Most clock factors and dividers in the H6 PLLs use a "+1 encoding", > which we were missing on two occasions. can someone please confirm that I didn't mess this up? Cheers, Andre > > This fixes the MMC clock setup on the H6, which could be slightly off due > to the wrong parent frequency: > mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000 > > Also the CPU frequency was a tad too high before. > > Signed-off-by: Andre Przywara > --- > Changelog v1 .. v2: > - Also fix PLL5 factor calculation (video, currently unused) > - Also fix PLL1 factor calculation (CPU clock) > > arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 4 ++-- > arch/arm/mach-sunxi/clock_sun50i_h6.c | 2 +- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > index 62abfc4ef6b..2e076cf594d 100644 > --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h > @@ -233,14 +233,14 @@ struct sunxi_ccm_reg { > #define CCM_PLL1_OUT_EN BIT(27) > #define CCM_PLL1_CLOCK_TIME_2 (2 << 24) > #define CCM_PLL1_CTRL_P(p) ((p) << 16) > -#define CCM_PLL1_CTRL_N(n) ((n) << 8) > +#define CCM_PLL1_CTRL_N(n) (((n) - 1) << 8) > > /* pll5 bit field */ > #define CCM_PLL5_CTRL_EN BIT(31) > #define CCM_PLL5_LOCK_EN BIT(29) > #define CCM_PLL5_LOCK BIT(28) > #define CCM_PLL5_OUT_EN BIT(27) > -#define CCM_PLL5_CTRL_N(n) ((n) << 8) > +#define CCM_PLL5_CTRL_N(n) (((n) - 1) << 8) > #define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) > #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) > > diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c > index 492fc4a3fca..a947463e0a5 100644 > --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c > +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c > @@ -94,7 +94,7 @@ unsigned int clock_get_pll6(void) > int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? 4 : 2; > > uint32_t rval = readl(&ccm->pll6_cfg); > - int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); > + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; > int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> > CCM_PLL6_CTRL_DIV1_SHIFT) + 1; > int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>