tree: https://git.kernel.org/pub/scm/virt/kvm/kvm.git master head: f7d7a93c553f6242b1732b64edc8120c7a061b78 commit: 37a3ce1ca196ed06edcef4fe20bd19a05af7d56c [128/130] KVM: x86: introduce KVM_X86_QUIRK_TSC_HOST_ACCESS config: x86_64-allyesconfig (attached as .config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 reproduce (this is a W=1 build): # https://git.kernel.org/pub/scm/virt/kvm/kvm.git/commit/?id=37a3ce1ca196ed06edcef4fe20bd19a05af7d56c git remote add kvm https://git.kernel.org/pub/scm/virt/kvm/kvm.git git fetch --no-tags kvm master git checkout 37a3ce1ca196ed06edcef4fe20bd19a05af7d56c # save the attached .config to linux build tree make W=1 ARCH=x86_64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All warnings (new ones prefixed by >>): In file included from arch/x86/kvm/x86.c:19: include/linux/kvm_host.h: In function 'kvm_vcpu_can_poll': include/linux/kvm_host.h:270:9: error: implicit declaration of function 'single_task_running' [-Werror=implicit-function-declaration] 270 | return single_task_running() && !need_resched() && ktime_before(cur, stop); | ^~~~~~~~~~~~~~~~~~~ In file included from arch/x86/kvm/x86.c:57: include/linux/sched/stat.h: At top level: include/linux/sched/stat.h:20:13: error: conflicting types for 'single_task_running' 20 | extern bool single_task_running(void); | ^~~~~~~~~~~~~~~~~~~ In file included from arch/x86/kvm/x86.c:19: include/linux/kvm_host.h:270:9: note: previous implicit declaration of 'single_task_running' was here 270 | return single_task_running() && !need_resched() && ktime_before(cur, stop); | ^~~~~~~~~~~~~~~~~~~ arch/x86/kvm/x86.c: In function 'kvm_get_msr_common': >> arch/x86/kvm/x86.c:3606:3: warning: this 'if' clause does not guard... [-Wmisleading-indentation] 3606 | if (msr_info->host_initiated && | ^~ arch/x86/kvm/x86.c:3609:4: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if' 3609 | ratio = vcpu->arch.l1_tsc_scaling_ratio; | ^~~~~ >> arch/x86/kvm/x86.c:3595:15: warning: variable 'ratio' set but not used [-Wunused-but-set-variable] 3595 | u64 offset, ratio; | ^~~~~ >> arch/x86/kvm/x86.c:3595:7: warning: variable 'offset' set but not used [-Wunused-but-set-variable] 3595 | u64 offset, ratio; | ^~~~~~ arch/x86/kvm/x86.c:3610:5: error: 'else' without a previous 'if' 3610 | } else { | ^~~~ arch/x86/kvm/x86.c:3611:4: error: 'offset' undeclared (first use in this function); did you mean 'off_t'? 3611 | offset = vcpu->arch.tsc_offset; | ^~~~~~ | off_t arch/x86/kvm/x86.c:3611:4: note: each undeclared identifier is reported only once for each function it appears in arch/x86/kvm/x86.c:3612:4: error: 'ratio' undeclared (first use in this function) 3612 | ratio = vcpu->arch.tsc_scaling_ratio; | ^~~~~ arch/x86/kvm/x86.c:3617:2: error: case label not within a switch statement 3617 | case MSR_MTRRcap: | ^~~~ arch/x86/kvm/x86.c:3618:2: error: case label not within a switch statement 3618 | case 0x200 ... 0x2ff: | ^~~~ arch/x86/kvm/x86.c:3620:2: error: case label not within a switch statement 3620 | case 0xcd: /* fsb frequency */ | ^~~~ arch/x86/kvm/x86.c:3622:3: error: break statement not within loop or switch 3622 | break; | ^~~~~ arch/x86/kvm/x86.c:3634:2: error: case label not within a switch statement 3634 | case MSR_EBC_FREQUENCY_ID: | ^~~~ arch/x86/kvm/x86.c:3636:3: error: break statement not within loop or switch 3636 | break; | ^~~~~ arch/x86/kvm/x86.c:3637:2: error: case label not within a switch statement 3637 | case MSR_IA32_APICBASE: | ^~~~ arch/x86/kvm/x86.c:3639:3: error: break statement not within loop or switch 3639 | break; | ^~~~~ arch/x86/kvm/x86.c:3640:2: error: case label not within a switch statement 3640 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: | ^~~~ arch/x86/kvm/x86.c:3642:2: error: case label not within a switch statement 3642 | case MSR_IA32_TSC_DEADLINE: | ^~~~ arch/x86/kvm/x86.c:3644:3: error: break statement not within loop or switch 3644 | break; | ^~~~~ arch/x86/kvm/x86.c:3645:2: error: case label not within a switch statement 3645 | case MSR_IA32_TSC_ADJUST: | ^~~~ arch/x86/kvm/x86.c:3649:3: error: break statement not within loop or switch 3649 | break; | ^~~~~ arch/x86/kvm/x86.c:3650:2: error: case label not within a switch statement 3650 | case MSR_IA32_MISC_ENABLE: | ^~~~ arch/x86/kvm/x86.c:3652:3: error: break statement not within loop or switch 3652 | break; | ^~~~~ arch/x86/kvm/x86.c:3653:2: error: case label not within a switch statement 3653 | case MSR_IA32_SMBASE: | ^~~~ arch/x86/kvm/x86.c:3657:3: error: break statement not within loop or switch 3657 | break; | ^~~~~ arch/x86/kvm/x86.c:3658:2: error: case label not within a switch statement 3658 | case MSR_SMI_COUNT: | ^~~~ arch/x86/kvm/x86.c:3660:3: error: break statement not within loop or switch 3660 | break; | ^~~~~ arch/x86/kvm/x86.c:3661:2: error: case label not within a switch statement 3661 | case MSR_IA32_PERF_STATUS: | ^~~~ arch/x86/kvm/x86.c:3666:3: error: break statement not within loop or switch 3666 | break; | ^~~~~ arch/x86/kvm/x86.c:3667:2: error: case label not within a switch statement 3667 | case MSR_EFER: | ^~~~ arch/x86/kvm/x86.c:3669:3: error: break statement not within loop or switch 3669 | break; | ^~~~~ arch/x86/kvm/x86.c:3670:2: error: case label not within a switch statement 3670 | case MSR_KVM_WALL_CLOCK: | ^~~~ arch/x86/kvm/x86.c:3675:3: error: break statement not within loop or switch 3675 | break; | ^~~~~ arch/x86/kvm/x86.c:3676:2: error: case label not within a switch statement 3676 | case MSR_KVM_WALL_CLOCK_NEW: | ^~~~ arch/x86/kvm/x86.c:3681:3: error: break statement not within loop or switch 3681 | break; | ^~~~~ arch/x86/kvm/x86.c:3682:2: error: case label not within a switch statement 3682 | case MSR_KVM_SYSTEM_TIME: | ^~~~ arch/x86/kvm/x86.c:3687:3: error: break statement not within loop or switch 3687 | break; | ^~~~~ vim +/if +3606 arch/x86/kvm/x86.c 3527 3528 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 3529 { 3530 switch (msr_info->index) { 3531 case MSR_IA32_PLATFORM_ID: 3532 case MSR_IA32_EBL_CR_POWERON: 3533 case MSR_IA32_LASTBRANCHFROMIP: 3534 case MSR_IA32_LASTBRANCHTOIP: 3535 case MSR_IA32_LASTINTFROMIP: 3536 case MSR_IA32_LASTINTTOIP: 3537 case MSR_K8_SYSCFG: 3538 case MSR_K8_TSEG_ADDR: 3539 case MSR_K8_TSEG_MASK: 3540 case MSR_VM_HSAVE_PA: 3541 case MSR_K8_INT_PENDING_MSG: 3542 case MSR_AMD64_NB_CFG: 3543 case MSR_FAM10H_MMIO_CONF_BASE: 3544 case MSR_AMD64_BU_CFG2: 3545 case MSR_IA32_PERF_CTL: 3546 case MSR_AMD64_DC_CFG: 3547 case MSR_F15H_EX_CFG: 3548 /* 3549 * Intel Sandy Bridge CPUs must support the RAPL (running average power 3550 * limit) MSRs. Just return 0, as we do not want to expose the host 3551 * data here. Do not conditionalize this on CPUID, as KVM does not do 3552 * so for existing CPU-specific MSRs. 3553 */ 3554 case MSR_RAPL_POWER_UNIT: 3555 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ 3556 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ 3557 case MSR_PKG_ENERGY_STATUS: /* Total package */ 3558 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ 3559 msr_info->data = 0; 3560 break; 3561 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: 3562 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3563 return kvm_pmu_get_msr(vcpu, msr_info); 3564 if (!msr_info->host_initiated) 3565 return 1; 3566 msr_info->data = 0; 3567 break; 3568 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: 3569 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: 3570 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: 3571 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: 3572 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3573 return kvm_pmu_get_msr(vcpu, msr_info); 3574 msr_info->data = 0; 3575 break; 3576 case MSR_IA32_UCODE_REV: 3577 msr_info->data = vcpu->arch.microcode_version; 3578 break; 3579 case MSR_IA32_ARCH_CAPABILITIES: 3580 if (!msr_info->host_initiated && 3581 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) 3582 return 1; 3583 msr_info->data = vcpu->arch.arch_capabilities; 3584 break; 3585 case MSR_IA32_PERF_CAPABILITIES: 3586 if (!msr_info->host_initiated && 3587 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) 3588 return 1; 3589 msr_info->data = vcpu->arch.perf_capabilities; 3590 break; 3591 case MSR_IA32_POWER_CTL: 3592 msr_info->data = vcpu->arch.msr_ia32_power_ctl; 3593 break; 3594 case MSR_IA32_TSC: { > 3595 u64 offset, ratio; 3596 3597 /* 3598 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset 3599 * even when not intercepted. AMD manual doesn't explicitly 3600 * state this but appears to behave the same. 3601 * 3602 * On userspace reads and writes, when KVM_X86_QUIRK_TSC_HOST_ACCESS 3603 * is present, however, we unconditionally return L1's TSC value 3604 * to ensure backwards-compatible behavior for migration. 3605 */ > 3606 if (msr_info->host_initiated && 3607 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_TSC_HOST_ACCESS)) 3608 offset = vcpu->arch.l1_tsc_offset; 3609 ratio = vcpu->arch.l1_tsc_scaling_ratio; 3610 } else { 3611 offset = vcpu->arch.tsc_offset; 3612 ratio = vcpu->arch.tsc_scaling_ratio; 3613 } 3614 msr_info->data = kvm_scale_tsc(vcpu, rdtsc(), ratio) + offset; 3615 break; 3616 } 3617 case MSR_MTRRcap: 3618 case 0x200 ... 0x2ff: 3619 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); 3620 case 0xcd: /* fsb frequency */ 3621 msr_info->data = 3; 3622 break; 3623 /* 3624 * MSR_EBC_FREQUENCY_ID 3625 * Conservative value valid for even the basic CPU models. 3626 * Models 0,1: 000 in bits 23:21 indicating a bus speed of 3627 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, 3628 * and 266MHz for model 3, or 4. Set Core Clock 3629 * Frequency to System Bus Frequency Ratio to 1 (bits 3630 * 31:24) even though these are only valid for CPU 3631 * models > 2, however guests may end up dividing or 3632 * multiplying by zero otherwise. 3633 */ 3634 case MSR_EBC_FREQUENCY_ID: 3635 msr_info->data = 1 << 24; 3636 break; 3637 case MSR_IA32_APICBASE: 3638 msr_info->data = kvm_get_apic_base(vcpu); 3639 break; 3640 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: 3641 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); 3642 case MSR_IA32_TSC_DEADLINE: 3643 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); 3644 break; 3645 case MSR_IA32_TSC_ADJUST: 3646 if (!guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST) && 3647 !msr_info->host_initiated) 3648 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; 3649 break; 3650 case MSR_IA32_MISC_ENABLE: 3651 msr_info->data = vcpu->arch.ia32_misc_enable_msr; 3652 break; 3653 case MSR_IA32_SMBASE: 3654 if (!msr_info->host_initiated) 3655 return 1; 3656 msr_info->data = vcpu->arch.smbase; 3657 break; 3658 case MSR_SMI_COUNT: 3659 msr_info->data = vcpu->arch.smi_count; 3660 break; 3661 case MSR_IA32_PERF_STATUS: 3662 /* TSC increment by tick */ 3663 msr_info->data = 1000ULL; 3664 /* CPU multiplier */ 3665 msr_info->data |= (((uint64_t)4ULL) << 40); 3666 break; 3667 case MSR_EFER: 3668 msr_info->data = vcpu->arch.efer; 3669 break; 3670 case MSR_KVM_WALL_CLOCK: 3671 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3672 return 1; 3673 3674 msr_info->data = vcpu->kvm->arch.wall_clock; 3675 break; 3676 case MSR_KVM_WALL_CLOCK_NEW: 3677 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3678 return 1; 3679 3680 msr_info->data = vcpu->kvm->arch.wall_clock; 3681 break; 3682 case MSR_KVM_SYSTEM_TIME: 3683 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) 3684 return 1; 3685 3686 msr_info->data = vcpu->arch.time; 3687 break; 3688 case MSR_KVM_SYSTEM_TIME_NEW: 3689 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) 3690 return 1; 3691 3692 msr_info->data = vcpu->arch.time; 3693 break; 3694 case MSR_KVM_ASYNC_PF_EN: 3695 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3696 return 1; 3697 3698 msr_info->data = vcpu->arch.apf.msr_en_val; 3699 break; 3700 case MSR_KVM_ASYNC_PF_INT: 3701 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) 3702 return 1; 3703 3704 msr_info->data = vcpu->arch.apf.msr_int_val; 3705 break; 3706 case MSR_KVM_ASYNC_PF_ACK: 3707 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) 3708 return 1; 3709 3710 msr_info->data = 0; 3711 break; 3712 case MSR_KVM_STEAL_TIME: 3713 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) 3714 return 1; 3715 3716 msr_info->data = vcpu->arch.st.msr_val; 3717 break; 3718 case MSR_KVM_PV_EOI_EN: 3719 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) 3720 return 1; 3721 3722 msr_info->data = vcpu->arch.pv_eoi.msr_val; 3723 break; 3724 case MSR_KVM_POLL_CONTROL: 3725 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) 3726 return 1; 3727 3728 msr_info->data = vcpu->arch.msr_kvm_poll_control; 3729 break; 3730 case MSR_IA32_P5_MC_ADDR: 3731 case MSR_IA32_P5_MC_TYPE: 3732 case MSR_IA32_MCG_CAP: 3733 case MSR_IA32_MCG_CTL: 3734 case MSR_IA32_MCG_STATUS: 3735 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: 3736 return get_msr_mce(vcpu, msr_info->index, &msr_info->data, 3737 msr_info->host_initiated); 3738 case MSR_IA32_XSS: 3739 if (!msr_info->host_initiated && 3740 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) 3741 return 1; 3742 msr_info->data = vcpu->arch.ia32_xss; 3743 break; 3744 case MSR_K7_CLK_CTL: 3745 /* 3746 * Provide expected ramp-up count for K7. All other 3747 * are set to zero, indicating minimum divisors for 3748 * every field. 3749 * 3750 * This prevents guest kernels on AMD host with CPU 3751 * type 6, model 8 and higher from exploding due to 3752 * the rdmsr failing. 3753 */ 3754 msr_info->data = 0x20000000; 3755 break; 3756 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: 3757 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: 3758 case HV_X64_MSR_SYNDBG_OPTIONS: 3759 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: 3760 case HV_X64_MSR_CRASH_CTL: 3761 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: 3762 case HV_X64_MSR_REENLIGHTENMENT_CONTROL: 3763 case HV_X64_MSR_TSC_EMULATION_CONTROL: 3764 case HV_X64_MSR_TSC_EMULATION_STATUS: 3765 return kvm_hv_get_msr_common(vcpu, 3766 msr_info->index, &msr_info->data, 3767 msr_info->host_initiated); 3768 case MSR_IA32_BBL_CR_CTL3: 3769 /* This legacy MSR exists but isn't fully documented in current 3770 * silicon. It is however accessed by winxp in very narrow 3771 * scenarios where it sets bit #19, itself documented as 3772 * a "reserved" bit. Best effort attempt to source coherent 3773 * read data here should the balance of the register be 3774 * interpreted by the guest: 3775 * 3776 * L2 cache control register 3: 64GB range, 256KB size, 3777 * enabled, latency 0x1, configured 3778 */ 3779 msr_info->data = 0xbe702111; 3780 break; 3781 case MSR_AMD64_OSVW_ID_LENGTH: 3782 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3783 return 1; 3784 msr_info->data = vcpu->arch.osvw.length; 3785 break; 3786 case MSR_AMD64_OSVW_STATUS: 3787 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) 3788 return 1; 3789 msr_info->data = vcpu->arch.osvw.status; 3790 break; 3791 case MSR_PLATFORM_INFO: 3792 if (!msr_info->host_initiated && 3793 !vcpu->kvm->arch.guest_can_read_msr_platform_info) 3794 return 1; 3795 msr_info->data = vcpu->arch.msr_platform_info; 3796 break; 3797 case MSR_MISC_FEATURES_ENABLES: 3798 msr_info->data = vcpu->arch.msr_misc_features_enables; 3799 break; 3800 case MSR_K7_HWCR: 3801 msr_info->data = vcpu->arch.msr_hwcr; 3802 break; 3803 default: 3804 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) 3805 return kvm_pmu_get_msr(vcpu, msr_info); 3806 return KVM_MSR_RET_INVALID; 3807 } 3808 return 0; 3809 } 3810 EXPORT_SYMBOL_GPL(kvm_get_msr_common); 3811 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org