* [Intel-gfx] [PATCH 0/9] Enhance pipe color support for multi segmented luts
@ 2021-06-01 10:41 ` Uma Shankar
0 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
Modern hardwares have multi segmented lut approach to prioritize
the darker regions of the spectrum. This series introduces a new
UAPI to define the lut ranges supported by the respective hardware.
This also enables Pipe Color Management Support for Intel's XE_LPD hw.
Enable Support for Pipe Degamma with the increased lut samples
supported by hardware. This also adds support for newly introduced
Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
The Logarithmic gamma implementation on XE_LPD is non linear and adds 25
segments with non linear lut samples in each segment. The expectation
is userspace will create the luts as per this distribution and pass
the final samples to driver to be programmed in hardware.
+-----+------------------------------+
| x | 2 pow x segment|No of Entries
| | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 2 | 2 |
| 2 | 4 | 2 |
| 3 | 8 | 2 |
| 4 | 16 | 2 |
| 5 | 32 | 4 |
| 6 | 64 | 4 |
| 7 | 128 | 4 |
| 8 | 256 | 8 |
| 9 | 512 | 8 |
| 10 | 1024 | 8 |
| 11 | 2048 | 16 |
| 12 | 4096 | 16 |
| 13 | 8192 | 16 |
| 14 | 16384 | 32 |
| 15 | 32768 | 32 |
| 16 | 65536 | 64 |
| 17 | 131072 | 64 |
| 18 | 262144 | 64 |
| 19 | 524288 | 32 |
| 20 | 1048576 | 32 |
| 21 | 2097152 | 32 |
| 22 | 4194304 | 32 |
| 23 | 8388608 | 32 |
| 24 | 16777216 | 1 |
| | Total Entries | 511 |
-----+-----------------+------------+
Credits: Special mention and credits to Ville Syrjala for coming up
with a design for this feature and inputs. This series is based on
his original design.
Note: Userspace support for this new UAPI will be done on Chrome and
plan is to get this supported on mutter as well. We will notify the
list once we have that ready for review.
Uma Shankar (9):
drm: Add gamma mode property
drm/i915/xelpd: Define color lut range structure
drm/i915/xelpd: Add support for Logarithmic gamma mode
drm/i915/xelpd: Attach gamma mode property
drm: Add Client Cap for advance gamma mode
drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode
drm/i915/xelpd: Enable Pipe Degamma
drm/i915/xelpd: Add Pipe Color Lut caps to platform config
drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
drivers/gpu/drm/drm_atomic_uapi.c | 8 +
drivers/gpu/drm/drm_color_mgmt.c | 75 ++++
drivers/gpu/drm/drm_ioctl.c | 5 +
drivers/gpu/drm/i915/display/intel_color.c | 454 ++++++++++++++++++++-
drivers/gpu/drm/i915/i915_pci.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 7 +
include/drm/drm_atomic.h | 1 +
include/drm/drm_color_mgmt.h | 8 +
include/drm/drm_crtc.h | 25 ++
include/drm/drm_file.h | 8 +
include/uapi/drm/drm.h | 8 +
include/uapi/drm/drm_mode.h | 43 ++
12 files changed, 630 insertions(+), 15 deletions(-)
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 1/9] drm: Add gamma mode property
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
@ 2021-06-01 10:41 ` Uma Shankar
-1 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Uma Shankar, bhanuprakash.modem
Add a gamma mode property to enable various kind of
gamma modes supported by platforms like: Interpolated, Split,
Multi Segmented, Logarithmic etc. Userspace can get this property
and should be able to get the platform capabilities wrt various
gamma modes possible and the possible ranges.
It can select one of the modes exposed as blob_id as an
enum and set the respective mode.
It can then create the LUT and send it to driver using
already available GAMMA_LUT property as blob.
Note: This is based on design by Ville and is being carried forward
based on his original idea.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/drm_atomic_uapi.c | 5 +++
drivers/gpu/drm/drm_color_mgmt.c | 75 +++++++++++++++++++++++++++++++
include/drm/drm_color_mgmt.h | 8 ++++
include/drm/drm_crtc.h | 14 ++++++
include/uapi/drm/drm_mode.h | 43 ++++++++++++++++++
5 files changed, 145 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
index 438e9585b225..a5470a0ebbe6 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -471,6 +471,9 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
&replaced);
state->color_mgmt_changed |= replaced;
return ret;
+ } else if (property == crtc->gamma_mode_property) {
+ state->gamma_mode = val;
+ state->color_mgmt_changed |= true;
} else if (property == config->prop_out_fence_ptr) {
s32 __user *fence_ptr = u64_to_user_ptr(val);
@@ -510,6 +513,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
*val = (state->mode_blob) ? state->mode_blob->base.id : 0;
else if (property == config->prop_vrr_enabled)
*val = state->vrr_enabled;
+ else if (property == crtc->gamma_mode_property)
+ *val = state->gamma_mode;
else if (property == config->degamma_lut_property)
*val = (state->degamma_lut) ? state->degamma_lut->base.id : 0;
else if (property == config->ctm_property)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index bb14f488c8f6..766d0fd14daa 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -187,6 +187,81 @@ void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
}
EXPORT_SYMBOL(drm_crtc_enable_color_mgmt);
+void drm_crtc_attach_gamma_mode_property(struct drm_crtc *crtc)
+{
+ if (!crtc->gamma_mode_property)
+ return;
+
+ drm_object_attach_property(&crtc->base,
+ crtc->gamma_mode_property, 0);
+}
+EXPORT_SYMBOL(drm_crtc_attach_gamma_mode_property);
+
+int drm_color_create_gamma_mode_property(struct drm_crtc *crtc,
+ int num_values)
+{
+ struct drm_property *prop;
+
+ prop = drm_property_create(crtc->dev,
+ DRM_MODE_PROP_ENUM,
+ "GAMMA_MODE", num_values);
+ if (!prop)
+ return -ENOMEM;
+
+ crtc->gamma_mode_property = prop;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_color_create_gamma_mode_property);
+
+int drm_color_add_gamma_mode_range(struct drm_crtc *crtc,
+ const char *name,
+ const struct drm_color_lut_range *ranges,
+ size_t length)
+{
+ struct drm_property_blob *blob;
+ struct drm_property *prop;
+ int num_ranges = length / sizeof(ranges[0]);
+ int i, ret, num_types_0;
+
+ prop = crtc->gamma_mode_property;
+ if (!prop)
+ return -EINVAL;
+
+ if (length == 0 && name)
+ return drm_property_add_enum(prop, 0, name);
+
+ if (WARN_ON(length == 0 || length % sizeof(ranges[0]) != 0))
+ return -EINVAL;
+
+ num_types_0 = hweight8(ranges[0].flags & (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_DEGAMMA));
+ if (num_types_0 == 0)
+ return -EINVAL;
+
+ for (i = 1; i < num_ranges; i++) {
+ int num_types = hweight8(ranges[i].flags & (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_DEGAMMA));
+
+ /* either all ranges have DEGAMMA|GAMMA or none have it */
+ if (num_types_0 != num_types)
+ return -EINVAL;
+ }
+
+ blob = drm_property_create_blob(crtc->dev, length, ranges);
+ if (IS_ERR(blob))
+ return PTR_ERR(blob);
+
+ ret = drm_property_add_enum(prop, blob->base.id, name);
+ if (ret) {
+ drm_property_blob_put(blob);
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_color_add_gamma_mode_range);
+
/**
* drm_mode_crtc_set_gamma_size - set the gamma table size
* @crtc: CRTC to set the gamma table size for
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index 81c298488b0c..db68f42f6d12 100644
--- a/include/drm/drm_color_mgmt.h
+++ b/include/drm/drm_color_mgmt.h
@@ -74,6 +74,14 @@ static inline int drm_color_lut_size(const struct drm_property_blob *blob)
return blob->length / sizeof(struct drm_color_lut);
}
+int drm_color_create_gamma_mode_property(struct drm_crtc *crtc,
+ int num_values);
+void drm_crtc_attach_gamma_mode_property(struct drm_crtc *crtc);
+int drm_color_add_gamma_mode_range(struct drm_crtc *crtc,
+ const char *name,
+ const struct drm_color_lut_range *ranges,
+ size_t length);
+
enum drm_color_encoding {
DRM_COLOR_YCBCR_BT601,
DRM_COLOR_YCBCR_BT709,
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 13eeba2a750a..b1eead03ebe8 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -262,6 +262,13 @@ struct drm_crtc_state {
*/
struct drm_property_blob *mode_blob;
+ /**
+ * @gamma_mode: This is a blob_id and exposes the platform capabilities
+ * wrt to various gamma modes and the respective lut ranges. This also
+ * helps user select a gamma mode amongst the supported ones.
+ */
+ u32 gamma_mode;
+
/**
* @degamma_lut:
*
@@ -1096,6 +1103,13 @@ struct drm_crtc {
*/
struct drm_property *scaling_filter_property;
+ /**
+ * @gamma_mode_property: Optional CRTC property to enumerate and
+ * select the mode of the crtc gamma/degmama LUTs. This also exposes
+ * the lut ranges of the various supported gamma modes to userspace.
+ */
+ struct drm_property *gamma_mode_property;
+
/**
* @state:
*
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 9b6722d45f36..d7758d351936 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -819,6 +819,49 @@ struct hdr_output_metadata {
};
};
+/*
+ * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and means the LUT
+ * can be used for either purpose, but not simultaneously. To expose
+ * modes that support gamma and degamma simultaneously the gamma mode
+ * must declare distinct DRM_MODE_LUT_GAMMA and DRM_MODE_LUT_DEGAMMA
+ * ranges.
+ */
+/* LUT is for gamma (after CTM) */
+#define DRM_MODE_LUT_GAMMA BIT(0)
+/* LUT is for degamma (before CTM) */
+#define DRM_MODE_LUT_DEGAMMA BIT(1)
+/* linearly interpolate between the points */
+#define DRM_MODE_LUT_INTERPOLATE BIT(2)
+/*
+ * the last value of the previous range is the
+ * first value of the current range.
+ */
+#define DRM_MODE_LUT_REUSE_LAST BIT(3)
+/* the curve must be non-decreasing */
+#define DRM_MODE_LUT_NON_DECREASING BIT(4)
+/* the curve is reflected across origin for negative inputs */
+#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5)
+/* the same curve (red) is used for blue and green channels as well */
+#define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6)
+
+struct drm_color_lut_range {
+ /* DRM_MODE_LUT_* */
+ __u32 flags;
+ /* number of points on the curve */
+ __u16 count;
+ /* input/output bits per component */
+ __u8 input_bpc, output_bpc;
+ /* input start/end values */
+ __s32 start, end;
+ /* output min/max values */
+ __s32 min, max;
+};
+
+enum lut_type {
+ LUT_TYPE_DEGAMMA = 0,
+ LUT_TYPE_GAMMA = 1,
+};
+
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
--
2.26.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH 1/9] drm: Add gamma mode property
@ 2021-06-01 10:41 ` Uma Shankar
0 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
Add a gamma mode property to enable various kind of
gamma modes supported by platforms like: Interpolated, Split,
Multi Segmented, Logarithmic etc. Userspace can get this property
and should be able to get the platform capabilities wrt various
gamma modes possible and the possible ranges.
It can select one of the modes exposed as blob_id as an
enum and set the respective mode.
It can then create the LUT and send it to driver using
already available GAMMA_LUT property as blob.
Note: This is based on design by Ville and is being carried forward
based on his original idea.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/drm_atomic_uapi.c | 5 +++
drivers/gpu/drm/drm_color_mgmt.c | 75 +++++++++++++++++++++++++++++++
include/drm/drm_color_mgmt.h | 8 ++++
include/drm/drm_crtc.h | 14 ++++++
include/uapi/drm/drm_mode.h | 43 ++++++++++++++++++
5 files changed, 145 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
index 438e9585b225..a5470a0ebbe6 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -471,6 +471,9 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
&replaced);
state->color_mgmt_changed |= replaced;
return ret;
+ } else if (property == crtc->gamma_mode_property) {
+ state->gamma_mode = val;
+ state->color_mgmt_changed |= true;
} else if (property == config->prop_out_fence_ptr) {
s32 __user *fence_ptr = u64_to_user_ptr(val);
@@ -510,6 +513,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc,
*val = (state->mode_blob) ? state->mode_blob->base.id : 0;
else if (property == config->prop_vrr_enabled)
*val = state->vrr_enabled;
+ else if (property == crtc->gamma_mode_property)
+ *val = state->gamma_mode;
else if (property == config->degamma_lut_property)
*val = (state->degamma_lut) ? state->degamma_lut->base.id : 0;
else if (property == config->ctm_property)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c
index bb14f488c8f6..766d0fd14daa 100644
--- a/drivers/gpu/drm/drm_color_mgmt.c
+++ b/drivers/gpu/drm/drm_color_mgmt.c
@@ -187,6 +187,81 @@ void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,
}
EXPORT_SYMBOL(drm_crtc_enable_color_mgmt);
+void drm_crtc_attach_gamma_mode_property(struct drm_crtc *crtc)
+{
+ if (!crtc->gamma_mode_property)
+ return;
+
+ drm_object_attach_property(&crtc->base,
+ crtc->gamma_mode_property, 0);
+}
+EXPORT_SYMBOL(drm_crtc_attach_gamma_mode_property);
+
+int drm_color_create_gamma_mode_property(struct drm_crtc *crtc,
+ int num_values)
+{
+ struct drm_property *prop;
+
+ prop = drm_property_create(crtc->dev,
+ DRM_MODE_PROP_ENUM,
+ "GAMMA_MODE", num_values);
+ if (!prop)
+ return -ENOMEM;
+
+ crtc->gamma_mode_property = prop;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_color_create_gamma_mode_property);
+
+int drm_color_add_gamma_mode_range(struct drm_crtc *crtc,
+ const char *name,
+ const struct drm_color_lut_range *ranges,
+ size_t length)
+{
+ struct drm_property_blob *blob;
+ struct drm_property *prop;
+ int num_ranges = length / sizeof(ranges[0]);
+ int i, ret, num_types_0;
+
+ prop = crtc->gamma_mode_property;
+ if (!prop)
+ return -EINVAL;
+
+ if (length == 0 && name)
+ return drm_property_add_enum(prop, 0, name);
+
+ if (WARN_ON(length == 0 || length % sizeof(ranges[0]) != 0))
+ return -EINVAL;
+
+ num_types_0 = hweight8(ranges[0].flags & (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_DEGAMMA));
+ if (num_types_0 == 0)
+ return -EINVAL;
+
+ for (i = 1; i < num_ranges; i++) {
+ int num_types = hweight8(ranges[i].flags & (DRM_MODE_LUT_GAMMA |
+ DRM_MODE_LUT_DEGAMMA));
+
+ /* either all ranges have DEGAMMA|GAMMA or none have it */
+ if (num_types_0 != num_types)
+ return -EINVAL;
+ }
+
+ blob = drm_property_create_blob(crtc->dev, length, ranges);
+ if (IS_ERR(blob))
+ return PTR_ERR(blob);
+
+ ret = drm_property_add_enum(prop, blob->base.id, name);
+ if (ret) {
+ drm_property_blob_put(blob);
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_color_add_gamma_mode_range);
+
/**
* drm_mode_crtc_set_gamma_size - set the gamma table size
* @crtc: CRTC to set the gamma table size for
diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h
index 81c298488b0c..db68f42f6d12 100644
--- a/include/drm/drm_color_mgmt.h
+++ b/include/drm/drm_color_mgmt.h
@@ -74,6 +74,14 @@ static inline int drm_color_lut_size(const struct drm_property_blob *blob)
return blob->length / sizeof(struct drm_color_lut);
}
+int drm_color_create_gamma_mode_property(struct drm_crtc *crtc,
+ int num_values);
+void drm_crtc_attach_gamma_mode_property(struct drm_crtc *crtc);
+int drm_color_add_gamma_mode_range(struct drm_crtc *crtc,
+ const char *name,
+ const struct drm_color_lut_range *ranges,
+ size_t length);
+
enum drm_color_encoding {
DRM_COLOR_YCBCR_BT601,
DRM_COLOR_YCBCR_BT709,
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 13eeba2a750a..b1eead03ebe8 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -262,6 +262,13 @@ struct drm_crtc_state {
*/
struct drm_property_blob *mode_blob;
+ /**
+ * @gamma_mode: This is a blob_id and exposes the platform capabilities
+ * wrt to various gamma modes and the respective lut ranges. This also
+ * helps user select a gamma mode amongst the supported ones.
+ */
+ u32 gamma_mode;
+
/**
* @degamma_lut:
*
@@ -1096,6 +1103,13 @@ struct drm_crtc {
*/
struct drm_property *scaling_filter_property;
+ /**
+ * @gamma_mode_property: Optional CRTC property to enumerate and
+ * select the mode of the crtc gamma/degmama LUTs. This also exposes
+ * the lut ranges of the various supported gamma modes to userspace.
+ */
+ struct drm_property *gamma_mode_property;
+
/**
* @state:
*
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 9b6722d45f36..d7758d351936 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -819,6 +819,49 @@ struct hdr_output_metadata {
};
};
+/*
+ * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and means the LUT
+ * can be used for either purpose, but not simultaneously. To expose
+ * modes that support gamma and degamma simultaneously the gamma mode
+ * must declare distinct DRM_MODE_LUT_GAMMA and DRM_MODE_LUT_DEGAMMA
+ * ranges.
+ */
+/* LUT is for gamma (after CTM) */
+#define DRM_MODE_LUT_GAMMA BIT(0)
+/* LUT is for degamma (before CTM) */
+#define DRM_MODE_LUT_DEGAMMA BIT(1)
+/* linearly interpolate between the points */
+#define DRM_MODE_LUT_INTERPOLATE BIT(2)
+/*
+ * the last value of the previous range is the
+ * first value of the current range.
+ */
+#define DRM_MODE_LUT_REUSE_LAST BIT(3)
+/* the curve must be non-decreasing */
+#define DRM_MODE_LUT_NON_DECREASING BIT(4)
+/* the curve is reflected across origin for negative inputs */
+#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5)
+/* the same curve (red) is used for blue and green channels as well */
+#define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6)
+
+struct drm_color_lut_range {
+ /* DRM_MODE_LUT_* */
+ __u32 flags;
+ /* number of points on the curve */
+ __u16 count;
+ /* input/output bits per component */
+ __u8 input_bpc, output_bpc;
+ /* input start/end values */
+ __s32 start, end;
+ /* output min/max values */
+ __s32 min, max;
+};
+
+enum lut_type {
+ LUT_TYPE_DEGAMMA = 0,
+ LUT_TYPE_GAMMA = 1,
+};
+
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 1/9] drm: Add gamma mode property
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
@ 2021-06-02 9:09 ` Pekka Paalanen
-1 siblings, 0 replies; 48+ messages in thread
From: Pekka Paalanen @ 2021-06-02 9:09 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, dri-devel, bhanuprakash.modem
[-- Attachment #1: Type: text/plain, Size: 4392 bytes --]
On Tue, 1 Jun 2021 16:11:27 +0530
Uma Shankar <uma.shankar@intel.com> wrote:
> Add a gamma mode property to enable various kind of
> gamma modes supported by platforms like: Interpolated, Split,
> Multi Segmented, Logarithmic etc. Userspace can get this property
> and should be able to get the platform capabilities wrt various
> gamma modes possible and the possible ranges.
>
> It can select one of the modes exposed as blob_id as an
> enum and set the respective mode.
>
> It can then create the LUT and send it to driver using
> already available GAMMA_LUT property as blob.
>
> Note: This is based on design by Ville and is being carried forward
> based on his original idea.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/drm_atomic_uapi.c | 5 +++
> drivers/gpu/drm/drm_color_mgmt.c | 75 +++++++++++++++++++++++++++++++
> include/drm/drm_color_mgmt.h | 8 ++++
> include/drm/drm_crtc.h | 14 ++++++
> include/uapi/drm/drm_mode.h | 43 ++++++++++++++++++
> 5 files changed, 145 insertions(+)
>
...
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index 13eeba2a750a..b1eead03ebe8 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -262,6 +262,13 @@ struct drm_crtc_state {
> */
> struct drm_property_blob *mode_blob;
>
> + /**
> + * @gamma_mode: This is a blob_id and exposes the platform capabilities
> + * wrt to various gamma modes and the respective lut ranges. This also
> + * helps user select a gamma mode amongst the supported ones.
> + */
> + u32 gamma_mode;
> +
> /**
> * @degamma_lut:
> *
> @@ -1096,6 +1103,13 @@ struct drm_crtc {
> */
> struct drm_property *scaling_filter_property;
>
> + /**
> + * @gamma_mode_property: Optional CRTC property to enumerate and
> + * select the mode of the crtc gamma/degmama LUTs. This also exposes
> + * the lut ranges of the various supported gamma modes to userspace.
> + */
> + struct drm_property *gamma_mode_property;
> +
> /**
> * @state:
> *
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index 9b6722d45f36..d7758d351936 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -819,6 +819,49 @@ struct hdr_output_metadata {
> };
> };
>
> +/*
> + * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and means the LUT
> + * can be used for either purpose, but not simultaneously. To expose
> + * modes that support gamma and degamma simultaneously the gamma mode
> + * must declare distinct DRM_MODE_LUT_GAMMA and DRM_MODE_LUT_DEGAMMA
> + * ranges.
> + */
> +/* LUT is for gamma (after CTM) */
> +#define DRM_MODE_LUT_GAMMA BIT(0)
> +/* LUT is for degamma (before CTM) */
> +#define DRM_MODE_LUT_DEGAMMA BIT(1)
> +/* linearly interpolate between the points */
> +#define DRM_MODE_LUT_INTERPOLATE BIT(2)
> +/*
> + * the last value of the previous range is the
> + * first value of the current range.
> + */
> +#define DRM_MODE_LUT_REUSE_LAST BIT(3)
> +/* the curve must be non-decreasing */
> +#define DRM_MODE_LUT_NON_DECREASING BIT(4)
> +/* the curve is reflected across origin for negative inputs */
> +#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5)
> +/* the same curve (red) is used for blue and green channels as well */
> +#define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6)
> +
> +struct drm_color_lut_range {
> + /* DRM_MODE_LUT_* */
> + __u32 flags;
> + /* number of points on the curve */
> + __u16 count;
> + /* input/output bits per component */
> + __u8 input_bpc, output_bpc;
> + /* input start/end values */
> + __s32 start, end;
> + /* output min/max values */
> + __s32 min, max;
> +};
> +
> +enum lut_type {
> + LUT_TYPE_DEGAMMA = 0,
> + LUT_TYPE_GAMMA = 1,
> +};
> +
> #define DRM_MODE_PAGE_FLIP_EVENT 0x01
> #define DRM_MODE_PAGE_FLIP_ASYNC 0x02
> #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
Hi,
where is the UAPI documentation for this new GAMMA_MODE?
As a userspace dev, I have no idea what to do with the above based on
what's written here.
Also, reading the description of DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES in
patch 5/9, what difference does it make whether userspace sets or does
not set that cap? I don't understand the implications from the
description.
Thanks,
pq
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^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH 1/9] drm: Add gamma mode property
@ 2021-06-02 9:09 ` Pekka Paalanen
0 siblings, 0 replies; 48+ messages in thread
From: Pekka Paalanen @ 2021-06-02 9:09 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 4392 bytes --]
On Tue, 1 Jun 2021 16:11:27 +0530
Uma Shankar <uma.shankar@intel.com> wrote:
> Add a gamma mode property to enable various kind of
> gamma modes supported by platforms like: Interpolated, Split,
> Multi Segmented, Logarithmic etc. Userspace can get this property
> and should be able to get the platform capabilities wrt various
> gamma modes possible and the possible ranges.
>
> It can select one of the modes exposed as blob_id as an
> enum and set the respective mode.
>
> It can then create the LUT and send it to driver using
> already available GAMMA_LUT property as blob.
>
> Note: This is based on design by Ville and is being carried forward
> based on his original idea.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/drm_atomic_uapi.c | 5 +++
> drivers/gpu/drm/drm_color_mgmt.c | 75 +++++++++++++++++++++++++++++++
> include/drm/drm_color_mgmt.h | 8 ++++
> include/drm/drm_crtc.h | 14 ++++++
> include/uapi/drm/drm_mode.h | 43 ++++++++++++++++++
> 5 files changed, 145 insertions(+)
>
...
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index 13eeba2a750a..b1eead03ebe8 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -262,6 +262,13 @@ struct drm_crtc_state {
> */
> struct drm_property_blob *mode_blob;
>
> + /**
> + * @gamma_mode: This is a blob_id and exposes the platform capabilities
> + * wrt to various gamma modes and the respective lut ranges. This also
> + * helps user select a gamma mode amongst the supported ones.
> + */
> + u32 gamma_mode;
> +
> /**
> * @degamma_lut:
> *
> @@ -1096,6 +1103,13 @@ struct drm_crtc {
> */
> struct drm_property *scaling_filter_property;
>
> + /**
> + * @gamma_mode_property: Optional CRTC property to enumerate and
> + * select the mode of the crtc gamma/degmama LUTs. This also exposes
> + * the lut ranges of the various supported gamma modes to userspace.
> + */
> + struct drm_property *gamma_mode_property;
> +
> /**
> * @state:
> *
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index 9b6722d45f36..d7758d351936 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -819,6 +819,49 @@ struct hdr_output_metadata {
> };
> };
>
> +/*
> + * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and means the LUT
> + * can be used for either purpose, but not simultaneously. To expose
> + * modes that support gamma and degamma simultaneously the gamma mode
> + * must declare distinct DRM_MODE_LUT_GAMMA and DRM_MODE_LUT_DEGAMMA
> + * ranges.
> + */
> +/* LUT is for gamma (after CTM) */
> +#define DRM_MODE_LUT_GAMMA BIT(0)
> +/* LUT is for degamma (before CTM) */
> +#define DRM_MODE_LUT_DEGAMMA BIT(1)
> +/* linearly interpolate between the points */
> +#define DRM_MODE_LUT_INTERPOLATE BIT(2)
> +/*
> + * the last value of the previous range is the
> + * first value of the current range.
> + */
> +#define DRM_MODE_LUT_REUSE_LAST BIT(3)
> +/* the curve must be non-decreasing */
> +#define DRM_MODE_LUT_NON_DECREASING BIT(4)
> +/* the curve is reflected across origin for negative inputs */
> +#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5)
> +/* the same curve (red) is used for blue and green channels as well */
> +#define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6)
> +
> +struct drm_color_lut_range {
> + /* DRM_MODE_LUT_* */
> + __u32 flags;
> + /* number of points on the curve */
> + __u16 count;
> + /* input/output bits per component */
> + __u8 input_bpc, output_bpc;
> + /* input start/end values */
> + __s32 start, end;
> + /* output min/max values */
> + __s32 min, max;
> +};
> +
> +enum lut_type {
> + LUT_TYPE_DEGAMMA = 0,
> + LUT_TYPE_GAMMA = 1,
> +};
> +
> #define DRM_MODE_PAGE_FLIP_EVENT 0x01
> #define DRM_MODE_PAGE_FLIP_ASYNC 0x02
> #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
Hi,
where is the UAPI documentation for this new GAMMA_MODE?
As a userspace dev, I have no idea what to do with the above based on
what's written here.
Also, reading the description of DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES in
patch 5/9, what difference does it make whether userspace sets or does
not set that cap? I don't understand the implications from the
description.
Thanks,
pq
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread* RE: [PATCH 1/9] drm: Add gamma mode property
2021-06-02 9:09 ` [Intel-gfx] " Pekka Paalanen
@ 2021-06-02 20:18 ` Shankar, Uma
-1 siblings, 0 replies; 48+ messages in thread
From: Shankar, Uma @ 2021-06-02 20:18 UTC (permalink / raw)
To: Pekka Paalanen; +Cc: intel-gfx, dri-devel, Modem, Bhanuprakash
> -----Original Message-----
> From: Pekka Paalanen <ppaalanen@gmail.com>
> Sent: Wednesday, June 2, 2021 2:40 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Modem,
> Bhanuprakash <bhanuprakash.modem@intel.com>
> Subject: Re: [PATCH 1/9] drm: Add gamma mode property
>
> On Tue, 1 Jun 2021 16:11:27 +0530
> Uma Shankar <uma.shankar@intel.com> wrote:
>
> > Add a gamma mode property to enable various kind of gamma modes
> > supported by platforms like: Interpolated, Split, Multi Segmented,
> > Logarithmic etc. Userspace can get this property and should be able to
> > get the platform capabilities wrt various gamma modes possible and the
> > possible ranges.
> >
> > It can select one of the modes exposed as blob_id as an enum and set
> > the respective mode.
> >
> > It can then create the LUT and send it to driver using already
> > available GAMMA_LUT property as blob.
> >
> > Note: This is based on design by Ville and is being carried forward
> > based on his original idea.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/drm_atomic_uapi.c | 5 +++
> > drivers/gpu/drm/drm_color_mgmt.c | 75 +++++++++++++++++++++++++++++++
> > include/drm/drm_color_mgmt.h | 8 ++++
> > include/drm/drm_crtc.h | 14 ++++++
> > include/uapi/drm/drm_mode.h | 43 ++++++++++++++++++
> > 5 files changed, 145 insertions(+)
> >
>
> ...
>
> > diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index
> > 13eeba2a750a..b1eead03ebe8 100644
> > --- a/include/drm/drm_crtc.h
> > +++ b/include/drm/drm_crtc.h
> > @@ -262,6 +262,13 @@ struct drm_crtc_state {
> > */
> > struct drm_property_blob *mode_blob;
> >
> > + /**
> > + * @gamma_mode: This is a blob_id and exposes the platform capabilities
> > + * wrt to various gamma modes and the respective lut ranges. This also
> > + * helps user select a gamma mode amongst the supported ones.
> > + */
> > + u32 gamma_mode;
> > +
> > /**
> > * @degamma_lut:
> > *
> > @@ -1096,6 +1103,13 @@ struct drm_crtc {
> > */
> > struct drm_property *scaling_filter_property;
> >
> > + /**
> > + * @gamma_mode_property: Optional CRTC property to enumerate and
> > + * select the mode of the crtc gamma/degmama LUTs. This also exposes
> > + * the lut ranges of the various supported gamma modes to userspace.
> > + */
> > + struct drm_property *gamma_mode_property;
> > +
> > /**
> > * @state:
> > *
> > diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> > index 9b6722d45f36..d7758d351936 100644
> > --- a/include/uapi/drm/drm_mode.h
> > +++ b/include/uapi/drm/drm_mode.h
> > @@ -819,6 +819,49 @@ struct hdr_output_metadata {
> > };
> > };
> >
> > +/*
> > + * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and means
> the LUT
> > + * can be used for either purpose, but not simultaneously. To expose
> > + * modes that support gamma and degamma simultaneously the gamma mode
> > + * must declare distinct DRM_MODE_LUT_GAMMA and
> DRM_MODE_LUT_DEGAMMA
> > + * ranges.
> > + */
> > +/* LUT is for gamma (after CTM) */
> > +#define DRM_MODE_LUT_GAMMA BIT(0)
> > +/* LUT is for degamma (before CTM) */ #define DRM_MODE_LUT_DEGAMMA
> > +BIT(1)
> > +/* linearly interpolate between the points */ #define
> > +DRM_MODE_LUT_INTERPOLATE BIT(2)
> > +/*
> > + * the last value of the previous range is the
> > + * first value of the current range.
> > + */
> > +#define DRM_MODE_LUT_REUSE_LAST BIT(3)
> > +/* the curve must be non-decreasing */ #define
> > +DRM_MODE_LUT_NON_DECREASING BIT(4)
> > +/* the curve is reflected across origin for negative inputs */
> > +#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5)
> > +/* the same curve (red) is used for blue and green channels as well
> > +*/ #define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6)
> > +
> > +struct drm_color_lut_range {
> > + /* DRM_MODE_LUT_* */
> > + __u32 flags;
> > + /* number of points on the curve */
> > + __u16 count;
> > + /* input/output bits per component */
> > + __u8 input_bpc, output_bpc;
> > + /* input start/end values */
> > + __s32 start, end;
> > + /* output min/max values */
> > + __s32 min, max;
> > +};
> > +
> > +enum lut_type {
> > + LUT_TYPE_DEGAMMA = 0,
> > + LUT_TYPE_GAMMA = 1,
> > +};
> > +
> > #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define
> > DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define
> > DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
>
> Hi,
>
> where is the UAPI documentation for this new GAMMA_MODE?
> As a userspace dev, I have no idea what to do with the above based on what's
> written here.
Got that, I will add more details on the UAPI usage to make things a bit clearer.
> Also, reading the description of DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES in
> patch 5/9, what difference does it make whether userspace sets or does not set that
> cap? I don't understand the implications from the description.
The reason we have this Client caps is to have it co-exist with legacy crtc color properties.
The idea is that driver will describe the h/w luts to userspace through GAMMA_MODE UAPI,
but the actual lut samples will still be sent through the legacy GAMMA_LUT UAPI. This client
cap will help distinguish between legacy and this new implementation.
I will add more details in the UAPI description to avoid ambiguity and explain the rationale and
usage of this UAPI.
Thanks Pekka for the looking into the series and the initial feedback.
Regards,
Uma Shankar
>
> Thanks,
> pq
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH 1/9] drm: Add gamma mode property
@ 2021-06-02 20:18 ` Shankar, Uma
0 siblings, 0 replies; 48+ messages in thread
From: Shankar, Uma @ 2021-06-02 20:18 UTC (permalink / raw)
To: Pekka Paalanen; +Cc: intel-gfx, dri-devel
> -----Original Message-----
> From: Pekka Paalanen <ppaalanen@gmail.com>
> Sent: Wednesday, June 2, 2021 2:40 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Modem,
> Bhanuprakash <bhanuprakash.modem@intel.com>
> Subject: Re: [PATCH 1/9] drm: Add gamma mode property
>
> On Tue, 1 Jun 2021 16:11:27 +0530
> Uma Shankar <uma.shankar@intel.com> wrote:
>
> > Add a gamma mode property to enable various kind of gamma modes
> > supported by platforms like: Interpolated, Split, Multi Segmented,
> > Logarithmic etc. Userspace can get this property and should be able to
> > get the platform capabilities wrt various gamma modes possible and the
> > possible ranges.
> >
> > It can select one of the modes exposed as blob_id as an enum and set
> > the respective mode.
> >
> > It can then create the LUT and send it to driver using already
> > available GAMMA_LUT property as blob.
> >
> > Note: This is based on design by Ville and is being carried forward
> > based on his original idea.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/drm_atomic_uapi.c | 5 +++
> > drivers/gpu/drm/drm_color_mgmt.c | 75 +++++++++++++++++++++++++++++++
> > include/drm/drm_color_mgmt.h | 8 ++++
> > include/drm/drm_crtc.h | 14 ++++++
> > include/uapi/drm/drm_mode.h | 43 ++++++++++++++++++
> > 5 files changed, 145 insertions(+)
> >
>
> ...
>
> > diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index
> > 13eeba2a750a..b1eead03ebe8 100644
> > --- a/include/drm/drm_crtc.h
> > +++ b/include/drm/drm_crtc.h
> > @@ -262,6 +262,13 @@ struct drm_crtc_state {
> > */
> > struct drm_property_blob *mode_blob;
> >
> > + /**
> > + * @gamma_mode: This is a blob_id and exposes the platform capabilities
> > + * wrt to various gamma modes and the respective lut ranges. This also
> > + * helps user select a gamma mode amongst the supported ones.
> > + */
> > + u32 gamma_mode;
> > +
> > /**
> > * @degamma_lut:
> > *
> > @@ -1096,6 +1103,13 @@ struct drm_crtc {
> > */
> > struct drm_property *scaling_filter_property;
> >
> > + /**
> > + * @gamma_mode_property: Optional CRTC property to enumerate and
> > + * select the mode of the crtc gamma/degmama LUTs. This also exposes
> > + * the lut ranges of the various supported gamma modes to userspace.
> > + */
> > + struct drm_property *gamma_mode_property;
> > +
> > /**
> > * @state:
> > *
> > diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> > index 9b6722d45f36..d7758d351936 100644
> > --- a/include/uapi/drm/drm_mode.h
> > +++ b/include/uapi/drm/drm_mode.h
> > @@ -819,6 +819,49 @@ struct hdr_output_metadata {
> > };
> > };
> >
> > +/*
> > + * DRM_MODE_LUT_GAMMA|DRM_MODE_LUT_DEGAMMA is legal and means
> the LUT
> > + * can be used for either purpose, but not simultaneously. To expose
> > + * modes that support gamma and degamma simultaneously the gamma mode
> > + * must declare distinct DRM_MODE_LUT_GAMMA and
> DRM_MODE_LUT_DEGAMMA
> > + * ranges.
> > + */
> > +/* LUT is for gamma (after CTM) */
> > +#define DRM_MODE_LUT_GAMMA BIT(0)
> > +/* LUT is for degamma (before CTM) */ #define DRM_MODE_LUT_DEGAMMA
> > +BIT(1)
> > +/* linearly interpolate between the points */ #define
> > +DRM_MODE_LUT_INTERPOLATE BIT(2)
> > +/*
> > + * the last value of the previous range is the
> > + * first value of the current range.
> > + */
> > +#define DRM_MODE_LUT_REUSE_LAST BIT(3)
> > +/* the curve must be non-decreasing */ #define
> > +DRM_MODE_LUT_NON_DECREASING BIT(4)
> > +/* the curve is reflected across origin for negative inputs */
> > +#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5)
> > +/* the same curve (red) is used for blue and green channels as well
> > +*/ #define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6)
> > +
> > +struct drm_color_lut_range {
> > + /* DRM_MODE_LUT_* */
> > + __u32 flags;
> > + /* number of points on the curve */
> > + __u16 count;
> > + /* input/output bits per component */
> > + __u8 input_bpc, output_bpc;
> > + /* input start/end values */
> > + __s32 start, end;
> > + /* output min/max values */
> > + __s32 min, max;
> > +};
> > +
> > +enum lut_type {
> > + LUT_TYPE_DEGAMMA = 0,
> > + LUT_TYPE_GAMMA = 1,
> > +};
> > +
> > #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define
> > DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define
> > DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
>
> Hi,
>
> where is the UAPI documentation for this new GAMMA_MODE?
> As a userspace dev, I have no idea what to do with the above based on what's
> written here.
Got that, I will add more details on the UAPI usage to make things a bit clearer.
> Also, reading the description of DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES in
> patch 5/9, what difference does it make whether userspace sets or does not set that
> cap? I don't understand the implications from the description.
The reason we have this Client caps is to have it co-exist with legacy crtc color properties.
The idea is that driver will describe the h/w luts to userspace through GAMMA_MODE UAPI,
but the actual lut samples will still be sent through the legacy GAMMA_LUT UAPI. This client
cap will help distinguish between legacy and this new implementation.
I will add more details in the UAPI description to avoid ambiguity and explain the rationale and
usage of this UAPI.
Thanks Pekka for the looking into the series and the initial feedback.
Regards,
Uma Shankar
>
> Thanks,
> pq
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [PATCH 1/9] drm: Add gamma mode property
2021-06-02 20:18 ` [Intel-gfx] " Shankar, Uma
@ 2021-06-03 8:05 ` Pekka Paalanen
-1 siblings, 0 replies; 48+ messages in thread
From: Pekka Paalanen @ 2021-06-03 8:05 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-gfx, dri-devel, Modem, Bhanuprakash
[-- Attachment #1: Type: text/plain, Size: 2785 bytes --]
On Wed, 2 Jun 2021 20:18:19 +0000
"Shankar, Uma" <uma.shankar@intel.com> wrote:
> > -----Original Message-----
> > From: Pekka Paalanen <ppaalanen@gmail.com>
> > Sent: Wednesday, June 2, 2021 2:40 PM
> > To: Shankar, Uma <uma.shankar@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Modem,
> > Bhanuprakash <bhanuprakash.modem@intel.com>
> > Subject: Re: [PATCH 1/9] drm: Add gamma mode property
> >
> > On Tue, 1 Jun 2021 16:11:27 +0530
> > Uma Shankar <uma.shankar@intel.com> wrote:
> >
> > > Add a gamma mode property to enable various kind of gamma modes
> > > supported by platforms like: Interpolated, Split, Multi Segmented,
> > > Logarithmic etc. Userspace can get this property and should be able to
> > > get the platform capabilities wrt various gamma modes possible and the
> > > possible ranges.
> > >
> > > It can select one of the modes exposed as blob_id as an enum and set
> > > the respective mode.
> > >
> > > It can then create the LUT and send it to driver using already
> > > available GAMMA_LUT property as blob.
> > >
> > > Note: This is based on design by Ville and is being carried forward
> > > based on his original idea.
> > >
> > > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > > ---
> > > drivers/gpu/drm/drm_atomic_uapi.c | 5 +++
> > > drivers/gpu/drm/drm_color_mgmt.c | 75 +++++++++++++++++++++++++++++++
> > > include/drm/drm_color_mgmt.h | 8 ++++
> > > include/drm/drm_crtc.h | 14 ++++++
> > > include/uapi/drm/drm_mode.h | 43 ++++++++++++++++++
> > > 5 files changed, 145 insertions(+)
...
> > Hi,
> >
> > where is the UAPI documentation for this new GAMMA_MODE?
> > As a userspace dev, I have no idea what to do with the above based on what's
> > written here.
>
> Got that, I will add more details on the UAPI usage to make things a bit clearer.
>
> > Also, reading the description of DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES in
> > patch 5/9, what difference does it make whether userspace sets or does not set that
> > cap? I don't understand the implications from the description.
>
> The reason we have this Client caps is to have it co-exist with legacy crtc color properties.
> The idea is that driver will describe the h/w luts to userspace through GAMMA_MODE UAPI,
> but the actual lut samples will still be sent through the legacy GAMMA_LUT UAPI. This client
> cap will help distinguish between legacy and this new implementation.
>
> I will add more details in the UAPI description to avoid ambiguity and explain the rationale and
> usage of this UAPI.
>
> Thanks Pekka for the looking into the series and the initial feedback.
Thanks a lot, will be interesting to read those docs.
pq
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^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 1/9] drm: Add gamma mode property
@ 2021-06-03 8:05 ` Pekka Paalanen
0 siblings, 0 replies; 48+ messages in thread
From: Pekka Paalanen @ 2021-06-03 8:05 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-gfx, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 2785 bytes --]
On Wed, 2 Jun 2021 20:18:19 +0000
"Shankar, Uma" <uma.shankar@intel.com> wrote:
> > -----Original Message-----
> > From: Pekka Paalanen <ppaalanen@gmail.com>
> > Sent: Wednesday, June 2, 2021 2:40 PM
> > To: Shankar, Uma <uma.shankar@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Modem,
> > Bhanuprakash <bhanuprakash.modem@intel.com>
> > Subject: Re: [PATCH 1/9] drm: Add gamma mode property
> >
> > On Tue, 1 Jun 2021 16:11:27 +0530
> > Uma Shankar <uma.shankar@intel.com> wrote:
> >
> > > Add a gamma mode property to enable various kind of gamma modes
> > > supported by platforms like: Interpolated, Split, Multi Segmented,
> > > Logarithmic etc. Userspace can get this property and should be able to
> > > get the platform capabilities wrt various gamma modes possible and the
> > > possible ranges.
> > >
> > > It can select one of the modes exposed as blob_id as an enum and set
> > > the respective mode.
> > >
> > > It can then create the LUT and send it to driver using already
> > > available GAMMA_LUT property as blob.
> > >
> > > Note: This is based on design by Ville and is being carried forward
> > > based on his original idea.
> > >
> > > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > > ---
> > > drivers/gpu/drm/drm_atomic_uapi.c | 5 +++
> > > drivers/gpu/drm/drm_color_mgmt.c | 75 +++++++++++++++++++++++++++++++
> > > include/drm/drm_color_mgmt.h | 8 ++++
> > > include/drm/drm_crtc.h | 14 ++++++
> > > include/uapi/drm/drm_mode.h | 43 ++++++++++++++++++
> > > 5 files changed, 145 insertions(+)
...
> > Hi,
> >
> > where is the UAPI documentation for this new GAMMA_MODE?
> > As a userspace dev, I have no idea what to do with the above based on what's
> > written here.
>
> Got that, I will add more details on the UAPI usage to make things a bit clearer.
>
> > Also, reading the description of DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES in
> > patch 5/9, what difference does it make whether userspace sets or does not set that
> > cap? I don't understand the implications from the description.
>
> The reason we have this Client caps is to have it co-exist with legacy crtc color properties.
> The idea is that driver will describe the h/w luts to userspace through GAMMA_MODE UAPI,
> but the actual lut samples will still be sent through the legacy GAMMA_LUT UAPI. This client
> cap will help distinguish between legacy and this new implementation.
>
> I will add more details in the UAPI description to avoid ambiguity and explain the rationale and
> usage of this UAPI.
>
> Thanks Pekka for the looking into the series and the initial feedback.
Thanks a lot, will be interesting to read those docs.
pq
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 2/9] drm/i915/xelpd: Define color lut range structure
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
@ 2021-06-01 10:41 ` Uma Shankar
-1 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Uma Shankar, bhanuprakash.modem
This defines the color lut ranges for logarithmic gamma which
is being introduced from XE_LPD onwards.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 250 ++++++++++++++++++++-
1 file changed, 246 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index dab892d2251b..0b59d8a89761 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2093,6 +2093,238 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
}
}
+#define D13_GAMMA_CAPABILITY_FLAG (DRM_MODE_LUT_GAMMA | \
+ DRM_MODE_LUT_REFLECT_NEGATIVE | \
+ DRM_MODE_LUT_INTERPOLATE | \
+ DRM_MODE_LUT_NON_DECREASING)
+ /* FIXME input bpc? */
+static const struct drm_color_lut_range d13_logarithmic_gamma[] = {
+ /* segment 0 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = 0, .end = 0,
+ .min = 0, .max = 0,
+ },
+ /* segment 1 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = 0, .end = (1 << 0),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 2 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 2,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 0), .end = (1 << 1),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 3 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 2,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 1), .end = (1 << 2),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 4 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 2,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 2), .end = (1 << 3),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 5 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 2,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 3), .end = (1 << 4),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 6 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 4,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 4), .end = (1 << 5),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 7 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 4,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 5), .end = (1 << 6),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 8 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 4,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 6), .end = (1 << 7),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 9 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 8,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 7), .end = (1 << 8),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 10 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 8,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 8), .end = (1 << 9),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 11 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 8,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 9), .end = (1 << 10),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 12 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 16,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 10), .end = (1 << 11),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 13 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 16,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 11), .end = (1 << 12),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 14 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 16,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 12), .end = (1 << 13),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 15 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 13), .end = (1 << 14),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 16 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 14), .end = (1 << 15),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 17 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 64,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 15), .end = (1 << 16),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 18 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 64,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 16), .end = (1 << 17),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 19 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 64,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 17), .end = (1 << 18),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 20 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 18), .end = (1 << 19),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 21 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 19), .end = (1 << 20),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 22 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 20), .end = (1 << 21),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 23 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 21), .end = (1 << 22),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 24 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 22), .end = (1 << 23),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 3 aka. coarse segment / PAL_GC_MAX */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG | DRM_MODE_LUT_REUSE_LAST,
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 24), .end = (3 << 24),
+ .min = 0, .max = 1 << 16,
+ },
+ /* PAL_EXT_GC_MAX */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG | DRM_MODE_LUT_REUSE_LAST,
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (3 << 24), .end = (7 << 24),
+ .min = 0, .max = (8 << 16) - 1,
+ },
+ /* PAL_EXT2_GC_MAX */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG | DRM_MODE_LUT_REUSE_LAST,
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (7 << 24), .end = (7 << 24),
+ .min = 0, .max = (8 << 16) - 1,
+ },
+};
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2118,14 +2350,24 @@ void intel_color_init(struct intel_crtc *crtc)
dev_priv->display.read_luts = i9xx_read_luts;
}
} else {
- if (DISPLAY_VER(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 13) {
+ dev_priv->display.color_check = icl_color_check;
+ drm_color_create_gamma_mode_property(&crtc->base, 2);
+ drm_color_add_gamma_mode_range(&crtc->base,
+ "no gamma", NULL, 0);
+ drm_color_add_gamma_mode_range(&crtc->base,
+ "logarithmic gamma",
+ d13_logarithmic_gamma,
+ sizeof(d13_logarithmic_gamma));
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.color_check = icl_color_check;
- else if (DISPLAY_VER(dev_priv) >= 10)
+ } else if (DISPLAY_VER(dev_priv) >= 10) {
dev_priv->display.color_check = glk_color_check;
- else if (DISPLAY_VER(dev_priv) >= 7)
+ } else if (DISPLAY_VER(dev_priv) >= 7) {
dev_priv->display.color_check = ivb_color_check;
- else
+ } else {
dev_priv->display.color_check = ilk_color_check;
+ }
if (DISPLAY_VER(dev_priv) >= 9)
dev_priv->display.color_commit = skl_color_commit;
--
2.26.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH 2/9] drm/i915/xelpd: Define color lut range structure
@ 2021-06-01 10:41 ` Uma Shankar
0 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
This defines the color lut ranges for logarithmic gamma which
is being introduced from XE_LPD onwards.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 250 ++++++++++++++++++++-
1 file changed, 246 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index dab892d2251b..0b59d8a89761 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2093,6 +2093,238 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
}
}
+#define D13_GAMMA_CAPABILITY_FLAG (DRM_MODE_LUT_GAMMA | \
+ DRM_MODE_LUT_REFLECT_NEGATIVE | \
+ DRM_MODE_LUT_INTERPOLATE | \
+ DRM_MODE_LUT_NON_DECREASING)
+ /* FIXME input bpc? */
+static const struct drm_color_lut_range d13_logarithmic_gamma[] = {
+ /* segment 0 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = 0, .end = 0,
+ .min = 0, .max = 0,
+ },
+ /* segment 1 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = 0, .end = (1 << 0),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 2 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 2,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 0), .end = (1 << 1),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 3 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 2,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 1), .end = (1 << 2),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 4 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 2,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 2), .end = (1 << 3),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 5 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 2,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 3), .end = (1 << 4),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 6 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 4,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 4), .end = (1 << 5),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 7 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 4,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 5), .end = (1 << 6),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 8 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 4,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 6), .end = (1 << 7),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 9 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 8,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 7), .end = (1 << 8),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 10 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 8,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 8), .end = (1 << 9),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 11 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 8,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 9), .end = (1 << 10),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 12 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 16,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 10), .end = (1 << 11),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 13 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 16,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 11), .end = (1 << 12),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 14 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 16,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 12), .end = (1 << 13),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 15 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 13), .end = (1 << 14),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 16 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 14), .end = (1 << 15),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 17 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 64,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 15), .end = (1 << 16),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 18 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 64,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 16), .end = (1 << 17),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 19 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 64,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 17), .end = (1 << 18),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 20 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 18), .end = (1 << 19),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 21 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 19), .end = (1 << 20),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 22 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 20), .end = (1 << 21),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 23 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 21), .end = (1 << 22),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 24 */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG,
+ .count = 32,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 22), .end = (1 << 23),
+ .min = 0, .max = (1 << 16) - 1,
+ },
+ /* segment 3 aka. coarse segment / PAL_GC_MAX */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG | DRM_MODE_LUT_REUSE_LAST,
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (1 << 24), .end = (3 << 24),
+ .min = 0, .max = 1 << 16,
+ },
+ /* PAL_EXT_GC_MAX */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG | DRM_MODE_LUT_REUSE_LAST,
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (3 << 24), .end = (7 << 24),
+ .min = 0, .max = (8 << 16) - 1,
+ },
+ /* PAL_EXT2_GC_MAX */
+ {
+ .flags = D13_GAMMA_CAPABILITY_FLAG | DRM_MODE_LUT_REUSE_LAST,
+ .count = 1,
+ .input_bpc = 24, .output_bpc = 16,
+ .start = (7 << 24), .end = (7 << 24),
+ .min = 0, .max = (8 << 16) - 1,
+ },
+};
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2118,14 +2350,24 @@ void intel_color_init(struct intel_crtc *crtc)
dev_priv->display.read_luts = i9xx_read_luts;
}
} else {
- if (DISPLAY_VER(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 13) {
+ dev_priv->display.color_check = icl_color_check;
+ drm_color_create_gamma_mode_property(&crtc->base, 2);
+ drm_color_add_gamma_mode_range(&crtc->base,
+ "no gamma", NULL, 0);
+ drm_color_add_gamma_mode_range(&crtc->base,
+ "logarithmic gamma",
+ d13_logarithmic_gamma,
+ sizeof(d13_logarithmic_gamma));
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.color_check = icl_color_check;
- else if (DISPLAY_VER(dev_priv) >= 10)
+ } else if (DISPLAY_VER(dev_priv) >= 10) {
dev_priv->display.color_check = glk_color_check;
- else if (DISPLAY_VER(dev_priv) >= 7)
+ } else if (DISPLAY_VER(dev_priv) >= 7) {
dev_priv->display.color_check = ivb_color_check;
- else
+ } else {
dev_priv->display.color_check = ilk_color_check;
+ }
if (DISPLAY_VER(dev_priv) >= 9)
dev_priv->display.color_commit = skl_color_commit;
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 3/9] drm/i915/xelpd: Add support for Logarithmic gamma mode
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
@ 2021-06-01 10:41 ` Uma Shankar
-1 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Uma Shankar, bhanuprakash.modem
XE_LPD hardware introduced a new gamma mode i.e, Logarithmic
gamma mode. Added support for the same.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 111 ++++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
include/drm/drm_crtc.h | 3 +
3 files changed, 110 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 0b59d8a89761..12cacd3aeead 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -75,6 +75,21 @@
#define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
+#define GAMMA_MODE_LEGACY_PALETTE_8BIT BIT(0)
+#define GAMMA_MODE_PRECISION_PALETTE_10BIT BIT(1)
+#define GAMMA_MODE_INTERPOLATED_12BIT BIT(2)
+#define GAMMA_MODE_MULTI_SEGMENTED_12BIT BIT(3)
+#define GAMMA_MODE_SPLIT_12BIT BIT(4)
+#define GAMMA_MODE_LOGARITHMIC_12BIT BIT(5) /* D13+ */
+
+#define INTEL_GAMMA_MODE_MASK (\
+ GAMMA_MODE_LEGACY_PALETTE_8BIT | \
+ GAMMA_MODE_PRECISION_PALETTE_10BIT | \
+ GAMMA_MODE_INTERPOLATED_12BIT | \
+ GAMMA_MODE_MULTI_SEGMENTED_12BIT | \
+ GAMMA_MODE_SPLIT_12BIT \
+ GAMMA_MODE_LOGARITHMIC_12BIT)
+
/* Nop pre/post offsets */
static const u16 ilk_csc_off_zero[3] = {};
@@ -929,12 +944,20 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
const struct drm_color_lut *color)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
enum pipe pipe = crtc->pipe;
- /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red);
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green);
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ if (DISPLAY_VER(i915) >= 13) {
+ /* MAx val from UAPI is 16bit only, so setting fixed for GC max */
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), 1 << 16);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), 1 << 16);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), 1 << 16);
+ } else {
+ /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ }
}
static void
@@ -1585,6 +1608,9 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
if (!crtc_state->hw.gamma_lut ||
crtc_state_is_legacy_gamma(crtc_state))
gamma_mode |= GAMMA_MODE_MODE_8BIT;
+ else if (crtc_state->uapi.gamma_mode_type ==
+ GAMMA_MODE_LOGARITHMIC_12BIT)
+ gamma_mode |= GAMMA_MODE_MODE_12BIT_LOGARITHMIC;
else
gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
@@ -1607,12 +1633,33 @@ static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
static int icl_color_check(struct intel_crtc_state *crtc_state)
{
+ struct drm_device *dev = crtc_state->uapi.crtc->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_property *property = crtc_state->uapi.crtc->gamma_mode_property;
+ struct drm_property_enum *prop_enum;
+ u32 index = 0;
int ret;
ret = check_luts(crtc_state);
if (ret)
return ret;
+ if (DISPLAY_VER(dev_priv) >= 13) {
+ list_for_each_entry(prop_enum, &property->enum_list, head) {
+ if (prop_enum->value == crtc_state->uapi.gamma_mode) {
+ if (!strcmp(prop_enum->name,
+ "logarithmic gamma")) {
+ crtc_state->uapi.gamma_mode_type =
+ GAMMA_MODE_LOGARITHMIC_12BIT;
+ drm_dbg_kms(dev,
+ "logarithmic gamma enabled\n");
+ }
+ break;
+ }
+ index++;
+ }
+ }
+
crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
crtc_state->csc_mode = icl_csc_mode(crtc_state);
@@ -2325,6 +2372,58 @@ static const struct drm_color_lut_range d13_logarithmic_gamma[] = {
},
};
+static void
+d13_program_logarithmic_gamma_lut(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
+ const u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ const struct drm_color_lut *lut;
+ enum pipe pipe = crtc->pipe;
+ u32 i;
+
+ if (!blob || !blob->data)
+ return;
+
+ lut = blob->data;
+ intel_dsb_reg_write(crtc_state, PREC_PAL_INDEX(pipe),
+ PAL_PREC_AUTO_INCREMENT);
+
+ for (i = 0; i < lut_size - 3; i++) {
+ intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
+ ilk_lut_12p4_ldw(&lut[i]));
+ intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
+ ilk_lut_12p4_udw(&lut[i]));
+ }
+
+ icl_load_gcmax(crtc_state, &lut[i]);
+ ivb_load_lut_ext_max(crtc_state);
+}
+
+static void d13_load_luts(const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (crtc_state->hw.degamma_lut)
+ glk_load_degamma_lut(crtc_state);
+
+ switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
+ case GAMMA_MODE_MODE_8BIT:
+ ilk_load_lut_8(crtc, gamma_lut);
+ break;
+ case GAMMA_MODE_MODE_12BIT_LOGARITHMIC:
+ d13_program_logarithmic_gamma_lut(crtc_state);
+ break;
+ default:
+ bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
+ ivb_load_lut_ext_max(crtc_state);
+ }
+
+ intel_dsb_commit(crtc_state);
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2376,7 +2475,9 @@ void intel_color_init(struct intel_crtc *crtc)
else
dev_priv->display.color_commit = ilk_color_commit;
- if (DISPLAY_VER(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 13) {
+ dev_priv->display.load_luts = d13_load_luts;
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
dev_priv->display.read_luts = icl_read_luts;
} else if (DISPLAY_VER(dev_priv) == 10) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24307c49085f..957f97edf035 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7749,6 +7749,7 @@ enum {
#define GAMMA_MODE_MODE_12BIT (2 << 0)
#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
+#define GAMMA_MODE_MODE_12BIT_LOGARITHMIC (3 << 0) /* D13+ + */
/* DMC */
#define DMC_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index b1eead03ebe8..5a594f134a81 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -269,6 +269,9 @@ struct drm_crtc_state {
*/
u32 gamma_mode;
+ /** Gamma mode type programmed on the pipe */
+ u32 gamma_mode_type;
+
/**
* @degamma_lut:
*
--
2.26.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH 3/9] drm/i915/xelpd: Add support for Logarithmic gamma mode
@ 2021-06-01 10:41 ` Uma Shankar
0 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
XE_LPD hardware introduced a new gamma mode i.e, Logarithmic
gamma mode. Added support for the same.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 111 ++++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
include/drm/drm_crtc.h | 3 +
3 files changed, 110 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 0b59d8a89761..12cacd3aeead 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -75,6 +75,21 @@
#define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
+#define GAMMA_MODE_LEGACY_PALETTE_8BIT BIT(0)
+#define GAMMA_MODE_PRECISION_PALETTE_10BIT BIT(1)
+#define GAMMA_MODE_INTERPOLATED_12BIT BIT(2)
+#define GAMMA_MODE_MULTI_SEGMENTED_12BIT BIT(3)
+#define GAMMA_MODE_SPLIT_12BIT BIT(4)
+#define GAMMA_MODE_LOGARITHMIC_12BIT BIT(5) /* D13+ */
+
+#define INTEL_GAMMA_MODE_MASK (\
+ GAMMA_MODE_LEGACY_PALETTE_8BIT | \
+ GAMMA_MODE_PRECISION_PALETTE_10BIT | \
+ GAMMA_MODE_INTERPOLATED_12BIT | \
+ GAMMA_MODE_MULTI_SEGMENTED_12BIT | \
+ GAMMA_MODE_SPLIT_12BIT \
+ GAMMA_MODE_LOGARITHMIC_12BIT)
+
/* Nop pre/post offsets */
static const u16 ilk_csc_off_zero[3] = {};
@@ -929,12 +944,20 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
const struct drm_color_lut *color)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
enum pipe pipe = crtc->pipe;
- /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red);
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green);
- intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ if (DISPLAY_VER(i915) >= 13) {
+ /* MAx val from UAPI is 16bit only, so setting fixed for GC max */
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), 1 << 16);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), 1 << 16);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), 1 << 16);
+ } else {
+ /* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 0), color->red);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 1), color->green);
+ intel_dsb_reg_write(crtc_state, PREC_PAL_GC_MAX(pipe, 2), color->blue);
+ }
}
static void
@@ -1585,6 +1608,9 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
if (!crtc_state->hw.gamma_lut ||
crtc_state_is_legacy_gamma(crtc_state))
gamma_mode |= GAMMA_MODE_MODE_8BIT;
+ else if (crtc_state->uapi.gamma_mode_type ==
+ GAMMA_MODE_LOGARITHMIC_12BIT)
+ gamma_mode |= GAMMA_MODE_MODE_12BIT_LOGARITHMIC;
else
gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
@@ -1607,12 +1633,33 @@ static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state)
static int icl_color_check(struct intel_crtc_state *crtc_state)
{
+ struct drm_device *dev = crtc_state->uapi.crtc->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_property *property = crtc_state->uapi.crtc->gamma_mode_property;
+ struct drm_property_enum *prop_enum;
+ u32 index = 0;
int ret;
ret = check_luts(crtc_state);
if (ret)
return ret;
+ if (DISPLAY_VER(dev_priv) >= 13) {
+ list_for_each_entry(prop_enum, &property->enum_list, head) {
+ if (prop_enum->value == crtc_state->uapi.gamma_mode) {
+ if (!strcmp(prop_enum->name,
+ "logarithmic gamma")) {
+ crtc_state->uapi.gamma_mode_type =
+ GAMMA_MODE_LOGARITHMIC_12BIT;
+ drm_dbg_kms(dev,
+ "logarithmic gamma enabled\n");
+ }
+ break;
+ }
+ index++;
+ }
+ }
+
crtc_state->gamma_mode = icl_gamma_mode(crtc_state);
crtc_state->csc_mode = icl_csc_mode(crtc_state);
@@ -2325,6 +2372,58 @@ static const struct drm_color_lut_range d13_logarithmic_gamma[] = {
},
};
+static void
+d13_program_logarithmic_gamma_lut(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
+ const u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ const struct drm_color_lut *lut;
+ enum pipe pipe = crtc->pipe;
+ u32 i;
+
+ if (!blob || !blob->data)
+ return;
+
+ lut = blob->data;
+ intel_dsb_reg_write(crtc_state, PREC_PAL_INDEX(pipe),
+ PAL_PREC_AUTO_INCREMENT);
+
+ for (i = 0; i < lut_size - 3; i++) {
+ intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
+ ilk_lut_12p4_ldw(&lut[i]));
+ intel_dsb_indexed_reg_write(crtc_state, PREC_PAL_DATA(pipe),
+ ilk_lut_12p4_udw(&lut[i]));
+ }
+
+ icl_load_gcmax(crtc_state, &lut[i]);
+ ivb_load_lut_ext_max(crtc_state);
+}
+
+static void d13_load_luts(const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (crtc_state->hw.degamma_lut)
+ glk_load_degamma_lut(crtc_state);
+
+ switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
+ case GAMMA_MODE_MODE_8BIT:
+ ilk_load_lut_8(crtc, gamma_lut);
+ break;
+ case GAMMA_MODE_MODE_12BIT_LOGARITHMIC:
+ d13_program_logarithmic_gamma_lut(crtc_state);
+ break;
+ default:
+ bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
+ ivb_load_lut_ext_max(crtc_state);
+ }
+
+ intel_dsb_commit(crtc_state);
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2376,7 +2475,9 @@ void intel_color_init(struct intel_crtc *crtc)
else
dev_priv->display.color_commit = ilk_color_commit;
- if (DISPLAY_VER(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 13) {
+ dev_priv->display.load_luts = d13_load_luts;
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
dev_priv->display.read_luts = icl_read_luts;
} else if (DISPLAY_VER(dev_priv) == 10) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24307c49085f..957f97edf035 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7749,6 +7749,7 @@ enum {
#define GAMMA_MODE_MODE_12BIT (2 << 0)
#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
+#define GAMMA_MODE_MODE_12BIT_LOGARITHMIC (3 << 0) /* D13+ + */
/* DMC */
#define DMC_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index b1eead03ebe8..5a594f134a81 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -269,6 +269,9 @@ struct drm_crtc_state {
*/
u32 gamma_mode;
+ /** Gamma mode type programmed on the pipe */
+ u32 gamma_mode_type;
+
/**
* @degamma_lut:
*
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 4/9] drm/i915/xelpd: Attach gamma mode property
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
@ 2021-06-01 10:41 ` Uma Shankar
-1 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Uma Shankar, bhanuprakash.modem
Attach the gamma mode property to allow userspace set the gamma mode
and provide the luts for the same.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 12cacd3aeead..cae96fbec1a7 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2458,6 +2458,7 @@ void intel_color_init(struct intel_crtc *crtc)
"logarithmic gamma",
d13_logarithmic_gamma,
sizeof(d13_logarithmic_gamma));
+ drm_crtc_attach_gamma_mode_property(&crtc->base);
} else if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.color_check = icl_color_check;
} else if (DISPLAY_VER(dev_priv) >= 10) {
--
2.26.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH 4/9] drm/i915/xelpd: Attach gamma mode property
@ 2021-06-01 10:41 ` Uma Shankar
0 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
Attach the gamma mode property to allow userspace set the gamma mode
and provide the luts for the same.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 12cacd3aeead..cae96fbec1a7 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2458,6 +2458,7 @@ void intel_color_init(struct intel_crtc *crtc)
"logarithmic gamma",
d13_logarithmic_gamma,
sizeof(d13_logarithmic_gamma));
+ drm_crtc_attach_gamma_mode_property(&crtc->base);
} else if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.color_check = icl_color_check;
} else if (DISPLAY_VER(dev_priv) >= 10) {
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 5/9] drm: Add Client Cap for advance gamma mode
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
@ 2021-06-01 10:41 ` Uma Shankar
-1 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Uma Shankar, bhanuprakash.modem
Introduced a client cap for advance cap mode capability. Userspace
should set this to get to be able to use the new gamma_mode property.
If this is not set, driver will work in legacy mode.
Note: This is suggested by Ville and based on his idea, the new
gamma mode handling is designed.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/drm_atomic_uapi.c | 3 +++
drivers/gpu/drm/drm_ioctl.c | 5 +++++
include/drm/drm_atomic.h | 1 +
include/drm/drm_crtc.h | 8 ++++++++
include/drm/drm_file.h | 8 ++++++++
include/uapi/drm/drm.h | 8 ++++++++
6 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
index a5470a0ebbe6..7ee35bc14455 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -1036,6 +1036,8 @@ int drm_atomic_set_property(struct drm_atomic_state *state,
break;
}
+ crtc_state->advance_gamma_mode_active =
+ state->advance_gamma_mode_active;
ret = drm_atomic_crtc_set_property(crtc,
crtc_state, prop, prop_value);
break;
@@ -1372,6 +1374,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
state->acquire_ctx = &ctx;
state->allow_modeset = !!(arg->flags & DRM_MODE_ATOMIC_ALLOW_MODESET);
+ state->advance_gamma_mode_active = file_priv->advance_gamma_mode_active;
retry:
copied_objs = 0;
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 53d314103a37..d51f72213882 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -361,6 +361,11 @@ drm_setclientcap(struct drm_device *dev, void *data, struct drm_file *file_priv)
return -EINVAL;
file_priv->writeback_connectors = req->value;
break;
+ case DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES:
+ if (req->value > 1)
+ return -EINVAL;
+ file_priv->advance_gamma_mode_active = req->value;
+ break;
default:
return -EINVAL;
}
diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
index ac5a28eff2c8..5a398a249c80 100644
--- a/include/drm/drm_atomic.h
+++ b/include/drm/drm_atomic.h
@@ -379,6 +379,7 @@ struct drm_atomic_state {
* states.
*/
bool duplicated : 1;
+ bool advance_gamma_mode_active : 1;
struct __drm_planes_state *planes;
struct __drm_crtcs_state *crtcs;
int num_connector;
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 5a594f134a81..f4339fbad086 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -170,6 +170,11 @@ struct drm_crtc_state {
*/
bool color_mgmt_changed : 1;
+ /**
+ * This is to indicate advance gamma mode support
+ */
+ bool advance_gamma_mode_active : 1;
+
/**
* @no_vblank:
*
@@ -1036,6 +1041,9 @@ struct drm_crtc {
*/
bool enabled;
+ /** To handle advance gamma mode support */
+ bool advance_gamma_mode_active : 1;
+
/**
* @mode:
*
diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h
index b81b3bfb08c8..4af3e1a2a158 100644
--- a/include/drm/drm_file.h
+++ b/include/drm/drm_file.h
@@ -201,6 +201,14 @@ struct drm_file {
*/
bool writeback_connectors;
+ /**
+ * This is to enable advance gamma modes using
+ * gamma_mode property
+ *
+ * True if client understands advance gamma
+ */
+ bool advance_gamma_mode_active : 1;
+
/**
* @was_master:
*
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 67b94bc3c885..661efdf0c969 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -816,6 +816,14 @@ struct drm_get_cap {
*/
#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
+/**
+ * Add support for advance gamma mode UAPI
+ * If set to 1, DRM will enable advance gamma mode
+ * UAPI to process the gamma mode based on extended
+ * range and segments.
+ */
+#define DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES 6
+
/* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
struct drm_set_client_cap {
__u64 capability;
--
2.26.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH 5/9] drm: Add Client Cap for advance gamma mode
@ 2021-06-01 10:41 ` Uma Shankar
0 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
Introduced a client cap for advance cap mode capability. Userspace
should set this to get to be able to use the new gamma_mode property.
If this is not set, driver will work in legacy mode.
Note: This is suggested by Ville and based on his idea, the new
gamma mode handling is designed.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/drm_atomic_uapi.c | 3 +++
drivers/gpu/drm/drm_ioctl.c | 5 +++++
include/drm/drm_atomic.h | 1 +
include/drm/drm_crtc.h | 8 ++++++++
include/drm/drm_file.h | 8 ++++++++
include/uapi/drm/drm.h | 8 ++++++++
6 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
index a5470a0ebbe6..7ee35bc14455 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -1036,6 +1036,8 @@ int drm_atomic_set_property(struct drm_atomic_state *state,
break;
}
+ crtc_state->advance_gamma_mode_active =
+ state->advance_gamma_mode_active;
ret = drm_atomic_crtc_set_property(crtc,
crtc_state, prop, prop_value);
break;
@@ -1372,6 +1374,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
state->acquire_ctx = &ctx;
state->allow_modeset = !!(arg->flags & DRM_MODE_ATOMIC_ALLOW_MODESET);
+ state->advance_gamma_mode_active = file_priv->advance_gamma_mode_active;
retry:
copied_objs = 0;
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 53d314103a37..d51f72213882 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -361,6 +361,11 @@ drm_setclientcap(struct drm_device *dev, void *data, struct drm_file *file_priv)
return -EINVAL;
file_priv->writeback_connectors = req->value;
break;
+ case DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES:
+ if (req->value > 1)
+ return -EINVAL;
+ file_priv->advance_gamma_mode_active = req->value;
+ break;
default:
return -EINVAL;
}
diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
index ac5a28eff2c8..5a398a249c80 100644
--- a/include/drm/drm_atomic.h
+++ b/include/drm/drm_atomic.h
@@ -379,6 +379,7 @@ struct drm_atomic_state {
* states.
*/
bool duplicated : 1;
+ bool advance_gamma_mode_active : 1;
struct __drm_planes_state *planes;
struct __drm_crtcs_state *crtcs;
int num_connector;
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 5a594f134a81..f4339fbad086 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -170,6 +170,11 @@ struct drm_crtc_state {
*/
bool color_mgmt_changed : 1;
+ /**
+ * This is to indicate advance gamma mode support
+ */
+ bool advance_gamma_mode_active : 1;
+
/**
* @no_vblank:
*
@@ -1036,6 +1041,9 @@ struct drm_crtc {
*/
bool enabled;
+ /** To handle advance gamma mode support */
+ bool advance_gamma_mode_active : 1;
+
/**
* @mode:
*
diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h
index b81b3bfb08c8..4af3e1a2a158 100644
--- a/include/drm/drm_file.h
+++ b/include/drm/drm_file.h
@@ -201,6 +201,14 @@ struct drm_file {
*/
bool writeback_connectors;
+ /**
+ * This is to enable advance gamma modes using
+ * gamma_mode property
+ *
+ * True if client understands advance gamma
+ */
+ bool advance_gamma_mode_active : 1;
+
/**
* @was_master:
*
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 67b94bc3c885..661efdf0c969 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -816,6 +816,14 @@ struct drm_get_cap {
*/
#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
+/**
+ * Add support for advance gamma mode UAPI
+ * If set to 1, DRM will enable advance gamma mode
+ * UAPI to process the gamma mode based on extended
+ * range and segments.
+ */
+#define DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES 6
+
/* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
struct drm_set_client_cap {
__u64 capability;
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread* Re: [PATCH 5/9] drm: Add Client Cap for advance gamma mode
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
(?)
@ 2021-06-02 2:53 ` kernel test robot
-1 siblings, 0 replies; 48+ messages in thread
From: kernel test robot @ 2021-06-02 2:53 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, dri-devel
Cc: Uma Shankar, kbuild-all, bhanuprakash.modem
Hi Uma,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master v5.13-rc4 next-20210601]
[cannot apply to drm/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Uma-Shankar/Enhance-pipe-color-support-for-multi-segmented-luts/20210601-180720
base: git://anongit.freedesktop.org/drm-intel for-linux-next
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce:
cd tools/perf && ./check-headers.sh
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
perfheadercheck warnings: (new ones prefixed by >>)
Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 819> /**
>> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 820> * Add support for advance gamma mode UAPI
>> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 821> * If set to 1, DRM will enable advance gamma mode
>> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 822> * UAPI to process the gamma mode based on extended
>> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 823> * range and segments.
Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 824> */
>> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 825> #define DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES 6
Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 826>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 5/9] drm: Add Client Cap for advance gamma mode
@ 2021-06-02 2:53 ` kernel test robot
0 siblings, 0 replies; 48+ messages in thread
From: kernel test robot @ 2021-06-02 2:53 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 2309 bytes --]
Hi Uma,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master v5.13-rc4 next-20210601]
[cannot apply to drm/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Uma-Shankar/Enhance-pipe-color-support-for-multi-segmented-luts/20210601-180720
base: git://anongit.freedesktop.org/drm-intel for-linux-next
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce:
cd tools/perf && ./check-headers.sh
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
perfheadercheck warnings: (new ones prefixed by >>)
Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 819> /**
>> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 820> * Add support for advance gamma mode UAPI
>> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 821> * If set to 1, DRM will enable advance gamma mode
>> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 822> * UAPI to process the gamma mode based on extended
>> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 823> * range and segments.
Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 824> */
>> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 825> #define DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES 6
Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 826>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 5/9] drm: Add Client Cap for advance gamma mode
@ 2021-06-02 2:53 ` kernel test robot
0 siblings, 0 replies; 48+ messages in thread
From: kernel test robot @ 2021-06-02 2:53 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, dri-devel; +Cc: kbuild-all
Hi Uma,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master v5.13-rc4 next-20210601]
[cannot apply to drm/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Uma-Shankar/Enhance-pipe-color-support-for-multi-segmented-luts/20210601-180720
base: git://anongit.freedesktop.org/drm-intel for-linux-next
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce:
cd tools/perf && ./check-headers.sh
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
perfheadercheck warnings: (new ones prefixed by >>)
Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 819> /**
>> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 820> * Add support for advance gamma mode UAPI
>> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 821> * If set to 1, DRM will enable advance gamma mode
>> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 822> * UAPI to process the gamma mode based on extended
>> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 823> * range and segments.
Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 824> */
>> Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 825> #define DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES 6
Warning: Kernel ABI header at 'tools/include/uapi/drm/drm.h' differs from latest version at 'include/uapi/drm/drm.h': 826>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 5/9] drm: Add Client Cap for advance gamma mode
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
@ 2021-06-02 9:03 ` Pekka Paalanen
-1 siblings, 0 replies; 48+ messages in thread
From: Pekka Paalanen @ 2021-06-02 9:03 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, dri-devel, bhanuprakash.modem
[-- Attachment #1: Type: text/plain, Size: 4642 bytes --]
On Tue, 1 Jun 2021 16:11:31 +0530
Uma Shankar <uma.shankar@intel.com> wrote:
> Introduced a client cap for advance cap mode capability. Userspace
Typo: "cap mode" should be "gamma mode"?
> should set this to get to be able to use the new gamma_mode property.
>
> If this is not set, driver will work in legacy mode.
>
> Note: This is suggested by Ville and based on his idea, the new
> gamma mode handling is designed.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/drm_atomic_uapi.c | 3 +++
> drivers/gpu/drm/drm_ioctl.c | 5 +++++
> include/drm/drm_atomic.h | 1 +
> include/drm/drm_crtc.h | 8 ++++++++
> include/drm/drm_file.h | 8 ++++++++
> include/uapi/drm/drm.h | 8 ++++++++
> 6 files changed, 33 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
> index a5470a0ebbe6..7ee35bc14455 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -1036,6 +1036,8 @@ int drm_atomic_set_property(struct drm_atomic_state *state,
> break;
> }
>
> + crtc_state->advance_gamma_mode_active =
> + state->advance_gamma_mode_active;
> ret = drm_atomic_crtc_set_property(crtc,
> crtc_state, prop, prop_value);
> break;
> @@ -1372,6 +1374,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
> drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
> state->acquire_ctx = &ctx;
> state->allow_modeset = !!(arg->flags & DRM_MODE_ATOMIC_ALLOW_MODESET);
> + state->advance_gamma_mode_active = file_priv->advance_gamma_mode_active;
>
> retry:
> copied_objs = 0;
> diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
> index 53d314103a37..d51f72213882 100644
> --- a/drivers/gpu/drm/drm_ioctl.c
> +++ b/drivers/gpu/drm/drm_ioctl.c
> @@ -361,6 +361,11 @@ drm_setclientcap(struct drm_device *dev, void *data, struct drm_file *file_priv)
> return -EINVAL;
> file_priv->writeback_connectors = req->value;
> break;
> + case DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES:
> + if (req->value > 1)
> + return -EINVAL;
> + file_priv->advance_gamma_mode_active = req->value;
> + break;
> default:
> return -EINVAL;
> }
> diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
> index ac5a28eff2c8..5a398a249c80 100644
> --- a/include/drm/drm_atomic.h
> +++ b/include/drm/drm_atomic.h
> @@ -379,6 +379,7 @@ struct drm_atomic_state {
> * states.
> */
> bool duplicated : 1;
> + bool advance_gamma_mode_active : 1;
"advance" is a verb. Did you mean "advanced"?
> struct __drm_planes_state *planes;
> struct __drm_crtcs_state *crtcs;
> int num_connector;
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index 5a594f134a81..f4339fbad086 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -170,6 +170,11 @@ struct drm_crtc_state {
> */
> bool color_mgmt_changed : 1;
>
> + /**
> + * This is to indicate advance gamma mode support
> + */
> + bool advance_gamma_mode_active : 1;
Same here.
> +
> /**
> * @no_vblank:
> *
> @@ -1036,6 +1041,9 @@ struct drm_crtc {
> */
> bool enabled;
>
> + /** To handle advance gamma mode support */
> + bool advance_gamma_mode_active : 1;
Same here.
> +
> /**
> * @mode:
> *
> diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h
> index b81b3bfb08c8..4af3e1a2a158 100644
> --- a/include/drm/drm_file.h
> +++ b/include/drm/drm_file.h
> @@ -201,6 +201,14 @@ struct drm_file {
> */
> bool writeback_connectors;
>
> + /**
> + * This is to enable advance gamma modes using
> + * gamma_mode property
> + *
> + * True if client understands advance gamma
> + */
> + bool advance_gamma_mode_active : 1;
Same here.
> +
> /**
> * @was_master:
> *
> diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
> index 67b94bc3c885..661efdf0c969 100644
> --- a/include/uapi/drm/drm.h
> +++ b/include/uapi/drm/drm.h
> @@ -816,6 +816,14 @@ struct drm_get_cap {
> */
> #define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
>
> +/**
> + * Add support for advance gamma mode UAPI
> + * If set to 1, DRM will enable advance gamma mode
> + * UAPI to process the gamma mode based on extended
> + * range and segments.
> + */
> +#define DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES 6
Same here.
> +
> /* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
> struct drm_set_client_cap {
> __u64 capability;
Thanks,
pq
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^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH 5/9] drm: Add Client Cap for advance gamma mode
@ 2021-06-02 9:03 ` Pekka Paalanen
0 siblings, 0 replies; 48+ messages in thread
From: Pekka Paalanen @ 2021-06-02 9:03 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 4642 bytes --]
On Tue, 1 Jun 2021 16:11:31 +0530
Uma Shankar <uma.shankar@intel.com> wrote:
> Introduced a client cap for advance cap mode capability. Userspace
Typo: "cap mode" should be "gamma mode"?
> should set this to get to be able to use the new gamma_mode property.
>
> If this is not set, driver will work in legacy mode.
>
> Note: This is suggested by Ville and based on his idea, the new
> gamma mode handling is designed.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/drm_atomic_uapi.c | 3 +++
> drivers/gpu/drm/drm_ioctl.c | 5 +++++
> include/drm/drm_atomic.h | 1 +
> include/drm/drm_crtc.h | 8 ++++++++
> include/drm/drm_file.h | 8 ++++++++
> include/uapi/drm/drm.h | 8 ++++++++
> 6 files changed, 33 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
> index a5470a0ebbe6..7ee35bc14455 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -1036,6 +1036,8 @@ int drm_atomic_set_property(struct drm_atomic_state *state,
> break;
> }
>
> + crtc_state->advance_gamma_mode_active =
> + state->advance_gamma_mode_active;
> ret = drm_atomic_crtc_set_property(crtc,
> crtc_state, prop, prop_value);
> break;
> @@ -1372,6 +1374,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
> drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
> state->acquire_ctx = &ctx;
> state->allow_modeset = !!(arg->flags & DRM_MODE_ATOMIC_ALLOW_MODESET);
> + state->advance_gamma_mode_active = file_priv->advance_gamma_mode_active;
>
> retry:
> copied_objs = 0;
> diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
> index 53d314103a37..d51f72213882 100644
> --- a/drivers/gpu/drm/drm_ioctl.c
> +++ b/drivers/gpu/drm/drm_ioctl.c
> @@ -361,6 +361,11 @@ drm_setclientcap(struct drm_device *dev, void *data, struct drm_file *file_priv)
> return -EINVAL;
> file_priv->writeback_connectors = req->value;
> break;
> + case DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES:
> + if (req->value > 1)
> + return -EINVAL;
> + file_priv->advance_gamma_mode_active = req->value;
> + break;
> default:
> return -EINVAL;
> }
> diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
> index ac5a28eff2c8..5a398a249c80 100644
> --- a/include/drm/drm_atomic.h
> +++ b/include/drm/drm_atomic.h
> @@ -379,6 +379,7 @@ struct drm_atomic_state {
> * states.
> */
> bool duplicated : 1;
> + bool advance_gamma_mode_active : 1;
"advance" is a verb. Did you mean "advanced"?
> struct __drm_planes_state *planes;
> struct __drm_crtcs_state *crtcs;
> int num_connector;
> diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
> index 5a594f134a81..f4339fbad086 100644
> --- a/include/drm/drm_crtc.h
> +++ b/include/drm/drm_crtc.h
> @@ -170,6 +170,11 @@ struct drm_crtc_state {
> */
> bool color_mgmt_changed : 1;
>
> + /**
> + * This is to indicate advance gamma mode support
> + */
> + bool advance_gamma_mode_active : 1;
Same here.
> +
> /**
> * @no_vblank:
> *
> @@ -1036,6 +1041,9 @@ struct drm_crtc {
> */
> bool enabled;
>
> + /** To handle advance gamma mode support */
> + bool advance_gamma_mode_active : 1;
Same here.
> +
> /**
> * @mode:
> *
> diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h
> index b81b3bfb08c8..4af3e1a2a158 100644
> --- a/include/drm/drm_file.h
> +++ b/include/drm/drm_file.h
> @@ -201,6 +201,14 @@ struct drm_file {
> */
> bool writeback_connectors;
>
> + /**
> + * This is to enable advance gamma modes using
> + * gamma_mode property
> + *
> + * True if client understands advance gamma
> + */
> + bool advance_gamma_mode_active : 1;
Same here.
> +
> /**
> * @was_master:
> *
> diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
> index 67b94bc3c885..661efdf0c969 100644
> --- a/include/uapi/drm/drm.h
> +++ b/include/uapi/drm/drm.h
> @@ -816,6 +816,14 @@ struct drm_get_cap {
> */
> #define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
>
> +/**
> + * Add support for advance gamma mode UAPI
> + * If set to 1, DRM will enable advance gamma mode
> + * UAPI to process the gamma mode based on extended
> + * range and segments.
> + */
> +#define DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES 6
Same here.
> +
> /* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
> struct drm_set_client_cap {
> __u64 capability;
Thanks,
pq
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread* RE: [PATCH 5/9] drm: Add Client Cap for advance gamma mode
2021-06-02 9:03 ` [Intel-gfx] " Pekka Paalanen
@ 2021-06-02 20:08 ` Shankar, Uma
-1 siblings, 0 replies; 48+ messages in thread
From: Shankar, Uma @ 2021-06-02 20:08 UTC (permalink / raw)
To: Pekka Paalanen; +Cc: intel-gfx, dri-devel, Modem, Bhanuprakash
> -----Original Message-----
> From: Pekka Paalanen <ppaalanen@gmail.com>
> Sent: Wednesday, June 2, 2021 2:33 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Modem,
> Bhanuprakash <bhanuprakash.modem@intel.com>
> Subject: Re: [PATCH 5/9] drm: Add Client Cap for advance gamma mode
>
> On Tue, 1 Jun 2021 16:11:31 +0530
> Uma Shankar <uma.shankar@intel.com> wrote:
>
> > Introduced a client cap for advance cap mode capability. Userspace
>
> Typo: "cap mode" should be "gamma mode"?
Yeah, will fix this.
> > should set this to get to be able to use the new gamma_mode property.
> >
> > If this is not set, driver will work in legacy mode.
> >
> > Note: This is suggested by Ville and based on his idea, the new gamma
> > mode handling is designed.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/drm_atomic_uapi.c | 3 +++
> > drivers/gpu/drm/drm_ioctl.c | 5 +++++
> > include/drm/drm_atomic.h | 1 +
> > include/drm/drm_crtc.h | 8 ++++++++
> > include/drm/drm_file.h | 8 ++++++++
> > include/uapi/drm/drm.h | 8 ++++++++
> > 6 files changed, 33 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> > b/drivers/gpu/drm/drm_atomic_uapi.c
> > index a5470a0ebbe6..7ee35bc14455 100644
> > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > @@ -1036,6 +1036,8 @@ int drm_atomic_set_property(struct drm_atomic_state
> *state,
> > break;
> > }
> >
> > + crtc_state->advance_gamma_mode_active =
> > + state->advance_gamma_mode_active;
> > ret = drm_atomic_crtc_set_property(crtc,
> > crtc_state, prop, prop_value);
> > break;
> > @@ -1372,6 +1374,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
> > drm_modeset_acquire_init(&ctx,
> DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
> > state->acquire_ctx = &ctx;
> > state->allow_modeset = !!(arg->flags &
> > DRM_MODE_ATOMIC_ALLOW_MODESET);
> > + state->advance_gamma_mode_active =
> > +file_priv->advance_gamma_mode_active;
> >
> > retry:
> > copied_objs = 0;
> > diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
> > index 53d314103a37..d51f72213882 100644
> > --- a/drivers/gpu/drm/drm_ioctl.c
> > +++ b/drivers/gpu/drm/drm_ioctl.c
> > @@ -361,6 +361,11 @@ drm_setclientcap(struct drm_device *dev, void *data,
> struct drm_file *file_priv)
> > return -EINVAL;
> > file_priv->writeback_connectors = req->value;
> > break;
> > + case DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES:
> > + if (req->value > 1)
> > + return -EINVAL;
> > + file_priv->advance_gamma_mode_active = req->value;
> > + break;
> > default:
> > return -EINVAL;
> > }
> > diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index
> > ac5a28eff2c8..5a398a249c80 100644
> > --- a/include/drm/drm_atomic.h
> > +++ b/include/drm/drm_atomic.h
> > @@ -379,6 +379,7 @@ struct drm_atomic_state {
> > * states.
> > */
> > bool duplicated : 1;
> > + bool advance_gamma_mode_active : 1;
>
> "advance" is a verb. Did you mean "advanced"?
Right, will rename it.
>
> > struct __drm_planes_state *planes;
> > struct __drm_crtcs_state *crtcs;
> > int num_connector;
> > diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index
> > 5a594f134a81..f4339fbad086 100644
> > --- a/include/drm/drm_crtc.h
> > +++ b/include/drm/drm_crtc.h
> > @@ -170,6 +170,11 @@ struct drm_crtc_state {
> > */
> > bool color_mgmt_changed : 1;
> >
> > + /**
> > + * This is to indicate advance gamma mode support
> > + */
> > + bool advance_gamma_mode_active : 1;
>
> Same here.
>
> > +
> > /**
> > * @no_vblank:
> > *
> > @@ -1036,6 +1041,9 @@ struct drm_crtc {
> > */
> > bool enabled;
> >
> > + /** To handle advance gamma mode support */
> > + bool advance_gamma_mode_active : 1;
>
> Same here.
>
> > +
> > /**
> > * @mode:
> > *
> > diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h index
> > b81b3bfb08c8..4af3e1a2a158 100644
> > --- a/include/drm/drm_file.h
> > +++ b/include/drm/drm_file.h
> > @@ -201,6 +201,14 @@ struct drm_file {
> > */
> > bool writeback_connectors;
> >
> > + /**
> > + * This is to enable advance gamma modes using
> > + * gamma_mode property
> > + *
> > + * True if client understands advance gamma
> > + */
> > + bool advance_gamma_mode_active : 1;
>
> Same here.
>
> > +
> > /**
> > * @was_master:
> > *
> > diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index
> > 67b94bc3c885..661efdf0c969 100644
> > --- a/include/uapi/drm/drm.h
> > +++ b/include/uapi/drm/drm.h
> > @@ -816,6 +816,14 @@ struct drm_get_cap {
> > */
> > #define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
> >
> > +/**
> > + * Add support for advance gamma mode UAPI
> > + * If set to 1, DRM will enable advance gamma mode
> > + * UAPI to process the gamma mode based on extended
> > + * range and segments.
> > + */
> > +#define DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES 6
>
> Same here.
>
> > +
> > /* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ struct
> > drm_set_client_cap {
> > __u64 capability;
>
>
> Thanks,
> pq
^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [Intel-gfx] [PATCH 5/9] drm: Add Client Cap for advance gamma mode
@ 2021-06-02 20:08 ` Shankar, Uma
0 siblings, 0 replies; 48+ messages in thread
From: Shankar, Uma @ 2021-06-02 20:08 UTC (permalink / raw)
To: Pekka Paalanen; +Cc: intel-gfx, dri-devel
> -----Original Message-----
> From: Pekka Paalanen <ppaalanen@gmail.com>
> Sent: Wednesday, June 2, 2021 2:33 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Modem,
> Bhanuprakash <bhanuprakash.modem@intel.com>
> Subject: Re: [PATCH 5/9] drm: Add Client Cap for advance gamma mode
>
> On Tue, 1 Jun 2021 16:11:31 +0530
> Uma Shankar <uma.shankar@intel.com> wrote:
>
> > Introduced a client cap for advance cap mode capability. Userspace
>
> Typo: "cap mode" should be "gamma mode"?
Yeah, will fix this.
> > should set this to get to be able to use the new gamma_mode property.
> >
> > If this is not set, driver will work in legacy mode.
> >
> > Note: This is suggested by Ville and based on his idea, the new gamma
> > mode handling is designed.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/drm_atomic_uapi.c | 3 +++
> > drivers/gpu/drm/drm_ioctl.c | 5 +++++
> > include/drm/drm_atomic.h | 1 +
> > include/drm/drm_crtc.h | 8 ++++++++
> > include/drm/drm_file.h | 8 ++++++++
> > include/uapi/drm/drm.h | 8 ++++++++
> > 6 files changed, 33 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> > b/drivers/gpu/drm/drm_atomic_uapi.c
> > index a5470a0ebbe6..7ee35bc14455 100644
> > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > @@ -1036,6 +1036,8 @@ int drm_atomic_set_property(struct drm_atomic_state
> *state,
> > break;
> > }
> >
> > + crtc_state->advance_gamma_mode_active =
> > + state->advance_gamma_mode_active;
> > ret = drm_atomic_crtc_set_property(crtc,
> > crtc_state, prop, prop_value);
> > break;
> > @@ -1372,6 +1374,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
> > drm_modeset_acquire_init(&ctx,
> DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
> > state->acquire_ctx = &ctx;
> > state->allow_modeset = !!(arg->flags &
> > DRM_MODE_ATOMIC_ALLOW_MODESET);
> > + state->advance_gamma_mode_active =
> > +file_priv->advance_gamma_mode_active;
> >
> > retry:
> > copied_objs = 0;
> > diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
> > index 53d314103a37..d51f72213882 100644
> > --- a/drivers/gpu/drm/drm_ioctl.c
> > +++ b/drivers/gpu/drm/drm_ioctl.c
> > @@ -361,6 +361,11 @@ drm_setclientcap(struct drm_device *dev, void *data,
> struct drm_file *file_priv)
> > return -EINVAL;
> > file_priv->writeback_connectors = req->value;
> > break;
> > + case DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES:
> > + if (req->value > 1)
> > + return -EINVAL;
> > + file_priv->advance_gamma_mode_active = req->value;
> > + break;
> > default:
> > return -EINVAL;
> > }
> > diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index
> > ac5a28eff2c8..5a398a249c80 100644
> > --- a/include/drm/drm_atomic.h
> > +++ b/include/drm/drm_atomic.h
> > @@ -379,6 +379,7 @@ struct drm_atomic_state {
> > * states.
> > */
> > bool duplicated : 1;
> > + bool advance_gamma_mode_active : 1;
>
> "advance" is a verb. Did you mean "advanced"?
Right, will rename it.
>
> > struct __drm_planes_state *planes;
> > struct __drm_crtcs_state *crtcs;
> > int num_connector;
> > diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index
> > 5a594f134a81..f4339fbad086 100644
> > --- a/include/drm/drm_crtc.h
> > +++ b/include/drm/drm_crtc.h
> > @@ -170,6 +170,11 @@ struct drm_crtc_state {
> > */
> > bool color_mgmt_changed : 1;
> >
> > + /**
> > + * This is to indicate advance gamma mode support
> > + */
> > + bool advance_gamma_mode_active : 1;
>
> Same here.
>
> > +
> > /**
> > * @no_vblank:
> > *
> > @@ -1036,6 +1041,9 @@ struct drm_crtc {
> > */
> > bool enabled;
> >
> > + /** To handle advance gamma mode support */
> > + bool advance_gamma_mode_active : 1;
>
> Same here.
>
> > +
> > /**
> > * @mode:
> > *
> > diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h index
> > b81b3bfb08c8..4af3e1a2a158 100644
> > --- a/include/drm/drm_file.h
> > +++ b/include/drm/drm_file.h
> > @@ -201,6 +201,14 @@ struct drm_file {
> > */
> > bool writeback_connectors;
> >
> > + /**
> > + * This is to enable advance gamma modes using
> > + * gamma_mode property
> > + *
> > + * True if client understands advance gamma
> > + */
> > + bool advance_gamma_mode_active : 1;
>
> Same here.
>
> > +
> > /**
> > * @was_master:
> > *
> > diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index
> > 67b94bc3c885..661efdf0c969 100644
> > --- a/include/uapi/drm/drm.h
> > +++ b/include/uapi/drm/drm.h
> > @@ -816,6 +816,14 @@ struct drm_get_cap {
> > */
> > #define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
> >
> > +/**
> > + * Add support for advance gamma mode UAPI
> > + * If set to 1, DRM will enable advance gamma mode
> > + * UAPI to process the gamma mode based on extended
> > + * range and segments.
> > + */
> > +#define DRM_CLIENT_CAP_ADVANCE_GAMMA_MODES 6
>
> Same here.
>
> > +
> > /* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ struct
> > drm_set_client_cap {
> > __u64 capability;
>
>
> Thanks,
> pq
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 6/9] drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
@ 2021-06-01 10:41 ` Uma Shankar
-1 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Uma Shankar, bhanuprakash.modem
Only Enable Logarithmic Gamma if client caps for advance gamma mode
is enabled. Fallback to 10bit gamma in case its not supported.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index cae96fbec1a7..18b51b9cc2aa 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1606,13 +1606,17 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
gamma_mode |= POST_CSC_GAMMA_ENABLE;
if (!crtc_state->hw.gamma_lut ||
- crtc_state_is_legacy_gamma(crtc_state))
+ crtc_state_is_legacy_gamma(crtc_state)) {
gamma_mode |= GAMMA_MODE_MODE_8BIT;
- else if (crtc_state->uapi.gamma_mode_type ==
- GAMMA_MODE_LOGARITHMIC_12BIT)
- gamma_mode |= GAMMA_MODE_MODE_12BIT_LOGARITHMIC;
- else
+ } else if (crtc_state->uapi.gamma_mode_type ==
+ GAMMA_MODE_LOGARITHMIC_12BIT) {
+ if (crtc_state->uapi.advance_gamma_mode_active)
+ gamma_mode |= GAMMA_MODE_MODE_12BIT_LOGARITHMIC;
+ else
+ gamma_mode |= GAMMA_MODE_MODE_10BIT;
+ } else {
gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
+ }
return gamma_mode;
}
--
2.26.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH 6/9] drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode
@ 2021-06-01 10:41 ` Uma Shankar
0 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
Only Enable Logarithmic Gamma if client caps for advance gamma mode
is enabled. Fallback to 10bit gamma in case its not supported.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index cae96fbec1a7..18b51b9cc2aa 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1606,13 +1606,17 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state)
gamma_mode |= POST_CSC_GAMMA_ENABLE;
if (!crtc_state->hw.gamma_lut ||
- crtc_state_is_legacy_gamma(crtc_state))
+ crtc_state_is_legacy_gamma(crtc_state)) {
gamma_mode |= GAMMA_MODE_MODE_8BIT;
- else if (crtc_state->uapi.gamma_mode_type ==
- GAMMA_MODE_LOGARITHMIC_12BIT)
- gamma_mode |= GAMMA_MODE_MODE_12BIT_LOGARITHMIC;
- else
+ } else if (crtc_state->uapi.gamma_mode_type ==
+ GAMMA_MODE_LOGARITHMIC_12BIT) {
+ if (crtc_state->uapi.advance_gamma_mode_active)
+ gamma_mode |= GAMMA_MODE_MODE_12BIT_LOGARITHMIC;
+ else
+ gamma_mode |= GAMMA_MODE_MODE_10BIT;
+ } else {
gamma_mode |= GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED;
+ }
return gamma_mode;
}
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 7/9] drm/i915/xelpd: Enable Pipe Degamma
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
@ 2021-06-01 10:41 ` Uma Shankar
-1 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Uma Shankar, bhanuprakash.modem
Enable Pipe Degamma for XE_LPD. Extend the legacy implementation
to incorparate the extended lut size for XE_LPD.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 18b51b9cc2aa..a8b771f22880 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -829,6 +829,12 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
+ u32 extended_lut_size = 0;
+
+ if (DISPLAY_VER(dev_priv) >= 13)
+ extended_lut_size = 131;
+ else
+ extended_lut_size = 35;
/*
* When setting the auto-increment bit, the hardware seems to
@@ -841,8 +847,8 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
for (i = 0; i < lut_size; i++) {
/*
- * First 33 entries represent range from 0 to 1.0
- * 34th and 35th entry will represent extended range
+ * First lut_size entries represent range from 0 to 1.0
+ * 3 additional lut entries will represent extended range
* inputs 3.0 and 7.0 respectively, currently clamped
* at 1.0. Since the precision is 16bit, the user
* value can be directly filled to register.
@@ -858,7 +864,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
}
/* Clamp values > 1.0. */
- while (i++ < 35)
+ while (i++ < extended_lut_size)
intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
--
2.26.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH 7/9] drm/i915/xelpd: Enable Pipe Degamma
@ 2021-06-01 10:41 ` Uma Shankar
0 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
Enable Pipe Degamma for XE_LPD. Extend the legacy implementation
to incorparate the extended lut size for XE_LPD.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 18b51b9cc2aa..a8b771f22880 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -829,6 +829,12 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
+ u32 extended_lut_size = 0;
+
+ if (DISPLAY_VER(dev_priv) >= 13)
+ extended_lut_size = 131;
+ else
+ extended_lut_size = 35;
/*
* When setting the auto-increment bit, the hardware seems to
@@ -841,8 +847,8 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
for (i = 0; i < lut_size; i++) {
/*
- * First 33 entries represent range from 0 to 1.0
- * 34th and 35th entry will represent extended range
+ * First lut_size entries represent range from 0 to 1.0
+ * 3 additional lut entries will represent extended range
* inputs 3.0 and 7.0 respectively, currently clamped
* at 1.0. Since the precision is 16bit, the user
* value can be directly filled to register.
@@ -858,7 +864,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
}
/* Clamp values > 1.0. */
- while (i++ < 35)
+ while (i++ < extended_lut_size)
intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16);
intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0);
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 8/9] drm/i915/xelpd: Add Pipe Color Lut caps to platform config
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
@ 2021-06-01 10:41 ` Uma Shankar
-1 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Uma Shankar, bhanuprakash.modem
XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for
extended range. It has 511 entries for gamma with additional 2 entries
for extended range.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 97c98f4fb265..844d08e37ec5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -947,7 +947,8 @@ static const struct intel_device_info adl_s_info = {
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
.dbuf.size = 4096, \
- .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4)
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4), \
+ .color = { .degamma_lut_size = 128, .gamma_lut_size = 513 }
static const struct intel_device_info adl_p_info = {
GEN12_FEATURES,
--
2.26.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH 8/9] drm/i915/xelpd: Add Pipe Color Lut caps to platform config
@ 2021-06-01 10:41 ` Uma Shankar
0 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
XE_LPD has 128 Lut entries for Degamma, with additional 3 entries for
extended range. It has 511 entries for gamma with additional 2 entries
for extended range.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 97c98f4fb265..844d08e37ec5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -947,7 +947,8 @@ static const struct intel_device_info adl_s_info = {
.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
.dbuf.size = 4096, \
- .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4)
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4), \
+ .color = { .degamma_lut_size = 128, .gamma_lut_size = 513 }
static const struct intel_device_info adl_p_info = {
GEN12_FEATURES,
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 9/9] drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
@ 2021-06-01 10:41 ` Uma Shankar
-1 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Uma Shankar, bhanuprakash.modem
Enable support for Logarithmic gamma readout for XE_LPD.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 72 ++++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 6 ++
2 files changed, 78 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index a8b771f22880..1238fe05b358 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -486,6 +486,17 @@ static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw
REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
}
+static void d13_lut_logarithmic_pack(struct drm_color_lut *entry,
+ u32 ldw, u32 udw)
+{
+ entry->red = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_RED_UDW_MASK, udw) << 6 |
+ REG_FIELD_GET(PAL_PREC_LOGARITHMIC_RED_LDW_MASK, ldw);
+ entry->green = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_GREEN_UDW_MASK, udw) << 6 |
+ REG_FIELD_GET(PAL_PREC_LOGARITHMIC_GREEN_LDW_MASK, ldw);
+ entry->blue = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_BLUE_UDW_MASK, udw) << 6 |
+ REG_FIELD_GET(PAL_PREC_LOGARITHMIC_BLUE_LDW_MASK, ldw);
+}
+
static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -2434,6 +2445,66 @@ static void d13_load_luts(const struct intel_crtc_state *crtc_state)
intel_dsb_commit(crtc_state);
}
+static struct drm_property_blob *
+d13_read_lut_logarithmic(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *lut;
+ u32 gamma_max_val = 0xFFFF;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ lut = blob->data;
+
+ intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
+ PAL_PREC_AUTO_INCREMENT);
+
+ for (i = 0; i < lut_size - 3; i++) {
+ u32 ldw = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
+ u32 udw = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
+
+ d13_lut_logarithmic_pack(&lut[i], ldw, udw);
+ }
+
+ /* All the extended ranges are now limited to last value of 1.0 */
+ while (i < lut_size) {
+ lut[i].red = gamma_max_val;
+ lut[i].green = gamma_max_val;
+ lut[i].blue = gamma_max_val;
+ i++;
+ };
+
+ intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
+
+ return blob;
+}
+
+static void d13_read_luts(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
+ return;
+
+ switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
+ case GAMMA_MODE_MODE_8BIT:
+ crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
+ break;
+ case GAMMA_MODE_MODE_12BIT_LOGARITHMIC:
+ crtc_state->hw.gamma_lut = d13_read_lut_logarithmic(crtc);
+ break;
+ default:
+ crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
+ }
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2488,6 +2559,7 @@ void intel_color_init(struct intel_crtc *crtc)
if (DISPLAY_VER(dev_priv) >= 13) {
dev_priv->display.load_luts = d13_load_luts;
+ dev_priv->display.read_luts = d13_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
dev_priv->display.read_luts = icl_read_luts;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 957f97edf035..dc10b5e2ff3c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7750,6 +7750,12 @@ enum {
#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
#define GAMMA_MODE_MODE_12BIT_LOGARITHMIC (3 << 0) /* D13+ + */
+#define PAL_PREC_LOGARITHMIC_RED_LDW_MASK REG_GENMASK(29, 24)
+#define PAL_PREC_LOGARITHMIC_RED_UDW_MASK REG_GENMASK(29, 20)
+#define PAL_PREC_LOGARITHMIC_GREEN_LDW_MASK REG_GENMASK(19, 14)
+#define PAL_PREC_LOGARITHMIC_GREEN_UDW_MASK REG_GENMASK(19, 10)
+#define PAL_PREC_LOGARITHMIC_BLUE_LDW_MASK REG_GENMASK(9, 4)
+#define PAL_PREC_LOGARITHMIC_BLUE_UDW_MASK REG_GENMASK(9, 0)
/* DMC */
#define DMC_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
--
2.26.2
^ permalink raw reply related [flat|nested] 48+ messages in thread* [Intel-gfx] [PATCH 9/9] drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
@ 2021-06-01 10:41 ` Uma Shankar
0 siblings, 0 replies; 48+ messages in thread
From: Uma Shankar @ 2021-06-01 10:41 UTC (permalink / raw)
To: intel-gfx, dri-devel
Enable support for Logarithmic gamma readout for XE_LPD.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 72 ++++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 6 ++
2 files changed, 78 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index a8b771f22880..1238fe05b358 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -486,6 +486,17 @@ static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32 udw
REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
}
+static void d13_lut_logarithmic_pack(struct drm_color_lut *entry,
+ u32 ldw, u32 udw)
+{
+ entry->red = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_RED_UDW_MASK, udw) << 6 |
+ REG_FIELD_GET(PAL_PREC_LOGARITHMIC_RED_LDW_MASK, ldw);
+ entry->green = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_GREEN_UDW_MASK, udw) << 6 |
+ REG_FIELD_GET(PAL_PREC_LOGARITHMIC_GREEN_LDW_MASK, ldw);
+ entry->blue = REG_FIELD_GET(PAL_PREC_LOGARITHMIC_BLUE_UDW_MASK, udw) << 6 |
+ REG_FIELD_GET(PAL_PREC_LOGARITHMIC_BLUE_LDW_MASK, ldw);
+}
+
static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -2434,6 +2445,66 @@ static void d13_load_luts(const struct intel_crtc_state *crtc_state)
intel_dsb_commit(crtc_state);
}
+static struct drm_property_blob *
+d13_read_lut_logarithmic(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *lut;
+ u32 gamma_max_val = 0xFFFF;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ lut = blob->data;
+
+ intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
+ PAL_PREC_AUTO_INCREMENT);
+
+ for (i = 0; i < lut_size - 3; i++) {
+ u32 ldw = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
+ u32 udw = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
+
+ d13_lut_logarithmic_pack(&lut[i], ldw, udw);
+ }
+
+ /* All the extended ranges are now limited to last value of 1.0 */
+ while (i < lut_size) {
+ lut[i].red = gamma_max_val;
+ lut[i].green = gamma_max_val;
+ lut[i].blue = gamma_max_val;
+ i++;
+ };
+
+ intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
+
+ return blob;
+}
+
+static void d13_read_luts(struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
+ if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
+ return;
+
+ switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
+ case GAMMA_MODE_MODE_8BIT:
+ crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
+ break;
+ case GAMMA_MODE_MODE_12BIT_LOGARITHMIC:
+ crtc_state->hw.gamma_lut = d13_read_lut_logarithmic(crtc);
+ break;
+ default:
+ crtc_state->hw.gamma_lut = bdw_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
+ }
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2488,6 +2559,7 @@ void intel_color_init(struct intel_crtc *crtc)
if (DISPLAY_VER(dev_priv) >= 13) {
dev_priv->display.load_luts = d13_load_luts;
+ dev_priv->display.read_luts = d13_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
dev_priv->display.read_luts = icl_read_luts;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 957f97edf035..dc10b5e2ff3c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7750,6 +7750,12 @@ enum {
#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */
#define GAMMA_MODE_MODE_12BIT_LOGARITHMIC (3 << 0) /* D13+ + */
+#define PAL_PREC_LOGARITHMIC_RED_LDW_MASK REG_GENMASK(29, 24)
+#define PAL_PREC_LOGARITHMIC_RED_UDW_MASK REG_GENMASK(29, 20)
+#define PAL_PREC_LOGARITHMIC_GREEN_LDW_MASK REG_GENMASK(19, 14)
+#define PAL_PREC_LOGARITHMIC_GREEN_UDW_MASK REG_GENMASK(19, 10)
+#define PAL_PREC_LOGARITHMIC_BLUE_LDW_MASK REG_GENMASK(9, 4)
+#define PAL_PREC_LOGARITHMIC_BLUE_UDW_MASK REG_GENMASK(9, 0)
/* DMC */
#define DMC_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 48+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enhance pipe color support for multi segmented luts
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
` (9 preceding siblings ...)
(?)
@ 2021-06-01 12:47 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2021-06-01 12:47 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
== Series Details ==
Series: Enhance pipe color support for multi segmented luts
URL : https://patchwork.freedesktop.org/series/90821/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:316:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:293:16: error: incompatible types in comparison expression (different type sizes):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:293:16: unsigned long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:293:16: unsigned long long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:276:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:276:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:276:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:330:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:330:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:330:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.c:37:6: warning: symbol 'amdgpu_kms_compat_ioctl' was not declared. Should it be static?
+drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h:90:56: error: marked inline, but without a definition
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:312:49: error: static assertion failed: "amd_sriov_msg_vf2
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^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Enhance pipe color support for multi segmented luts
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
` (10 preceding siblings ...)
(?)
@ 2021-06-01 13:15 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2021-06-01 13:15 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4630 bytes --]
== Series Details ==
Series: Enhance pipe color support for multi segmented luts
URL : https://patchwork.freedesktop.org/series/90821/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10154 -> Patchwork_20248
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/index.html
Known issues
------------
Here are the changes found in Patchwork_20248 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][1] ([i915#3303]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][3] ([i915#1372]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
#### Warnings ####
* igt@runner@aborted:
- fi-cfl-8700k: [FAIL][5] ([i915#3363]) -> [FAIL][6] ([i915#2426] / [i915#3363])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cfl-8700k/igt@runner@aborted.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-cfl-8700k/igt@runner@aborted.html
- fi-glk-dsi: [FAIL][7] ([i915#2426] / [i915#3363] / [k.org#202321]) -> [FAIL][8] ([i915#3363] / [k.org#202321])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-glk-dsi/igt@runner@aborted.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-glk-dsi/igt@runner@aborted.html
- fi-kbl-soraka: [FAIL][9] ([i915#1436] / [i915#3363]) -> [FAIL][10] ([i915#1436] / [i915#2426] / [i915#3363])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-soraka/igt@runner@aborted.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-kbl-soraka/igt@runner@aborted.html
- fi-kbl-guc: [FAIL][11] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][12] ([i915#1436] / [i915#3363])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-kbl-guc/igt@runner@aborted.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-kbl-guc/igt@runner@aborted.html
- fi-cfl-guc: [FAIL][13] ([i915#2426] / [i915#3363]) -> [FAIL][14] ([i915#3363])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/fi-cfl-guc/igt@runner@aborted.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/fi-cfl-guc/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (47 -> 42)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10154 -> Patchwork_20248
CI-20190529: 20190529
CI_DRM_10154: 810010ed3d29e0500d452a90010a88a0879f2b45 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6097: f823d8ec14b34a6dd2c0804c684b07b0a50f7bb7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20248: 69e66620a121b94c53f9b381c048c32f45eb4fe2 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
69e66620a121 drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
6a09b3df0e61 drm/i915/xelpd: Add Pipe Color Lut caps to platform config
185822ca6347 drm/i915/xelpd: Enable Pipe Degamma
0a9c33e8f72b drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode
7709e4e8ae04 drm: Add Client Cap for advance gamma mode
0db66299eaaf drm/i915/xelpd: Attach gamma mode property
0abd23286aa0 drm/i915/xelpd: Add support for Logarithmic gamma mode
fbd5ad2e2de9 drm/i915/xelpd: Define color lut range structure
cbbd9a9e8e24 drm: Add gamma mode property
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for Enhance pipe color support for multi segmented luts
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
` (11 preceding siblings ...)
(?)
@ 2021-06-01 17:12 ` Patchwork
-1 siblings, 0 replies; 48+ messages in thread
From: Patchwork @ 2021-06-01 17:12 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
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== Series Details ==
Series: Enhance pipe color support for multi segmented luts
URL : https://patchwork.freedesktop.org/series/90821/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10154_full -> Patchwork_20248_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_20248_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-2x:
- shard-tglb: NOTRUN -> [SKIP][1] ([i915#1839])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@feature_discovery@display-2x.html
- shard-iclb: NOTRUN -> [SKIP][2] ([i915#1839])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@feature_discovery@display-2x.html
* igt@gem_create@create-clear:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#3160])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk9/igt@gem_create@create-clear.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-glk8/igt@gem_create@create-clear.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#198] / [i915#2910])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl9/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-apl3/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-apl3/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_ctx_persistence@engines-queued:
- shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-snb5/igt@gem_ctx_persistence@engines-queued.html
* igt@gem_ctx_ringsize@active@bcs0:
- shard-skl: [PASS][10] -> [INCOMPLETE][11] ([i915#3316])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl8/igt@gem_ctx_ringsize@active@bcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl10/igt@gem_ctx_ringsize@active@bcs0.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-iclb: [PASS][12] -> [TIMEOUT][13] ([i915#3070])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb6/igt@gem_eio@in-flight-contexts-10ms.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@unwedge-stress:
- shard-snb: NOTRUN -> [FAIL][14] ([i915#3354])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-snb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-tglb: NOTRUN -> [FAIL][15] ([i915#2842]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@gem_exec_fair@basic-none-vip@rcs0.html
- shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#2842]) +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-glk2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
- shard-tglb: [PASS][19] -> [FAIL][20] ([i915#2842])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-tglb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][21] -> [FAIL][22] ([i915#2849])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_whisper@basic-fds-forked:
- shard-glk: [PASS][23] -> [DMESG-WARN][24] ([i915#118] / [i915#95])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk9/igt@gem_exec_whisper@basic-fds-forked.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-glk4/igt@gem_exec_whisper@basic-fds-forked.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#2190])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-apl2/igt@gem_huc_copy@huc-copy.html
- shard-kbl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#2190])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-kbl3/igt@gem_huc_copy@huc-copy.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy:
- shard-skl: NOTRUN -> [INCOMPLETE][27] ([i915#198] / [i915#3468])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl5/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
- shard-iclb: NOTRUN -> [INCOMPLETE][28] ([i915#2910] / [i915#3468])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb1/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
- shard-kbl: [PASS][29] -> [INCOMPLETE][30] ([i915#3468]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl4/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-kbl1/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
* igt@gem_mmap_gtt@fault-concurrent:
- shard-skl: NOTRUN -> [INCOMPLETE][31] ([i915#1888] / [i915#3468])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl4/igt@gem_mmap_gtt@fault-concurrent.html
* igt@gem_mmap_gtt@fault-concurrent-y:
- shard-apl: NOTRUN -> [INCOMPLETE][32] ([i915#3468])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-apl2/igt@gem_mmap_gtt@fault-concurrent-y.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl: NOTRUN -> [SKIP][33] ([fdo#109271]) +70 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-kbl3/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][34] ([i915#3002])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-apl6/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@unsync-overlap:
- shard-tglb: NOTRUN -> [SKIP][35] ([i915#3297])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb5/igt@gem_userptr_blits@unsync-overlap.html
* igt@gem_userptr_blits@vma-merge:
- shard-snb: NOTRUN -> [FAIL][36] ([i915#2724])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-snb2/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@bb-large:
- shard-tglb: NOTRUN -> [SKIP][37] ([i915#2527])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@gen9_exec_parse@bb-large.html
- shard-iclb: NOTRUN -> [SKIP][38] ([i915#2527])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@gen9_exec_parse@bb-large.html
* igt@i915_pm_dc@dc6-dpms:
- shard-kbl: NOTRUN -> [FAIL][39] ([i915#454])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-kbl3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-apl: NOTRUN -> [SKIP][40] ([fdo#109271]) +210 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-apl3/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_pm_rpm@pc8-residency:
- shard-tglb: NOTRUN -> [SKIP][41] ([fdo#109506] / [i915#2411])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb5/igt@i915_pm_rpm@pc8-residency.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][42] ([fdo#110725] / [fdo#111614])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@kms_big_fb@linear-32bpp-rotate-90.html
- shard-tglb: NOTRUN -> [SKIP][43] ([fdo#111614])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-tglb: NOTRUN -> [SKIP][44] ([fdo#111615])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo:
- shard-snb: NOTRUN -> [SKIP][45] ([fdo#109271]) +417 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-snb6/igt@kms_ccs@pipe-a-ccs-on-another-bo.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +21 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-apl3/igt@kms_chamelium@vga-hpd.html
* igt@kms_color@pipe-d-ctm-negative:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109278] / [i915#1149])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@kms_color@pipe-d-ctm-negative.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +3 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-kbl2/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-iclb: NOTRUN -> [SKIP][49] ([fdo#109284] / [fdo#111827]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-iclb: NOTRUN -> [SKIP][50] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
* igt@kms_color_chamelium@pipe-d-ctm-0-5:
- shard-skl: NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl4/igt@kms_color_chamelium@pipe-d-ctm-0-5.html
* igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
- shard-snb: NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +18 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-snb2/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html
* igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes:
- shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109284] / [fdo#111827]) +5 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb5/igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][54] ([i915#1319])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-apl6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@legacy:
- shard-iclb: NOTRUN -> [SKIP][55] ([fdo#109300] / [fdo#111066])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb1/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][56] ([i915#3319])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@kms_cursor_crc@pipe-b-cursor-32x32-rapid-movement.html
* igt@kms_cursor_crc@pipe-c-cursor-512x512-sliding:
- shard-iclb: NOTRUN -> [SKIP][57] ([fdo#109278] / [fdo#109279])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb1/igt@kms_cursor_crc@pipe-c-cursor-512x512-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-max-size-onscreen:
- shard-tglb: NOTRUN -> [SKIP][58] ([i915#3359]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@kms_cursor_crc@pipe-c-cursor-max-size-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-64x64-random:
- shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109278]) +6 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@kms_cursor_crc@pipe-d-cursor-64x64-random.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109274] / [fdo#109278])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][61] -> [FAIL][62] ([i915#2346])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [PASS][63] -> [INCOMPLETE][64] ([i915#155] / [i915#180] / [i915#636])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-wf_vblank:
- shard-iclb: NOTRUN -> [SKIP][65] ([fdo#109274]) +3 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@kms_flip@2x-flip-vs-wf_vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: NOTRUN -> [DMESG-WARN][66] ([i915#180]) +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend@c-edp1:
- shard-skl: [PASS][67] -> [INCOMPLETE][68] ([i915#198])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl10/igt@kms_flip@flip-vs-suspend@c-edp1.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl3/igt@kms_flip@flip-vs-suspend@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-tglb: NOTRUN -> [SKIP][69] ([i915#2587])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271]) +20 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-tglb: NOTRUN -> [SKIP][71] ([fdo#111825]) +15 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][72] ([fdo#109280]) +12 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][73] -> [FAIL][74] ([i915#1188])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl5/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_hdr@static-toggle-suspend:
- shard-tglb: NOTRUN -> [SKIP][75] ([i915#1187])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@kms_hdr@static-toggle-suspend.html
- shard-iclb: NOTRUN -> [SKIP][76] ([i915#1187])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
- shard-iclb: NOTRUN -> [SKIP][77] ([fdo#109289]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb1/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html
* igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c:
- shard-tglb: NOTRUN -> [SKIP][78] ([fdo#109289])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-skl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#533])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl5/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#533])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-apl3/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#533])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-kbl2/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-kbl: [PASS][82] -> [DMESG-WARN][83] ([i915#180]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][84] ([fdo#108145] / [i915#265]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][85] ([i915#265]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][86] -> [FAIL][87] ([fdo#108145] / [i915#265])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][88] ([i915#265])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-kbl2/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-iclb: NOTRUN -> [SKIP][89] ([i915#658])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
- shard-tglb: NOTRUN -> [SKIP][90] ([i915#2920])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#658]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-kbl2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3:
- shard-apl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#658]) +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-apl3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
- shard-skl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#658])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][94] -> [SKIP][95] ([fdo#109441]) +2 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: NOTRUN -> [SKIP][96] ([fdo#109441])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@kms_psr@psr2_primary_page_flip.html
- shard-tglb: NOTRUN -> [FAIL][97] ([i915#132] / [i915#3467])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_psr@psr2_suspend:
- shard-tglb: NOTRUN -> [FAIL][98] ([i915#132])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb5/igt@kms_psr@psr2_suspend.html
* igt@kms_setmode@basic:
- shard-snb: NOTRUN -> [FAIL][99] ([i915#31])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-snb2/igt@kms_setmode@basic.html
* igt@kms_writeback@writeback-fb-id:
- shard-kbl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#2437])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-kbl3/igt@kms_writeback@writeback-fb-id.html
* igt@nouveau_crc@pipe-a-ctx-flip-detection:
- shard-iclb: NOTRUN -> [SKIP][101] ([i915#2530]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@nouveau_crc@pipe-a-ctx-flip-detection.html
* igt@nouveau_crc@pipe-d-source-outp-inactive:
- shard-tglb: NOTRUN -> [SKIP][102] ([i915#2530]) +1 similar issue
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@nouveau_crc@pipe-d-source-outp-inactive.html
- shard-iclb: NOTRUN -> [SKIP][103] ([fdo#109278] / [i915#2530])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@nouveau_crc@pipe-d-source-outp-inactive.html
* igt@perf@blocking:
- shard-skl: [PASS][104] -> [FAIL][105] ([i915#1542])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl10/igt@perf@blocking.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl3/igt@perf@blocking.html
* igt@perf@polling-small-buf:
- shard-skl: [PASS][106] -> [FAIL][107] ([i915#1722])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl1/igt@perf@polling-small-buf.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl5/igt@perf@polling-small-buf.html
* igt@prime_nv_api@nv_self_import_to_different_fd:
- shard-tglb: NOTRUN -> [SKIP][108] ([fdo#109291]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb5/igt@prime_nv_api@nv_self_import_to_different_fd.html
* igt@prime_nv_test@nv_i915_sharing:
- shard-iclb: NOTRUN -> [SKIP][109] ([fdo#109291])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@prime_nv_test@nv_i915_sharing.html
* igt@sysfs_clients@create:
- shard-apl: NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#2994]) +2 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-apl6/igt@sysfs_clients@create.html
* igt@sysfs_clients@recycle-many:
- shard-skl: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#2994]) +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl5/igt@sysfs_clients@recycle-many.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [DMESG-WARN][112] ([i915#180]) -> [PASS][113] +6 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl2/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_ctx_persistence@many-contexts:
- shard-iclb: [INCOMPLETE][114] ([i915#3057]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb3/igt@gem_ctx_persistence@many-contexts.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb1/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][116] ([i915#2369] / [i915#3063]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-tglb1/igt@gem_eio@unwedge-stress.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][118] ([i915#2842]) -> [PASS][119] +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [FAIL][120] ([i915#2842]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-kbl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
- shard-tglb: [INCOMPLETE][122] ([i915#2910] / [i915#3468]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-tglb6/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb5/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
- shard-tglb: [INCOMPLETE][124] ([i915#3468]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-tglb7/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-tglb2/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
- shard-iclb: [INCOMPLETE][126] ([i915#3468]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb1/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb8/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-iclb: [FAIL][128] ([i915#307]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb7/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@kms_color@pipe-b-ctm-0-25:
- shard-skl: [DMESG-WARN][130] ([i915#1982]) -> [PASS][131] +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl1/igt@kms_color@pipe-b-ctm-0-25.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl9/igt@kms_color@pipe-b-ctm-0-25.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [FAIL][132] ([i915#72]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-iclb: [FAIL][134] ([i915#2346]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-iclb2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-iclb1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [FAIL][136] ([i915#79]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [FAIL][138] ([i915#2122]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/shard-skl5/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][140] ([fdo#108145] / [i915#265]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10154/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.ht
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20248/index.html
[-- Attachment #1.2: Type: text/html, Size: 33755 bytes --]
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_______________________________________________
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^ permalink raw reply [flat|nested] 48+ messages in thread* Re: [PATCH 0/9] Enhance pipe color support for multi segmented luts
2021-06-01 10:41 ` [Intel-gfx] " Uma Shankar
@ 2021-06-04 18:51 ` Harry Wentland
-1 siblings, 0 replies; 48+ messages in thread
From: Harry Wentland @ 2021-06-04 18:51 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, dri-devel; +Cc: bhanuprakash.modem
On 2021-06-01 6:41 a.m., Uma Shankar wrote:
> Modern hardwares have multi segmented lut approach to prioritize
> the darker regions of the spectrum. This series introduces a new
> UAPI to define the lut ranges supported by the respective hardware.
>
> This also enables Pipe Color Management Support for Intel's XE_LPD hw.
> Enable Support for Pipe Degamma with the increased lut samples
> supported by hardware. This also adds support for newly introduced
> Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
>
> The Logarithmic gamma implementation on XE_LPD is non linear and adds 25
> segments with non linear lut samples in each segment. The expectation
> is userspace will create the luts as per this distribution and pass
> the final samples to driver to be programmed in hardware.
>
Is this design targetting Intel XE_LPD HW in particular or is it intended
to be generic?
If this is intended to be generic I think it would benefit from a lot more
documentation. At this point it's difficult for me to see how to adapt this
to AMD HW. It would take me a while to be comfortable to make a call on whether
we can use it or not. And what about other vendors?
I think we need to be cautious in directly exposing HW functionality through
UAPI. The CM parts of AMD HW seem to be changing in some way each generation
and it looks like the same is true for Intel. The trouble we have with adapting
the old gamma/degamma properties to modern HW is some indication to me that
this approach is somewhat problematic.
It would be useful to understand and document the specific use-cases we want to
provide to userspace implementers with this functionality. Do we want to support
modern transfer functions such as PQ or HLG? If so, it might be beneficial to
have an API to explicitly specify that, and then use LUT tables in drivers that
are optimized for the implementing HW. Or is the use case tone mapping? If so,
would a parametric definition of tone mapping be easier to manage?
> +-----+------------------------------+
> | x | 2 pow x segment|No of Entries
> | | 0 | 1 |
> | 0 | 1 | 1 |
> | 1 | 2 | 2 |
> | 2 | 4 | 2 |
> | 3 | 8 | 2 |
> | 4 | 16 | 2 |
> | 5 | 32 | 4 |
> | 6 | 64 | 4 |
> | 7 | 128 | 4 |
> | 8 | 256 | 8 |
> | 9 | 512 | 8 |
> | 10 | 1024 | 8 |
> | 11 | 2048 | 16 |
> | 12 | 4096 | 16 |
> | 13 | 8192 | 16 |
> | 14 | 16384 | 32 |
> | 15 | 32768 | 32 |
> | 16 | 65536 | 64 |
> | 17 | 131072 | 64 |
> | 18 | 262144 | 64 |
> | 19 | 524288 | 32 |
> | 20 | 1048576 | 32 |
> | 21 | 2097152 | 32 |
> | 22 | 4194304 | 32 |
> | 23 | 8388608 | 32 |
> | 24 | 16777216 | 1 |
> | | Total Entries | 511 |
> -----+-----------------+------------+
>
> Credits: Special mention and credits to Ville Syrjala for coming up
> with a design for this feature and inputs. This series is based on
> his original design.
>
> Note: Userspace support for this new UAPI will be done on Chrome and
> plan is to get this supported on mutter as well. We will notify the
> list once we have that ready for review.
>
Is this an RFC? If so it would be good to mark it as such.
Harry
> Uma Shankar (9):
> drm: Add gamma mode property
> drm/i915/xelpd: Define color lut range structure
> drm/i915/xelpd: Add support for Logarithmic gamma mode
> drm/i915/xelpd: Attach gamma mode property
> drm: Add Client Cap for advance gamma mode
> drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode
> drm/i915/xelpd: Enable Pipe Degamma
> drm/i915/xelpd: Add Pipe Color Lut caps to platform config
> drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
>
> drivers/gpu/drm/drm_atomic_uapi.c | 8 +
> drivers/gpu/drm/drm_color_mgmt.c | 75 ++++
> drivers/gpu/drm/drm_ioctl.c | 5 +
> drivers/gpu/drm/i915/display/intel_color.c | 454 ++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_pci.c | 3 +-
> drivers/gpu/drm/i915/i915_reg.h | 7 +
> include/drm/drm_atomic.h | 1 +
> include/drm/drm_color_mgmt.h | 8 +
> include/drm/drm_crtc.h | 25 ++
> include/drm/drm_file.h | 8 +
> include/uapi/drm/drm.h | 8 +
> include/uapi/drm/drm_mode.h | 43 ++
> 12 files changed, 630 insertions(+), 15 deletions(-)
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 0/9] Enhance pipe color support for multi segmented luts
@ 2021-06-04 18:51 ` Harry Wentland
0 siblings, 0 replies; 48+ messages in thread
From: Harry Wentland @ 2021-06-04 18:51 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, dri-devel; +Cc: Cyr, Aric
On 2021-06-01 6:41 a.m., Uma Shankar wrote:
> Modern hardwares have multi segmented lut approach to prioritize
> the darker regions of the spectrum. This series introduces a new
> UAPI to define the lut ranges supported by the respective hardware.
>
> This also enables Pipe Color Management Support for Intel's XE_LPD hw.
> Enable Support for Pipe Degamma with the increased lut samples
> supported by hardware. This also adds support for newly introduced
> Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
>
> The Logarithmic gamma implementation on XE_LPD is non linear and adds 25
> segments with non linear lut samples in each segment. The expectation
> is userspace will create the luts as per this distribution and pass
> the final samples to driver to be programmed in hardware.
>
Is this design targetting Intel XE_LPD HW in particular or is it intended
to be generic?
If this is intended to be generic I think it would benefit from a lot more
documentation. At this point it's difficult for me to see how to adapt this
to AMD HW. It would take me a while to be comfortable to make a call on whether
we can use it or not. And what about other vendors?
I think we need to be cautious in directly exposing HW functionality through
UAPI. The CM parts of AMD HW seem to be changing in some way each generation
and it looks like the same is true for Intel. The trouble we have with adapting
the old gamma/degamma properties to modern HW is some indication to me that
this approach is somewhat problematic.
It would be useful to understand and document the specific use-cases we want to
provide to userspace implementers with this functionality. Do we want to support
modern transfer functions such as PQ or HLG? If so, it might be beneficial to
have an API to explicitly specify that, and then use LUT tables in drivers that
are optimized for the implementing HW. Or is the use case tone mapping? If so,
would a parametric definition of tone mapping be easier to manage?
> +-----+------------------------------+
> | x | 2 pow x segment|No of Entries
> | | 0 | 1 |
> | 0 | 1 | 1 |
> | 1 | 2 | 2 |
> | 2 | 4 | 2 |
> | 3 | 8 | 2 |
> | 4 | 16 | 2 |
> | 5 | 32 | 4 |
> | 6 | 64 | 4 |
> | 7 | 128 | 4 |
> | 8 | 256 | 8 |
> | 9 | 512 | 8 |
> | 10 | 1024 | 8 |
> | 11 | 2048 | 16 |
> | 12 | 4096 | 16 |
> | 13 | 8192 | 16 |
> | 14 | 16384 | 32 |
> | 15 | 32768 | 32 |
> | 16 | 65536 | 64 |
> | 17 | 131072 | 64 |
> | 18 | 262144 | 64 |
> | 19 | 524288 | 32 |
> | 20 | 1048576 | 32 |
> | 21 | 2097152 | 32 |
> | 22 | 4194304 | 32 |
> | 23 | 8388608 | 32 |
> | 24 | 16777216 | 1 |
> | | Total Entries | 511 |
> -----+-----------------+------------+
>
> Credits: Special mention and credits to Ville Syrjala for coming up
> with a design for this feature and inputs. This series is based on
> his original design.
>
> Note: Userspace support for this new UAPI will be done on Chrome and
> plan is to get this supported on mutter as well. We will notify the
> list once we have that ready for review.
>
Is this an RFC? If so it would be good to mark it as such.
Harry
> Uma Shankar (9):
> drm: Add gamma mode property
> drm/i915/xelpd: Define color lut range structure
> drm/i915/xelpd: Add support for Logarithmic gamma mode
> drm/i915/xelpd: Attach gamma mode property
> drm: Add Client Cap for advance gamma mode
> drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode
> drm/i915/xelpd: Enable Pipe Degamma
> drm/i915/xelpd: Add Pipe Color Lut caps to platform config
> drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
>
> drivers/gpu/drm/drm_atomic_uapi.c | 8 +
> drivers/gpu/drm/drm_color_mgmt.c | 75 ++++
> drivers/gpu/drm/drm_ioctl.c | 5 +
> drivers/gpu/drm/i915/display/intel_color.c | 454 ++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_pci.c | 3 +-
> drivers/gpu/drm/i915/i915_reg.h | 7 +
> include/drm/drm_atomic.h | 1 +
> include/drm/drm_color_mgmt.h | 8 +
> include/drm/drm_crtc.h | 25 ++
> include/drm/drm_file.h | 8 +
> include/uapi/drm/drm.h | 8 +
> include/uapi/drm/drm_mode.h | 43 ++
> 12 files changed, 630 insertions(+), 15 deletions(-)
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 0/9] Enhance pipe color support for multi segmented luts
2021-06-04 18:51 ` [Intel-gfx] " Harry Wentland
@ 2021-06-07 7:29 ` Pekka Paalanen
-1 siblings, 0 replies; 48+ messages in thread
From: Pekka Paalanen @ 2021-06-07 7:29 UTC (permalink / raw)
To: Harry Wentland
Cc: intel-gfx, Uma Shankar, Sebastian Wick, dri-devel, bhanuprakash.modem
[-- Attachment #1: Type: text/plain, Size: 5694 bytes --]
On Fri, 4 Jun 2021 14:51:25 -0400
Harry Wentland <harry.wentland@amd.com> wrote:
> On 2021-06-01 6:41 a.m., Uma Shankar wrote:
> > Modern hardwares have multi segmented lut approach to prioritize
> > the darker regions of the spectrum. This series introduces a new
> > UAPI to define the lut ranges supported by the respective hardware.
> >
> > This also enables Pipe Color Management Support for Intel's XE_LPD hw.
> > Enable Support for Pipe Degamma with the increased lut samples
> > supported by hardware. This also adds support for newly introduced
> > Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
> >
> > The Logarithmic gamma implementation on XE_LPD is non linear and adds 25
> > segments with non linear lut samples in each segment. The expectation
> > is userspace will create the luts as per this distribution and pass
> > the final samples to driver to be programmed in hardware.
> >
>
> Is this design targetting Intel XE_LPD HW in particular or is it intended
> to be generic?
>
> If this is intended to be generic I think it would benefit from a lot more
> documentation. At this point it's difficult for me to see how to adapt this
> to AMD HW. It would take me a while to be comfortable to make a call on whether
> we can use it or not. And what about other vendors?
>
> I think we need to be cautious in directly exposing HW functionality through
> UAPI. The CM parts of AMD HW seem to be changing in some way each generation
> and it looks like the same is true for Intel. The trouble we have with adapting
> the old gamma/degamma properties to modern HW is some indication to me that
> this approach is somewhat problematic.
>
> It would be useful to understand and document the specific use-cases we want to
> provide to userspace implementers with this functionality. Do we want to support
> modern transfer functions such as PQ or HLG? If so, it might be beneficial to
> have an API to explicitly specify that, and then use LUT tables in drivers that
> are optimized for the implementing HW.
Hi Harry,
from my very limited understanding so far, enum might be fine for PQ,
but HLG is not just one transfer function, although it may often be
confused as one. PQ and HLG are fundamentally different designs to HDR
broadcasting I believe. It would be unfortunate to make a mistake here,
engraving it into UAPI.
> Or is the use case tone mapping? If so,
> would a parametric definition of tone mapping be easier to manage?
A very good question at least I have no idea about.
Thanks,
pq
> > +-----+------------------------------+
> > | x | 2 pow x segment|No of Entries
> > | | 0 | 1 |
> > | 0 | 1 | 1 |
> > | 1 | 2 | 2 |
> > | 2 | 4 | 2 |
> > | 3 | 8 | 2 |
> > | 4 | 16 | 2 |
> > | 5 | 32 | 4 |
> > | 6 | 64 | 4 |
> > | 7 | 128 | 4 |
> > | 8 | 256 | 8 |
> > | 9 | 512 | 8 |
> > | 10 | 1024 | 8 |
> > | 11 | 2048 | 16 |
> > | 12 | 4096 | 16 |
> > | 13 | 8192 | 16 |
> > | 14 | 16384 | 32 |
> > | 15 | 32768 | 32 |
> > | 16 | 65536 | 64 |
> > | 17 | 131072 | 64 |
> > | 18 | 262144 | 64 |
> > | 19 | 524288 | 32 |
> > | 20 | 1048576 | 32 |
> > | 21 | 2097152 | 32 |
> > | 22 | 4194304 | 32 |
> > | 23 | 8388608 | 32 |
> > | 24 | 16777216 | 1 |
> > | | Total Entries | 511 |
> > -----+-----------------+------------+
> >
> > Credits: Special mention and credits to Ville Syrjala for coming up
> > with a design for this feature and inputs. This series is based on
> > his original design.
> >
> > Note: Userspace support for this new UAPI will be done on Chrome and
> > plan is to get this supported on mutter as well. We will notify the
> > list once we have that ready for review.
> >
>
> Is this an RFC? If so it would be good to mark it as such.
>
> Harry
>
> > Uma Shankar (9):
> > drm: Add gamma mode property
> > drm/i915/xelpd: Define color lut range structure
> > drm/i915/xelpd: Add support for Logarithmic gamma mode
> > drm/i915/xelpd: Attach gamma mode property
> > drm: Add Client Cap for advance gamma mode
> > drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode
> > drm/i915/xelpd: Enable Pipe Degamma
> > drm/i915/xelpd: Add Pipe Color Lut caps to platform config
> > drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
> >
> > drivers/gpu/drm/drm_atomic_uapi.c | 8 +
> > drivers/gpu/drm/drm_color_mgmt.c | 75 ++++
> > drivers/gpu/drm/drm_ioctl.c | 5 +
> > drivers/gpu/drm/i915/display/intel_color.c | 454 ++++++++++++++++++++-
> > drivers/gpu/drm/i915/i915_pci.c | 3 +-
> > drivers/gpu/drm/i915/i915_reg.h | 7 +
> > include/drm/drm_atomic.h | 1 +
> > include/drm/drm_color_mgmt.h | 8 +
> > include/drm/drm_crtc.h | 25 ++
> > include/drm/drm_file.h | 8 +
> > include/uapi/drm/drm.h | 8 +
> > include/uapi/drm/drm_mode.h | 43 ++
> > 12 files changed, 630 insertions(+), 15 deletions(-)
> >
>
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 0/9] Enhance pipe color support for multi segmented luts
@ 2021-06-07 7:29 ` Pekka Paalanen
0 siblings, 0 replies; 48+ messages in thread
From: Pekka Paalanen @ 2021-06-07 7:29 UTC (permalink / raw)
To: Harry Wentland; +Cc: intel-gfx, Sebastian Wick, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 5694 bytes --]
On Fri, 4 Jun 2021 14:51:25 -0400
Harry Wentland <harry.wentland@amd.com> wrote:
> On 2021-06-01 6:41 a.m., Uma Shankar wrote:
> > Modern hardwares have multi segmented lut approach to prioritize
> > the darker regions of the spectrum. This series introduces a new
> > UAPI to define the lut ranges supported by the respective hardware.
> >
> > This also enables Pipe Color Management Support for Intel's XE_LPD hw.
> > Enable Support for Pipe Degamma with the increased lut samples
> > supported by hardware. This also adds support for newly introduced
> > Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
> >
> > The Logarithmic gamma implementation on XE_LPD is non linear and adds 25
> > segments with non linear lut samples in each segment. The expectation
> > is userspace will create the luts as per this distribution and pass
> > the final samples to driver to be programmed in hardware.
> >
>
> Is this design targetting Intel XE_LPD HW in particular or is it intended
> to be generic?
>
> If this is intended to be generic I think it would benefit from a lot more
> documentation. At this point it's difficult for me to see how to adapt this
> to AMD HW. It would take me a while to be comfortable to make a call on whether
> we can use it or not. And what about other vendors?
>
> I think we need to be cautious in directly exposing HW functionality through
> UAPI. The CM parts of AMD HW seem to be changing in some way each generation
> and it looks like the same is true for Intel. The trouble we have with adapting
> the old gamma/degamma properties to modern HW is some indication to me that
> this approach is somewhat problematic.
>
> It would be useful to understand and document the specific use-cases we want to
> provide to userspace implementers with this functionality. Do we want to support
> modern transfer functions such as PQ or HLG? If so, it might be beneficial to
> have an API to explicitly specify that, and then use LUT tables in drivers that
> are optimized for the implementing HW.
Hi Harry,
from my very limited understanding so far, enum might be fine for PQ,
but HLG is not just one transfer function, although it may often be
confused as one. PQ and HLG are fundamentally different designs to HDR
broadcasting I believe. It would be unfortunate to make a mistake here,
engraving it into UAPI.
> Or is the use case tone mapping? If so,
> would a parametric definition of tone mapping be easier to manage?
A very good question at least I have no idea about.
Thanks,
pq
> > +-----+------------------------------+
> > | x | 2 pow x segment|No of Entries
> > | | 0 | 1 |
> > | 0 | 1 | 1 |
> > | 1 | 2 | 2 |
> > | 2 | 4 | 2 |
> > | 3 | 8 | 2 |
> > | 4 | 16 | 2 |
> > | 5 | 32 | 4 |
> > | 6 | 64 | 4 |
> > | 7 | 128 | 4 |
> > | 8 | 256 | 8 |
> > | 9 | 512 | 8 |
> > | 10 | 1024 | 8 |
> > | 11 | 2048 | 16 |
> > | 12 | 4096 | 16 |
> > | 13 | 8192 | 16 |
> > | 14 | 16384 | 32 |
> > | 15 | 32768 | 32 |
> > | 16 | 65536 | 64 |
> > | 17 | 131072 | 64 |
> > | 18 | 262144 | 64 |
> > | 19 | 524288 | 32 |
> > | 20 | 1048576 | 32 |
> > | 21 | 2097152 | 32 |
> > | 22 | 4194304 | 32 |
> > | 23 | 8388608 | 32 |
> > | 24 | 16777216 | 1 |
> > | | Total Entries | 511 |
> > -----+-----------------+------------+
> >
> > Credits: Special mention and credits to Ville Syrjala for coming up
> > with a design for this feature and inputs. This series is based on
> > his original design.
> >
> > Note: Userspace support for this new UAPI will be done on Chrome and
> > plan is to get this supported on mutter as well. We will notify the
> > list once we have that ready for review.
> >
>
> Is this an RFC? If so it would be good to mark it as such.
>
> Harry
>
> > Uma Shankar (9):
> > drm: Add gamma mode property
> > drm/i915/xelpd: Define color lut range structure
> > drm/i915/xelpd: Add support for Logarithmic gamma mode
> > drm/i915/xelpd: Attach gamma mode property
> > drm: Add Client Cap for advance gamma mode
> > drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode
> > drm/i915/xelpd: Enable Pipe Degamma
> > drm/i915/xelpd: Add Pipe Color Lut caps to platform config
> > drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
> >
> > drivers/gpu/drm/drm_atomic_uapi.c | 8 +
> > drivers/gpu/drm/drm_color_mgmt.c | 75 ++++
> > drivers/gpu/drm/drm_ioctl.c | 5 +
> > drivers/gpu/drm/i915/display/intel_color.c | 454 ++++++++++++++++++++-
> > drivers/gpu/drm/i915/i915_pci.c | 3 +-
> > drivers/gpu/drm/i915/i915_reg.h | 7 +
> > include/drm/drm_atomic.h | 1 +
> > include/drm/drm_color_mgmt.h | 8 +
> > include/drm/drm_crtc.h | 25 ++
> > include/drm/drm_file.h | 8 +
> > include/uapi/drm/drm.h | 8 +
> > include/uapi/drm/drm_mode.h | 43 ++
> > 12 files changed, 630 insertions(+), 15 deletions(-)
> >
>
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* RE: [PATCH 0/9] Enhance pipe color support for multi segmented luts
2021-06-07 7:29 ` [Intel-gfx] " Pekka Paalanen
@ 2021-06-07 18:07 ` Shankar, Uma
-1 siblings, 0 replies; 48+ messages in thread
From: Shankar, Uma @ 2021-06-07 18:07 UTC (permalink / raw)
To: Pekka Paalanen, Harry Wentland
Cc: intel-gfx, Sebastian Wick, dri-devel, Modem, Bhanuprakash
> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Pekka
> Paalanen
> Sent: Monday, June 7, 2021 1:00 PM
> To: Harry Wentland <harry.wentland@amd.com>
> Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Sebastian Wick <sebastian@sebastianwick.net>; dri-devel@lists.freedesktop.org;
> Modem, Bhanuprakash <bhanuprakash.modem@intel.com>
> Subject: Re: [PATCH 0/9] Enhance pipe color support for multi segmented luts
>
> On Fri, 4 Jun 2021 14:51:25 -0400
> Harry Wentland <harry.wentland@amd.com> wrote:
>
> > On 2021-06-01 6:41 a.m., Uma Shankar wrote:
> > > Modern hardwares have multi segmented lut approach to prioritize the
> > > darker regions of the spectrum. This series introduces a new UAPI to
> > > define the lut ranges supported by the respective hardware.
> > >
> > > This also enables Pipe Color Management Support for Intel's XE_LPD hw.
> > > Enable Support for Pipe Degamma with the increased lut samples
> > > supported by hardware. This also adds support for newly introduced
> > > Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
> > >
> > > The Logarithmic gamma implementation on XE_LPD is non linear and
> > > adds 25 segments with non linear lut samples in each segment. The
> > > expectation is userspace will create the luts as per this
> > > distribution and pass the final samples to driver to be programmed in hardware.
> > >
> >
> > Is this design targetting Intel XE_LPD HW in particular or is it
> > intended to be generic?
> >
> > If this is intended to be generic I think it would benefit from a lot
> > more documentation. At this point it's difficult for me to see how to
> > adapt this to AMD HW. It would take me a while to be comfortable to
> > make a call on whether we can use it or not. And what about other vendors?
> >
> > I think we need to be cautious in directly exposing HW functionality
> > through UAPI. The CM parts of AMD HW seem to be changing in some way
> > each generation and it looks like the same is true for Intel. The
> > trouble we have with adapting the old gamma/degamma properties to
> > modern HW is some indication to me that this approach is somewhat problematic.
> >
> > It would be useful to understand and document the specific use-cases
> > we want to provide to userspace implementers with this functionality.
> > Do we want to support modern transfer functions such as PQ or HLG? If
> > so, it might be beneficial to have an API to explicitly specify that,
> > and then use LUT tables in drivers that are optimized for the implementing HW.
>
> Hi Harry,
>
> from my very limited understanding so far, enum might be fine for PQ, but HLG is not
> just one transfer function, although it may often be confused as one. PQ and HLG
> are fundamentally different designs to HDR broadcasting I believe. It would be
> unfortunate to make a mistake here, engraving it into UAPI.
Yes Pekka, putting this in UAPI may limit us.
> > Or is the use case tone mapping? If so, would a parametric definition
> > of tone mapping be easier to manage?
>
> A very good question at least I have no idea about.
Responded on earlier mail in thread. For non linear lut (gamma block), usecase is primarily tone
mapping but there are implementations where non linear blending is seeked (AFAIR Android does that),
so it leaves room for those usecases as well.
Regards,
Uma Shankar
>
> Thanks,
> pq
>
> > > +-----+------------------------------+
> > > | x | 2 pow x segment|No of Entries
> > > | | 0 | 1 |
> > > | 0 | 1 | 1 |
> > > | 1 | 2 | 2 |
> > > | 2 | 4 | 2 |
> > > | 3 | 8 | 2 |
> > > | 4 | 16 | 2 |
> > > | 5 | 32 | 4 |
> > > | 6 | 64 | 4 |
> > > | 7 | 128 | 4 |
> > > | 8 | 256 | 8 |
> > > | 9 | 512 | 8 |
> > > | 10 | 1024 | 8 |
> > > | 11 | 2048 | 16 |
> > > | 12 | 4096 | 16 |
> > > | 13 | 8192 | 16 |
> > > | 14 | 16384 | 32 |
> > > | 15 | 32768 | 32 |
> > > | 16 | 65536 | 64 |
> > > | 17 | 131072 | 64 |
> > > | 18 | 262144 | 64 |
> > > | 19 | 524288 | 32 |
> > > | 20 | 1048576 | 32 |
> > > | 21 | 2097152 | 32 |
> > > | 22 | 4194304 | 32 |
> > > | 23 | 8388608 | 32 |
> > > | 24 | 16777216 | 1 |
> > > | | Total Entries | 511 |
> > > -----+-----------------+------------+
> > >
> > > Credits: Special mention and credits to Ville Syrjala for coming up
> > > with a design for this feature and inputs. This series is based on
> > > his original design.
> > >
> > > Note: Userspace support for this new UAPI will be done on Chrome and
> > > plan is to get this supported on mutter as well. We will notify the
> > > list once we have that ready for review.
> > >
> >
> > Is this an RFC? If so it would be good to mark it as such.
> >
> > Harry
> >
> > > Uma Shankar (9):
> > > drm: Add gamma mode property
> > > drm/i915/xelpd: Define color lut range structure
> > > drm/i915/xelpd: Add support for Logarithmic gamma mode
> > > drm/i915/xelpd: Attach gamma mode property
> > > drm: Add Client Cap for advance gamma mode
> > > drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode
> > > drm/i915/xelpd: Enable Pipe Degamma
> > > drm/i915/xelpd: Add Pipe Color Lut caps to platform config
> > > drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
> > >
> > > drivers/gpu/drm/drm_atomic_uapi.c | 8 +
> > > drivers/gpu/drm/drm_color_mgmt.c | 75 ++++
> > > drivers/gpu/drm/drm_ioctl.c | 5 +
> > > drivers/gpu/drm/i915/display/intel_color.c | 454 ++++++++++++++++++++-
> > > drivers/gpu/drm/i915/i915_pci.c | 3 +-
> > > drivers/gpu/drm/i915/i915_reg.h | 7 +
> > > include/drm/drm_atomic.h | 1 +
> > > include/drm/drm_color_mgmt.h | 8 +
> > > include/drm/drm_crtc.h | 25 ++
> > > include/drm/drm_file.h | 8 +
> > > include/uapi/drm/drm.h | 8 +
> > > include/uapi/drm/drm_mode.h | 43 ++
> > > 12 files changed, 630 insertions(+), 15 deletions(-)
> > >
> >
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 0/9] Enhance pipe color support for multi segmented luts
@ 2021-06-07 18:07 ` Shankar, Uma
0 siblings, 0 replies; 48+ messages in thread
From: Shankar, Uma @ 2021-06-07 18:07 UTC (permalink / raw)
To: Pekka Paalanen, Harry Wentland; +Cc: intel-gfx, Sebastian Wick, dri-devel
> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Pekka
> Paalanen
> Sent: Monday, June 7, 2021 1:00 PM
> To: Harry Wentland <harry.wentland@amd.com>
> Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Sebastian Wick <sebastian@sebastianwick.net>; dri-devel@lists.freedesktop.org;
> Modem, Bhanuprakash <bhanuprakash.modem@intel.com>
> Subject: Re: [PATCH 0/9] Enhance pipe color support for multi segmented luts
>
> On Fri, 4 Jun 2021 14:51:25 -0400
> Harry Wentland <harry.wentland@amd.com> wrote:
>
> > On 2021-06-01 6:41 a.m., Uma Shankar wrote:
> > > Modern hardwares have multi segmented lut approach to prioritize the
> > > darker regions of the spectrum. This series introduces a new UAPI to
> > > define the lut ranges supported by the respective hardware.
> > >
> > > This also enables Pipe Color Management Support for Intel's XE_LPD hw.
> > > Enable Support for Pipe Degamma with the increased lut samples
> > > supported by hardware. This also adds support for newly introduced
> > > Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
> > >
> > > The Logarithmic gamma implementation on XE_LPD is non linear and
> > > adds 25 segments with non linear lut samples in each segment. The
> > > expectation is userspace will create the luts as per this
> > > distribution and pass the final samples to driver to be programmed in hardware.
> > >
> >
> > Is this design targetting Intel XE_LPD HW in particular or is it
> > intended to be generic?
> >
> > If this is intended to be generic I think it would benefit from a lot
> > more documentation. At this point it's difficult for me to see how to
> > adapt this to AMD HW. It would take me a while to be comfortable to
> > make a call on whether we can use it or not. And what about other vendors?
> >
> > I think we need to be cautious in directly exposing HW functionality
> > through UAPI. The CM parts of AMD HW seem to be changing in some way
> > each generation and it looks like the same is true for Intel. The
> > trouble we have with adapting the old gamma/degamma properties to
> > modern HW is some indication to me that this approach is somewhat problematic.
> >
> > It would be useful to understand and document the specific use-cases
> > we want to provide to userspace implementers with this functionality.
> > Do we want to support modern transfer functions such as PQ or HLG? If
> > so, it might be beneficial to have an API to explicitly specify that,
> > and then use LUT tables in drivers that are optimized for the implementing HW.
>
> Hi Harry,
>
> from my very limited understanding so far, enum might be fine for PQ, but HLG is not
> just one transfer function, although it may often be confused as one. PQ and HLG
> are fundamentally different designs to HDR broadcasting I believe. It would be
> unfortunate to make a mistake here, engraving it into UAPI.
Yes Pekka, putting this in UAPI may limit us.
> > Or is the use case tone mapping? If so, would a parametric definition
> > of tone mapping be easier to manage?
>
> A very good question at least I have no idea about.
Responded on earlier mail in thread. For non linear lut (gamma block), usecase is primarily tone
mapping but there are implementations where non linear blending is seeked (AFAIR Android does that),
so it leaves room for those usecases as well.
Regards,
Uma Shankar
>
> Thanks,
> pq
>
> > > +-----+------------------------------+
> > > | x | 2 pow x segment|No of Entries
> > > | | 0 | 1 |
> > > | 0 | 1 | 1 |
> > > | 1 | 2 | 2 |
> > > | 2 | 4 | 2 |
> > > | 3 | 8 | 2 |
> > > | 4 | 16 | 2 |
> > > | 5 | 32 | 4 |
> > > | 6 | 64 | 4 |
> > > | 7 | 128 | 4 |
> > > | 8 | 256 | 8 |
> > > | 9 | 512 | 8 |
> > > | 10 | 1024 | 8 |
> > > | 11 | 2048 | 16 |
> > > | 12 | 4096 | 16 |
> > > | 13 | 8192 | 16 |
> > > | 14 | 16384 | 32 |
> > > | 15 | 32768 | 32 |
> > > | 16 | 65536 | 64 |
> > > | 17 | 131072 | 64 |
> > > | 18 | 262144 | 64 |
> > > | 19 | 524288 | 32 |
> > > | 20 | 1048576 | 32 |
> > > | 21 | 2097152 | 32 |
> > > | 22 | 4194304 | 32 |
> > > | 23 | 8388608 | 32 |
> > > | 24 | 16777216 | 1 |
> > > | | Total Entries | 511 |
> > > -----+-----------------+------------+
> > >
> > > Credits: Special mention and credits to Ville Syrjala for coming up
> > > with a design for this feature and inputs. This series is based on
> > > his original design.
> > >
> > > Note: Userspace support for this new UAPI will be done on Chrome and
> > > plan is to get this supported on mutter as well. We will notify the
> > > list once we have that ready for review.
> > >
> >
> > Is this an RFC? If so it would be good to mark it as such.
> >
> > Harry
> >
> > > Uma Shankar (9):
> > > drm: Add gamma mode property
> > > drm/i915/xelpd: Define color lut range structure
> > > drm/i915/xelpd: Add support for Logarithmic gamma mode
> > > drm/i915/xelpd: Attach gamma mode property
> > > drm: Add Client Cap for advance gamma mode
> > > drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode
> > > drm/i915/xelpd: Enable Pipe Degamma
> > > drm/i915/xelpd: Add Pipe Color Lut caps to platform config
> > > drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
> > >
> > > drivers/gpu/drm/drm_atomic_uapi.c | 8 +
> > > drivers/gpu/drm/drm_color_mgmt.c | 75 ++++
> > > drivers/gpu/drm/drm_ioctl.c | 5 +
> > > drivers/gpu/drm/i915/display/intel_color.c | 454 ++++++++++++++++++++-
> > > drivers/gpu/drm/i915/i915_pci.c | 3 +-
> > > drivers/gpu/drm/i915/i915_reg.h | 7 +
> > > include/drm/drm_atomic.h | 1 +
> > > include/drm/drm_color_mgmt.h | 8 +
> > > include/drm/drm_crtc.h | 25 ++
> > > include/drm/drm_file.h | 8 +
> > > include/uapi/drm/drm.h | 8 +
> > > include/uapi/drm/drm_mode.h | 43 ++
> > > 12 files changed, 630 insertions(+), 15 deletions(-)
> > >
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 0/9] Enhance pipe color support for multi segmented luts
2021-06-07 18:07 ` [Intel-gfx] " Shankar, Uma
@ 2021-06-08 7:59 ` Pekka Paalanen
-1 siblings, 0 replies; 48+ messages in thread
From: Pekka Paalanen @ 2021-06-08 7:59 UTC (permalink / raw)
To: Shankar, Uma, Harry Wentland
Cc: intel-gfx, Sebastian Wick, dri-devel, Modem, Bhanuprakash
[-- Attachment #1: Type: text/plain, Size: 4792 bytes --]
On Mon, 7 Jun 2021 18:07:23 +0000
"Shankar, Uma" <uma.shankar@intel.com> wrote:
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Pekka
> > Paalanen
> > Sent: Monday, June 7, 2021 1:00 PM
> > To: Harry Wentland <harry.wentland@amd.com>
> > Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> > Sebastian Wick <sebastian@sebastianwick.net>; dri-devel@lists.freedesktop.org;
> > Modem, Bhanuprakash <bhanuprakash.modem@intel.com>
> > Subject: Re: [PATCH 0/9] Enhance pipe color support for multi segmented luts
> >
> > On Fri, 4 Jun 2021 14:51:25 -0400
> > Harry Wentland <harry.wentland@amd.com> wrote:
> >
> > > On 2021-06-01 6:41 a.m., Uma Shankar wrote:
> > > > Modern hardwares have multi segmented lut approach to prioritize the
> > > > darker regions of the spectrum. This series introduces a new UAPI to
> > > > define the lut ranges supported by the respective hardware.
> > > >
> > > > This also enables Pipe Color Management Support for Intel's XE_LPD hw.
> > > > Enable Support for Pipe Degamma with the increased lut samples
> > > > supported by hardware. This also adds support for newly introduced
> > > > Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
> > > >
> > > > The Logarithmic gamma implementation on XE_LPD is non linear and
> > > > adds 25 segments with non linear lut samples in each segment. The
> > > > expectation is userspace will create the luts as per this
> > > > distribution and pass the final samples to driver to be programmed in hardware.
> > > >
> > >
> > > Is this design targetting Intel XE_LPD HW in particular or is it
> > > intended to be generic?
> > >
> > > If this is intended to be generic I think it would benefit from a lot
> > > more documentation. At this point it's difficult for me to see how to
> > > adapt this to AMD HW. It would take me a while to be comfortable to
> > > make a call on whether we can use it or not. And what about other vendors?
> > >
> > > I think we need to be cautious in directly exposing HW functionality
> > > through UAPI. The CM parts of AMD HW seem to be changing in some way
> > > each generation and it looks like the same is true for Intel. The
> > > trouble we have with adapting the old gamma/degamma properties to
> > > modern HW is some indication to me that this approach is somewhat problematic.
> > >
> > > It would be useful to understand and document the specific use-cases
> > > we want to provide to userspace implementers with this functionality.
> > > Do we want to support modern transfer functions such as PQ or HLG? If
> > > so, it might be beneficial to have an API to explicitly specify that,
> > > and then use LUT tables in drivers that are optimized for the implementing HW.
> >
> > Hi Harry,
> >
> > from my very limited understanding so far, enum might be fine for PQ, but HLG is not
> > just one transfer function, although it may often be confused as one. PQ and HLG
> > are fundamentally different designs to HDR broadcasting I believe. It would be
> > unfortunate to make a mistake here, engraving it into UAPI.
>
> Yes Pekka, putting this in UAPI may limit us.
>
> > > Or is the use case tone mapping? If so, would a parametric definition
> > > of tone mapping be easier to manage?
> >
> > A very good question at least I have no idea about.
>
> Responded on earlier mail in thread. For non linear lut (gamma
> block), usecase is primarily tone mapping but there are
> implementations where non linear blending is seeked (AFAIR Android
> does that), so it leaves room for those usecases as well.
Yes, non-linear blending is a thing, unfortunately. Developers do not
usually understand what could be wrong with simply blending "RGBA
values", so most software just does that. It produces *a* result, and
if all you use it for is shades of black (shadows) or rounded window
corners, you never even see anything wrong with it. So the world has
accustomed to seeing "incorrect blending" so much that they think doing
anything else is wrong and complain if you try to move to physically
correct blending, because it changes the strength of shadows. Hence
any software migrating to a more correct blending formula may be met
with bug reports.
What's worse, pre-multiplied alpha is used as an optimization, as
implemented everywhere including Wayland, in a way that is actually a
step *away* from correct blending. If one wants to do correct blending,
you first need to divide out the pre-multiplied alpha, then linearize,
then blend.
Luckily(?), non-linear blending of HDR content will probably look a lot
worse than the same mistake on SDR content.
Thanks,
pq
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 0/9] Enhance pipe color support for multi segmented luts
@ 2021-06-08 7:59 ` Pekka Paalanen
0 siblings, 0 replies; 48+ messages in thread
From: Pekka Paalanen @ 2021-06-08 7:59 UTC (permalink / raw)
To: Shankar, Uma, Harry Wentland; +Cc: intel-gfx, Sebastian Wick, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 4792 bytes --]
On Mon, 7 Jun 2021 18:07:23 +0000
"Shankar, Uma" <uma.shankar@intel.com> wrote:
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Pekka
> > Paalanen
> > Sent: Monday, June 7, 2021 1:00 PM
> > To: Harry Wentland <harry.wentland@amd.com>
> > Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> > Sebastian Wick <sebastian@sebastianwick.net>; dri-devel@lists.freedesktop.org;
> > Modem, Bhanuprakash <bhanuprakash.modem@intel.com>
> > Subject: Re: [PATCH 0/9] Enhance pipe color support for multi segmented luts
> >
> > On Fri, 4 Jun 2021 14:51:25 -0400
> > Harry Wentland <harry.wentland@amd.com> wrote:
> >
> > > On 2021-06-01 6:41 a.m., Uma Shankar wrote:
> > > > Modern hardwares have multi segmented lut approach to prioritize the
> > > > darker regions of the spectrum. This series introduces a new UAPI to
> > > > define the lut ranges supported by the respective hardware.
> > > >
> > > > This also enables Pipe Color Management Support for Intel's XE_LPD hw.
> > > > Enable Support for Pipe Degamma with the increased lut samples
> > > > supported by hardware. This also adds support for newly introduced
> > > > Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
> > > >
> > > > The Logarithmic gamma implementation on XE_LPD is non linear and
> > > > adds 25 segments with non linear lut samples in each segment. The
> > > > expectation is userspace will create the luts as per this
> > > > distribution and pass the final samples to driver to be programmed in hardware.
> > > >
> > >
> > > Is this design targetting Intel XE_LPD HW in particular or is it
> > > intended to be generic?
> > >
> > > If this is intended to be generic I think it would benefit from a lot
> > > more documentation. At this point it's difficult for me to see how to
> > > adapt this to AMD HW. It would take me a while to be comfortable to
> > > make a call on whether we can use it or not. And what about other vendors?
> > >
> > > I think we need to be cautious in directly exposing HW functionality
> > > through UAPI. The CM parts of AMD HW seem to be changing in some way
> > > each generation and it looks like the same is true for Intel. The
> > > trouble we have with adapting the old gamma/degamma properties to
> > > modern HW is some indication to me that this approach is somewhat problematic.
> > >
> > > It would be useful to understand and document the specific use-cases
> > > we want to provide to userspace implementers with this functionality.
> > > Do we want to support modern transfer functions such as PQ or HLG? If
> > > so, it might be beneficial to have an API to explicitly specify that,
> > > and then use LUT tables in drivers that are optimized for the implementing HW.
> >
> > Hi Harry,
> >
> > from my very limited understanding so far, enum might be fine for PQ, but HLG is not
> > just one transfer function, although it may often be confused as one. PQ and HLG
> > are fundamentally different designs to HDR broadcasting I believe. It would be
> > unfortunate to make a mistake here, engraving it into UAPI.
>
> Yes Pekka, putting this in UAPI may limit us.
>
> > > Or is the use case tone mapping? If so, would a parametric definition
> > > of tone mapping be easier to manage?
> >
> > A very good question at least I have no idea about.
>
> Responded on earlier mail in thread. For non linear lut (gamma
> block), usecase is primarily tone mapping but there are
> implementations where non linear blending is seeked (AFAIR Android
> does that), so it leaves room for those usecases as well.
Yes, non-linear blending is a thing, unfortunately. Developers do not
usually understand what could be wrong with simply blending "RGBA
values", so most software just does that. It produces *a* result, and
if all you use it for is shades of black (shadows) or rounded window
corners, you never even see anything wrong with it. So the world has
accustomed to seeing "incorrect blending" so much that they think doing
anything else is wrong and complain if you try to move to physically
correct blending, because it changes the strength of shadows. Hence
any software migrating to a more correct blending formula may be met
with bug reports.
What's worse, pre-multiplied alpha is used as an optimization, as
implemented everywhere including Wayland, in a way that is actually a
step *away* from correct blending. If one wants to do correct blending,
you first need to divide out the pre-multiplied alpha, then linearize,
then blend.
Luckily(?), non-linear blending of HDR content will probably look a lot
worse than the same mistake on SDR content.
Thanks,
pq
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* RE: [PATCH 0/9] Enhance pipe color support for multi segmented luts
2021-06-04 18:51 ` [Intel-gfx] " Harry Wentland
@ 2021-06-07 18:01 ` Shankar, Uma
-1 siblings, 0 replies; 48+ messages in thread
From: Shankar, Uma @ 2021-06-07 18:01 UTC (permalink / raw)
To: Harry Wentland, intel-gfx, dri-devel; +Cc: Modem, Bhanuprakash
> -----Original Message-----
> From: Harry Wentland <harry.wentland@amd.com>
> Sent: Saturday, June 5, 2021 12:21 AM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org; dri-
> devel@lists.freedesktop.org
> Cc: Modem, Bhanuprakash <bhanuprakash.modem@intel.com>; Cyr, Aric
> <Aric.Cyr@amd.com>
> Subject: Re: [PATCH 0/9] Enhance pipe color support for multi segmented luts
>
> On 2021-06-01 6:41 a.m., Uma Shankar wrote:
> > Modern hardwares have multi segmented lut approach to prioritize the
> > darker regions of the spectrum. This series introduces a new UAPI to
> > define the lut ranges supported by the respective hardware.
> >
> > This also enables Pipe Color Management Support for Intel's XE_LPD hw.
> > Enable Support for Pipe Degamma with the increased lut samples
> > supported by hardware. This also adds support for newly introduced
> > Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
> >
> > The Logarithmic gamma implementation on XE_LPD is non linear and adds
> > 25 segments with non linear lut samples in each segment. The
> > expectation is userspace will create the luts as per this distribution
> > and pass the final samples to driver to be programmed in hardware.
> >
>
> Is this design targetting Intel XE_LPD HW in particular or is it intended to be generic?
>
> If this is intended to be generic I think it would benefit from a lot more
> documentation. At this point it's difficult for me to see how to adapt this to AMD
> HW. It would take me a while to be comfortable to make a call on whether we can
> use it or not. And what about other vendors?
This is expected to be generic for all vendors. XE_LPD is just a reference implementation.
It's basically an extension of what we have for crtc color but designing the UAPI to have it
more scalable for future hardware. The legacy hardware implementation which we have in
crtc properties can easily fit in this new UAPI and this can help represent hardware better
with more precision and scalability. Credits to Ville as to this is his idea of how we can represent
hardware generically and advertise to userspace.
Sure, I will add more documentation to make this clearer.
> I think we need to be cautious in directly exposing HW functionality through UAPI.
> The CM parts of AMD HW seem to be changing in some way each generation and it
> looks like the same is true for Intel. The trouble we have with adapting the old
> gamma/degamma properties to modern HW is some indication to me that this
> approach is somewhat problematic.
>
The advantage of having flexibility in userspace is that we give access of hardware to
userspace.It can then control things based on various usecases and not limited by just
a subset of operations what we define (in the lack of such an implementation).
> It would be useful to understand and document the specific use-cases we want to
> provide to userspace implementers with this functionality. Do we want to support
> modern transfer functions such as PQ or HLG? If so, it might be beneficial to have an
> API to explicitly specify that, and then use LUT tables in drivers that are optimized for
> the implementing HW. Or is the use case tone mapping? If so, would a parametric
> definition of tone mapping be easier to manage?
>
Yes right, ideally this is what intend to achieve here. We cant have fixed tables for operations
like Tone mapping as it will depend on mastering luminance values which can vary along with
other attributes of metadata. Eventually this operation would be done by the gamma block
(non linear luts), the values for which would be calculated and send by userspace. Thus making
all this very generic. Also we can't do any color math in driver as it has lot of floating operations.
So here the trade-off is between having a UAPI where userspace controls hw, computes and sends
values vs having just a fixed function operations with hard coded lut tables in driver.
Maybe we can have both the options in order to give flexibility to hardware vendors. We can
document the usage of the UAPI we create which can help things co-exist. Userspace can query
the supported properties and implement based on the properties exposed by the respective
vendor driver implementation.
My personal preference would be to go with generic option (expose hardware to userspace) which
will make life easier for userspace developers. This will help use hardware for any color operation not
just limited to linearization, CSC conversions and tone mapping. Also this is already done for crtc, so it just
need to be extended to planes.
> > +-----+------------------------------+
> > | x | 2 pow x segment|No of Entries
> > | | 0 | 1 |
> > | 0 | 1 | 1 |
> > | 1 | 2 | 2 |
> > | 2 | 4 | 2 |
> > | 3 | 8 | 2 |
> > | 4 | 16 | 2 |
> > | 5 | 32 | 4 |
> > | 6 | 64 | 4 |
> > | 7 | 128 | 4 |
> > | 8 | 256 | 8 |
> > | 9 | 512 | 8 |
> > | 10 | 1024 | 8 |
> > | 11 | 2048 | 16 |
> > | 12 | 4096 | 16 |
> > | 13 | 8192 | 16 |
> > | 14 | 16384 | 32 |
> > | 15 | 32768 | 32 |
> > | 16 | 65536 | 64 |
> > | 17 | 131072 | 64 |
> > | 18 | 262144 | 64 |
> > | 19 | 524288 | 32 |
> > | 20 | 1048576 | 32 |
> > | 21 | 2097152 | 32 |
> > | 22 | 4194304 | 32 |
> > | 23 | 8388608 | 32 |
> > | 24 | 16777216 | 1 |
> > | | Total Entries | 511 |
> > -----+-----------------+------------+
> >
> > Credits: Special mention and credits to Ville Syrjala for coming up
> > with a design for this feature and inputs. This series is based on his
> > original design.
> >
> > Note: Userspace support for this new UAPI will be done on Chrome and
> > plan is to get this supported on mutter as well. We will notify the
> > list once we have that ready for review.
> >
>
> Is this an RFC? If so it would be good to mark it as such.
Yes, sure will update the tag.
Thanks Harry for the feedback.
Regards,
Uma Shankar
> Harry
>
> > Uma Shankar (9):
> > drm: Add gamma mode property
> > drm/i915/xelpd: Define color lut range structure
> > drm/i915/xelpd: Add support for Logarithmic gamma mode
> > drm/i915/xelpd: Attach gamma mode property
> > drm: Add Client Cap for advance gamma mode
> > drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode
> > drm/i915/xelpd: Enable Pipe Degamma
> > drm/i915/xelpd: Add Pipe Color Lut caps to platform config
> > drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
> >
> > drivers/gpu/drm/drm_atomic_uapi.c | 8 +
> > drivers/gpu/drm/drm_color_mgmt.c | 75 ++++
> > drivers/gpu/drm/drm_ioctl.c | 5 +
> > drivers/gpu/drm/i915/display/intel_color.c | 454 ++++++++++++++++++++-
> > drivers/gpu/drm/i915/i915_pci.c | 3 +-
> > drivers/gpu/drm/i915/i915_reg.h | 7 +
> > include/drm/drm_atomic.h | 1 +
> > include/drm/drm_color_mgmt.h | 8 +
> > include/drm/drm_crtc.h | 25 ++
> > include/drm/drm_file.h | 8 +
> > include/uapi/drm/drm.h | 8 +
> > include/uapi/drm/drm_mode.h | 43 ++
> > 12 files changed, 630 insertions(+), 15 deletions(-)
> >
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 0/9] Enhance pipe color support for multi segmented luts
@ 2021-06-07 18:01 ` Shankar, Uma
0 siblings, 0 replies; 48+ messages in thread
From: Shankar, Uma @ 2021-06-07 18:01 UTC (permalink / raw)
To: Harry Wentland, intel-gfx, dri-devel; +Cc: Cyr, Aric
> -----Original Message-----
> From: Harry Wentland <harry.wentland@amd.com>
> Sent: Saturday, June 5, 2021 12:21 AM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org; dri-
> devel@lists.freedesktop.org
> Cc: Modem, Bhanuprakash <bhanuprakash.modem@intel.com>; Cyr, Aric
> <Aric.Cyr@amd.com>
> Subject: Re: [PATCH 0/9] Enhance pipe color support for multi segmented luts
>
> On 2021-06-01 6:41 a.m., Uma Shankar wrote:
> > Modern hardwares have multi segmented lut approach to prioritize the
> > darker regions of the spectrum. This series introduces a new UAPI to
> > define the lut ranges supported by the respective hardware.
> >
> > This also enables Pipe Color Management Support for Intel's XE_LPD hw.
> > Enable Support for Pipe Degamma with the increased lut samples
> > supported by hardware. This also adds support for newly introduced
> > Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
> >
> > The Logarithmic gamma implementation on XE_LPD is non linear and adds
> > 25 segments with non linear lut samples in each segment. The
> > expectation is userspace will create the luts as per this distribution
> > and pass the final samples to driver to be programmed in hardware.
> >
>
> Is this design targetting Intel XE_LPD HW in particular or is it intended to be generic?
>
> If this is intended to be generic I think it would benefit from a lot more
> documentation. At this point it's difficult for me to see how to adapt this to AMD
> HW. It would take me a while to be comfortable to make a call on whether we can
> use it or not. And what about other vendors?
This is expected to be generic for all vendors. XE_LPD is just a reference implementation.
It's basically an extension of what we have for crtc color but designing the UAPI to have it
more scalable for future hardware. The legacy hardware implementation which we have in
crtc properties can easily fit in this new UAPI and this can help represent hardware better
with more precision and scalability. Credits to Ville as to this is his idea of how we can represent
hardware generically and advertise to userspace.
Sure, I will add more documentation to make this clearer.
> I think we need to be cautious in directly exposing HW functionality through UAPI.
> The CM parts of AMD HW seem to be changing in some way each generation and it
> looks like the same is true for Intel. The trouble we have with adapting the old
> gamma/degamma properties to modern HW is some indication to me that this
> approach is somewhat problematic.
>
The advantage of having flexibility in userspace is that we give access of hardware to
userspace.It can then control things based on various usecases and not limited by just
a subset of operations what we define (in the lack of such an implementation).
> It would be useful to understand and document the specific use-cases we want to
> provide to userspace implementers with this functionality. Do we want to support
> modern transfer functions such as PQ or HLG? If so, it might be beneficial to have an
> API to explicitly specify that, and then use LUT tables in drivers that are optimized for
> the implementing HW. Or is the use case tone mapping? If so, would a parametric
> definition of tone mapping be easier to manage?
>
Yes right, ideally this is what intend to achieve here. We cant have fixed tables for operations
like Tone mapping as it will depend on mastering luminance values which can vary along with
other attributes of metadata. Eventually this operation would be done by the gamma block
(non linear luts), the values for which would be calculated and send by userspace. Thus making
all this very generic. Also we can't do any color math in driver as it has lot of floating operations.
So here the trade-off is between having a UAPI where userspace controls hw, computes and sends
values vs having just a fixed function operations with hard coded lut tables in driver.
Maybe we can have both the options in order to give flexibility to hardware vendors. We can
document the usage of the UAPI we create which can help things co-exist. Userspace can query
the supported properties and implement based on the properties exposed by the respective
vendor driver implementation.
My personal preference would be to go with generic option (expose hardware to userspace) which
will make life easier for userspace developers. This will help use hardware for any color operation not
just limited to linearization, CSC conversions and tone mapping. Also this is already done for crtc, so it just
need to be extended to planes.
> > +-----+------------------------------+
> > | x | 2 pow x segment|No of Entries
> > | | 0 | 1 |
> > | 0 | 1 | 1 |
> > | 1 | 2 | 2 |
> > | 2 | 4 | 2 |
> > | 3 | 8 | 2 |
> > | 4 | 16 | 2 |
> > | 5 | 32 | 4 |
> > | 6 | 64 | 4 |
> > | 7 | 128 | 4 |
> > | 8 | 256 | 8 |
> > | 9 | 512 | 8 |
> > | 10 | 1024 | 8 |
> > | 11 | 2048 | 16 |
> > | 12 | 4096 | 16 |
> > | 13 | 8192 | 16 |
> > | 14 | 16384 | 32 |
> > | 15 | 32768 | 32 |
> > | 16 | 65536 | 64 |
> > | 17 | 131072 | 64 |
> > | 18 | 262144 | 64 |
> > | 19 | 524288 | 32 |
> > | 20 | 1048576 | 32 |
> > | 21 | 2097152 | 32 |
> > | 22 | 4194304 | 32 |
> > | 23 | 8388608 | 32 |
> > | 24 | 16777216 | 1 |
> > | | Total Entries | 511 |
> > -----+-----------------+------------+
> >
> > Credits: Special mention and credits to Ville Syrjala for coming up
> > with a design for this feature and inputs. This series is based on his
> > original design.
> >
> > Note: Userspace support for this new UAPI will be done on Chrome and
> > plan is to get this supported on mutter as well. We will notify the
> > list once we have that ready for review.
> >
>
> Is this an RFC? If so it would be good to mark it as such.
Yes, sure will update the tag.
Thanks Harry for the feedback.
Regards,
Uma Shankar
> Harry
>
> > Uma Shankar (9):
> > drm: Add gamma mode property
> > drm/i915/xelpd: Define color lut range structure
> > drm/i915/xelpd: Add support for Logarithmic gamma mode
> > drm/i915/xelpd: Attach gamma mode property
> > drm: Add Client Cap for advance gamma mode
> > drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode
> > drm/i915/xelpd: Enable Pipe Degamma
> > drm/i915/xelpd: Add Pipe Color Lut caps to platform config
> > drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
> >
> > drivers/gpu/drm/drm_atomic_uapi.c | 8 +
> > drivers/gpu/drm/drm_color_mgmt.c | 75 ++++
> > drivers/gpu/drm/drm_ioctl.c | 5 +
> > drivers/gpu/drm/i915/display/intel_color.c | 454 ++++++++++++++++++++-
> > drivers/gpu/drm/i915/i915_pci.c | 3 +-
> > drivers/gpu/drm/i915/i915_reg.h | 7 +
> > include/drm/drm_atomic.h | 1 +
> > include/drm/drm_color_mgmt.h | 8 +
> > include/drm/drm_crtc.h | 25 ++
> > include/drm/drm_file.h | 8 +
> > include/uapi/drm/drm.h | 8 +
> > include/uapi/drm/drm_mode.h | 43 ++
> > 12 files changed, 630 insertions(+), 15 deletions(-)
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 0/9] Enhance pipe color support for multi segmented luts
2021-06-07 18:01 ` [Intel-gfx] " Shankar, Uma
@ 2021-06-07 21:00 ` Harry Wentland
-1 siblings, 0 replies; 48+ messages in thread
From: Harry Wentland @ 2021-06-07 21:00 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx, dri-devel; +Cc: Modem, Bhanuprakash
On 2021-06-07 2:01 p.m., Shankar, Uma wrote:
>
>
>> -----Original Message-----
>> From: Harry Wentland <harry.wentland@amd.com>
>> Sent: Saturday, June 5, 2021 12:21 AM
>> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org; dri-
>> devel@lists.freedesktop.org
>> Cc: Modem, Bhanuprakash <bhanuprakash.modem@intel.com>; Cyr, Aric
>> <Aric.Cyr@amd.com>
>> Subject: Re: [PATCH 0/9] Enhance pipe color support for multi segmented luts
>>
>> On 2021-06-01 6:41 a.m., Uma Shankar wrote:
>>> Modern hardwares have multi segmented lut approach to prioritize the
>>> darker regions of the spectrum. This series introduces a new UAPI to
>>> define the lut ranges supported by the respective hardware.
>>>
>>> This also enables Pipe Color Management Support for Intel's XE_LPD hw.
>>> Enable Support for Pipe Degamma with the increased lut samples
>>> supported by hardware. This also adds support for newly introduced
>>> Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
>>>
>>> The Logarithmic gamma implementation on XE_LPD is non linear and adds
>>> 25 segments with non linear lut samples in each segment. The
>>> expectation is userspace will create the luts as per this distribution
>>> and pass the final samples to driver to be programmed in hardware.
>>>
>>
>> Is this design targetting Intel XE_LPD HW in particular or is it intended to be generic?
>>
>> If this is intended to be generic I think it would benefit from a lot more
>> documentation. At this point it's difficult for me to see how to adapt this to AMD
>> HW. It would take me a while to be comfortable to make a call on whether we can
>> use it or not. And what about other vendors?
>
> This is expected to be generic for all vendors. XE_LPD is just a reference implementation.
> It's basically an extension of what we have for crtc color but designing the UAPI to have it
> more scalable for future hardware. The legacy hardware implementation which we have in
> crtc properties can easily fit in this new UAPI and this can help represent hardware better
> with more precision and scalability. Credits to Ville as to this is his idea of how we can represent
> hardware generically and advertise to userspace.
>
> Sure, I will add more documentation to make this clearer.
>
>> I think we need to be cautious in directly exposing HW functionality through UAPI.
>> The CM parts of AMD HW seem to be changing in some way each generation and it
>> looks like the same is true for Intel. The trouble we have with adapting the old
>> gamma/degamma properties to modern HW is some indication to me that this
>> approach is somewhat problematic.
>>
>
> The advantage of having flexibility in userspace is that we give access of hardware to
> userspace.It can then control things based on various usecases and not limited by just
> a subset of operations what we define (in the lack of such an implementation).
>
>> It would be useful to understand and document the specific use-cases we want to
>> provide to userspace implementers with this functionality. Do we want to support
>> modern transfer functions such as PQ or HLG? If so, it might be beneficial to have an
>> API to explicitly specify that, and then use LUT tables in drivers that are optimized for
>> the implementing HW. Or is the use case tone mapping? If so, would a parametric
>> definition of tone mapping be easier to manage?
>>
>
> Yes right, ideally this is what intend to achieve here. We cant have fixed tables for operations
> like Tone mapping as it will depend on mastering luminance values which can vary along with
> other attributes of metadata. Eventually this operation would be done by the gamma block
> (non linear luts), the values for which would be calculated and send by userspace. Thus making
> all this very generic. Also we can't do any color math in driver as it has lot of floating operations.
>
> So here the trade-off is between having a UAPI where userspace controls hw, computes and sends
> values vs having just a fixed function operations with hard coded lut tables in driver.
>
> Maybe we can have both the options in order to give flexibility to hardware vendors. We can
> document the usage of the UAPI we create which can help things co-exist. Userspace can query
> the supported properties and implement based on the properties exposed by the respective
> vendor driver implementation.
>
> My personal preference would be to go with generic option (expose hardware to userspace) which
> will make life easier for userspace developers. This will help use hardware for any color operation not
> just limited to linearization, CSC conversions and tone mapping. Also this is already done for crtc, so it just
> need to be extended to planes.
>
Thanks for providing more background.
How would a driver handle this segmented LUT when the implementing HW
doesn't have 512 points, but uses more, or less, or differently
distributed points?
What about HW that doesn't support RAM LUTs and only supports ROMs?
Obviously such HW would likely not be able to do tone mapping in HW
but could still linearize the content.
Harry
>>> +-----+------------------------------+
>>> | x | 2 pow x segment|No of Entries
>>> | | 0 | 1 |
>>> | 0 | 1 | 1 |
>>> | 1 | 2 | 2 |
>>> | 2 | 4 | 2 |
>>> | 3 | 8 | 2 |
>>> | 4 | 16 | 2 |
>>> | 5 | 32 | 4 |
>>> | 6 | 64 | 4 |
>>> | 7 | 128 | 4 |
>>> | 8 | 256 | 8 |
>>> | 9 | 512 | 8 |
>>> | 10 | 1024 | 8 |
>>> | 11 | 2048 | 16 |
>>> | 12 | 4096 | 16 |
>>> | 13 | 8192 | 16 |
>>> | 14 | 16384 | 32 |
>>> | 15 | 32768 | 32 |
>>> | 16 | 65536 | 64 |
>>> | 17 | 131072 | 64 |
>>> | 18 | 262144 | 64 |
>>> | 19 | 524288 | 32 |
>>> | 20 | 1048576 | 32 |
>>> | 21 | 2097152 | 32 |
>>> | 22 | 4194304 | 32 |
>>> | 23 | 8388608 | 32 |
>>> | 24 | 16777216 | 1 |
>>> | | Total Entries | 511 |
>>> -----+-----------------+------------+
>>>
>>> Credits: Special mention and credits to Ville Syrjala for coming up
>>> with a design for this feature and inputs. This series is based on his
>>> original design.
>>>
>>> Note: Userspace support for this new UAPI will be done on Chrome and
>>> plan is to get this supported on mutter as well. We will notify the
>>> list once we have that ready for review.
>>>
>>
>> Is this an RFC? If so it would be good to mark it as such.
>
> Yes, sure will update the tag.
>
> Thanks Harry for the feedback.
>
> Regards,
> Uma Shankar
>
>> Harry
>>
>>> Uma Shankar (9):
>>> drm: Add gamma mode property
>>> drm/i915/xelpd: Define color lut range structure
>>> drm/i915/xelpd: Add support for Logarithmic gamma mode
>>> drm/i915/xelpd: Attach gamma mode property
>>> drm: Add Client Cap for advance gamma mode
>>> drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode
>>> drm/i915/xelpd: Enable Pipe Degamma
>>> drm/i915/xelpd: Add Pipe Color Lut caps to platform config
>>> drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
>>>
>>> drivers/gpu/drm/drm_atomic_uapi.c | 8 +
>>> drivers/gpu/drm/drm_color_mgmt.c | 75 ++++
>>> drivers/gpu/drm/drm_ioctl.c | 5 +
>>> drivers/gpu/drm/i915/display/intel_color.c | 454 ++++++++++++++++++++-
>>> drivers/gpu/drm/i915/i915_pci.c | 3 +-
>>> drivers/gpu/drm/i915/i915_reg.h | 7 +
>>> include/drm/drm_atomic.h | 1 +
>>> include/drm/drm_color_mgmt.h | 8 +
>>> include/drm/drm_crtc.h | 25 ++
>>> include/drm/drm_file.h | 8 +
>>> include/uapi/drm/drm.h | 8 +
>>> include/uapi/drm/drm_mode.h | 43 ++
>>> 12 files changed, 630 insertions(+), 15 deletions(-)
>>>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [Intel-gfx] [PATCH 0/9] Enhance pipe color support for multi segmented luts
@ 2021-06-07 21:00 ` Harry Wentland
0 siblings, 0 replies; 48+ messages in thread
From: Harry Wentland @ 2021-06-07 21:00 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx, dri-devel; +Cc: Cyr, Aric
On 2021-06-07 2:01 p.m., Shankar, Uma wrote:
>
>
>> -----Original Message-----
>> From: Harry Wentland <harry.wentland@amd.com>
>> Sent: Saturday, June 5, 2021 12:21 AM
>> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org; dri-
>> devel@lists.freedesktop.org
>> Cc: Modem, Bhanuprakash <bhanuprakash.modem@intel.com>; Cyr, Aric
>> <Aric.Cyr@amd.com>
>> Subject: Re: [PATCH 0/9] Enhance pipe color support for multi segmented luts
>>
>> On 2021-06-01 6:41 a.m., Uma Shankar wrote:
>>> Modern hardwares have multi segmented lut approach to prioritize the
>>> darker regions of the spectrum. This series introduces a new UAPI to
>>> define the lut ranges supported by the respective hardware.
>>>
>>> This also enables Pipe Color Management Support for Intel's XE_LPD hw.
>>> Enable Support for Pipe Degamma with the increased lut samples
>>> supported by hardware. This also adds support for newly introduced
>>> Logarithmic Gamma for XE_LPD. Also added the gamma readout support.
>>>
>>> The Logarithmic gamma implementation on XE_LPD is non linear and adds
>>> 25 segments with non linear lut samples in each segment. The
>>> expectation is userspace will create the luts as per this distribution
>>> and pass the final samples to driver to be programmed in hardware.
>>>
>>
>> Is this design targetting Intel XE_LPD HW in particular or is it intended to be generic?
>>
>> If this is intended to be generic I think it would benefit from a lot more
>> documentation. At this point it's difficult for me to see how to adapt this to AMD
>> HW. It would take me a while to be comfortable to make a call on whether we can
>> use it or not. And what about other vendors?
>
> This is expected to be generic for all vendors. XE_LPD is just a reference implementation.
> It's basically an extension of what we have for crtc color but designing the UAPI to have it
> more scalable for future hardware. The legacy hardware implementation which we have in
> crtc properties can easily fit in this new UAPI and this can help represent hardware better
> with more precision and scalability. Credits to Ville as to this is his idea of how we can represent
> hardware generically and advertise to userspace.
>
> Sure, I will add more documentation to make this clearer.
>
>> I think we need to be cautious in directly exposing HW functionality through UAPI.
>> The CM parts of AMD HW seem to be changing in some way each generation and it
>> looks like the same is true for Intel. The trouble we have with adapting the old
>> gamma/degamma properties to modern HW is some indication to me that this
>> approach is somewhat problematic.
>>
>
> The advantage of having flexibility in userspace is that we give access of hardware to
> userspace.It can then control things based on various usecases and not limited by just
> a subset of operations what we define (in the lack of such an implementation).
>
>> It would be useful to understand and document the specific use-cases we want to
>> provide to userspace implementers with this functionality. Do we want to support
>> modern transfer functions such as PQ or HLG? If so, it might be beneficial to have an
>> API to explicitly specify that, and then use LUT tables in drivers that are optimized for
>> the implementing HW. Or is the use case tone mapping? If so, would a parametric
>> definition of tone mapping be easier to manage?
>>
>
> Yes right, ideally this is what intend to achieve here. We cant have fixed tables for operations
> like Tone mapping as it will depend on mastering luminance values which can vary along with
> other attributes of metadata. Eventually this operation would be done by the gamma block
> (non linear luts), the values for which would be calculated and send by userspace. Thus making
> all this very generic. Also we can't do any color math in driver as it has lot of floating operations.
>
> So here the trade-off is between having a UAPI where userspace controls hw, computes and sends
> values vs having just a fixed function operations with hard coded lut tables in driver.
>
> Maybe we can have both the options in order to give flexibility to hardware vendors. We can
> document the usage of the UAPI we create which can help things co-exist. Userspace can query
> the supported properties and implement based on the properties exposed by the respective
> vendor driver implementation.
>
> My personal preference would be to go with generic option (expose hardware to userspace) which
> will make life easier for userspace developers. This will help use hardware for any color operation not
> just limited to linearization, CSC conversions and tone mapping. Also this is already done for crtc, so it just
> need to be extended to planes.
>
Thanks for providing more background.
How would a driver handle this segmented LUT when the implementing HW
doesn't have 512 points, but uses more, or less, or differently
distributed points?
What about HW that doesn't support RAM LUTs and only supports ROMs?
Obviously such HW would likely not be able to do tone mapping in HW
but could still linearize the content.
Harry
>>> +-----+------------------------------+
>>> | x | 2 pow x segment|No of Entries
>>> | | 0 | 1 |
>>> | 0 | 1 | 1 |
>>> | 1 | 2 | 2 |
>>> | 2 | 4 | 2 |
>>> | 3 | 8 | 2 |
>>> | 4 | 16 | 2 |
>>> | 5 | 32 | 4 |
>>> | 6 | 64 | 4 |
>>> | 7 | 128 | 4 |
>>> | 8 | 256 | 8 |
>>> | 9 | 512 | 8 |
>>> | 10 | 1024 | 8 |
>>> | 11 | 2048 | 16 |
>>> | 12 | 4096 | 16 |
>>> | 13 | 8192 | 16 |
>>> | 14 | 16384 | 32 |
>>> | 15 | 32768 | 32 |
>>> | 16 | 65536 | 64 |
>>> | 17 | 131072 | 64 |
>>> | 18 | 262144 | 64 |
>>> | 19 | 524288 | 32 |
>>> | 20 | 1048576 | 32 |
>>> | 21 | 2097152 | 32 |
>>> | 22 | 4194304 | 32 |
>>> | 23 | 8388608 | 32 |
>>> | 24 | 16777216 | 1 |
>>> | | Total Entries | 511 |
>>> -----+-----------------+------------+
>>>
>>> Credits: Special mention and credits to Ville Syrjala for coming up
>>> with a design for this feature and inputs. This series is based on his
>>> original design.
>>>
>>> Note: Userspace support for this new UAPI will be done on Chrome and
>>> plan is to get this supported on mutter as well. We will notify the
>>> list once we have that ready for review.
>>>
>>
>> Is this an RFC? If so it would be good to mark it as such.
>
> Yes, sure will update the tag.
>
> Thanks Harry for the feedback.
>
> Regards,
> Uma Shankar
>
>> Harry
>>
>>> Uma Shankar (9):
>>> drm: Add gamma mode property
>>> drm/i915/xelpd: Define color lut range structure
>>> drm/i915/xelpd: Add support for Logarithmic gamma mode
>>> drm/i915/xelpd: Attach gamma mode property
>>> drm: Add Client Cap for advance gamma mode
>>> drm/i915/xelpd: logarithmic gamma enabled only with advance gamma mode
>>> drm/i915/xelpd: Enable Pipe Degamma
>>> drm/i915/xelpd: Add Pipe Color Lut caps to platform config
>>> drm/i915/xelpd: Enable XE_LPD Gamma Lut readout
>>>
>>> drivers/gpu/drm/drm_atomic_uapi.c | 8 +
>>> drivers/gpu/drm/drm_color_mgmt.c | 75 ++++
>>> drivers/gpu/drm/drm_ioctl.c | 5 +
>>> drivers/gpu/drm/i915/display/intel_color.c | 454 ++++++++++++++++++++-
>>> drivers/gpu/drm/i915/i915_pci.c | 3 +-
>>> drivers/gpu/drm/i915/i915_reg.h | 7 +
>>> include/drm/drm_atomic.h | 1 +
>>> include/drm/drm_color_mgmt.h | 8 +
>>> include/drm/drm_crtc.h | 25 ++
>>> include/drm/drm_file.h | 8 +
>>> include/uapi/drm/drm.h | 8 +
>>> include/uapi/drm/drm_mode.h | 43 ++
>>> 12 files changed, 630 insertions(+), 15 deletions(-)
>>>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 48+ messages in thread