* [Intel-gfx] [PATCH 0/7] Finish conversion to GRAPHICS_VER
@ 2021-05-27 18:16 Lucas De Marchi
2021-05-27 18:16 ` [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER Lucas De Marchi
` (10 more replies)
0 siblings, 11 replies; 20+ messages in thread
From: Lucas De Marchi @ 2021-05-27 18:16 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-gvt-dev
Latest version of previous series "drm/i915: Extend GEN renames to the
rest of the driver" (https://patchwork.freedesktop.org/series/88825/)
dropped one patch converting all the instances of IS_GEN() and
INTEL_GEN() to GRAPHICS_VER() due to the patches changing the
meaning of the macros IS_GRAPHICS_VER/GRAPHICS_VER and removal of
IS_GRAPHICS_RANGE().
I couldn't find a way to convince coccinelle to fix all places, so I
just did it manually in separate commits the places that were not
updated.
Finish the conversion splitting the changes so it can go to the
different branches (drm-intel-gt-next and drm-intel-next). I also split
the gvt changes, but I think it would be easeir to take this directly on
drm-intel-next.
Also, please do not apply this series as I have other series I'd like to
rebase on top before landing it.
Cc: intel-gvt-dev@lists.freedesktop.org
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Lucas De Marchi (7):
drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
drm/i915/gt: Add remaining conversions to GRAPHICS_VER
drm/i915/gem: replace IS_GEN and friends with IS_GRAPHICS_VER
drm/i915/gvt: replace IS_GEN and friends with IS_GRAPHICS_VER
drm/i915: replace IS_GEN and friends with IS_GRAPHICS_VER
drm/i915: Add remaining conversions to GRAPHICS_VER
drm/i915/display: replace IS_GEN() in commented code
drivers/gpu/drm/i915/display/intel_tv.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +-
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 10 +--
.../gpu/drm/i915/gem/i915_gem_object_blt.c | 8 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 16 ++--
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 12 +--
.../i915/gem/selftests/i915_gem_client_blt.c | 10 +--
.../i915/gem/selftests/i915_gem_coherency.c | 4 +-
.../drm/i915/gem/selftests/i915_gem_context.c | 16 ++--
.../drm/i915/gem/selftests/i915_gem_mman.c | 14 ++--
.../drm/i915/gem/selftests/igt_gem_utils.c | 10 +--
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 40 +++++-----
drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 54 ++++++-------
drivers/gpu/drm/i915/gt/intel_engine_types.h | 4 +-
.../drm/i915/gt/intel_execlists_submission.c | 18 ++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 18 ++---
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 34 ++++----
drivers/gpu/drm/i915/gt/intel_gt.c | 27 ++++---
.../gpu/drm/i915/gt/intel_gt_clock_utils.c | 12 +--
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 6 +-
drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 10 +--
drivers/gpu/drm/i915/gt/intel_gtt.c | 14 ++--
drivers/gpu/drm/i915/gt/intel_llc.c | 6 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 46 +++++------
drivers/gpu/drm/i915/gt/intel_mocs.c | 8 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 6 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 16 ++--
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 12 +--
.../gpu/drm/i915/gt/intel_ring_submission.c | 64 +++++++--------
drivers/gpu/drm/i915/gt/intel_rps.c | 60 +++++++-------
drivers/gpu/drm/i915/gt/intel_sseu.c | 14 ++--
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 6 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +++++++--------
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 6 +-
drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 4 +-
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 +-
drivers/gpu/drm/i915/gt/selftest_llc.c | 4 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c | 8 +-
drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rc6.c | 4 +-
.../drm/i915/gt/selftest_ring_submission.c | 6 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 16 ++--
drivers/gpu/drm/i915/gt/selftest_timeline.c | 6 +-
.../gpu/drm/i915/gt/selftest_workarounds.c | 8 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +--
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
drivers/gpu/drm/i915/gvt/cmd_parser.c | 8 +-
drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c | 10 +--
drivers/gpu/drm/i915/gvt/gtt.c | 4 +-
drivers/gpu/drm/i915/gvt/handlers.c | 6 +-
drivers/gpu/drm/i915/gvt/interrupt.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 10 +--
drivers/gpu/drm/i915/gvt/scheduler.c | 4 +-
drivers/gpu/drm/i915/gvt/vgpu.c | 4 +-
drivers/gpu/drm/i915/i915_cmd_parser.c | 10 +--
drivers/gpu/drm/i915/i915_debugfs.c | 32 ++++----
drivers/gpu/drm/i915/i915_drv.c | 20 ++---
drivers/gpu/drm/i915/i915_drv.h | 35 ++++----
drivers/gpu/drm/i915/i915_gem.c | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 80 +++++++++----------
drivers/gpu/drm/i915/i915_irq.c | 34 ++++----
drivers/gpu/drm/i915/i915_perf.c | 44 +++++-----
drivers/gpu/drm/i915/i915_pmu.c | 8 +-
drivers/gpu/drm/i915/i915_reg.h | 26 +++---
drivers/gpu/drm/i915/i915_request.c | 4 +-
drivers/gpu/drm/i915/i915_suspend.c | 16 ++--
drivers/gpu/drm/i915/i915_sysfs.c | 2 +-
drivers/gpu/drm/i915/i915_vgpu.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 22 ++---
drivers/gpu/drm/i915/intel_dram.c | 14 ++--
drivers/gpu/drm/i915/intel_pch.c | 10 +--
drivers/gpu/drm/i915/intel_pm.c | 14 ++--
drivers/gpu/drm/i915/intel_sideband.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 26 +++---
drivers/gpu/drm/i915/intel_wopcm.c | 10 +--
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 +-
drivers/gpu/drm/i915/selftests/i915_perf.c | 6 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 8 +-
drivers/gpu/drm/i915/selftests/igt_spinner.c | 12 +--
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +-
92 files changed, 631 insertions(+), 631 deletions(-)
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
2021-05-27 18:16 [Intel-gfx] [PATCH 0/7] Finish conversion to GRAPHICS_VER Lucas De Marchi
@ 2021-05-27 18:16 ` Lucas De Marchi
2021-06-01 16:58 ` Matt Roper
2021-05-27 18:16 ` [Intel-gfx] [PATCH 2/7] drm/i915/gt: Add remaining conversions to GRAPHICS_VER Lucas De Marchi
` (9 subsequent siblings)
10 siblings, 1 reply; 20+ messages in thread
From: Lucas De Marchi @ 2021-05-27 18:16 UTC (permalink / raw)
To: intel-gfx
This was done by the following semantic patch:
@@ expression dev_priv, E; @@
- INTEL_GEN(dev_priv) == E
+ IS_GRAPHICS_VER(dev_priv, E)
@@ expression dev_priv; @@
- INTEL_GEN(dev_priv)
+ GRAPHICS_VER(dev_priv)
@@ expression dev_priv; expression E; @@
- IS_GEN(dev_priv, E)
+ IS_GRAPHICS_VER(dev_priv, E)
@@
expression dev_priv;
expression from, until;
@@
- IS_GEN_RANGE(dev_priv, from, until)
+ IS_GRAPHICS_RANGE(dev_priv, from, until)
@def@
expression E;
identifier id =~ "^gen$";
@@
- id = GRAPHICS_VER(E)
+ ver = GRAPHICS_VER(E)
@@
identifier def.id;
@@
- id
+ ver
It also takes care of renaming the variable we assign to GRAPHICS_VER()
so to use "ver" rather than "gen".
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 38 +++++------
drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 54 +++++++--------
.../drm/i915/gt/intel_execlists_submission.c | 18 ++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 18 ++---
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 34 +++++-----
drivers/gpu/drm/i915/gt/intel_gt.c | 27 ++++----
.../gpu/drm/i915/gt/intel_gt_clock_utils.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 6 +-
drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 10 +--
drivers/gpu/drm/i915/gt/intel_gtt.c | 14 ++--
drivers/gpu/drm/i915/gt/intel_llc.c | 6 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 46 ++++++-------
drivers/gpu/drm/i915/gt/intel_mocs.c | 8 +--
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 6 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 16 ++---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 12 ++--
.../gpu/drm/i915/gt/intel_ring_submission.c | 64 +++++++++---------
drivers/gpu/drm/i915/gt/intel_rps.c | 60 ++++++++---------
drivers/gpu/drm/i915/gt/intel_sseu.c | 14 ++--
drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +++++++++----------
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 6 +-
drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 4 +-
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +--
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 +--
drivers/gpu/drm/i915/gt/selftest_llc.c | 4 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c | 8 +--
drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rc6.c | 4 +-
.../drm/i915/gt/selftest_ring_submission.c | 6 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 16 ++---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 6 +-
.../gpu/drm/i915/gt/selftest_workarounds.c | 8 +--
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +--
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
44 files changed, 323 insertions(+), 322 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index d4f4452ce5ed..0389bceebd06 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -85,14 +85,14 @@ static int gen6_drpc(struct seq_file *m)
gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
- if (INTEL_GEN(i915) >= 9) {
+ if (GRAPHICS_VER(i915) >= 9) {
gen9_powergate_enable =
intel_uncore_read(uncore, GEN9_PG_ENABLE);
gen9_powergate_status =
intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
}
- if (INTEL_GEN(i915) <= 7)
+ if (GRAPHICS_VER(i915) <= 7)
sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
&rc6vids, NULL);
@@ -100,7 +100,7 @@ static int gen6_drpc(struct seq_file *m)
yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
seq_printf(m, "RC6 Enabled: %s\n",
yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
- if (INTEL_GEN(i915) >= 9) {
+ if (GRAPHICS_VER(i915) >= 9) {
seq_printf(m, "Render Well Gating Enabled: %s\n",
yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
seq_printf(m, "Media Well Gating Enabled: %s\n",
@@ -134,7 +134,7 @@ static int gen6_drpc(struct seq_file *m)
seq_printf(m, "Core Power Down: %s\n",
yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
- if (INTEL_GEN(i915) >= 9) {
+ if (GRAPHICS_VER(i915) >= 9) {
seq_printf(m, "Render Power Well: %s\n",
(gen9_powergate_status &
GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
@@ -150,7 +150,7 @@ static int gen6_drpc(struct seq_file *m)
print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
- if (INTEL_GEN(i915) <= 7) {
+ if (GRAPHICS_VER(i915) <= 7) {
seq_printf(m, "RC6 voltage: %dmV\n",
GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
seq_printf(m, "RC6+ voltage: %dmV\n",
@@ -250,7 +250,7 @@ static int frequency_show(struct seq_file *m, void *unused)
wakeref = intel_runtime_pm_get(uncore->rpm);
- if (IS_GEN(i915, 5)) {
+ if (GRAPHICS_VER(i915) == 5) {
u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
@@ -296,7 +296,7 @@ static int frequency_show(struct seq_file *m, void *unused)
seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
intel_gpu_freq(rps, rps->efficient_freq));
- } else if (INTEL_GEN(i915) >= 6) {
+ } else if (GRAPHICS_VER(i915) >= 6) {
u32 rp_state_limits;
u32 gt_perf_status;
u32 rp_state_cap;
@@ -321,7 +321,7 @@ static int frequency_show(struct seq_file *m, void *unused)
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
- if (INTEL_GEN(i915) >= 9) {
+ if (GRAPHICS_VER(i915) >= 9) {
reqf >>= 23;
} else {
reqf &= ~GEN6_TURBO_DISABLE;
@@ -354,7 +354,7 @@ static int frequency_show(struct seq_file *m, void *unused)
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
- if (INTEL_GEN(i915) >= 11) {
+ if (GRAPHICS_VER(i915) >= 11) {
pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
/*
@@ -363,7 +363,7 @@ static int frequency_show(struct seq_file *m, void *unused)
*/
pm_isr = 0;
pm_iir = 0;
- } else if (INTEL_GEN(i915) >= 8) {
+ } else if (GRAPHICS_VER(i915) >= 8) {
pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
@@ -386,14 +386,14 @@ static int frequency_show(struct seq_file *m, void *unused)
seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
pm_ier, pm_imr, pm_mask);
- if (INTEL_GEN(i915) <= 10)
+ if (GRAPHICS_VER(i915) <= 10)
seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
pm_isr, pm_iir);
seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
rps->pm_intrmsk_mbz);
seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
seq_printf(m, "Render p-state ratio: %d\n",
- (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
+ (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
seq_printf(m, "Render p-state VID: %d\n",
gt_perf_status & 0xff);
seq_printf(m, "Render p-state limit: %d\n",
@@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void *unused)
max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
rp_state_cap >> 16) & 0xff;
max_freq *= (IS_GEN9_BC(i915) ||
- INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
+ GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
intel_gpu_freq(rps, max_freq));
max_freq = (rp_state_cap & 0xff00) >> 8;
max_freq *= (IS_GEN9_BC(i915) ||
- INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
+ GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
intel_gpu_freq(rps, max_freq));
max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
rp_state_cap >> 0) & 0xff;
max_freq *= (IS_GEN9_BC(i915) ||
- INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
+ GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
intel_gpu_freq(rps, max_freq));
seq_printf(m, "Max overclocked frequency: %dMHz\n",
@@ -488,7 +488,7 @@ static int llc_show(struct seq_file *m, void *data)
{
struct intel_gt *gt = m->private;
struct drm_i915_private *i915 = gt->i915;
- const bool edram = INTEL_GEN(i915) > 8;
+ const bool edram = GRAPHICS_VER(i915) > 8;
struct intel_rps *rps = >->rps;
unsigned int max_gpu_freq, min_gpu_freq;
intel_wakeref_t wakeref;
@@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data)
min_gpu_freq = rps->min_freq;
max_gpu_freq = rps->max_freq;
- if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
+ if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
/* Convert GT frequency to 50 HZ units */
min_gpu_freq /= GEN9_FREQ_SCALER;
max_gpu_freq /= GEN9_FREQ_SCALER;
@@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data)
intel_gpu_freq(rps,
(gpu_freq *
(IS_GEN9_BC(i915) ||
- INTEL_GEN(i915) >= 10 ?
+ GRAPHICS_VER(i915) >= 10 ?
GEN9_FREQ_SCALER : 1))),
((ia_freq >> 0) & 0xff) * 100,
((ia_freq >> 8) & 0xff) * 100);
@@ -580,7 +580,7 @@ static int rps_boost_show(struct seq_file *m, void *data)
seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
- if (INTEL_GEN(i915) >= 6 && intel_rps_is_active(rps)) {
+ if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) {
struct intel_uncore *uncore = gt->uncore;
u32 rpup, rpupei;
u32 rpdown, rpdownei;
diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
index 9646200d2792..61383830505e 100644
--- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
@@ -74,7 +74,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
cmd = MI_FLUSH;
if (mode & EMIT_INVALIDATE) {
cmd |= MI_EXE_FLUSH;
- if (IS_G4X(rq->engine->i915) || IS_GEN(rq->engine->i915, 5))
+ if (IS_G4X(rq->engine->i915) || GRAPHICS_VER(rq->engine->i915) == 5)
cmd |= MI_INVALIDATE_ISP;
}
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 732c2ed1d933..94e0a5669f90 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -38,7 +38,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
* On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
* pipe control.
*/
- if (IS_GEN(rq->engine->i915, 9))
+ if (GRAPHICS_VER(rq->engine->i915) == 9)
vf_flush_wa = true;
/* WaForGAMHang:kbl */
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index e3a8924d2286..21c8b7350b7a 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -709,7 +709,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
*
* Gen12 has inherited the same read-only fault issue from gen11.
*/
- ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12);
+ ppgtt->vm.has_read_only = !IS_GRAPHICS_VER(gt->i915, 11, 12);
if (HAS_LMEM(gt->i915))
ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;
diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
index 8dfd8f656aaa..e86d8255feec 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
@@ -76,7 +76,7 @@ intel_context_reconfigure_sseu(struct intel_context *ce,
{
int ret;
- GEM_BUG_ON(INTEL_GEN(ce->engine->i915) < 8);
+ GEM_BUG_ON(GRAPHICS_VER(ce->engine->i915) < 8);
ret = intel_context_lock_pinned(ce);
if (ret)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3f9a811eb02b..54baf17b81b6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -240,10 +240,10 @@ void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
* Though they added more rings on g4x/ilk, they did not add
* per-engine HWSTAM until gen6.
*/
- if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS)
+ if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)
return;
- if (INTEL_GEN(engine->i915) >= 3)
+ if (GRAPHICS_VER(engine->i915) >= 3)
ENGINE_WRITE(engine, RING_HWSTAM, mask);
else
ENGINE_WRITE16(engine, RING_HWSTAM, mask);
@@ -315,7 +315,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
CONFIG_DRM_I915_TIMESLICE_DURATION;
/* Override to uninterruptible for OpenCL workloads. */
- if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS)
+ if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
engine->props.preempt_timeout_ms = 0;
engine->defaults = engine->props; /* never to change again */
@@ -352,8 +352,8 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
* HEVC support is present on first engine instance
* before Gen11 and on all instances afterwards.
*/
- if (INTEL_GEN(i915) >= 11 ||
- (INTEL_GEN(i915) >= 9 && engine->instance == 0))
+ if (GRAPHICS_VER(i915) >= 11 ||
+ (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
engine->uabi_capabilities |=
I915_VIDEO_CLASS_CAPABILITY_HEVC;
@@ -361,14 +361,14 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
* SFC block is present only on even logical engine
* instances.
*/
- if ((INTEL_GEN(i915) >= 11 &&
+ if ((GRAPHICS_VER(i915) >= 11 &&
(engine->gt->info.vdbox_sfc_access &
BIT(engine->instance))) ||
- (INTEL_GEN(i915) >= 9 && engine->instance == 0))
+ (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
engine->uabi_capabilities |=
I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
} else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
- if (INTEL_GEN(i915) >= 9)
+ if (GRAPHICS_VER(i915) >= 9)
engine->uabi_capabilities |=
I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
}
@@ -466,7 +466,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
- if (INTEL_GEN(i915) < 11)
+ if (GRAPHICS_VER(i915) < 11)
return info->engine_mask;
media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
@@ -492,7 +492,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
* hooked up to an SFC (Scaler & Format Converter) unit.
* In TGL each VDBOX has access to an SFC.
*/
- if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
+ if (GRAPHICS_VER(i915) >= 12 || logical_vdbox++ % 2 == 0)
gt->info.vdbox_sfc_access |= BIT(i);
}
drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
@@ -729,7 +729,7 @@ static int engine_setup_common(struct intel_engine_cs *engine)
intel_engine_init_whitelist(engine);
intel_engine_init_ctx_wa(engine);
- if (INTEL_GEN(engine->i915) >= 12)
+ if (GRAPHICS_VER(engine->i915) >= 12)
engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
return 0;
@@ -997,9 +997,9 @@ u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
u64 acthd;
- if (INTEL_GEN(i915) >= 8)
+ if (GRAPHICS_VER(i915) >= 8)
acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
- else if (INTEL_GEN(i915) >= 4)
+ else if (GRAPHICS_VER(i915) >= 4)
acthd = ENGINE_READ(engine, RING_ACTHD);
else
acthd = ENGINE_READ(engine, ACTHD);
@@ -1011,7 +1011,7 @@ u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
{
u64 bbaddr;
- if (INTEL_GEN(engine->i915) >= 8)
+ if (GRAPHICS_VER(engine->i915) >= 8)
bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
else
bbaddr = ENGINE_READ(engine, RING_BBADDR);
@@ -1058,7 +1058,7 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
{
int err = 0;
- if (INTEL_GEN(engine->i915) < 3)
+ if (GRAPHICS_VER(engine->i915) < 3)
return -ENODEV;
ENGINE_TRACE(engine, "\n");
@@ -1108,7 +1108,7 @@ read_subslice_reg(const struct intel_engine_cs *engine,
u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
enum forcewake_domains fw_domains;
- if (INTEL_GEN(i915) >= 11) {
+ if (GRAPHICS_VER(i915) >= 11) {
mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
} else {
@@ -1157,7 +1157,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
memset(instdone, 0, sizeof(*instdone));
- switch (INTEL_GEN(i915)) {
+ switch (GRAPHICS_VER(i915)) {
default:
instdone->instdone =
intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
@@ -1167,7 +1167,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
instdone->slice_common =
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
- if (INTEL_GEN(i915) >= 12) {
+ if (GRAPHICS_VER(i915) >= 12) {
instdone->slice_common_extra[0] =
intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
instdone->slice_common_extra[1] =
@@ -1230,7 +1230,7 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
idle = false;
/* No bit for gen2, so assume the CS parser is idle */
- if (INTEL_GEN(engine->i915) > 2 &&
+ if (GRAPHICS_VER(engine->i915) > 2 &&
!(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
idle = false;
@@ -1327,7 +1327,7 @@ void intel_engines_reset_default_submission(struct intel_gt *gt)
bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
{
- switch (INTEL_GEN(engine->i915)) {
+ switch (GRAPHICS_VER(engine->i915)) {
case 2:
return false; /* uses physical not virtual addresses */
case 3:
@@ -1432,7 +1432,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
struct intel_engine_execlists * const execlists = &engine->execlists;
u64 addr;
- if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
+ if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7))
drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
if (HAS_EXECLISTS(dev_priv)) {
drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
@@ -1449,13 +1449,13 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
ENGINE_READ(engine, RING_CTL),
ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
- if (INTEL_GEN(engine->i915) > 2) {
+ if (GRAPHICS_VER(engine->i915) > 2) {
drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
ENGINE_READ(engine, RING_MI_MODE),
ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
}
- if (INTEL_GEN(dev_priv) >= 6) {
+ if (GRAPHICS_VER(dev_priv) >= 6) {
drm_printf(m, "\tRING_IMR: 0x%08x\n",
ENGINE_READ(engine, RING_IMR));
drm_printf(m, "\tRING_ESR: 0x%08x\n",
@@ -1472,15 +1472,15 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
addr = intel_engine_get_last_batch_head(engine);
drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
upper_32_bits(addr), lower_32_bits(addr));
- if (INTEL_GEN(dev_priv) >= 8)
+ if (GRAPHICS_VER(dev_priv) >= 8)
addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
- else if (INTEL_GEN(dev_priv) >= 4)
+ else if (GRAPHICS_VER(dev_priv) >= 4)
addr = ENGINE_READ(engine, RING_DMA_FADD);
else
addr = ENGINE_READ(engine, DMA_FADD_I8XX);
drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
upper_32_bits(addr), lower_32_bits(addr));
- if (INTEL_GEN(dev_priv) >= 4) {
+ if (GRAPHICS_VER(dev_priv) >= 4) {
drm_printf(m, "\tIPEIR: 0x%08x\n",
ENGINE_READ(engine, RING_IPEIR));
drm_printf(m, "\tIPEHR: 0x%08x\n",
@@ -1559,7 +1559,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
}
rcu_read_unlock();
execlists_active_unlock_bh(execlists);
- } else if (INTEL_GEN(dev_priv) > 6) {
+ } else if (GRAPHICS_VER(dev_priv) > 6) {
drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
ENGINE_READ(engine, RING_PP_DIR_BASE));
drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 8db200422950..fc77592d88a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1847,7 +1847,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n",
head, upper_32_bits(csb), lower_32_bits(csb));
- if (INTEL_GEN(engine->i915) >= 12)
+ if (GRAPHICS_VER(engine->i915) >= 12)
promote = gen12_csb_parse(csb);
else
promote = gen8_csb_parse(csb);
@@ -2772,7 +2772,7 @@ static void enable_execlists(struct intel_engine_cs *engine)
intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
- if (INTEL_GEN(engine->i915) >= 11)
+ if (GRAPHICS_VER(engine->i915) >= 11)
mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
else
mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
@@ -3103,7 +3103,7 @@ static void execlists_park(struct intel_engine_cs *engine)
static bool can_preempt(struct intel_engine_cs *engine)
{
- if (INTEL_GEN(engine->i915) > 8)
+ if (GRAPHICS_VER(engine->i915) > 8)
return true;
/* GPGPU on bdw requires extra w/a; not implemented */
@@ -3156,13 +3156,13 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
engine->emit_flush = gen8_emit_flush_xcs;
engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
- if (INTEL_GEN(engine->i915) >= 12) {
+ if (GRAPHICS_VER(engine->i915) >= 12) {
engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;
engine->emit_flush = gen12_emit_flush_xcs;
}
engine->set_default_submission = execlists_set_default_submission;
- if (INTEL_GEN(engine->i915) < 11) {
+ if (GRAPHICS_VER(engine->i915) < 11) {
engine->irq_enable = gen8_logical_ring_enable_irq;
engine->irq_disable = gen8_logical_ring_disable_irq;
} else {
@@ -3195,7 +3195,7 @@ static void logical_ring_default_irqs(struct intel_engine_cs *engine)
{
unsigned int shift = 0;
- if (INTEL_GEN(engine->i915) < 11) {
+ if (GRAPHICS_VER(engine->i915) < 11) {
const u8 irq_shifts[] = {
[RCS0] = GEN8_RCS_IRQ_SHIFT,
[BCS0] = GEN8_BCS_IRQ_SHIFT,
@@ -3215,7 +3215,7 @@ static void logical_ring_default_irqs(struct intel_engine_cs *engine)
static void rcs_submission_override(struct intel_engine_cs *engine)
{
- switch (INTEL_GEN(engine->i915)) {
+ switch (GRAPHICS_VER(engine->i915)) {
case 12:
engine->emit_flush = gen12_emit_flush_rcs;
engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
@@ -3266,13 +3266,13 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
execlists->csb_write =
&engine->status_page.addr[intel_hws_csb_write_index(i915)];
- if (INTEL_GEN(i915) < 11)
+ if (GRAPHICS_VER(i915) < 11)
execlists->csb_size = GEN8_CSB_ENTRIES;
else
execlists->csb_size = GEN11_CSB_ENTRIES;
engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);
- if (INTEL_GEN(engine->i915) >= 11) {
+ if (GRAPHICS_VER(engine->i915) >= 11) {
execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 35069ca5d7de..19bd8856ce84 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -107,10 +107,10 @@ static bool needs_idle_maps(struct drm_i915_private *i915)
if (!intel_vtd_active())
return false;
- if (IS_GEN(i915, 5) && IS_MOBILE(i915))
+ if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
return true;
- if (IS_GEN(i915, 12))
+ if (GRAPHICS_VER(i915) == 12)
return true; /* XXX DMAR fault reason 7 */
return false;
@@ -176,7 +176,7 @@ static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
gen8_ggtt_invalidate(ggtt);
- if (INTEL_GEN(i915) >= 12)
+ if (GRAPHICS_VER(i915) >= 12)
intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
GEN12_GUC_TLB_INV_CR_INVALIDATE);
else
@@ -820,7 +820,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
* resort to an uncached mapping. The WC issue is easily caught by the
* readback check when writing GTT PTE entries.
*/
- if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
+ if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 10)
ggtt->gsm = ioremap(phys_addr, size);
else
ggtt->gsm = ioremap_wc(phys_addr, size);
@@ -1065,7 +1065,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.pte_encode = hsw_pte_encode;
else if (IS_VALLEYVIEW(i915))
ggtt->vm.pte_encode = byt_pte_encode;
- else if (INTEL_GEN(i915) >= 7)
+ else if (GRAPHICS_VER(i915) >= 7)
ggtt->vm.pte_encode = ivb_pte_encode;
else
ggtt->vm.pte_encode = snb_pte_encode;
@@ -1137,9 +1137,9 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
ggtt->vm.dma = i915->drm.dev;
dma_resv_init(&ggtt->vm.resv);
- if (INTEL_GEN(i915) <= 5)
+ if (GRAPHICS_VER(i915) <= 5)
ret = i915_gmch_probe(ggtt);
- else if (INTEL_GEN(i915) < 8)
+ else if (GRAPHICS_VER(i915) < 8)
ret = gen6_gmch_probe(ggtt);
else
ret = gen8_gmch_probe(ggtt);
@@ -1196,7 +1196,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
int i915_ggtt_enable_hw(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) < 6 && !intel_enable_gtt())
+ if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
return -EIO;
return 0;
@@ -1261,7 +1261,7 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt)
if (flush)
wbinvd_on_all_cpus();
- if (INTEL_GEN(ggtt->vm.i915) >= 8)
+ if (GRAPHICS_VER(ggtt->vm.i915) >= 8)
setup_private_pat(ggtt->vm.gt->uncore);
intel_ggtt_restore_fences(ggtt);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index 7bf84cd21543..cac7f3f44642 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -56,7 +56,7 @@ static void i965_write_fence_reg(struct i915_fence_reg *fence)
int fence_pitch_shift;
u64 val;
- if (INTEL_GEN(fence_to_i915(fence)) >= 6) {
+ if (GRAPHICS_VER(fence_to_i915(fence)) >= 6) {
fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
fence_reg_hi = FENCE_REG_GEN6_HI(fence->id);
fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
@@ -173,9 +173,9 @@ static void fence_write(struct i915_fence_reg *fence)
* and explicitly managed for internal users.
*/
- if (IS_GEN(i915, 2))
+ if (GRAPHICS_VER(i915) == 2)
i830_write_fence_reg(fence);
- else if (IS_GEN(i915, 3))
+ else if (GRAPHICS_VER(i915) == 3)
i915_write_fence_reg(fence);
else
i965_write_fence_reg(fence);
@@ -188,7 +188,7 @@ static void fence_write(struct i915_fence_reg *fence)
static bool gpu_uses_fence_registers(struct i915_fence_reg *fence)
{
- return INTEL_GEN(fence_to_i915(fence)) < 4;
+ return GRAPHICS_VER(fence_to_i915(fence)) < 4;
}
static int fence_update(struct i915_fence_reg *fence,
@@ -569,7 +569,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
- if (INTEL_GEN(i915) >= 8 || IS_VALLEYVIEW(i915)) {
+ if (GRAPHICS_VER(i915) >= 8 || IS_VALLEYVIEW(i915)) {
/*
* On BDW+, swizzling is not used. We leave the CPU memory
* controller in charge of optimizing memory accesses without
@@ -579,7 +579,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
*/
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
- } else if (INTEL_GEN(i915) >= 6) {
+ } else if (GRAPHICS_VER(i915) >= 6) {
if (i915->preserve_bios_swizzle) {
if (intel_uncore_read(uncore, DISP_ARB_CTL) &
DISP_TILE_SURFACE_SWIZZLING) {
@@ -611,14 +611,14 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
}
}
- } else if (IS_GEN(i915, 5)) {
+ } else if (GRAPHICS_VER(i915) == 5) {
/*
* On Ironlake whatever DRAM config, GPU always do
* same swizzling setup.
*/
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
swizzle_y = I915_BIT_6_SWIZZLE_9;
- } else if (IS_GEN(i915, 2)) {
+ } else if (GRAPHICS_VER(i915) == 2) {
/*
* As far as we know, the 865 doesn't have these bit 6
* swizzling issues.
@@ -697,7 +697,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
}
/* check for L-shaped memory aka modified enhanced addressing */
- if (IS_GEN(i915, 4) &&
+ if (GRAPHICS_VER(i915) == 4 &&
!(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
@@ -844,10 +844,10 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
if (!i915_ggtt_has_aperture(ggtt))
num_fences = 0;
- else if (INTEL_GEN(i915) >= 7 &&
+ else if (GRAPHICS_VER(i915) >= 7 &&
!(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
num_fences = 32;
- else if (INTEL_GEN(i915) >= 4 ||
+ else if (GRAPHICS_VER(i915) >= 4 ||
IS_I945G(i915) || IS_I945GM(i915) ||
IS_G33(i915) || IS_PINEVIEW(i915))
num_fences = 16;
@@ -895,29 +895,29 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore = gt->uncore;
- if (INTEL_GEN(i915) < 5 ||
+ if (GRAPHICS_VER(i915) < 5 ||
i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
return;
intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
- if (IS_GEN(i915, 5))
+ if (GRAPHICS_VER(i915) == 5)
return;
intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL);
- if (IS_GEN(i915, 6))
+ if (GRAPHICS_VER(i915) == 6)
intel_uncore_write(uncore,
ARB_MODE,
_MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
- else if (IS_GEN(i915, 7))
+ else if (GRAPHICS_VER(i915) == 7)
intel_uncore_write(uncore,
ARB_MODE,
_MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
- else if (IS_GEN(i915, 8))
+ else if (GRAPHICS_VER(i915) == 8)
intel_uncore_write(uncore,
GAMTARBMODE,
_MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
else
- MISSING_CASE(INTEL_GEN(i915));
+ MISSING_CASE(GRAPHICS_VER(i915));
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 8d77dcbad059..7f24301cef18 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -115,10 +115,10 @@ static void init_unused_rings(struct intel_gt *gt)
init_unused_ring(gt, SRB1_BASE);
init_unused_ring(gt, SRB2_BASE);
init_unused_ring(gt, SRB3_BASE);
- } else if (IS_GEN(i915, 2)) {
+ } else if (GRAPHICS_VER(i915) == 2) {
init_unused_ring(gt, SRB0_BASE);
init_unused_ring(gt, SRB1_BASE);
- } else if (IS_GEN(i915, 3)) {
+ } else if (GRAPHICS_VER(i915) == 3) {
init_unused_ring(gt, PRB1_BASE);
init_unused_ring(gt, PRB2_BASE);
}
@@ -135,7 +135,7 @@ int intel_gt_init_hw(struct intel_gt *gt)
/* Double layer security blanket, see i915_gem_init() */
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
- if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
+ if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
if (IS_HASWELL(i915))
@@ -208,10 +208,10 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
struct intel_uncore *uncore = gt->uncore;
u32 eir;
- if (!IS_GEN(i915, 2))
+ if (GRAPHICS_VER(i915) != 2)
clear_register(uncore, PGTBL_ER);
- if (INTEL_GEN(i915) < 4)
+ if (GRAPHICS_VER(i915) < 4)
clear_register(uncore, IPEIR(RENDER_RING_BASE));
else
clear_register(uncore, IPEIR_I965);
@@ -229,13 +229,13 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
I915_MASTER_ERROR_INTERRUPT);
}
- if (INTEL_GEN(i915) >= 12) {
+ if (GRAPHICS_VER(i915) >= 12) {
rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
- } else if (INTEL_GEN(i915) >= 8) {
+ } else if (GRAPHICS_VER(i915) >= 8) {
rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
- } else if (INTEL_GEN(i915) >= 6) {
+ } else if (GRAPHICS_VER(i915) >= 6) {
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -273,7 +273,7 @@ static void gen8_check_faults(struct intel_gt *gt)
i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
u32 fault;
- if (INTEL_GEN(gt->i915) >= 12) {
+ if (GRAPHICS_VER(gt->i915) >= 12) {
fault_reg = GEN12_RING_FAULT_REG;
fault_data0_reg = GEN12_FAULT_TLB_DATA0;
fault_data1_reg = GEN12_FAULT_TLB_DATA1;
@@ -313,9 +313,9 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
struct drm_i915_private *i915 = gt->i915;
/* From GEN8 onwards we only have one 'All Engine Fault Register' */
- if (INTEL_GEN(i915) >= 8)
+ if (GRAPHICS_VER(i915) >= 8)
gen8_check_faults(gt);
- else if (INTEL_GEN(i915) >= 6)
+ else if (GRAPHICS_VER(i915) >= 6)
gen6_check_faults(gt);
else
return;
@@ -367,7 +367,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
void intel_gt_chipset_flush(struct intel_gt *gt)
{
wmb();
- if (INTEL_GEN(gt->i915) < 6)
+ if (GRAPHICS_VER(gt->i915) < 6)
intel_gtt_chipset_flush();
}
@@ -591,7 +591,8 @@ int intel_gt_init(struct intel_gt *gt)
*/
intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
- err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K);
+ err = intel_gt_init_scratch(gt,
+ GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
if (err)
goto out_fw;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 582fcaee11aa..9f0e729d2d15 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -76,7 +76,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
u32 f19_2_mhz = 19200000;
u32 f24_mhz = 24000000;
- if (INTEL_GEN(uncore->i915) <= 4) {
+ if (GRAPHICS_VER(uncore->i915) <= 4) {
/*
* PRMs say:
*
@@ -85,7 +85,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
* (“CLKCFG”) MCHBAR register)
*/
return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
- } else if (INTEL_GEN(uncore->i915) <= 8) {
+ } else if (GRAPHICS_VER(uncore->i915) <= 8) {
/*
* PRMs say:
*
@@ -94,7 +94,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
* rolling over every 1.5 hours).
*/
return f12_5_mhz;
- } else if (INTEL_GEN(uncore->i915) <= 9) {
+ } else if (GRAPHICS_VER(uncore->i915) <= 9) {
u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
u32 freq = 0;
@@ -113,7 +113,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
}
return freq;
- } else if (INTEL_GEN(uncore->i915) <= 12) {
+ } else if (GRAPHICS_VER(uncore->i915) <= 12) {
u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
u32 freq = 0;
@@ -128,7 +128,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
} else {
u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
- if (INTEL_GEN(uncore->i915) <= 10)
+ if (GRAPHICS_VER(uncore->i915) <= 10)
freq = gen10_get_crystal_clock_freq(uncore, c0);
else
freq = gen11_get_crystal_clock_freq(uncore, c0);
@@ -211,7 +211,7 @@ u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns)
* frozen machine.
*/
val = div_u64_roundup(intel_gt_ns_to_clock_interval(gt, ns), 16);
- if (IS_GEN(gt->i915, 6))
+ if (GRAPHICS_VER(gt->i915) == 6)
val = div_u64_roundup(val, 25) * 25;
return val;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index d29126c458ba..1ec63cceabf6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -395,7 +395,7 @@ void gen5_gt_irq_reset(struct intel_gt *gt)
struct intel_uncore *uncore = gt->uncore;
GEN3_IRQ_RESET(uncore, GT);
- if (INTEL_GEN(gt->i915) >= 6)
+ if (GRAPHICS_VER(gt->i915) >= 6)
GEN3_IRQ_RESET(uncore, GEN6_PM);
}
@@ -413,14 +413,14 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt)
}
gt_irqs |= GT_RENDER_USER_INTERRUPT;
- if (IS_GEN(gt->i915, 5))
+ if (GRAPHICS_VER(gt->i915) == 5)
gt_irqs |= ILK_BSD_USER_INTERRUPT;
else
gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs);
- if (INTEL_GEN(gt->i915) >= 6) {
+ if (GRAPHICS_VER(gt->i915) >= 6) {
/*
* RPS interrupts will get enabled/disabled on demand when RPS
* itself is enabled/disabled.
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
index 811a11ed181c..fe51f894b073 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
@@ -16,10 +16,10 @@ static void write_pm_imr(struct intel_gt *gt)
u32 mask = gt->pm_imr;
i915_reg_t reg;
- if (INTEL_GEN(i915) >= 11) {
+ if (GRAPHICS_VER(i915) >= 11) {
reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
mask <<= 16; /* pm is in upper half */
- } else if (INTEL_GEN(i915) >= 8) {
+ } else if (GRAPHICS_VER(i915) >= 8) {
reg = GEN8_GT_IMR(2);
} else {
reg = GEN6_PMIMR;
@@ -61,7 +61,7 @@ void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask)
void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)
{
struct intel_uncore *uncore = gt->uncore;
- i915_reg_t reg = INTEL_GEN(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
+ i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
lockdep_assert_held(>->irq_lock);
@@ -77,10 +77,10 @@ static void write_pm_ier(struct intel_gt *gt)
u32 mask = gt->pm_ier;
i915_reg_t reg;
- if (INTEL_GEN(i915) >= 11) {
+ if (GRAPHICS_VER(i915) >= 11) {
reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
mask <<= 16; /* pm is in upper half */
- } else if (INTEL_GEN(i915) >= 8) {
+ } else if (GRAPHICS_VER(i915) >= 8) {
reg = GEN8_GT_IER(2);
} else {
reg = GEN6_PMIER;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 9b98f9d9faa3..b9c9993573ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -327,7 +327,7 @@ void gtt_write_workarounds(struct intel_gt *gt)
intel_uncore_write(uncore,
GEN8_L3_LRA_1_GPGPU,
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
- else if (INTEL_GEN(i915) >= 9 && INTEL_GEN(i915) <= 11)
+ else if (GRAPHICS_VER(i915) >= 9 && GRAPHICS_VER(i915) <= 11)
intel_uncore_write(uncore,
GEN8_L3_LRA_1_GPGPU,
GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
@@ -344,13 +344,13 @@ void gtt_write_workarounds(struct intel_gt *gt)
* driver.
*/
if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
- INTEL_GEN(i915) <= 10)
+ GRAPHICS_VER(i915) <= 10)
intel_uncore_rmw(uncore,
GEN8_GAMW_ECO_DEV_RW_IA,
0,
GAMW_ECO_ENABLE_64K_IPS_FIELD);
- if (IS_GEN_RANGE(i915, 8, 11)) {
+ if (IS_GRAPHICS_VER(i915, 8, 11)) {
bool can_use_gtt_cache = true;
/*
@@ -432,7 +432,7 @@ static void bdw_setup_private_ppat(struct intel_uncore *uncore)
GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
/* for scanout with eLLC */
- if (INTEL_GEN(i915) >= 9)
+ if (GRAPHICS_VER(i915) >= 9)
pat |= GEN8_PPAT(2, GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE);
else
pat |= GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
@@ -481,11 +481,11 @@ void setup_private_pat(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore->i915;
- GEM_BUG_ON(INTEL_GEN(i915) < 8);
+ GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
- if (INTEL_GEN(i915) >= 12)
+ if (GRAPHICS_VER(i915) >= 12)
tgl_setup_private_ppat(uncore);
- else if (INTEL_GEN(i915) >= 10)
+ else if (GRAPHICS_VER(i915) >= 10)
cnl_setup_private_ppat(uncore);
else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))
chv_setup_private_ppat(uncore);
diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
index 075d741644ae..eb1a15deed22 100644
--- a/drivers/gpu/drm/i915/gt/intel_llc.c
+++ b/drivers/gpu/drm/i915/gt/intel_llc.c
@@ -64,7 +64,7 @@ static bool get_ia_constants(struct intel_llc *llc,
consts->min_gpu_freq = rps->min_freq;
consts->max_gpu_freq = rps->max_freq;
- if (INTEL_GEN(i915) >= 9) {
+ if (GRAPHICS_VER(i915) >= 9) {
/* Convert GT frequency to 50 HZ units */
consts->min_gpu_freq /= GEN9_FREQ_SCALER;
consts->max_gpu_freq /= GEN9_FREQ_SCALER;
@@ -83,13 +83,13 @@ static void calc_ia_freq(struct intel_llc *llc,
const int diff = consts->max_gpu_freq - gpu_freq;
unsigned int ia_freq = 0, ring_freq = 0;
- if (INTEL_GEN(i915) >= 9) {
+ if (GRAPHICS_VER(i915) >= 9) {
/*
* ring_freq = 2 * GT. ring_freq is in 100MHz units
* No floor required for ring frequency on SKL.
*/
ring_freq = gpu_freq;
- } else if (INTEL_GEN(i915) >= 8) {
+ } else if (GRAPHICS_VER(i915) >= 8) {
/* max(2 * GT, DDR). NB: GT is 50MHz units */
ring_freq = max(consts->min_ring_freq, gpu_freq);
} else if (IS_HASWELL(i915)) {
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index aafe2a4df496..a27bac0a4bfb 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -47,7 +47,7 @@ static void set_offsets(u32 *regs,
*regs = MI_LOAD_REGISTER_IMM(count);
if (flags & POSTED)
*regs |= MI_LRI_FORCE_POSTED;
- if (INTEL_GEN(engine->i915) >= 11)
+ if (GRAPHICS_VER(engine->i915) >= 11)
*regs |= MI_LRI_LRM_CS_MMIO;
regs++;
@@ -70,7 +70,7 @@ static void set_offsets(u32 *regs,
if (close) {
/* Close the batch; used mainly by live_lrc_layout() */
*regs = MI_BATCH_BUFFER_END;
- if (INTEL_GEN(engine->i915) >= 10)
+ if (GRAPHICS_VER(engine->i915) >= 10)
*regs |= BIT(0);
}
}
@@ -498,22 +498,22 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
* addressing to automatic fixup the register state between the
* physical engines for virtual engine.
*/
- GEM_BUG_ON(INTEL_GEN(engine->i915) >= 12 &&
+ GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
!intel_engine_has_relative_mmio(engine));
if (engine->class == RENDER_CLASS) {
- if (INTEL_GEN(engine->i915) >= 12)
+ if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_rcs_offsets;
- else if (INTEL_GEN(engine->i915) >= 11)
+ else if (GRAPHICS_VER(engine->i915) >= 11)
return gen11_rcs_offsets;
- else if (INTEL_GEN(engine->i915) >= 9)
+ else if (GRAPHICS_VER(engine->i915) >= 9)
return gen9_rcs_offsets;
else
return gen8_rcs_offsets;
} else {
- if (INTEL_GEN(engine->i915) >= 12)
+ if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_xcs_offsets;
- else if (INTEL_GEN(engine->i915) >= 9)
+ else if (GRAPHICS_VER(engine->i915) >= 9)
return gen9_xcs_offsets;
else
return gen8_xcs_offsets;
@@ -522,9 +522,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
{
- if (INTEL_GEN(engine->i915) >= 12)
+ if (GRAPHICS_VER(engine->i915) >= 12)
return 0x60;
- else if (INTEL_GEN(engine->i915) >= 9)
+ else if (GRAPHICS_VER(engine->i915) >= 9)
return 0x54;
else if (engine->class == RENDER_CLASS)
return 0x58;
@@ -534,9 +534,9 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
{
- if (INTEL_GEN(engine->i915) >= 12)
+ if (GRAPHICS_VER(engine->i915) >= 12)
return 0x74;
- else if (INTEL_GEN(engine->i915) >= 9)
+ else if (GRAPHICS_VER(engine->i915) >= 9)
return 0x68;
else if (engine->class == RENDER_CLASS)
return 0xd8;
@@ -546,9 +546,9 @@ static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
static int lrc_ring_wa_bb_per_ctx(const struct intel_engine_cs *engine)
{
- if (INTEL_GEN(engine->i915) >= 12)
+ if (GRAPHICS_VER(engine->i915) >= 12)
return 0x12;
- else if (INTEL_GEN(engine->i915) >= 9 || engine->class == RENDER_CLASS)
+ else if (GRAPHICS_VER(engine->i915) >= 9 || engine->class == RENDER_CLASS)
return 0x18;
else
return -1;
@@ -581,9 +581,9 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
if (engine->class != RENDER_CLASS)
return -1;
- if (INTEL_GEN(engine->i915) >= 12)
+ if (GRAPHICS_VER(engine->i915) >= 12)
return 0xb6;
- else if (INTEL_GEN(engine->i915) >= 11)
+ else if (GRAPHICS_VER(engine->i915) >= 11)
return 0xaa;
else
return -1;
@@ -592,9 +592,9 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
static u32
lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
{
- switch (INTEL_GEN(engine->i915)) {
+ switch (GRAPHICS_VER(engine->i915)) {
default:
- MISSING_CASE(INTEL_GEN(engine->i915));
+ MISSING_CASE(GRAPHICS_VER(engine->i915));
fallthrough;
case 12:
return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
@@ -637,7 +637,7 @@ static void init_common_regs(u32 * const regs,
ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
if (inhibit)
ctl |= CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT;
- if (INTEL_GEN(engine->i915) < 11)
+ if (GRAPHICS_VER(engine->i915) < 11)
ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
CTX_CTRL_RS_CTX_ENABLE);
regs[CTX_CONTEXT_CONTROL] = ctl;
@@ -805,7 +805,7 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
context_size += I915_GTT_PAGE_SIZE; /* for redzone */
- if (INTEL_GEN(engine->i915) == 12) {
+ if (GRAPHICS_VER(engine->i915) == 12) {
ce->wa_bb_page = context_size / PAGE_SIZE;
context_size += PAGE_SIZE;
}
@@ -1114,7 +1114,7 @@ static u32 lrc_descriptor(const struct intel_context *ce)
desc <<= GEN8_CTX_ADDRESSING_MODE_SHIFT;
desc |= GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
- if (IS_GEN(ce->vm->i915, 8))
+ if (GRAPHICS_VER(ce->vm->i915) == 8)
desc |= GEN8_CTX_L3LLC_COHERENT;
return i915_ggtt_offset(ce->state) | desc;
@@ -1469,7 +1469,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
if (engine->class != RENDER_CLASS)
return;
- switch (INTEL_GEN(engine->i915)) {
+ switch (GRAPHICS_VER(engine->i915)) {
case 12:
case 11:
return;
@@ -1486,7 +1486,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
wa_bb_fn[1] = NULL;
break;
default:
- MISSING_CASE(INTEL_GEN(engine->i915));
+ MISSING_CASE(GRAPHICS_VER(engine->i915));
return;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index b14138fd505c..17848807f111 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -344,11 +344,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
table->size = ARRAY_SIZE(dg1_mocs_table);
table->table = dg1_mocs_table;
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
- } else if (INTEL_GEN(i915) >= 12) {
+ } else if (GRAPHICS_VER(i915) >= 12) {
table->size = ARRAY_SIZE(tgl_mocs_table);
table->table = tgl_mocs_table;
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
- } else if (IS_GEN(i915, 11)) {
+ } else if (GRAPHICS_VER(i915) == 11) {
table->size = ARRAY_SIZE(icl_mocs_table);
table->table = icl_mocs_table;
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
@@ -361,7 +361,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
table->table = broxton_mocs_table;
} else {
- drm_WARN_ONCE(&i915->drm, INTEL_GEN(i915) >= 9,
+ drm_WARN_ONCE(&i915->drm, GRAPHICS_VER(i915) >= 9,
"Platform that should have a MOCS table does not.\n");
return 0;
}
@@ -370,7 +370,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
return 0;
/* WaDisableSkipCaching:skl,bxt,kbl,glk */
- if (IS_GEN(i915, 9)) {
+ if (GRAPHICS_VER(i915) == 9) {
int i;
for (i = 0; i < table->size; i++)
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 4e3d80c2295c..3891c078906e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -146,9 +146,9 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
gtt_write_workarounds(gt);
- if (IS_GEN(i915, 6))
+ if (GRAPHICS_VER(i915) == 6)
gen6_ppgtt_enable(gt);
- else if (IS_GEN(i915, 7))
+ else if (GRAPHICS_VER(i915) == 7)
gen7_ppgtt_enable(gt);
return 0;
@@ -157,7 +157,7 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
static struct i915_ppgtt *
__ppgtt_create(struct intel_gt *gt)
{
- if (INTEL_GEN(gt->i915) < 8)
+ if (GRAPHICS_VER(gt->i915) < 8)
return gen6_ppgtt_create(gt);
else
return gen8_ppgtt_create(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 3b7e62debe7e..259d7eb4e165 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -109,7 +109,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
GEN9_MEDIA_PG_ENABLE |
GEN11_MEDIA_SAMPLER_PG_ENABLE;
- if (INTEL_GEN(gt->i915) >= 12) {
+ if (GRAPHICS_VER(gt->i915) >= 12) {
for (i = 0; i < I915_MAX_VCS; i++)
if (HAS_ENGINE(gt, _VCS(i)))
pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
@@ -126,7 +126,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
enum intel_engine_id id;
/* 2b: Program RC6 thresholds.*/
- if (INTEL_GEN(rc6_to_i915(rc6)) >= 10) {
+ if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 10) {
set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
} else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
@@ -249,9 +249,9 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
rc6vids = 0;
ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
&rc6vids, NULL);
- if (IS_GEN(i915, 6) && ret) {
+ if (GRAPHICS_VER(i915) == 6 && ret) {
drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
- } else if (IS_GEN(i915, 6) &&
+ } else if (GRAPHICS_VER(i915) == 6 &&
(GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
drm_dbg(&i915->drm,
"You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
@@ -515,7 +515,7 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
struct intel_uncore *uncore = rc6_to_uncore(rc6);
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
- if (INTEL_GEN(i915) >= 9)
+ if (GRAPHICS_VER(i915) >= 9)
set(uncore, GEN9_PG_ENABLE, 0);
set(uncore, GEN6_RC_CONTROL, 0);
set(uncore, GEN6_RC_STATE, 0);
@@ -575,13 +575,13 @@ void intel_rc6_enable(struct intel_rc6 *rc6)
chv_rc6_enable(rc6);
else if (IS_VALLEYVIEW(i915))
vlv_rc6_enable(rc6);
- else if (INTEL_GEN(i915) >= 11)
+ else if (GRAPHICS_VER(i915) >= 11)
gen11_rc6_enable(rc6);
- else if (INTEL_GEN(i915) >= 9)
+ else if (GRAPHICS_VER(i915) >= 9)
gen9_rc6_enable(rc6);
else if (IS_BROADWELL(i915))
gen8_rc6_enable(rc6);
- else if (INTEL_GEN(i915) >= 6)
+ else if (GRAPHICS_VER(i915) >= 6)
gen6_rc6_enable(rc6);
rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE;
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
index b03e197b1d99..b575cd6e0b7a 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
@@ -15,7 +15,7 @@ render_state_get_rodata(const struct intel_engine_cs *engine)
if (engine->class != RENDER_CLASS)
return NULL;
- switch (INTEL_GEN(engine->i915)) {
+ switch (GRAPHICS_VER(engine->i915)) {
case 6:
return &gen6_null_state;
case 7:
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index d5094be6d90f..27315d7f8935 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -565,7 +565,7 @@ static int gen8_reset_engines(struct intel_gt *gt,
*/
}
- if (INTEL_GEN(gt->i915) >= 11)
+ if (GRAPHICS_VER(gt->i915) >= 11)
ret = gen11_reset_engines(gt, engine_mask, retry);
else
ret = gen6_reset_engines(gt, engine_mask, retry);
@@ -594,17 +594,17 @@ static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
if (is_mock_gt(gt))
return mock_reset;
- else if (INTEL_GEN(i915) >= 8)
+ else if (GRAPHICS_VER(i915) >= 8)
return gen8_reset_engines;
- else if (INTEL_GEN(i915) >= 6)
+ else if (GRAPHICS_VER(i915) >= 6)
return gen6_reset_engines;
- else if (INTEL_GEN(i915) >= 5)
+ else if (GRAPHICS_VER(i915) >= 5)
return ilk_do_reset;
else if (IS_G4X(i915))
return g4x_do_reset;
else if (IS_G33(i915) || IS_PINEVIEW(i915))
return g33_do_reset;
- else if (INTEL_GEN(i915) >= 3)
+ else if (GRAPHICS_VER(i915) >= 3)
return i915_do_reset;
else
return NULL;
@@ -656,7 +656,7 @@ bool intel_has_reset_engine(const struct intel_gt *gt)
int intel_reset_guc(struct intel_gt *gt)
{
u32 guc_domain =
- INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
+ GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
int ret;
GEM_BUG_ON(!HAS_GT_UC(gt->i915));
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 2b6dffcc2262..0c423f096e2b 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -29,7 +29,7 @@ static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
* lost interrupts following a reset.
*/
if (engine->class == RENDER_CLASS) {
- if (INTEL_GEN(engine->i915) >= 6)
+ if (GRAPHICS_VER(engine->i915) >= 6)
mask &= ~BIT(0);
else
mask &= ~I915_USER_INTERRUPT;
@@ -43,7 +43,7 @@ static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
u32 addr;
addr = lower_32_bits(phys);
- if (INTEL_GEN(engine->i915) >= 4)
+ if (GRAPHICS_VER(engine->i915) >= 4)
addr |= (phys >> 28) & 0xf0;
intel_uncore_write(engine->uncore, HWS_PGA, addr);
@@ -71,7 +71,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
* The ring status page addresses are no longer next to the rest of
* the ring registers as of gen7.
*/
- if (IS_GEN(engine->i915, 7)) {
+ if (GRAPHICS_VER(engine->i915) == 7) {
switch (engine->id) {
/*
* No more rings exist on Gen7. Default case is only to shut up
@@ -93,7 +93,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
hwsp = VEBOX_HWS_PGA_GEN7;
break;
}
- } else if (IS_GEN(engine->i915, 6)) {
+ } else if (GRAPHICS_VER(engine->i915) == 6) {
hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
} else {
hwsp = RING_HWS_PGA(engine->mmio_base);
@@ -105,7 +105,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
static void flush_cs_tlb(struct intel_engine_cs *engine)
{
- if (!IS_GEN_RANGE(engine->i915, 6, 7))
+ if (!IS_GRAPHICS_VER(engine->i915, 6, 7))
return;
/* ring should be idle before issuing a sync flush*/
@@ -153,7 +153,7 @@ static void set_pp_dir(struct intel_engine_cs *engine)
ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm));
- if (INTEL_GEN(engine->i915) >= 7) {
+ if (GRAPHICS_VER(engine->i915) >= 7) {
ENGINE_WRITE_FW(engine,
RING_MODE_GEN7,
_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
@@ -229,7 +229,7 @@ static int xcs_resume(struct intel_engine_cs *engine)
5000, 0, NULL))
goto err;
- if (INTEL_GEN(engine->i915) > 2)
+ if (GRAPHICS_VER(engine->i915) > 2)
ENGINE_WRITE_FW(engine,
RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
@@ -646,9 +646,9 @@ static int mi_set_context(struct i915_request *rq,
u32 *cs;
len = 4;
- if (IS_GEN(i915, 7))
+ if (GRAPHICS_VER(i915) == 7)
len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
- else if (IS_GEN(i915, 5))
+ else if (GRAPHICS_VER(i915) == 5)
len += 2;
if (flags & MI_FORCE_RESTORE) {
GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
@@ -662,7 +662,7 @@ static int mi_set_context(struct i915_request *rq,
return PTR_ERR(cs);
/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
- if (IS_GEN(i915, 7)) {
+ if (GRAPHICS_VER(i915) == 7) {
*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
if (num_engines) {
struct intel_engine_cs *signaller;
@@ -678,7 +678,7 @@ static int mi_set_context(struct i915_request *rq,
GEN6_PSMI_SLEEP_MSG_DISABLE);
}
}
- } else if (IS_GEN(i915, 5)) {
+ } else if (GRAPHICS_VER(i915) == 5) {
/*
* This w/a is only listed for pre-production ilk a/b steppings,
* but is also mentioned for programming the powerctx. To be
@@ -716,7 +716,7 @@ static int mi_set_context(struct i915_request *rq,
*/
*cs++ = MI_NOOP;
- if (IS_GEN(i915, 7)) {
+ if (GRAPHICS_VER(i915) == 7) {
if (num_engines) {
struct intel_engine_cs *signaller;
i915_reg_t last_reg = {}; /* keep gcc quiet */
@@ -740,7 +740,7 @@ static int mi_set_context(struct i915_request *rq,
*cs++ = MI_NOOP;
}
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
- } else if (IS_GEN(i915, 5)) {
+ } else if (GRAPHICS_VER(i915) == 5) {
*cs++ = MI_SUSPEND_FLUSH;
}
@@ -1001,7 +1001,7 @@ static void ring_release(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
- drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) > 2 &&
+ drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) > 2 &&
(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
intel_engine_cleanup_common(engine);
@@ -1029,13 +1029,13 @@ static void setup_irq(struct intel_engine_cs *engine)
intel_engine_set_irq_handler(engine, irq_handler);
- if (INTEL_GEN(i915) >= 6) {
+ if (GRAPHICS_VER(i915) >= 6) {
engine->irq_enable = gen6_irq_enable;
engine->irq_disable = gen6_irq_disable;
- } else if (INTEL_GEN(i915) >= 5) {
+ } else if (GRAPHICS_VER(i915) >= 5) {
engine->irq_enable = gen5_irq_enable;
engine->irq_disable = gen5_irq_disable;
- } else if (INTEL_GEN(i915) >= 3) {
+ } else if (GRAPHICS_VER(i915) >= 3) {
engine->irq_enable = gen3_irq_enable;
engine->irq_disable = gen3_irq_disable;
} else {
@@ -1049,7 +1049,7 @@ static void setup_common(struct intel_engine_cs *engine)
struct drm_i915_private *i915 = engine->i915;
/* gen8+ are only supported with execlists */
- GEM_BUG_ON(INTEL_GEN(i915) >= 8);
+ GEM_BUG_ON(GRAPHICS_VER(i915) >= 8);
setup_irq(engine);
@@ -1070,14 +1070,14 @@ static void setup_common(struct intel_engine_cs *engine)
* engine->emit_init_breadcrumb().
*/
engine->emit_fini_breadcrumb = gen3_emit_breadcrumb;
- if (IS_GEN(i915, 5))
+ if (GRAPHICS_VER(i915) == 5)
engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
engine->set_default_submission = i9xx_set_default_submission;
- if (INTEL_GEN(i915) >= 6)
+ if (GRAPHICS_VER(i915) >= 6)
engine->emit_bb_start = gen6_emit_bb_start;
- else if (INTEL_GEN(i915) >= 4)
+ else if (GRAPHICS_VER(i915) >= 4)
engine->emit_bb_start = gen4_emit_bb_start;
else if (IS_I830(i915) || IS_I845G(i915))
engine->emit_bb_start = i830_emit_bb_start;
@@ -1094,16 +1094,16 @@ static void setup_rcs(struct intel_engine_cs *engine)
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
- if (INTEL_GEN(i915) >= 7) {
+ if (GRAPHICS_VER(i915) >= 7) {
engine->emit_flush = gen7_emit_flush_rcs;
engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs;
- } else if (IS_GEN(i915, 6)) {
+ } else if (GRAPHICS_VER(i915) == 6) {
engine->emit_flush = gen6_emit_flush_rcs;
engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs;
- } else if (IS_GEN(i915, 5)) {
+ } else if (GRAPHICS_VER(i915) == 5) {
engine->emit_flush = gen4_emit_flush_rcs;
} else {
- if (INTEL_GEN(i915) < 4)
+ if (GRAPHICS_VER(i915) < 4)
engine->emit_flush = gen2_emit_flush;
else
engine->emit_flush = gen4_emit_flush_rcs;
@@ -1118,20 +1118,20 @@ static void setup_vcs(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
- if (INTEL_GEN(i915) >= 6) {
+ if (GRAPHICS_VER(i915) >= 6) {
/* gen6 bsd needs a special wa for tail updates */
- if (IS_GEN(i915, 6))
+ if (GRAPHICS_VER(i915) == 6)
engine->set_default_submission = gen6_bsd_set_default_submission;
engine->emit_flush = gen6_emit_flush_vcs;
engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
- if (IS_GEN(i915, 6))
+ if (GRAPHICS_VER(i915) == 6)
engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
else
engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
} else {
engine->emit_flush = gen4_emit_flush_vcs;
- if (IS_GEN(i915, 5))
+ if (GRAPHICS_VER(i915) == 5)
engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
else
engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
@@ -1145,7 +1145,7 @@ static void setup_bcs(struct intel_engine_cs *engine)
engine->emit_flush = gen6_emit_flush_xcs;
engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
- if (IS_GEN(i915, 6))
+ if (GRAPHICS_VER(i915) == 6)
engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
else
engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
@@ -1155,7 +1155,7 @@ static void setup_vecs(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
- GEM_BUG_ON(INTEL_GEN(i915) < 7);
+ GEM_BUG_ON(GRAPHICS_VER(i915) < 7);
engine->emit_flush = gen6_emit_flush_xcs;
engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
@@ -1203,7 +1203,7 @@ static struct i915_vma *gen7_ctx_vma(struct intel_engine_cs *engine)
struct i915_vma *vma;
int size, err;
- if (!IS_GEN(engine->i915, 7) || engine->class != RENDER_CLASS)
+ if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS)
return 0;
err = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */);
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 97cab1b99871..06e9a8ed4e03 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -196,7 +196,7 @@ static void rps_reset_interrupts(struct intel_rps *rps)
struct intel_gt *gt = rps_to_gt(rps);
spin_lock_irq(>->irq_lock);
- if (INTEL_GEN(gt->i915) >= 11)
+ if (GRAPHICS_VER(gt->i915) >= 11)
gen11_rps_reset_interrupts(rps);
else
gen6_rps_reset_interrupts(rps);
@@ -630,7 +630,7 @@ static u32 rps_limits(struct intel_rps *rps, u8 val)
* frequency, if the down threshold expires in that window we will not
* receive a down interrupt.
*/
- if (INTEL_GEN(rps_to_i915(rps)) >= 9) {
+ if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) {
limits = rps->max_freq_softlimit << 23;
if (val <= rps->min_freq_softlimit)
limits |= rps->min_freq_softlimit << 14;
@@ -697,7 +697,7 @@ static void rps_set_power(struct intel_rps *rps, int new_power)
intel_gt_ns_to_pm_interval(gt, ei_down * threshold_down * 10));
set(uncore, GEN6_RP_CONTROL,
- (INTEL_GEN(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
+ (GRAPHICS_VER(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
GEN6_RP_MEDIA_HW_NORMAL_MODE |
GEN6_RP_MEDIA_IS_GFX |
GEN6_RP_ENABLE |
@@ -771,7 +771,7 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val)
struct drm_i915_private *i915 = rps_to_i915(rps);
u32 swreq;
- if (INTEL_GEN(i915) >= 9)
+ if (GRAPHICS_VER(i915) >= 9)
swreq = GEN9_FREQUENCY(val);
else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
swreq = HSW_FREQUENCY(val);
@@ -812,14 +812,14 @@ static int rps_set(struct intel_rps *rps, u8 val, bool update)
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
err = vlv_rps_set(rps, val);
- else if (INTEL_GEN(i915) >= 6)
+ else if (GRAPHICS_VER(i915) >= 6)
err = gen6_rps_set(rps, val);
else
err = gen5_rps_set(rps, val);
if (err)
return err;
- if (update && INTEL_GEN(i915) >= 6)
+ if (update && GRAPHICS_VER(i915) >= 6)
gen6_rps_set_thresholds(rps, val);
rps->last_freq = val;
@@ -853,7 +853,7 @@ void intel_rps_unpark(struct intel_rps *rps)
if (intel_rps_uses_timer(rps))
rps_start_timer(rps);
- if (IS_GEN(rps_to_i915(rps), 5))
+ if (GRAPHICS_VER(rps_to_i915(rps)) == 5)
gen5_rps_update(rps);
}
@@ -999,7 +999,7 @@ static void gen6_rps_init(struct intel_rps *rps)
rps->efficient_freq = rps->rp1_freq;
if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
- IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
+ IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
u32 ddcc_status = 0;
if (sandybridge_pcode_read(i915,
@@ -1012,7 +1012,7 @@ static void gen6_rps_init(struct intel_rps *rps)
rps->max_freq);
}
- if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
+ if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
/* Store the frequency values in 16.66 MHZ units, which is
* the natural hardware unit for SKL
*/
@@ -1048,7 +1048,7 @@ static bool gen9_rps_enable(struct intel_rps *rps)
struct intel_uncore *uncore = gt->uncore;
/* Program defaults and thresholds for RPS */
- if (IS_GEN(gt->i915, 9))
+ if (GRAPHICS_VER(gt->i915) == 9)
intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ,
GEN9_FREQUENCY(rps->rp1_freq));
@@ -1365,16 +1365,16 @@ void intel_rps_enable(struct intel_rps *rps)
enabled = chv_rps_enable(rps);
else if (IS_VALLEYVIEW(i915))
enabled = vlv_rps_enable(rps);
- else if (INTEL_GEN(i915) >= 9)
+ else if (GRAPHICS_VER(i915) >= 9)
enabled = gen9_rps_enable(rps);
- else if (INTEL_GEN(i915) >= 8)
+ else if (GRAPHICS_VER(i915) >= 8)
enabled = gen8_rps_enable(rps);
- else if (INTEL_GEN(i915) >= 6)
+ else if (GRAPHICS_VER(i915) >= 6)
enabled = gen6_rps_enable(rps);
else if (IS_IRONLAKE_M(i915))
enabled = gen5_rps_enable(rps);
else
- MISSING_CASE(INTEL_GEN(i915));
+ MISSING_CASE(GRAPHICS_VER(i915));
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
if (!enabled)
return;
@@ -1393,7 +1393,7 @@ void intel_rps_enable(struct intel_rps *rps)
if (has_busy_stats(rps))
intel_rps_set_timer(rps);
- else if (INTEL_GEN(i915) >= 6)
+ else if (GRAPHICS_VER(i915) >= 6)
intel_rps_set_interrupts(rps);
else
/* Ironlake currently uses intel_ips.ko */ {}
@@ -1414,7 +1414,7 @@ void intel_rps_disable(struct intel_rps *rps)
intel_rps_clear_interrupts(rps);
intel_rps_clear_timer(rps);
- if (INTEL_GEN(i915) >= 6)
+ if (GRAPHICS_VER(i915) >= 6)
gen6_rps_disable(rps);
else if (IS_IRONLAKE_M(i915))
gen5_rps_disable(rps);
@@ -1453,14 +1453,14 @@ int intel_gpu_freq(struct intel_rps *rps, int val)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
- if (INTEL_GEN(i915) >= 9)
+ if (GRAPHICS_VER(i915) >= 9)
return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
GEN9_FREQ_SCALER);
else if (IS_CHERRYVIEW(i915))
return chv_gpu_freq(rps, val);
else if (IS_VALLEYVIEW(i915))
return byt_gpu_freq(rps, val);
- else if (INTEL_GEN(i915) >= 6)
+ else if (GRAPHICS_VER(i915) >= 6)
return val * GT_FREQUENCY_MULTIPLIER;
else
return val;
@@ -1470,14 +1470,14 @@ int intel_freq_opcode(struct intel_rps *rps, int val)
{
struct drm_i915_private *i915 = rps_to_i915(rps);
- if (INTEL_GEN(i915) >= 9)
+ if (GRAPHICS_VER(i915) >= 9)
return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
GT_FREQUENCY_MULTIPLIER);
else if (IS_CHERRYVIEW(i915))
return chv_freq_opcode(rps, val);
else if (IS_VALLEYVIEW(i915))
return byt_freq_opcode(rps, val);
- else if (INTEL_GEN(i915) >= 6)
+ else if (GRAPHICS_VER(i915) >= 6)
return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
else
return val;
@@ -1770,7 +1770,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
spin_unlock(>->irq_lock);
}
- if (INTEL_GEN(gt->i915) >= 8)
+ if (GRAPHICS_VER(gt->i915) >= 8)
return;
if (pm_iir & PM_VEBOX_USER_INTERRUPT)
@@ -1833,7 +1833,7 @@ void intel_rps_init(struct intel_rps *rps)
chv_rps_init(rps);
else if (IS_VALLEYVIEW(i915))
vlv_rps_init(rps);
- else if (INTEL_GEN(i915) >= 6)
+ else if (GRAPHICS_VER(i915) >= 6)
gen6_rps_init(rps);
else if (IS_IRONLAKE_M(i915))
gen5_rps_init(rps);
@@ -1843,7 +1843,7 @@ void intel_rps_init(struct intel_rps *rps)
rps->min_freq_softlimit = rps->min_freq;
/* After setting max-softlimit, find the overclock max freq */
- if (IS_GEN(i915, 6) || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
+ if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
u32 params = 0;
sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS,
@@ -1872,16 +1872,16 @@ void intel_rps_init(struct intel_rps *rps)
*
* TODO: verify if this can be reproduced on VLV,CHV.
*/
- if (INTEL_GEN(i915) <= 7)
+ if (GRAPHICS_VER(i915) <= 7)
rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
- if (INTEL_GEN(i915) >= 8 && INTEL_GEN(i915) < 11)
+ if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) < 11)
rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
}
void intel_rps_sanitize(struct intel_rps *rps)
{
- if (INTEL_GEN(rps_to_i915(rps)) >= 6)
+ if (GRAPHICS_VER(rps_to_i915(rps)) >= 6)
rps_disable_interrupts(rps);
}
@@ -1892,11 +1892,11 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
cagf = (rpstat >> 8) & 0xff;
- else if (INTEL_GEN(i915) >= 9)
+ else if (GRAPHICS_VER(i915) >= 9)
cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
- else if (INTEL_GEN(i915) >= 6)
+ else if (GRAPHICS_VER(i915) >= 6)
cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
else
cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >>
@@ -1915,7 +1915,7 @@ static u32 read_cagf(struct intel_rps *rps)
vlv_punit_get(i915);
freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
vlv_punit_put(i915);
- } else if (INTEL_GEN(i915) >= 6) {
+ } else if (GRAPHICS_VER(i915) >= 6) {
freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
} else {
freq = intel_uncore_read(uncore, MEMSTAT_ILK);
@@ -1968,7 +1968,7 @@ void intel_rps_driver_register(struct intel_rps *rps)
* We only register the i915 ips part with intel-ips once everything is
* set up, to avoid intel-ips sneaking in and reading bogus values.
*/
- if (IS_GEN(gt->i915, 5)) {
+ if (GRAPHICS_VER(gt->i915) == 5) {
GEM_BUG_ON(ips_mchdev);
rcu_assign_pointer(ips_mchdev, gt->i915);
ips_ping_for_i915_load();
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 0d9f74aec8fe..367fd44b81c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -590,13 +590,13 @@ void intel_sseu_info_init(struct intel_gt *gt)
cherryview_sseu_info_init(gt);
else if (IS_BROADWELL(i915))
bdw_sseu_info_init(gt);
- else if (IS_GEN(i915, 9))
+ else if (GRAPHICS_VER(i915) == 9)
gen9_sseu_info_init(gt);
- else if (IS_GEN(i915, 10))
+ else if (GRAPHICS_VER(i915) == 10)
gen10_sseu_info_init(gt);
- else if (IS_GEN(i915, 11))
+ else if (GRAPHICS_VER(i915) == 11)
gen11_sseu_info_init(gt);
- else if (INTEL_GEN(i915) >= 12)
+ else if (GRAPHICS_VER(i915) >= 12)
gen12_sseu_info_init(gt);
}
@@ -613,7 +613,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
* No explicit RPCS request is needed to ensure full
* slice/subslice/EU enablement prior to Gen9.
*/
- if (INTEL_GEN(i915) < 9)
+ if (GRAPHICS_VER(i915) < 9)
return 0;
/*
@@ -651,7 +651,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
* subslices are enabled, or a count between one and four on the first
* slice.
*/
- if (IS_GEN(i915, 11) &&
+ if (GRAPHICS_VER(i915) == 11 &&
slices == 1 &&
subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
GEM_BUG_ON(subslices & 1);
@@ -669,7 +669,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
if (sseu->has_slice_pg) {
u32 mask, val = slices;
- if (INTEL_GEN(i915) >= 11) {
+ if (GRAPHICS_VER(i915) >= 11) {
mask = GEN11_RPCS_S_CNT_MASK;
val <<= GEN11_RPCS_S_CNT_SHIFT;
} else {
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 62cb9ee5bfc3..b62d1e31a645 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -699,9 +699,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
if (IS_DG1(i915))
dg1_ctx_workarounds_init(engine, wal);
- else if (IS_GEN(i915, 12))
+ else if (GRAPHICS_VER(i915) == 12)
gen12_ctx_workarounds_init(engine, wal);
- else if (IS_GEN(i915, 11))
+ else if (GRAPHICS_VER(i915) == 11)
icl_ctx_workarounds_init(engine, wal);
else if (IS_CANNONLAKE(i915))
cnl_ctx_workarounds_init(engine, wal);
@@ -719,14 +719,14 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
chv_ctx_workarounds_init(engine, wal);
else if (IS_BROADWELL(i915))
bdw_ctx_workarounds_init(engine, wal);
- else if (IS_GEN(i915, 7))
+ else if (GRAPHICS_VER(i915) == 7)
gen7_ctx_workarounds_init(engine, wal);
- else if (IS_GEN(i915, 6))
+ else if (GRAPHICS_VER(i915) == 6)
gen6_ctx_workarounds_init(engine, wal);
- else if (INTEL_GEN(i915) < 8)
+ else if (GRAPHICS_VER(i915) < 8)
;
else
- MISSING_CASE(INTEL_GEN(i915));
+ MISSING_CASE(GRAPHICS_VER(i915));
wa_init_finish(wal);
}
@@ -950,7 +950,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
unsigned int slice, subslice;
u32 l3_en, mcr, mcr_mask;
- GEM_BUG_ON(INTEL_GEN(i915) < 10);
+ GEM_BUG_ON(GRAPHICS_VER(i915) < 10);
/*
* WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
@@ -980,7 +980,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
* of every MMIO read.
*/
- if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
+ if (GRAPHICS_VER(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
u32 l3_fuse =
intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
GEN10_L3BANK_MASK;
@@ -1002,7 +1002,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
}
subslice--;
- if (INTEL_GEN(i915) >= 11) {
+ if (GRAPHICS_VER(i915) >= 11) {
mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
} else {
@@ -1171,9 +1171,9 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
dg1_gt_workarounds_init(i915, wal);
else if (IS_TIGERLAKE(i915))
tgl_gt_workarounds_init(i915, wal);
- else if (IS_GEN(i915, 12))
+ else if (GRAPHICS_VER(i915) == 12)
gen12_gt_workarounds_init(i915, wal);
- else if (IS_GEN(i915, 11))
+ else if (GRAPHICS_VER(i915) == 11)
icl_gt_workarounds_init(i915, wal);
else if (IS_CANNONLAKE(i915))
cnl_gt_workarounds_init(i915, wal);
@@ -1193,18 +1193,18 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
vlv_gt_workarounds_init(i915, wal);
else if (IS_IVYBRIDGE(i915))
ivb_gt_workarounds_init(i915, wal);
- else if (IS_GEN(i915, 6))
+ else if (GRAPHICS_VER(i915) == 6)
snb_gt_workarounds_init(i915, wal);
- else if (IS_GEN(i915, 5))
+ else if (GRAPHICS_VER(i915) == 5)
ilk_gt_workarounds_init(i915, wal);
else if (IS_G4X(i915))
g4x_gt_workarounds_init(i915, wal);
- else if (IS_GEN(i915, 4))
+ else if (GRAPHICS_VER(i915) == 4)
gen4_gt_workarounds_init(i915, wal);
- else if (INTEL_GEN(i915) <= 8)
+ else if (GRAPHICS_VER(i915) <= 8)
;
else
- MISSING_CASE(INTEL_GEN(i915));
+ MISSING_CASE(GRAPHICS_VER(i915));
}
void intel_gt_init_workarounds(struct drm_i915_private *i915)
@@ -1558,9 +1558,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
if (IS_DG1(i915))
dg1_whitelist_build(engine);
- else if (IS_GEN(i915, 12))
+ else if (GRAPHICS_VER(i915) == 12)
tgl_whitelist_build(engine);
- else if (IS_GEN(i915, 11))
+ else if (GRAPHICS_VER(i915) == 11)
icl_whitelist_build(engine);
else if (IS_CANNONLAKE(i915))
cnl_whitelist_build(engine);
@@ -1576,10 +1576,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
bxt_whitelist_build(engine);
else if (IS_SKYLAKE(i915))
skl_whitelist_build(engine);
- else if (INTEL_GEN(i915) <= 8)
+ else if (GRAPHICS_VER(i915) <= 8)
;
else
- MISSING_CASE(INTEL_GEN(i915));
+ MISSING_CASE(GRAPHICS_VER(i915));
wa_init_finish(w);
}
@@ -1695,7 +1695,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
ENABLE_SMALLPL);
}
- if (IS_GEN(i915, 11)) {
+ if (GRAPHICS_VER(i915) == 11) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
_3D_CHICKEN3,
@@ -1793,7 +1793,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
FF_DOP_CLOCK_GATE_DISABLE);
}
- if (IS_GEN_RANGE(i915, 9, 12)) {
+ if (IS_GRAPHICS_VER(i915, 9, 12)) {
/* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
wa_masked_en(wal,
GEN7_FF_SLICE_CS_CHICKEN1,
@@ -1817,7 +1817,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
}
- if (IS_GEN(i915, 9)) {
+ if (GRAPHICS_VER(i915) == 9) {
/* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
wa_masked_en(wal,
GEN9_CSFE_CHICKEN1_RCS,
@@ -1921,7 +1921,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
}
- if (IS_GEN(i915, 7)) {
+ if (GRAPHICS_VER(i915) == 7) {
/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
wa_masked_en(wal,
GFX_MODE_GEN7,
@@ -1953,7 +1953,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN6_WIZ_HASHING_16x4);
}
- if (IS_GEN_RANGE(i915, 6, 7))
+ if (IS_GRAPHICS_VER(i915, 6, 7))
/*
* We need to disable the AsyncFlip performance optimisations in
* order to use MI_WAIT_FOR_EVENT within the CS. It should
@@ -1965,7 +1965,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
MI_MODE,
ASYNC_FLIP_PERF_DISABLE);
- if (IS_GEN(i915, 6)) {
+ if (GRAPHICS_VER(i915) == 6) {
/*
* Required for the hardware to program scanline values for
* waiting
@@ -2019,14 +2019,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
CM0_STC_EVICT_DISABLE_LRA_SNB);
}
- if (IS_GEN_RANGE(i915, 4, 6))
+ if (IS_GRAPHICS_VER(i915, 4, 6))
/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
wa_add(wal, MI_MODE,
0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
/* XXX bit doesn't stick on Broadwater */
IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
- if (IS_GEN(i915, 4))
+ if (GRAPHICS_VER(i915) == 4)
/*
* Disable CONSTANT_BUFFER before it is loaded from the context
* image. For as it is loaded, it is executed and the stored
@@ -2058,7 +2058,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
static void
engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
- if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4))
+ if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4))
return;
if (engine->class == RENDER_CLASS)
@@ -2071,7 +2071,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
{
struct i915_wa_list *wal = &engine->wa_list;
- if (INTEL_GEN(engine->i915) < 4)
+ if (GRAPHICS_VER(engine->i915) < 4)
return;
wa_init_start(wal, "engine", engine->name);
@@ -2112,9 +2112,9 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
const struct mcr_range *mcr_ranges;
int i;
- if (INTEL_GEN(i915) >= 12)
+ if (GRAPHICS_VER(i915) >= 12)
mcr_ranges = mcr_ranges_gen12;
- else if (INTEL_GEN(i915) >= 8)
+ else if (GRAPHICS_VER(i915) >= 8)
mcr_ranges = mcr_ranges_gen8;
else
return false;
@@ -2143,7 +2143,7 @@ wa_list_srm(struct i915_request *rq,
u32 srm, *cs;
srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
- if (INTEL_GEN(i915) >= 8)
+ if (GRAPHICS_VER(i915) >= 8)
srm++;
for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 3453eb77c498..64abf5feabfa 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -52,7 +52,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
return PTR_ERR(cs);
cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
- if (INTEL_GEN(rq->engine->i915) >= 8)
+ if (GRAPHICS_VER(rq->engine->i915) >= 8)
cmd++;
*cs++ = cmd;
*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
@@ -125,7 +125,7 @@ static int perf_mi_bb_start(void *arg)
enum intel_engine_id id;
int err = 0;
- if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+ if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
return 0;
perf_begin(gt);
@@ -249,7 +249,7 @@ static int perf_mi_noop(void *arg)
enum intel_engine_id id;
int err = 0;
- if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+ if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
return 0;
perf_begin(gt);
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
index 2c898622bdfb..72cca3f0da21 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
@@ -198,7 +198,7 @@ static int live_engine_timestamps(void *arg)
* the same CS clock.
*/
- if (INTEL_GEN(gt->i915) < 8)
+ if (GRAPHICS_VER(gt->i915) < 8)
return 0;
for_each_engine(engine, gt, id) {
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
index 1f93591a8c69..ea2203af0764 100644
--- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
+++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
@@ -3269,7 +3269,7 @@ static int live_preempt_user(void *arg)
if (!intel_engine_has_preemption(engine))
continue;
- if (IS_GEN(gt->i915, 8) && engine->class != RENDER_CLASS)
+ if (GRAPHICS_VER(gt->i915) == 8 && engine->class != RENDER_CLASS)
continue; /* we need per-context GPR */
if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {
@@ -4293,7 +4293,7 @@ static int live_virtual_preserved(void *arg)
return 0;
/* As we use CS_GPR we cannot run before they existed on all engines. */
- if (INTEL_GEN(gt->i915) < 9)
+ if (GRAPHICS_VER(gt->i915) < 9)
return 0;
for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index c0845bf72dd3..b9441217ca3d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -74,10 +74,10 @@ static int live_gt_clocks(void *arg)
return 0;
}
- if (INTEL_GEN(gt->i915) < 4) /* Any CS_TIMESTAMP? */
+ if (GRAPHICS_VER(gt->i915) < 4) /* Any CS_TIMESTAMP? */
return 0;
- if (IS_GEN(gt->i915, 5))
+ if (GRAPHICS_VER(gt->i915) == 5)
/*
* XXX CS_TIMESTAMP low dword is dysfunctional?
*
@@ -86,7 +86,7 @@ static int live_gt_clocks(void *arg)
*/
return 0;
- if (IS_GEN(gt->i915, 4))
+ if (GRAPHICS_VER(gt->i915) == 4)
/*
* XXX CS_TIMESTAMP appears gibberish
*
@@ -105,7 +105,7 @@ static int live_gt_clocks(void *arg)
u64 time;
u64 dt;
- if (INTEL_GEN(engine->i915) < 7 && engine->id != RCS0)
+ if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0)
continue;
measure_clocks(engine, &cycles, &dt);
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 5b63d4df8c93..853246fad05f 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -180,7 +180,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
goto cancel_rq;
batch = h->batch;
- if (INTEL_GEN(gt->i915) >= 8) {
+ if (GRAPHICS_VER(gt->i915) >= 8) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = lower_32_bits(hws_address(hws, rq));
*batch++ = upper_32_bits(hws_address(hws, rq));
@@ -194,7 +194,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
*batch++ = lower_32_bits(vma->node.start);
*batch++ = upper_32_bits(vma->node.start);
- } else if (INTEL_GEN(gt->i915) >= 6) {
+ } else if (GRAPHICS_VER(gt->i915) >= 6) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = 0;
*batch++ = lower_32_bits(hws_address(hws, rq));
@@ -207,7 +207,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
*batch++ = MI_NOOP;
*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
*batch++ = lower_32_bits(vma->node.start);
- } else if (INTEL_GEN(gt->i915) >= 4) {
+ } else if (GRAPHICS_VER(gt->i915) >= 4) {
*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*batch++ = 0;
*batch++ = lower_32_bits(hws_address(hws, rq));
@@ -243,7 +243,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
}
flags = 0;
- if (INTEL_GEN(gt->i915) <= 5)
+ if (GRAPHICS_VER(gt->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
index 94006f117bbd..459b775f163a 100644
--- a/drivers/gpu/drm/i915/gt/selftest_llc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
@@ -44,7 +44,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
if (found != ia_freq) {
pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected CPU freq, found %d, expected %d\n",
gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
- intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
+ intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
found, ia_freq);
err = -EINVAL;
break;
@@ -54,7 +54,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
if (found != ring_freq) {
pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected ring freq, found %d, expected %d\n",
gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
- intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
+ intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
found, ring_freq);
err = -EINVAL;
break;
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index d8f6623524e8..3119016d9910 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -584,7 +584,7 @@ static int __live_lrc_gpr(struct intel_engine_cs *engine,
int err;
int n;
- if (INTEL_GEN(engine->i915) < 9 && engine->class != RENDER_CLASS)
+ if (GRAPHICS_VER(engine->i915) < 9 && engine->class != RENDER_CLASS)
return 0; /* GPR only on rcs0 for gen8 */
err = gpr_make_dirty(engine->kernel_context);
@@ -1389,10 +1389,10 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
static bool skip_isolation(const struct intel_engine_cs *engine)
{
- if (engine->class == COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) == 9)
+ if (engine->class == COPY_ENGINE_CLASS && GRAPHICS_VER(engine->i915) == 9)
return true;
- if (engine->class == RENDER_CLASS && INTEL_GEN(engine->i915) == 11)
+ if (engine->class == RENDER_CLASS && GRAPHICS_VER(engine->i915) == 11)
return true;
return false;
@@ -1551,7 +1551,7 @@ static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)
/* We use the already reserved extra page in context state */
if (!a->wa_bb_page) {
GEM_BUG_ON(b->wa_bb_page);
- GEM_BUG_ON(INTEL_GEN(engine->i915) == 12);
+ GEM_BUG_ON(GRAPHICS_VER(engine->i915) == 12);
goto unpin_b;
}
diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
index e55a887d11e2..b9bb0e6e97f7 100644
--- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -183,7 +183,7 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
* which only controls CPU initiated MMIO. Routing does not
* work for CS access so we cannot verify them on this path.
*/
- return INTEL_GEN(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
+ return GRAPHICS_VER(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
}
static int check_l3cc_table(struct intel_engine_cs *engine,
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 710f825f6e5a..8c70b7e12074 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -140,7 +140,7 @@ static const u32 *__live_rc6_ctx(struct intel_context *ce)
}
cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
- if (INTEL_GEN(rq->engine->i915) >= 8)
+ if (GRAPHICS_VER(rq->engine->i915) >= 8)
cmd++;
*cs++ = cmd;
@@ -193,7 +193,7 @@ int live_rc6_ctx_wa(void *arg)
int err = 0;
/* A read of CTX_INFO upsets rc6. Poke the bear! */
- if (INTEL_GEN(gt->i915) < 8)
+ if (GRAPHICS_VER(gt->i915) < 8)
return 0;
engines = randomised_engines(gt, &prng, &count);
diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
index c12e74171b63..041954408d0f 100644
--- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
@@ -41,10 +41,10 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
return ERR_CAST(cs);
}
- if (INTEL_GEN(engine->i915) >= 6) {
+ if (GRAPHICS_VER(engine->i915) >= 6) {
*cs++ = MI_STORE_DWORD_IMM_GEN4;
*cs++ = 0;
- } else if (INTEL_GEN(engine->i915) >= 4) {
+ } else if (GRAPHICS_VER(engine->i915) >= 4) {
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = 0;
} else {
@@ -266,7 +266,7 @@ static int live_ctx_switch_wa(void *arg)
if (!intel_engine_can_store_dword(engine))
continue;
- if (IS_GEN_RANGE(gt->i915, 4, 5))
+ if (IS_GRAPHICS_VER(gt->i915, 4, 5))
continue; /* MI_STORE_DWORD is privileged! */
saved_wa = fetch_and_zero(&engine->wa_ctx.vma);
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 3ca1bd5793c3..7ee2513e15f9 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -204,7 +204,7 @@ static void show_pstate_limits(struct intel_rps *rps)
i915_mmio_reg_offset(BXT_RP_STATE_CAP),
intel_uncore_read(rps_to_uncore(rps),
BXT_RP_STATE_CAP));
- } else if (IS_GEN(i915, 9)) {
+ } else if (GRAPHICS_VER(i915) == 9) {
pr_info("P_STATE_LIMITS[%x]: 0x%08x\n",
i915_mmio_reg_offset(GEN9_RP_STATE_LIMITS),
intel_uncore_read(rps_to_uncore(rps),
@@ -222,7 +222,7 @@ int live_rps_clock_interval(void *arg)
struct igt_spinner spin;
int err = 0;
- if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
+ if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
return 0;
if (igt_spinner_init(&spin, gt))
@@ -506,7 +506,7 @@ static void show_pcu_config(struct intel_rps *rps)
min_gpu_freq = rps->min_freq;
max_gpu_freq = rps->max_freq;
- if (INTEL_GEN(i915) >= 9) {
+ if (GRAPHICS_VER(i915) >= 9) {
/* Convert GT frequency to 50 HZ units */
min_gpu_freq /= GEN9_FREQ_SCALER;
max_gpu_freq /= GEN9_FREQ_SCALER;
@@ -614,7 +614,7 @@ int live_rps_frequency_cs(void *arg)
if (!intel_rps_is_enabled(rps))
return 0;
- if (INTEL_GEN(gt->i915) < 8) /* for CS simplicity */
+ if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
return 0;
if (CPU_LATENCY >= 0)
@@ -755,7 +755,7 @@ int live_rps_frequency_srm(void *arg)
if (!intel_rps_is_enabled(rps))
return 0;
- if (INTEL_GEN(gt->i915) < 8) /* for CS simplicity */
+ if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
return 0;
if (CPU_LATENCY >= 0)
@@ -1031,7 +1031,7 @@ int live_rps_interrupt(void *arg)
* First, let's check whether or not we are receiving interrupts.
*/
- if (!intel_rps_has_interrupts(rps) || INTEL_GEN(gt->i915) < 6)
+ if (!intel_rps_has_interrupts(rps) || GRAPHICS_VER(gt->i915) < 6)
return 0;
intel_gt_pm_get(gt);
@@ -1136,7 +1136,7 @@ int live_rps_power(void *arg)
* that theory.
*/
- if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
+ if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
return 0;
if (!librapl_supported(gt->i915))
@@ -1240,7 +1240,7 @@ int live_rps_dynamic(void *arg)
* moving parts into dynamic reclocking based on load.
*/
- if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
+ if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
return 0;
if (igt_spinner_init(&spin, gt))
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index 9adbd9d147be..64da0c91dec1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -457,12 +457,12 @@ static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
if (IS_ERR(cs))
return PTR_ERR(cs);
- if (INTEL_GEN(rq->engine->i915) >= 8) {
+ if (GRAPHICS_VER(rq->engine->i915) >= 8) {
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = addr;
*cs++ = 0;
*cs++ = value;
- } else if (INTEL_GEN(rq->engine->i915) >= 4) {
+ } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = 0;
*cs++ = addr;
@@ -992,7 +992,7 @@ static int live_hwsp_read(void *arg)
* even across multiple wraps.
*/
- if (INTEL_GEN(gt->i915) < 8) /* CS convenience [SRM/LRM] */
+ if (GRAPHICS_VER(gt->i915) < 8) /* CS convenience [SRM/LRM] */
return 0;
tl = intel_timeline_create(gt);
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 64937ec3f2dc..c30754daf4b1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -145,7 +145,7 @@ read_nonprivs(struct intel_context *ce)
goto err_req;
srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
- if (INTEL_GEN(engine->i915) >= 8)
+ if (GRAPHICS_VER(engine->i915) >= 8)
srm++;
cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
@@ -546,7 +546,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
srm = MI_STORE_REGISTER_MEM;
lrm = MI_LOAD_REGISTER_MEM;
- if (INTEL_GEN(engine->i915) >= 8)
+ if (GRAPHICS_VER(engine->i915) >= 8)
lrm++, srm++;
pr_debug("%s: Writing garbage to %x\n",
@@ -749,7 +749,7 @@ static int live_dirty_whitelist(void *arg)
/* Can the user write to the whitelisted registers? */
- if (INTEL_GEN(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */
+ if (GRAPHICS_VER(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */
return 0;
for_each_engine(engine, gt, id) {
@@ -829,7 +829,7 @@ static int read_whitelisted_registers(struct intel_context *ce,
goto err_req;
srm = MI_STORE_REGISTER_MEM;
- if (INTEL_GEN(engine->i915) >= 8)
+ if (GRAPHICS_VER(engine->i915) >= 8)
srm++;
cs = intel_ring_begin(rq, 4 * engine->whitelist.count);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index adae04c47aab..84f806911370 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -60,7 +60,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
enum forcewake_domains fw_domains = 0;
unsigned int i;
- if (INTEL_GEN(gt->i915) >= 11) {
+ if (GRAPHICS_VER(gt->i915) >= 11) {
guc->send_regs.base =
i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
@@ -176,7 +176,7 @@ void intel_guc_init_early(struct intel_guc *guc)
mutex_init(&guc->send_mutex);
spin_lock_init(&guc->irq_lock);
- if (INTEL_GEN(i915) >= 11) {
+ if (GRAPHICS_VER(i915) >= 11) {
guc->notify_reg = GEN11_GUC_HOST_INTERRUPT;
guc->interrupts.reset = gen11_reset_guc_interrupts;
guc->interrupts.enable = gen11_enable_guc_interrupts;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 17526717368c..b32fafba2a90 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -162,7 +162,7 @@ static void __guc_ads_init(struct intel_guc *guc)
blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK] =
gt->info.vdbox_sfc_access;
- if (INTEL_GEN(i915) >= 12 && !IS_DGFX(i915)) {
+ if (GRAPHICS_VER(i915) >= 12 && !IS_DGFX(i915)) {
u32 distdbreg = intel_uncore_read(gt->uncore,
GEN12_DIST_DBS_POPULATED);
blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI] =
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 2270d6b3b272..76fe766ad1bc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -30,7 +30,7 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
else
intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
- if (IS_GEN(uncore->i915, 9)) {
+ if (GRAPHICS_VER(uncore->i915) == 9) {
/* DOP Clock Gating Enable for GuC clocks */
intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 335719f17490..541f6da1ec47 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -438,7 +438,7 @@ static void guc_interrupts_capture(struct intel_gt *gt)
u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
u32 dmask = irqs << 16 | irqs;
- GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
+ GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
/* Don't handle the ctx switch interrupt in GuC submission mode */
intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask, 0);
@@ -451,7 +451,7 @@ static void guc_interrupts_release(struct intel_gt *gt)
u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
u32 dmask = irqs << 16 | irqs;
- GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
+ GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
/* Handle ctx switch interrupts again */
intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0, dmask);
@@ -648,7 +648,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
engine->emit_flush = gen8_emit_flush_xcs;
engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
- if (INTEL_GEN(engine->i915) >= 12) {
+ if (GRAPHICS_VER(engine->i915) >= 12) {
engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;
engine->emit_flush = gen12_emit_flush_xcs;
}
@@ -670,7 +670,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
static void rcs_submission_override(struct intel_engine_cs *engine)
{
- switch (INTEL_GEN(engine->i915)) {
+ switch (GRAPHICS_VER(engine->i915)) {
case 12:
engine->emit_flush = gen12_emit_flush_rcs;
engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
@@ -700,7 +700,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
* The setup relies on several assumptions (e.g. irqs always enabled)
* that are only valid on gen11+
*/
- GEM_BUG_ON(INTEL_GEN(i915) < 11);
+ GEM_BUG_ON(GRAPHICS_VER(i915) < 11);
tasklet_setup(&engine->execlists.tasklet, guc_submission_tasklet);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 56d2144dc6a0..fc5387b410a2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -43,7 +43,7 @@ void intel_huc_init_early(struct intel_huc *huc)
intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC);
- if (INTEL_GEN(i915) >= 11) {
+ if (GRAPHICS_VER(i915) >= 11) {
huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
huc->status.mask = HUC_LOAD_SUCCESSFUL;
huc->status.value = HUC_LOAD_SUCCESSFUL;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 6abb8f2dc33d..6c2bf4b6bc10 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -23,7 +23,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
return;
/* Don't enable GuC/HuC on pre-Gen12 */
- if (INTEL_GEN(i915) < 12) {
+ if (GRAPHICS_VER(i915) < 12) {
i915->params.enable_guc = 0;
return;
}
@@ -467,7 +467,7 @@ static int __uc_init_hw(struct intel_uc *uc)
/* WaEnableuKernelHeaderValidFix:skl */
/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
- if (IS_GEN(i915, 9))
+ if (GRAPHICS_VER(i915) == 9)
attempts = 3;
else
attempts = 1;
--
2.31.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 2/7] drm/i915/gt: Add remaining conversions to GRAPHICS_VER
2021-05-27 18:16 [Intel-gfx] [PATCH 0/7] Finish conversion to GRAPHICS_VER Lucas De Marchi
2021-05-27 18:16 ` [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER Lucas De Marchi
@ 2021-05-27 18:16 ` Lucas De Marchi
2021-05-27 18:16 ` [Intel-gfx] [PATCH 3/7] drm/i915/gem: replace IS_GEN and friends with IS_GRAPHICS_VER Lucas De Marchi
` (8 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2021-05-27 18:16 UTC (permalink / raw)
To: intel-gfx
For some reason coccinelle misses a few cases in gt with calls to
INTEL_GEN()/IS_GEN(). Do a manual conversion for those.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 4 ++--
drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 6 +++---
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index 0389bceebd06..4270b5a34a83 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -230,7 +230,7 @@ static int drpc_show(struct seq_file *m, void *unused)
with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
err = vlv_drpc(m);
- else if (INTEL_GEN(i915) >= 6)
+ else if (GRAPHICS_VER(i915) >= 6)
err = gen6_drpc(m);
else
err = ilk_drpc(m);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 9ef349cd5cea..e113f93b3274 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -606,10 +606,10 @@ intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
}
#define instdone_has_slice(dev_priv___, sseu___, slice___) \
- ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & BIT(slice___))
+ ((GRAPHICS_VER(dev_priv___) == 7 ? 1 : ((sseu___)->slice_mask)) & BIT(slice___))
#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
- (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
+ (GRAPHICS_VER(dev_priv__) == 7 ? (1 & BIT(subslice__)) : \
intel_sseu_has_subslice(sseu__, 0, subslice__))
#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
index 51780282d872..714fe8495775 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
@@ -248,7 +248,7 @@ int intel_sseu_status(struct seq_file *m, struct intel_gt *gt)
struct sseu_dev_info sseu;
intel_wakeref_t wakeref;
- if (INTEL_GEN(i915) < 8)
+ if (GRAPHICS_VER(i915) < 8)
return -ENODEV;
seq_puts(m, "SSEU Device Info\n");
@@ -265,9 +265,9 @@ int intel_sseu_status(struct seq_file *m, struct intel_gt *gt)
cherryview_sseu_device_status(gt, &sseu);
else if (IS_BROADWELL(i915))
bdw_sseu_device_status(gt, &sseu);
- else if (IS_GEN(i915, 9))
+ else if (GRAPHICS_VER(i915) == 9)
gen9_sseu_device_status(gt, &sseu);
- else if (INTEL_GEN(i915) >= 10)
+ else if (GRAPHICS_VER(i915) >= 10)
gen10_sseu_device_status(gt, &sseu);
}
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 3/7] drm/i915/gem: replace IS_GEN and friends with IS_GRAPHICS_VER
2021-05-27 18:16 [Intel-gfx] [PATCH 0/7] Finish conversion to GRAPHICS_VER Lucas De Marchi
2021-05-27 18:16 ` [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER Lucas De Marchi
2021-05-27 18:16 ` [Intel-gfx] [PATCH 2/7] drm/i915/gt: Add remaining conversions to GRAPHICS_VER Lucas De Marchi
@ 2021-05-27 18:16 ` Lucas De Marchi
2021-05-27 18:16 ` [Intel-gfx] [PATCH 4/7] drm/i915/gvt: " Lucas De Marchi
` (7 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2021-05-27 18:16 UTC (permalink / raw)
To: intel-gfx
This was done by the following semantic patch:
@@ expression dev_priv, E; @@
- INTEL_GEN(dev_priv) == E
+ IS_GRAPHICS_VER(dev_priv, E)
@@ expression dev_priv; @@
- INTEL_GEN(dev_priv)
+ GRAPHICS_VER(dev_priv)
@@ expression dev_priv; expression E; @@
- IS_GEN(dev_priv, E)
+ IS_GRAPHICS_VER(dev_priv, E)
@@
expression dev_priv;
expression from, until;
@@
- IS_GEN_RANGE(dev_priv, from, until)
+ IS_GRAPHICS_RANGE(dev_priv, from, until)
@def@
expression E;
identifier id =~ "^gen$";
@@
- id = GRAPHICS_VER(E)
+ ver = GRAPHICS_VER(E)
@@
identifier def.id;
@@
- id
+ ver
It also takes care of renaming the variable we assign to GRAPHICS_VER()
so to use "ver" rather than "gen".
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +++---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 10 +++++-----
drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 8 ++++----
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 16 ++++++++--------
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 12 ++++++------
.../drm/i915/gem/selftests/i915_gem_client_blt.c | 10 +++++-----
.../drm/i915/gem/selftests/i915_gem_coherency.c | 4 ++--
.../drm/i915/gem/selftests/i915_gem_context.c | 16 ++++++++--------
.../gpu/drm/i915/gem/selftests/i915_gem_mman.c | 14 +++++++-------
.../gpu/drm/i915/gem/selftests/igt_gem_utils.c | 10 +++++-----
10 files changed, 53 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 188dee13e017..7720b8c22c81 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1190,7 +1190,7 @@ static void set_ppgtt_barrier(void *data)
{
struct i915_address_space *old = data;
- if (INTEL_GEN(old->i915) < 8)
+ if (GRAPHICS_VER(old->i915) < 8)
gen6_ppgtt_unpin_all(i915_vm_to_ppgtt(old));
i915_vm_close(old);
@@ -1436,7 +1436,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt,
context->max_eus_per_subslice = user->max_eus_per_subslice;
/* Part specific restrictions. */
- if (IS_GEN(i915, 11)) {
+ if (GRAPHICS_VER(i915) == 11) {
unsigned int hw_s = hweight8(device->slice_mask);
unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);
unsigned int req_s = hweight8(context->slice_mask);
@@ -1503,7 +1503,7 @@ static int set_sseu(struct i915_gem_context *ctx,
if (args->size < sizeof(user_sseu))
return -EINVAL;
- if (!IS_GEN(i915, 11))
+ if (GRAPHICS_VER(i915) != 11)
return -ENODEV;
if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 297143511f99..24c0582e46fb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -500,7 +500,7 @@ eb_validate_vma(struct i915_execbuffer *eb,
* also covers all platforms with local memory.
*/
if (entry->relocation_count &&
- INTEL_GEN(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
+ GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
return -EINVAL;
if (unlikely(entry->flags & eb->invalid_flags))
@@ -1439,7 +1439,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
static bool reloc_can_use_engine(const struct intel_engine_cs *engine)
{
- return engine->class != VIDEO_DECODE_CLASS || !IS_GEN(engine->i915, 6);
+ return engine->class != VIDEO_DECODE_CLASS || GRAPHICS_VER(engine->i915) != 6;
}
static u32 *reloc_gpu(struct i915_execbuffer *eb,
@@ -1671,7 +1671,7 @@ eb_relocate_entry(struct i915_execbuffer *eb,
* batchbuffers.
*/
if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
- IS_GEN(eb->i915, 6)) {
+ GRAPHICS_VER(eb->i915) == 6) {
err = i915_vma_bind(target->vma,
target->vma->obj->cache_level,
PIN_GLOBAL, NULL);
@@ -2332,7 +2332,7 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
u32 *cs;
int i;
- if (!IS_GEN(rq->engine->i915, 7) || rq->engine->id != RCS0) {
+ if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {
drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");
return -EINVAL;
}
@@ -3375,7 +3375,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
eb.batch_flags = 0;
if (args->flags & I915_EXEC_SECURE) {
- if (INTEL_GEN(i915) >= 11)
+ if (GRAPHICS_VER(i915) >= 11)
return -ENODEV;
/* Return -EPERM to trigger fallback code on old binaries. */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
index df8e8c18c6c9..3e28c68fda3e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
@@ -72,7 +72,7 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
- if (INTEL_GEN(i915) >= 8) {
+ if (GRAPHICS_VER(i915) >= 8) {
*cmd++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2);
*cmd++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
*cmd++ = 0;
@@ -232,7 +232,7 @@ static bool wa_1209644611_applies(struct drm_i915_private *i915, u32 size)
{
u32 height = size >> PAGE_SHIFT;
- if (!IS_GEN(i915, 11))
+ if (GRAPHICS_VER(i915) != 11)
return false;
return height % 4 == 3 && height <= 8;
@@ -297,7 +297,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
size = min_t(u64, rem, block_size);
GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
- if (INTEL_GEN(i915) >= 9 &&
+ if (GRAPHICS_VER(i915) >= 9 &&
!wa_1209644611_applies(i915, size)) {
*cmd++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);
*cmd++ = BLT_DEPTH_32 | PAGE_SIZE;
@@ -309,7 +309,7 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
*cmd++ = PAGE_SIZE;
*cmd++ = lower_32_bits(src_offset);
*cmd++ = upper_32_bits(src_offset);
- } else if (INTEL_GEN(i915) >= 8) {
+ } else if (GRAPHICS_VER(i915) >= 8) {
*cmd++ = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (10 - 2);
*cmd++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
*cmd++ = 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index b5553fc3ac4d..6022b9a86a06 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -38,7 +38,7 @@ int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *i915,
return -ENODEV;
/* WaSkipStolenMemoryFirstPage:bdw+ */
- if (INTEL_GEN(i915) >= 8 && start < 4096)
+ if (GRAPHICS_VER(i915) >= 8 && start < 4096)
start = 4096;
mutex_lock(&i915->mm.stolen_lock);
@@ -84,14 +84,14 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
*/
/* Make sure we don't clobber the GTT if it's within stolen memory */
- if (INTEL_GEN(i915) <= 4 &&
+ if (GRAPHICS_VER(i915) <= 4 &&
!IS_G33(i915) && !IS_PINEVIEW(i915) && !IS_G4X(i915)) {
struct resource stolen[2] = {*dsm, *dsm};
struct resource ggtt_res;
resource_size_t ggtt_start;
ggtt_start = intel_uncore_read(uncore, PGTBL_CTL);
- if (IS_GEN(i915, 4))
+ if (GRAPHICS_VER(i915) == 4)
ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) |
(ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28;
else
@@ -156,7 +156,7 @@ static int i915_adjust_stolen(struct drm_i915_private *i915,
* GEN3 firmware likes to smash pci bridges into the stolen
* range. Apparently this works.
*/
- if (!r && !IS_GEN(i915, 3)) {
+ if (!r && GRAPHICS_VER(i915) != 3) {
drm_err(&i915->drm,
"conflict detected with stolen region: %pR\n",
dsm);
@@ -197,7 +197,7 @@ static void g4x_get_stolen_reserved(struct drm_i915_private *i915,
* Whether ILK really reuses the ELK register for this is unclear.
* Let's see if we catch anyone with this supposedly enabled on ILK.
*/
- drm_WARN(&i915->drm, IS_GEN(i915, 5),
+ drm_WARN(&i915->drm, GRAPHICS_VER(i915) == 5,
"ILK stolen reserved found? 0x%08x\n",
reg_val);
@@ -399,7 +399,7 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
return 0;
}
- if (intel_vtd_active() && INTEL_GEN(i915) < 8) {
+ if (intel_vtd_active() && GRAPHICS_VER(i915) < 8) {
drm_notice(&i915->drm,
"%s, disabling use of stolen memory\n",
"DMAR active");
@@ -421,7 +421,7 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
reserved_base = stolen_top;
reserved_size = 0;
- switch (INTEL_GEN(i915)) {
+ switch (GRAPHICS_VER(i915)) {
case 2:
case 3:
break;
@@ -456,7 +456,7 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
&reserved_base, &reserved_size);
break;
default:
- MISSING_CASE(INTEL_GEN(i915));
+ MISSING_CASE(GRAPHICS_VER(i915));
fallthrough;
case 11:
case 12:
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index 9e8945013090..ef4d0f7dc118 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -62,14 +62,14 @@ u32 i915_gem_fence_size(struct drm_i915_private *i915,
GEM_BUG_ON(!stride);
- if (INTEL_GEN(i915) >= 4) {
+ if (GRAPHICS_VER(i915) >= 4) {
stride *= i915_gem_tile_height(tiling);
GEM_BUG_ON(!IS_ALIGNED(stride, I965_FENCE_PAGE));
return roundup(size, stride);
}
/* Previous chips need a power-of-two fence region when tiling */
- if (IS_GEN(i915, 3))
+ if (GRAPHICS_VER(i915) == 3)
ggtt_size = 1024*1024;
else
ggtt_size = 512*1024;
@@ -102,7 +102,7 @@ u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size,
if (tiling == I915_TILING_NONE)
return I915_GTT_MIN_ALIGNMENT;
- if (INTEL_GEN(i915) >= 4)
+ if (GRAPHICS_VER(i915) >= 4)
return I965_FENCE_PAGE;
/*
@@ -130,10 +130,10 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
/* check maximum stride & object size */
/* i965+ stores the end address of the gtt mapping in the fence
* reg, so dont bother to check the size */
- if (INTEL_GEN(i915) >= 7) {
+ if (GRAPHICS_VER(i915) >= 7) {
if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
return false;
- } else if (INTEL_GEN(i915) >= 4) {
+ } else if (GRAPHICS_VER(i915) >= 4) {
if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
return false;
} else {
@@ -144,7 +144,7 @@ i915_tiling_ok(struct drm_i915_gem_object *obj,
return false;
}
- if (IS_GEN(i915, 2) ||
+ if (GRAPHICS_VER(i915) == 2 ||
(tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)))
tile_width = 128;
else
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index d36873885cc1..176e6b22f87f 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -152,8 +152,8 @@ static int prepare_blit(const struct tiled_blits *t,
struct blit_buffer *src,
struct drm_i915_gem_object *batch)
{
- const int gen = INTEL_GEN(to_i915(batch->base.dev));
- bool use_64b_reloc = gen >= 8;
+ const int ver = GRAPHICS_VER(to_i915(batch->base.dev));
+ bool use_64b_reloc = ver >= 8;
u32 src_pitch, dst_pitch;
u32 cmd, *cs;
@@ -171,7 +171,7 @@ static int prepare_blit(const struct tiled_blits *t,
*cs++ = cmd;
cmd = MI_FLUSH_DW;
- if (gen >= 8)
+ if (ver >= 8)
cmd++;
*cs++ = cmd;
*cs++ = 0;
@@ -179,7 +179,7 @@ static int prepare_blit(const struct tiled_blits *t,
*cs++ = 0;
cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
- if (gen >= 8)
+ if (ver >= 8)
cmd += 2;
src_pitch = t->width * 4;
@@ -666,7 +666,7 @@ static int igt_client_tiled_blits(void *arg)
int inst = 0;
/* Test requires explicit BLT tiling controls */
- if (INTEL_GEN(i915) < 4)
+ if (GRAPHICS_VER(i915) < 4)
return 0;
if (bad_swizzling(i915)) /* Requires sane (sub-page) swizzling */
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
index e937b6629019..13b088cc787e 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
@@ -221,12 +221,12 @@ static int gpu_set(struct context *ctx, unsigned long offset, u32 v)
goto out_rq;
}
- if (INTEL_GEN(ctx->engine->i915) >= 8) {
+ if (GRAPHICS_VER(ctx->engine->i915) >= 8) {
*cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
*cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset);
*cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
*cs++ = v;
- } else if (INTEL_GEN(ctx->engine->i915) >= 4) {
+ } else if (GRAPHICS_VER(ctx->engine->i915) >= 4) {
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = 0;
*cs++ = i915_ggtt_offset(vma) + offset;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index ce70d0a3afb2..dbcfa28a9d91 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -897,7 +897,7 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v
{
u32 *cmd;
- GEM_BUG_ON(INTEL_GEN(vma->vm->i915) < 8);
+ GEM_BUG_ON(GRAPHICS_VER(vma->vm->i915) < 8);
cmd = i915_gem_object_pin_map(rpcs, I915_MAP_WB);
if (IS_ERR(cmd))
@@ -932,7 +932,7 @@ emit_rpcs_query(struct drm_i915_gem_object *obj,
GEM_BUG_ON(!intel_engine_can_store_dword(ce->engine));
- if (INTEL_GEN(i915) < 8)
+ if (GRAPHICS_VER(i915) < 8)
return -EINVAL;
vma = i915_vma_instance(obj, ce->vm, NULL);
@@ -1100,7 +1100,7 @@ __read_slice_count(struct intel_context *ce,
return ret;
}
- if (INTEL_GEN(ce->engine->i915) >= 11) {
+ if (GRAPHICS_VER(ce->engine->i915) >= 11) {
s_mask = GEN11_RPCS_S_CNT_MASK;
s_shift = GEN11_RPCS_S_CNT_SHIFT;
} else {
@@ -1229,7 +1229,7 @@ __igt_ctx_sseu(struct drm_i915_private *i915,
int inst = 0;
int ret = 0;
- if (INTEL_GEN(i915) < 9)
+ if (GRAPHICS_VER(i915) < 9)
return 0;
if (flags & TEST_RESET)
@@ -1518,7 +1518,7 @@ static int write_to_scratch(struct i915_gem_context *ctx,
}
*cmd++ = MI_STORE_DWORD_IMM_GEN4;
- if (INTEL_GEN(i915) >= 8) {
+ if (GRAPHICS_VER(i915) >= 8) {
*cmd++ = lower_32_bits(offset);
*cmd++ = upper_32_bits(offset);
} else {
@@ -1608,7 +1608,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
if (IS_ERR(obj))
return PTR_ERR(obj);
- if (INTEL_GEN(i915) >= 8) {
+ if (GRAPHICS_VER(i915) >= 8) {
const u32 GPR0 = engine->mmio_base + 0x600;
vm = i915_gem_context_get_vm_rcu(ctx);
@@ -1776,7 +1776,7 @@ static int igt_vm_isolation(void *arg)
u32 expected;
int err;
- if (INTEL_GEN(i915) < 7)
+ if (GRAPHICS_VER(i915) < 7)
return 0;
/*
@@ -1830,7 +1830,7 @@ static int igt_vm_isolation(void *arg)
continue;
/* Not all engines have their own GPR! */
- if (INTEL_GEN(i915) < 8 && engine->class != RENDER_CLASS)
+ if (GRAPHICS_VER(i915) < 8 && engine->class != RENDER_CLASS)
continue;
while (!__igt_timeout(end_time, NULL)) {
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 05a3b29f545e..3a30955285d6 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -273,7 +273,7 @@ static int check_partial_mappings(struct drm_i915_gem_object *obj,
static unsigned int
setup_tile_size(struct tile *tile, struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) <= 2) {
+ if (GRAPHICS_VER(i915) <= 2) {
tile->height = 16;
tile->width = 128;
tile->size = 11;
@@ -288,9 +288,9 @@ setup_tile_size(struct tile *tile, struct drm_i915_private *i915)
tile->size = 12;
}
- if (INTEL_GEN(i915) < 4)
+ if (GRAPHICS_VER(i915) < 4)
return 8192 / tile->width;
- else if (INTEL_GEN(i915) < 7)
+ else if (GRAPHICS_VER(i915) < 7)
return 128 * I965_FENCE_MAX_PITCH_VAL / tile->width;
else
return 128 * GEN7_FENCE_MAX_PITCH_VAL / tile->width;
@@ -386,7 +386,7 @@ static int igt_partial_tiling(void *arg)
if (err)
goto out_unlock;
- if (pitch > 2 && INTEL_GEN(i915) >= 4) {
+ if (pitch > 2 && GRAPHICS_VER(i915) >= 4) {
tile.stride = tile.width * (pitch - 1);
err = check_partial_mappings(obj, &tile, end);
if (err == -EINTR)
@@ -395,7 +395,7 @@ static int igt_partial_tiling(void *arg)
goto out_unlock;
}
- if (pitch < max_pitch && INTEL_GEN(i915) >= 4) {
+ if (pitch < max_pitch && GRAPHICS_VER(i915) >= 4) {
tile.stride = tile.width * (pitch + 1);
err = check_partial_mappings(obj, &tile, end);
if (err == -EINTR)
@@ -405,7 +405,7 @@ static int igt_partial_tiling(void *arg)
}
}
- if (INTEL_GEN(i915) >= 4) {
+ if (GRAPHICS_VER(i915) >= 4) {
for_each_prime_number(pitch, max_pitch) {
tile.stride = tile.width * pitch;
err = check_partial_mappings(obj, &tile, end);
@@ -501,7 +501,7 @@ static int igt_smoke_tiling(void *arg)
tile.stride =
i915_prandom_u32_max_state(max_pitch, &prng);
tile.stride = (1 + tile.stride) * tile.width;
- if (INTEL_GEN(i915) < 4)
+ if (GRAPHICS_VER(i915) < 4)
tile.stride = rounddown_pow_of_two(tile.stride);
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
index 0b092c62bb34..b35c1219c852 100644
--- a/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
+++ b/drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c
@@ -44,7 +44,7 @@ igt_emit_store_dw(struct i915_vma *vma,
u32 val)
{
struct drm_i915_gem_object *obj;
- const int gen = INTEL_GEN(vma->vm->i915);
+ const int ver = GRAPHICS_VER(vma->vm->i915);
unsigned long n, size;
u32 *cmd;
int err;
@@ -65,14 +65,14 @@ igt_emit_store_dw(struct i915_vma *vma,
offset += vma->node.start;
for (n = 0; n < count; n++) {
- if (gen >= 8) {
+ if (ver >= 8) {
*cmd++ = MI_STORE_DWORD_IMM_GEN4;
*cmd++ = lower_32_bits(offset);
*cmd++ = upper_32_bits(offset);
*cmd++ = val;
- } else if (gen >= 4) {
+ } else if (ver >= 4) {
*cmd++ = MI_STORE_DWORD_IMM_GEN4 |
- (gen < 6 ? MI_USE_GGTT : 0);
+ (ver < 6 ? MI_USE_GGTT : 0);
*cmd++ = 0;
*cmd++ = offset;
*cmd++ = val;
@@ -146,7 +146,7 @@ int igt_gpu_fill_dw(struct intel_context *ce,
goto skip_request;
flags = 0;
- if (INTEL_GEN(ce->vm->i915) <= 5)
+ if (GRAPHICS_VER(ce->vm->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
err = rq->engine->emit_bb_start(rq,
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 4/7] drm/i915/gvt: replace IS_GEN and friends with IS_GRAPHICS_VER
2021-05-27 18:16 [Intel-gfx] [PATCH 0/7] Finish conversion to GRAPHICS_VER Lucas De Marchi
` (2 preceding siblings ...)
2021-05-27 18:16 ` [Intel-gfx] [PATCH 3/7] drm/i915/gem: replace IS_GEN and friends with IS_GRAPHICS_VER Lucas De Marchi
@ 2021-05-27 18:16 ` Lucas De Marchi
2021-05-27 18:16 ` [Intel-gfx] [PATCH 5/7] drm/i915: " Lucas De Marchi
` (6 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2021-05-27 18:16 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-gvt-dev
This was done by the following semantic patch:
@@ expression dev_priv, E; @@
- INTEL_GEN(dev_priv) == E
+ IS_GRAPHICS_VER(dev_priv, E)
@@ expression dev_priv; @@
- INTEL_GEN(dev_priv)
+ GRAPHICS_VER(dev_priv)
@@ expression dev_priv; expression E; @@
- IS_GEN(dev_priv, E)
+ IS_GRAPHICS_VER(dev_priv, E)
@@
expression dev_priv;
expression from, until;
@@
- IS_GEN_RANGE(dev_priv, from, until)
+ IS_GRAPHICS_RANGE(dev_priv, from, until)
@def@
expression E;
identifier id =~ "^gen$";
@@
- id = GRAPHICS_VER(E)
+ ver = GRAPHICS_VER(E)
@@
identifier def.id;
@@
- id
+ ver
It also takes care of renaming the variable we assign to GRAPHICS_VER()
so to use "ver" rather than "gen".
Cc: intel-gvt-dev@lists.freedesktop.org
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 8 ++++----
drivers/gpu/drm/i915/gvt/dmabuf.c | 2 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c | 10 +++++-----
drivers/gpu/drm/i915/gvt/gtt.c | 4 ++--
drivers/gpu/drm/i915/gvt/handlers.c | 6 +++---
drivers/gpu/drm/i915/gvt/interrupt.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 10 +++++-----
drivers/gpu/drm/i915/gvt/scheduler.c | 4 ++--
drivers/gpu/drm/i915/gvt/vgpu.c | 4 ++--
9 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index ca9c9e27a43d..c4118b808268 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1006,7 +1006,7 @@ static int cmd_reg_handler(struct parser_exec_state *s,
* update reg values in it into vregs, so LRIs in workload with
* inhibit context will restore with correct values
*/
- if (IS_GEN(s->engine->i915, 9) &&
+ if (GRAPHICS_VER(s->engine->i915) == 9 &&
intel_gvt_mmio_is_sr_in_ctx(gvt, offset) &&
!strncmp(cmd, "lri", 3)) {
intel_gvt_hypervisor_read_gpa(s->vgpu,
@@ -1390,7 +1390,7 @@ static int gen8_check_mi_display_flip(struct parser_exec_state *s,
if (!info->async_flip)
return 0;
- if (INTEL_GEN(s->engine->i915) >= 9) {
+ if (GRAPHICS_VER(s->engine->i915) >= 9) {
stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
GENMASK(12, 10)) >> 10;
@@ -1418,7 +1418,7 @@ static int gen8_update_plane_mmio_from_mi_display_flip(
set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
info->surf_val << 12);
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (GRAPHICS_VER(dev_priv) >= 9) {
set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
info->stride_val);
set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
@@ -1446,7 +1446,7 @@ static int decode_mi_display_flip(struct parser_exec_state *s,
{
if (IS_BROADWELL(s->engine->i915))
return gen8_decode_mi_display_flip(s, info);
- if (INTEL_GEN(s->engine->i915) >= 9)
+ if (GRAPHICS_VER(s->engine->i915) >= 9)
return skl_decode_mi_display_flip(s, info);
return -ENODEV;
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
index d4f883f35b95..8e65cd8258b9 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.c
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -223,7 +223,7 @@ static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev,
obj->read_domains = I915_GEM_DOMAIN_GTT;
obj->write_domain = 0;
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (GRAPHICS_VER(dev_priv) >= 9) {
unsigned int tiling_mode = 0;
unsigned int stride = 0;
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 0889ad8291b0..11a8baba6822 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -151,7 +151,7 @@ static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;
u32 stride = stride_reg;
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (GRAPHICS_VER(dev_priv) >= 9) {
switch (tiled) {
case PLANE_CTL_TILED_LINEAR:
stride = stride_reg * 64;
@@ -215,7 +215,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
if (!plane->enabled)
return -ENODEV;
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (GRAPHICS_VER(dev_priv) >= 9) {
plane->tiled = val & PLANE_CTL_TILED_MASK;
fmt = skl_format_to_drm(
val & PLANE_CTL_FORMAT_MASK,
@@ -256,9 +256,9 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
}
plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,
- (INTEL_GEN(dev_priv) >= 9) ?
- (_PRI_PLANE_STRIDE_MASK >> 6) :
- _PRI_PLANE_STRIDE_MASK, plane->bpp);
+ (GRAPHICS_VER(dev_priv) >= 9) ?
+ (_PRI_PLANE_STRIDE_MASK >> 6) :
+ _PRI_PLANE_STRIDE_MASK, plane->bpp);
plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
_PIPE_H_SRCSZ_SHIFT;
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 9478c132d7b6..cc2c05e18206 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1055,12 +1055,12 @@ static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
{
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
- if (INTEL_GEN(dev_priv) == 9 || INTEL_GEN(dev_priv) == 10) {
+ if (GRAPHICS_VER(dev_priv) == 9 || GRAPHICS_VER(dev_priv) == 10) {
u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
GAMW_ECO_ENABLE_64K_IPS_FIELD;
return ips == GAMW_ECO_ENABLE_64K_IPS_FIELD;
- } else if (INTEL_GEN(dev_priv) >= 11) {
+ } else if (GRAPHICS_VER(dev_priv) >= 11) {
/* 64K paging only controlled by IPS bit in PTE now. */
return true;
} else
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 33496397a74f..98eb48c24c46 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -220,7 +220,7 @@ static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu,
{
u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;
- if (INTEL_GEN(vgpu->gvt->gt->i915) <= 10) {
+ if (GRAPHICS_VER(vgpu->gvt->gt->i915) <= 10) {
if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD)
gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id);
else if (!ips)
@@ -286,7 +286,7 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu,
old = vgpu_vreg(vgpu, offset);
new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
- if (INTEL_GEN(vgpu->gvt->gt->i915) >= 9) {
+ if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) {
switch (offset) {
case FORCEWAKE_RENDER_GEN9_REG:
ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
@@ -1174,7 +1174,7 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
write_vreg(vgpu, offset, p_data, bytes);
data = vgpu_vreg(vgpu, offset);
- if ((INTEL_GEN(vgpu->gvt->gt->i915) >= 9)
+ if ((GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9)
&& offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
/* SKL DPB/C/D aux ctl register changed */
return 0;
diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
index 497d28ce47df..614b951d919f 100644
--- a/drivers/gpu/drm/i915/gvt/interrupt.c
+++ b/drivers/gpu/drm/i915/gvt/interrupt.c
@@ -585,7 +585,7 @@ static void gen8_init_irq(
SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
- } else if (INTEL_GEN(gvt->gt->i915) >= 9) {
+ } else if (GRAPHICS_VER(gvt->gt->i915) >= 9) {
SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);
SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);
SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index c9589e26af93..b8ac80765461 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -373,7 +373,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu,
*/
fw = intel_uncore_forcewake_for_reg(uncore, reg,
FW_REG_READ | FW_REG_WRITE);
- if (engine->id == RCS0 && INTEL_GEN(engine->i915) >= 9)
+ if (engine->id == RCS0 && GRAPHICS_VER(engine->i915) >= 9)
fw |= FORCEWAKE_RENDER;
intel_uncore_forcewake_get(uncore, fw);
@@ -409,7 +409,7 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
if (drm_WARN_ON(&engine->i915->drm, engine->id >= ARRAY_SIZE(regs)))
return;
- if (engine->id == RCS0 && IS_GEN(engine->i915, 9))
+ if (engine->id == RCS0 && GRAPHICS_VER(engine->i915) == 9)
return;
if (!pre && !gen9_render_mocs.initialized)
@@ -474,7 +474,7 @@ static void switch_mmio(struct intel_vgpu *pre,
struct engine_mmio *mmio;
u32 old_v, new_v;
- if (INTEL_GEN(engine->i915) >= 9)
+ if (GRAPHICS_VER(engine->i915) >= 9)
switch_mocs(pre, next, engine);
for (mmio = engine->i915->gvt->engine_mmio_list.mmio;
@@ -486,7 +486,7 @@ static void switch_mmio(struct intel_vgpu *pre,
* state image on gen9, it's initialized by lri command and
* save or restore with context together.
*/
- if (IS_GEN(engine->i915, 9) && mmio->in_context)
+ if (GRAPHICS_VER(engine->i915) == 9 && mmio->in_context)
continue;
// save
@@ -580,7 +580,7 @@ void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
{
struct engine_mmio *mmio;
- if (INTEL_GEN(gvt->gt->i915) >= 9) {
+ if (GRAPHICS_VER(gvt->gt->i915) >= 9) {
gvt->engine_mmio_list.mmio = gen9_engine_mmio_list;
gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list;
gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list);
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index fc735692f21f..734c37c5e347 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -364,7 +364,7 @@ static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
u32 *cs;
int err;
- if (IS_GEN(req->engine->i915, 9) && is_inhibit_context(req->context))
+ if (GRAPHICS_VER(req->engine->i915) == 9 && is_inhibit_context(req->context))
intel_vgpu_restore_inhibit_context(vgpu, req);
/*
@@ -1148,7 +1148,7 @@ static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
static int workload_thread(void *arg)
{
struct intel_engine_cs *engine = arg;
- const bool need_force_wake = INTEL_GEN(engine->i915) >= 9;
+ const bool need_force_wake = GRAPHICS_VER(engine->i915) >= 9;
struct intel_gvt *gvt = engine->i915->gvt;
struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
struct intel_vgpu_workload *workload = NULL;
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 9039787f123a..fa6b92615799 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -149,10 +149,10 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm,
high_avail / vgpu_types[i].high_mm);
- if (IS_GEN(gvt->gt->i915, 8))
+ if (GRAPHICS_VER(gvt->gt->i915) == 8)
sprintf(gvt->types[i].name, "GVTg_V4_%s",
vgpu_types[i].name);
- else if (IS_GEN(gvt->gt->i915, 9))
+ else if (GRAPHICS_VER(gvt->gt->i915) == 9)
sprintf(gvt->types[i].name, "GVTg_V5_%s",
vgpu_types[i].name);
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 5/7] drm/i915: replace IS_GEN and friends with IS_GRAPHICS_VER
2021-05-27 18:16 [Intel-gfx] [PATCH 0/7] Finish conversion to GRAPHICS_VER Lucas De Marchi
` (3 preceding siblings ...)
2021-05-27 18:16 ` [Intel-gfx] [PATCH 4/7] drm/i915/gvt: " Lucas De Marchi
@ 2021-05-27 18:16 ` Lucas De Marchi
2021-05-27 18:16 ` [Intel-gfx] [PATCH 6/7] drm/i915: Add remaining conversions to GRAPHICS_VER Lucas De Marchi
` (5 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2021-05-27 18:16 UTC (permalink / raw)
To: intel-gfx
This was done by the following semantic patch:
@@ expression dev_priv, E; @@
- INTEL_GEN(dev_priv) == E
+ IS_GRAPHICS_VER(dev_priv, E)
@@ expression dev_priv; @@
- INTEL_GEN(dev_priv)
+ GRAPHICS_VER(dev_priv)
@@ expression dev_priv; expression E; @@
- IS_GEN(dev_priv, E)
+ IS_GRAPHICS_VER(dev_priv, E)
@@
expression dev_priv;
expression from, until;
@@
- IS_GEN_RANGE(dev_priv, from, until)
+ IS_GRAPHICS_RANGE(dev_priv, from, until)
@def@
expression E;
identifier id =~ "^gen$";
@@
- id = GRAPHICS_VER(E)
+ ver = GRAPHICS_VER(E)
@@
identifier def.id;
@@
- id
+ ver
It also takes care of renaming the variable we assign to GRAPHICS_VER()
so to use "ver" rather than "gen".
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 10 +--
drivers/gpu/drm/i915/i915_debugfs.c | 32 ++++----
drivers/gpu/drm/i915/i915_drv.c | 20 ++---
drivers/gpu/drm/i915/i915_gem.c | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 80 +++++++++----------
drivers/gpu/drm/i915/i915_irq.c | 34 ++++----
drivers/gpu/drm/i915/i915_perf.c | 44 +++++-----
drivers/gpu/drm/i915/i915_pmu.c | 8 +-
drivers/gpu/drm/i915/i915_request.c | 4 +-
drivers/gpu/drm/i915/i915_suspend.c | 16 ++--
drivers/gpu/drm/i915/i915_sysfs.c | 2 +-
drivers/gpu/drm/i915/i915_vgpu.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 22 ++---
drivers/gpu/drm/i915/intel_dram.c | 14 ++--
drivers/gpu/drm/i915/intel_pch.c | 10 +--
drivers/gpu/drm/i915/intel_pm.c | 14 ++--
drivers/gpu/drm/i915/intel_sideband.c | 2 +-
drivers/gpu/drm/i915/intel_uncore.c | 26 +++---
drivers/gpu/drm/i915/intel_wopcm.c | 10 +--
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 +-
drivers/gpu/drm/i915/selftests/i915_perf.c | 6 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 8 +-
drivers/gpu/drm/i915/selftests/igt_spinner.c | 12 +--
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +-
24 files changed, 193 insertions(+), 193 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 5b4b2bd46e7c..3992c25a191d 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -946,8 +946,8 @@ int intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
int cmd_table_count;
int ret;
- if (!IS_GEN(engine->i915, 7) && !(IS_GEN(engine->i915, 9) &&
- engine->class == COPY_ENGINE_CLASS))
+ if (GRAPHICS_VER(engine->i915) != 7 && !(GRAPHICS_VER(engine->i915) == 9 &&
+ engine->class == COPY_ENGINE_CLASS))
return 0;
switch (engine->class) {
@@ -977,7 +977,7 @@ int intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
break;
case COPY_ENGINE_CLASS:
engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
- if (IS_GEN(engine->i915, 9)) {
+ if (GRAPHICS_VER(engine->i915) == 9) {
cmd_tables = gen9_blt_cmd_table;
cmd_table_count = ARRAY_SIZE(gen9_blt_cmd_table);
engine->get_cmd_length_mask =
@@ -993,7 +993,7 @@ int intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
cmd_table_count = ARRAY_SIZE(gen7_blt_cmd_table);
}
- if (IS_GEN(engine->i915, 9)) {
+ if (GRAPHICS_VER(engine->i915) == 9) {
engine->reg_tables = gen9_blt_reg_tables;
engine->reg_table_count =
ARRAY_SIZE(gen9_blt_reg_tables);
@@ -1537,7 +1537,7 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
if (IS_HASWELL(engine->i915))
flags = MI_BATCH_NON_SECURE_HSW;
- GEM_BUG_ON(!IS_GEN_RANGE(engine->i915, 6, 7));
+ GEM_BUG_ON(!IS_GRAPHICS_VER(engine->i915, 6, 7));
__gen6_emit_bb_start(batch_end,
batch_addr,
flags);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a4d8a836bd57..0529576f069c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -361,7 +361,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
- if (IS_GEN(dev_priv, 5)) {
+ if (GRAPHICS_VER(dev_priv) == 5) {
u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
@@ -408,7 +408,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_printf(m,
"efficient (RPe) frequency: %d MHz\n",
intel_gpu_freq(rps, rps->efficient_freq));
- } else if (INTEL_GEN(dev_priv) >= 6) {
+ } else if (GRAPHICS_VER(dev_priv) >= 6) {
u32 rp_state_limits;
u32 gt_perf_status;
u32 rp_state_cap;
@@ -432,7 +432,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
reqf = intel_uncore_read(&dev_priv->uncore, GEN6_RPNSWREQ);
- if (INTEL_GEN(dev_priv) >= 9)
+ if (GRAPHICS_VER(dev_priv) >= 9)
reqf >>= 23;
else {
reqf &= ~GEN6_TURBO_DISABLE;
@@ -458,7 +458,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (GRAPHICS_VER(dev_priv) >= 11) {
pm_ier = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
pm_imr = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
/*
@@ -467,7 +467,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
*/
pm_isr = 0;
pm_iir = 0;
- } else if (INTEL_GEN(dev_priv) >= 8) {
+ } else if (GRAPHICS_VER(dev_priv) >= 8) {
pm_ier = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IER(2));
pm_imr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IMR(2));
pm_isr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_ISR(2));
@@ -490,14 +490,14 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
pm_ier, pm_imr, pm_mask);
- if (INTEL_GEN(dev_priv) <= 10)
+ if (GRAPHICS_VER(dev_priv) <= 10)
seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
pm_isr, pm_iir);
seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
rps->pm_intrmsk_mbz);
seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
seq_printf(m, "Render p-state ratio: %d\n",
- (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
+ (gt_perf_status & (GRAPHICS_VER(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
seq_printf(m, "Render p-state VID: %d\n",
gt_perf_status & 0xff);
seq_printf(m, "Render p-state limit: %d\n",
@@ -538,20 +538,20 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
rp_state_cap >> 16) & 0xff;
max_freq *= (IS_GEN9_BC(dev_priv) ||
- INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
+ GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
intel_gpu_freq(rps, max_freq));
max_freq = (rp_state_cap & 0xff00) >> 8;
max_freq *= (IS_GEN9_BC(dev_priv) ||
- INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
+ GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
intel_gpu_freq(rps, max_freq));
max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
rp_state_cap >> 0) & 0xff;
max_freq *= (IS_GEN9_BC(dev_priv) ||
- INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
+ GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
intel_gpu_freq(rps, max_freq));
seq_printf(m, "Max overclocked frequency: %dMHz\n",
@@ -622,12 +622,12 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
seq_puts(m, "L-shaped memory detected\n");
/* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */
- if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))
+ if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))
return 0;
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
- if (IS_GEN_RANGE(dev_priv, 3, 4)) {
+ if (IS_GRAPHICS_VER(dev_priv, 3, 4)) {
seq_printf(m, "DDC = 0x%08x\n",
intel_uncore_read(uncore, DCC));
seq_printf(m, "DDC2 = 0x%08x\n",
@@ -636,7 +636,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
intel_uncore_read16(uncore, C0DRB3_BW));
seq_printf(m, "C1DRB3 = 0x%04x\n",
intel_uncore_read16(uncore, C1DRB3_BW));
- } else if (INTEL_GEN(dev_priv) >= 6) {
+ } else if (GRAPHICS_VER(dev_priv) >= 6) {
seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
intel_uncore_read(uncore, MAD_DIMM_C0));
seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
@@ -645,7 +645,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
intel_uncore_read(uncore, MAD_DIMM_C2));
seq_printf(m, "TILECTL = 0x%08x\n",
intel_uncore_read(uncore, TILECTL));
- if (INTEL_GEN(dev_priv) >= 8)
+ if (GRAPHICS_VER(dev_priv) >= 8)
seq_printf(m, "GAMTARBMODE = 0x%08x\n",
intel_uncore_read(uncore, GAMTARBMODE));
else
@@ -956,7 +956,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
atomic_inc(>->user_wakeref);
intel_gt_pm_get(gt);
- if (INTEL_GEN(i915) >= 6)
+ if (GRAPHICS_VER(i915) >= 6)
intel_uncore_forcewake_user_get(gt->uncore);
return 0;
@@ -967,7 +967,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file)
struct drm_i915_private *i915 = inode->i_private;
struct intel_gt *gt = &i915->gt;
- if (INTEL_GEN(i915) >= 6)
+ if (GRAPHICS_VER(i915) >= 6)
intel_uncore_forcewake_user_put(&i915->uncore);
intel_gt_pm_put(gt);
atomic_dec(>->user_wakeref);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2f06bb7b3ed2..d5b3c5ba6bd2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -106,12 +106,12 @@ static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
static int
intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
{
- int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+ int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
u32 temp_lo, temp_hi = 0;
u64 mchbar_addr;
int ret;
- if (INTEL_GEN(dev_priv) >= 4)
+ if (GRAPHICS_VER(dev_priv) >= 4)
pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
@@ -138,7 +138,7 @@ intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
return ret;
}
- if (INTEL_GEN(dev_priv) >= 4)
+ if (GRAPHICS_VER(dev_priv) >= 4)
pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
upper_32_bits(dev_priv->mch_res.start));
@@ -151,7 +151,7 @@ intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
static void
intel_setup_mchbar(struct drm_i915_private *dev_priv)
{
- int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+ int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
u32 temp;
bool enabled;
@@ -190,7 +190,7 @@ intel_setup_mchbar(struct drm_i915_private *dev_priv)
static void
intel_teardown_mchbar(struct drm_i915_private *dev_priv)
{
- int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
+ int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
if (dev_priv->mchbar_need_disable) {
if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
@@ -475,7 +475,7 @@ static int i915_set_dma_info(struct drm_i915_private *i915)
goto mask_err;
/* overlay on gen2 is broken and can't address above 1G */
- if (IS_GEN(i915, 2))
+ if (GRAPHICS_VER(i915) == 2)
mask_size = 30;
/*
@@ -601,7 +601,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
* device. The kernel then disables that interrupt source and so
* prevents the other device from working properly.
*/
- if (INTEL_GEN(dev_priv) >= 5) {
+ if (GRAPHICS_VER(dev_priv) >= 5) {
if (pci_enable_msi(pdev) < 0)
drm_dbg(&dev_priv->drm, "can't enable MSI");
}
@@ -729,7 +729,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
intel_platform_name(INTEL_INFO(dev_priv)->platform),
intel_subplatform(RUNTIME_INFO(dev_priv),
INTEL_INFO(dev_priv)->platform),
- INTEL_GEN(dev_priv));
+ GRAPHICS_VER(dev_priv));
intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
@@ -803,7 +803,7 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
*/
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
- if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
+ if (GRAPHICS_VER(i915) >= 9 && i915_selftest.live < 0 &&
i915->params.fake_lmem_start) {
mkwrite_device_info(i915)->memory_regions =
REGION_SMEM | REGION_LMEM | REGION_STOLEN_SMEM;
@@ -1182,7 +1182,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
* Fujitsu FSC S7110
* Acer Aspire 1830T
*/
- if (!(hibernation && INTEL_GEN(dev_priv) < 6))
+ if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
pci_set_power_state(pdev, PCI_D3hot);
out:
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index cffd7f4f87dc..1aadc021d92e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -442,7 +442,7 @@ i915_gem_pread_ioctl(struct drm_device *dev, void *data,
/* PREAD is disallowed for all platforms after TGL-LP. This also
* covers all platforms with local memory.
*/
- if (INTEL_GEN(i915) >= 12 && !IS_TIGERLAKE(i915))
+ if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915))
return -EOPNOTSUPP;
if (args->size == 0)
@@ -722,7 +722,7 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
/* PWRITE is disallowed for all platforms after TGL-LP. This also
* covers all platforms with local memory.
*/
- if (INTEL_GEN(i915) >= 12 && !IS_TIGERLAKE(i915))
+ if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915))
return -EOPNOTSUPP;
if (args->size == 0)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 8b964e355cb5..292b9f832574 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -435,13 +435,13 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m,
err_printf(m, " INSTDONE: 0x%08x\n",
ee->instdone.instdone);
- if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3)
+ if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3)
return;
err_printf(m, " SC_INSTDONE: 0x%08x\n",
ee->instdone.slice_common);
- if (INTEL_GEN(m->i915) <= 6)
+ if (GRAPHICS_VER(m->i915) <= 6)
return;
for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
@@ -454,7 +454,7 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m,
slice, subslice,
ee->instdone.row[slice][subslice]);
- if (INTEL_GEN(m->i915) < 12)
+ if (GRAPHICS_VER(m->i915) < 12)
return;
err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n",
@@ -543,7 +543,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
upper_32_bits(start), lower_32_bits(start),
upper_32_bits(end), lower_32_bits(end));
}
- if (INTEL_GEN(m->i915) >= 4) {
+ if (GRAPHICS_VER(m->i915) >= 4) {
err_printf(m, " BBADDR: 0x%08x_%08x\n",
(u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate);
@@ -552,14 +552,14 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
err_printf(m, " INSTPM: 0x%08x\n", ee->instpm);
err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
lower_32_bits(ee->faddr));
- if (INTEL_GEN(m->i915) >= 6) {
+ if (GRAPHICS_VER(m->i915) >= 6) {
err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi);
err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg);
}
if (HAS_PPGTT(m->i915)) {
err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
- if (INTEL_GEN(m->i915) >= 8) {
+ if (GRAPHICS_VER(m->i915) >= 8) {
int i;
for (i = 0; i < 4; i++)
err_printf(m, " PDP%d: 0x%016llx\n",
@@ -706,25 +706,25 @@ static void err_print_gt(struct drm_i915_error_state_buf *m,
for (i = 0; i < gt->nfence; i++)
err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]);
- if (IS_GEN_RANGE(m->i915, 6, 11)) {
+ if (IS_GRAPHICS_VER(m->i915, 6, 11)) {
err_printf(m, "ERROR: 0x%08x\n", gt->error);
err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg);
}
- if (INTEL_GEN(m->i915) >= 8)
+ if (GRAPHICS_VER(m->i915) >= 8)
err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
gt->fault_data1, gt->fault_data0);
- if (IS_GEN(m->i915, 7))
+ if (GRAPHICS_VER(m->i915) == 7)
err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);
- if (IS_GEN_RANGE(m->i915, 8, 11))
+ if (IS_GRAPHICS_VER(m->i915, 8, 11))
err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);
- if (IS_GEN(m->i915, 12))
+ if (GRAPHICS_VER(m->i915) == 12)
err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err);
- if (INTEL_GEN(m->i915) >= 12) {
+ if (GRAPHICS_VER(m->i915) >= 12) {
int i;
for (i = 0; i < GEN12_SFC_DONE_MAX; i++)
@@ -1092,12 +1092,12 @@ static void gt_record_fences(struct intel_gt_coredump *gt)
struct intel_uncore *uncore = gt->_gt->uncore;
int i;
- if (INTEL_GEN(uncore->i915) >= 6) {
+ if (GRAPHICS_VER(uncore->i915) >= 6) {
for (i = 0; i < ggtt->num_fences; i++)
gt->fence[i] =
intel_uncore_read64(uncore,
FENCE_REG_GEN6_LO(i));
- } else if (INTEL_GEN(uncore->i915) >= 4) {
+ } else if (GRAPHICS_VER(uncore->i915) >= 4) {
for (i = 0; i < ggtt->num_fences; i++)
gt->fence[i] =
intel_uncore_read64(uncore,
@@ -1115,20 +1115,20 @@ static void engine_record_registers(struct intel_engine_coredump *ee)
const struct intel_engine_cs *engine = ee->engine;
struct drm_i915_private *i915 = engine->i915;
- if (INTEL_GEN(i915) >= 6) {
+ if (GRAPHICS_VER(i915) >= 6) {
ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
- if (INTEL_GEN(i915) >= 12)
+ if (GRAPHICS_VER(i915) >= 12)
ee->fault_reg = intel_uncore_read(engine->uncore,
GEN12_RING_FAULT_REG);
- else if (INTEL_GEN(i915) >= 8)
+ else if (GRAPHICS_VER(i915) >= 8)
ee->fault_reg = intel_uncore_read(engine->uncore,
GEN8_RING_FAULT_REG);
else
ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
}
- if (INTEL_GEN(i915) >= 4) {
+ if (GRAPHICS_VER(i915) >= 4) {
ee->esr = ENGINE_READ(engine, RING_ESR);
ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
@@ -1136,7 +1136,7 @@ static void engine_record_registers(struct intel_engine_coredump *ee)
ee->instps = ENGINE_READ(engine, RING_INSTPS);
ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);
ee->ccid = ENGINE_READ(engine, CCID);
- if (INTEL_GEN(i915) >= 8) {
+ if (GRAPHICS_VER(i915) >= 8) {
ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
}
@@ -1155,13 +1155,13 @@ static void engine_record_registers(struct intel_engine_coredump *ee)
ee->head = ENGINE_READ(engine, RING_HEAD);
ee->tail = ENGINE_READ(engine, RING_TAIL);
ee->ctl = ENGINE_READ(engine, RING_CTL);
- if (INTEL_GEN(i915) > 2)
+ if (GRAPHICS_VER(i915) > 2)
ee->mode = ENGINE_READ(engine, RING_MI_MODE);
if (!HWS_NEEDS_PHYSICAL(i915)) {
i915_reg_t mmio;
- if (IS_GEN(i915, 7)) {
+ if (GRAPHICS_VER(i915) == 7) {
switch (engine->id) {
default:
MISSING_CASE(engine->id);
@@ -1179,7 +1179,7 @@ static void engine_record_registers(struct intel_engine_coredump *ee)
mmio = VEBOX_HWS_PGA_GEN7;
break;
}
- } else if (IS_GEN(engine->i915, 6)) {
+ } else if (GRAPHICS_VER(engine->i915) == 6) {
mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
} else {
/* XXX: gen8 returns to sanity */
@@ -1196,13 +1196,13 @@ static void engine_record_registers(struct intel_engine_coredump *ee)
ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
- if (IS_GEN(i915, 6)) {
+ if (GRAPHICS_VER(i915) == 6) {
ee->vm_info.pp_dir_base =
ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
- } else if (IS_GEN(i915, 7)) {
+ } else if (GRAPHICS_VER(i915) == 7) {
ee->vm_info.pp_dir_base =
ENGINE_READ(engine, RING_PP_DIR_BASE);
- } else if (INTEL_GEN(i915) >= 8) {
+ } else if (GRAPHICS_VER(i915) >= 8) {
u32 base = engine->mmio_base;
for (i = 0; i < 4; i++) {
@@ -1534,52 +1534,52 @@ static void gt_record_regs(struct intel_gt_coredump *gt)
gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);
}
- if (IS_GEN(i915, 7))
+ if (GRAPHICS_VER(i915) == 7)
gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
- if (INTEL_GEN(i915) >= 12) {
+ if (GRAPHICS_VER(i915) >= 12) {
gt->fault_data0 = intel_uncore_read(uncore,
GEN12_FAULT_TLB_DATA0);
gt->fault_data1 = intel_uncore_read(uncore,
GEN12_FAULT_TLB_DATA1);
- } else if (INTEL_GEN(i915) >= 8) {
+ } else if (GRAPHICS_VER(i915) >= 8) {
gt->fault_data0 = intel_uncore_read(uncore,
GEN8_FAULT_TLB_DATA0);
gt->fault_data1 = intel_uncore_read(uncore,
GEN8_FAULT_TLB_DATA1);
}
- if (IS_GEN(i915, 6)) {
+ if (GRAPHICS_VER(i915) == 6) {
gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);
gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL);
gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE);
}
/* 2: Registers which belong to multiple generations */
- if (INTEL_GEN(i915) >= 7)
+ if (GRAPHICS_VER(i915) >= 7)
gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
- if (INTEL_GEN(i915) >= 6) {
+ if (GRAPHICS_VER(i915) >= 6) {
gt->derrmr = intel_uncore_read(uncore, DERRMR);
- if (INTEL_GEN(i915) < 12) {
+ if (GRAPHICS_VER(i915) < 12) {
gt->error = intel_uncore_read(uncore, ERROR_GEN6);
gt->done_reg = intel_uncore_read(uncore, DONE_REG);
}
}
/* 3: Feature specific registers */
- if (IS_GEN_RANGE(i915, 6, 7)) {
+ if (IS_GRAPHICS_VER(i915, 6, 7)) {
gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);
}
- if (IS_GEN_RANGE(i915, 8, 11))
+ if (IS_GRAPHICS_VER(i915, 8, 11))
gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);
- if (IS_GEN(i915, 12))
+ if (GRAPHICS_VER(i915) == 12)
gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG);
- if (INTEL_GEN(i915) >= 12) {
+ if (GRAPHICS_VER(i915) >= 12) {
for (i = 0; i < GEN12_SFC_DONE_MAX; i++) {
gt->sfc_done[i] =
intel_uncore_read(uncore, GEN12_SFC_DONE(i));
@@ -1589,7 +1589,7 @@ static void gt_record_regs(struct intel_gt_coredump *gt)
}
/* 4: Everything else */
- if (INTEL_GEN(i915) >= 11) {
+ if (GRAPHICS_VER(i915) >= 11) {
gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
gt->gtier[0] =
intel_uncore_read(uncore,
@@ -1608,7 +1608,7 @@ static void gt_record_regs(struct intel_gt_coredump *gt)
intel_uncore_read(uncore,
GEN11_GUNIT_CSME_INTR_ENABLE);
gt->ngtier = 6;
- } else if (INTEL_GEN(i915) >= 8) {
+ } else if (GRAPHICS_VER(i915) >= 8) {
gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
for (i = 0; i < 4; i++)
gt->gtier[i] =
@@ -1618,7 +1618,7 @@ static void gt_record_regs(struct intel_gt_coredump *gt)
gt->ier = intel_uncore_read(uncore, DEIER);
gt->gtier[0] = intel_uncore_read(uncore, GTIER);
gt->ngtier = 1;
- } else if (IS_GEN(i915, 2)) {
+ } else if (GRAPHICS_VER(i915) == 2) {
gt->ier = intel_uncore_read16(uncore, GEN2_IER);
} else if (!IS_VALLEYVIEW(i915)) {
gt->ier = intel_uncore_read(uncore, GEN2_IER);
@@ -1674,7 +1674,7 @@ static const char *error_msg(struct i915_gpu_coredump *error)
len = scnprintf(error->error_msg, sizeof(error->error_msg),
"GPU HANG: ecode %d:%x:%08x",
- INTEL_GEN(error->i915), hung_classes,
+ GRAPHICS_VER(error->i915), hung_classes,
generate_ecode(first));
if (first && first->context.pid) {
/* Just show the first executing process, more is confusing */
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9446a2758c3e..a11bdb667241 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2175,7 +2175,7 @@ static irqreturn_t ilk_irq_handler(int irq, void *arg)
gt_iir = raw_reg_read(regs, GTIIR);
if (gt_iir) {
raw_reg_write(regs, GTIIR, gt_iir);
- if (INTEL_GEN(i915) >= 6)
+ if (GRAPHICS_VER(i915) >= 6)
gen6_gt_irq_handler(&i915->gt, gt_iir);
else
gen5_gt_irq_handler(&i915->gt, gt_iir);
@@ -2192,7 +2192,7 @@ static irqreturn_t ilk_irq_handler(int irq, void *arg)
ret = IRQ_HANDLED;
}
- if (INTEL_GEN(i915) >= 6) {
+ if (GRAPHICS_VER(i915) >= 6) {
u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR);
if (pm_iir) {
raw_reg_write(regs, GEN6_PMIIR, pm_iir);
@@ -3039,7 +3039,7 @@ static void ilk_irq_reset(struct drm_i915_private *dev_priv)
GEN3_IRQ_RESET(uncore, DE);
dev_priv->irq_mask = ~0u;
- if (IS_GEN(dev_priv, 7))
+ if (GRAPHICS_VER(dev_priv) == 7)
intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
if (IS_HASWELL(dev_priv)) {
@@ -3658,7 +3658,7 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
struct intel_uncore *uncore = &dev_priv->uncore;
u32 display_mask, extra_mask;
- if (INTEL_GEN(dev_priv) >= 7) {
+ if (GRAPHICS_VER(dev_priv) >= 7) {
display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
@@ -4330,7 +4330,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev_priv->l3_parity.remap_info[i] = NULL;
/* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
- if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
+ if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11)
dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
if (!HAS_DISPLAY(dev_priv))
@@ -4401,18 +4401,18 @@ static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
return cherryview_irq_handler;
else if (IS_VALLEYVIEW(dev_priv))
return valleyview_irq_handler;
- else if (IS_GEN(dev_priv, 4))
+ else if (GRAPHICS_VER(dev_priv) == 4)
return i965_irq_handler;
- else if (IS_GEN(dev_priv, 3))
+ else if (GRAPHICS_VER(dev_priv) == 3)
return i915_irq_handler;
else
return i8xx_irq_handler;
} else {
if (HAS_MASTER_UNIT_IRQ(dev_priv))
return dg1_irq_handler;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (GRAPHICS_VER(dev_priv) >= 11)
return gen11_irq_handler;
- else if (INTEL_GEN(dev_priv) >= 8)
+ else if (GRAPHICS_VER(dev_priv) >= 8)
return gen8_irq_handler;
else
return ilk_irq_handler;
@@ -4426,16 +4426,16 @@ static void intel_irq_reset(struct drm_i915_private *dev_priv)
cherryview_irq_reset(dev_priv);
else if (IS_VALLEYVIEW(dev_priv))
valleyview_irq_reset(dev_priv);
- else if (IS_GEN(dev_priv, 4))
+ else if (GRAPHICS_VER(dev_priv) == 4)
i965_irq_reset(dev_priv);
- else if (IS_GEN(dev_priv, 3))
+ else if (GRAPHICS_VER(dev_priv) == 3)
i915_irq_reset(dev_priv);
else
i8xx_irq_reset(dev_priv);
} else {
- if (INTEL_GEN(dev_priv) >= 11)
+ if (GRAPHICS_VER(dev_priv) >= 11)
gen11_irq_reset(dev_priv);
- else if (INTEL_GEN(dev_priv) >= 8)
+ else if (GRAPHICS_VER(dev_priv) >= 8)
gen8_irq_reset(dev_priv);
else
ilk_irq_reset(dev_priv);
@@ -4449,16 +4449,16 @@ static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
cherryview_irq_postinstall(dev_priv);
else if (IS_VALLEYVIEW(dev_priv))
valleyview_irq_postinstall(dev_priv);
- else if (IS_GEN(dev_priv, 4))
+ else if (GRAPHICS_VER(dev_priv) == 4)
i965_irq_postinstall(dev_priv);
- else if (IS_GEN(dev_priv, 3))
+ else if (GRAPHICS_VER(dev_priv) == 3)
i915_irq_postinstall(dev_priv);
else
i8xx_irq_postinstall(dev_priv);
} else {
- if (INTEL_GEN(dev_priv) >= 11)
+ if (GRAPHICS_VER(dev_priv) >= 11)
gen11_irq_postinstall(dev_priv);
- else if (INTEL_GEN(dev_priv) >= 8)
+ else if (GRAPHICS_VER(dev_priv) >= 8)
gen8_irq_postinstall(dev_priv);
else
ilk_irq_postinstall(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index cb03e4152d2d..9f94914958c3 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -719,7 +719,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
* it to userspace...
*/
reason = ((report32[0] >> OAREPORT_REASON_SHIFT) &
- (IS_GEN(stream->perf->i915, 12) ?
+ (GRAPHICS_VER(stream->perf->i915) == 12 ?
OAREPORT_REASON_MASK_EXTENDED :
OAREPORT_REASON_MASK));
@@ -734,7 +734,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
* understand that the ID has been squashed by the kernel.
*/
if (!(report32[0] & stream->perf->gen8_valid_ctx_bit) &&
- INTEL_GEN(stream->perf->i915) <= 11)
+ GRAPHICS_VER(stream->perf->i915) <= 11)
ctx_id = report32[2] = INVALID_CTX_ID;
/*
@@ -801,7 +801,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
if (start_offset != *offset) {
i915_reg_t oaheadptr;
- oaheadptr = IS_GEN(stream->perf->i915, 12) ?
+ oaheadptr = GRAPHICS_VER(stream->perf->i915) == 12 ?
GEN12_OAG_OAHEADPTR : GEN8_OAHEADPTR;
spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
@@ -854,7 +854,7 @@ static int gen8_oa_read(struct i915_perf_stream *stream,
if (drm_WARN_ON(&uncore->i915->drm, !stream->oa_buffer.vaddr))
return -EIO;
- oastatus_reg = IS_GEN(stream->perf->i915, 12) ?
+ oastatus_reg = GRAPHICS_VER(stream->perf->i915) == 12 ?
GEN12_OAG_OASTATUS : GEN8_OASTATUS;
oastatus = intel_uncore_read(uncore, oastatus_reg);
@@ -901,7 +901,7 @@ static int gen8_oa_read(struct i915_perf_stream *stream,
intel_uncore_rmw(uncore, oastatus_reg,
GEN8_OASTATUS_COUNTER_OVERFLOW |
GEN8_OASTATUS_REPORT_LOST,
- IS_GEN_RANGE(uncore->i915, 8, 11) ?
+ IS_GRAPHICS_VER(uncore->i915, 8, 11) ?
(GEN8_OASTATUS_HEAD_POINTER_WRAP |
GEN8_OASTATUS_TAIL_POINTER_WRAP) : 0);
}
@@ -1243,7 +1243,7 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
if (IS_ERR(ce))
return PTR_ERR(ce);
- switch (INTEL_GEN(ce->engine->i915)) {
+ switch (GRAPHICS_VER(ce->engine->i915)) {
case 7: {
/*
* On Haswell we don't do any post processing of the reports
@@ -1297,7 +1297,7 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
}
default:
- MISSING_CASE(INTEL_GEN(ce->engine->i915));
+ MISSING_CASE(GRAPHICS_VER(ce->engine->i915));
}
ce->tag = stream->specific_ctx_id;
@@ -1602,7 +1602,7 @@ static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;
cmd |= MI_SRM_LRM_GLOBAL_GTT;
- if (INTEL_GEN(stream->perf->i915) >= 8)
+ if (GRAPHICS_VER(stream->perf->i915) >= 8)
cmd++;
for (d = 0; d < dword_count; d++) {
@@ -1731,7 +1731,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
*cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
/* Restart from the beginning if we had timestamps roll over. */
- *cs++ = (INTEL_GEN(i915) < 8 ?
+ *cs++ = (GRAPHICS_VER(i915) < 8 ?
MI_BATCH_BUFFER_START :
MI_BATCH_BUFFER_START_GEN8) |
MI_BATCH_PREDICATE;
@@ -1768,7 +1768,7 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
*cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
/* Predicate the jump. */
- *cs++ = (INTEL_GEN(i915) < 8 ?
+ *cs++ = (GRAPHICS_VER(i915) < 8 ?
MI_BATCH_BUFFER_START :
MI_BATCH_BUFFER_START_GEN8) |
MI_BATCH_PREDICATE;
@@ -1892,7 +1892,7 @@ alloc_oa_config_buffer(struct i915_perf_stream *stream,
oa_config->flex_regs_len);
/* Jump into the active wait. */
- *cs++ = (INTEL_GEN(stream->perf->i915) < 8 ?
+ *cs++ = (GRAPHICS_VER(stream->perf->i915) < 8 ?
MI_BATCH_BUFFER_START :
MI_BATCH_BUFFER_START_GEN8);
*cs++ = i915_ggtt_offset(stream->noa_wait);
@@ -2492,7 +2492,7 @@ gen8_enable_metric_set(struct i915_perf_stream *stream,
* be read back from automatically triggered reports, as part of the
* RPT_ID field.
*/
- if (IS_GEN_RANGE(stream->perf->i915, 9, 11)) {
+ if (IS_GRAPHICS_VER(stream->perf->i915, 9, 11)) {
intel_uncore_write(uncore, GEN8_OA_DEBUG,
_MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
@@ -2797,7 +2797,7 @@ get_default_sseu_config(struct intel_sseu *out_sseu,
*out_sseu = intel_sseu_from_device_info(devinfo_sseu);
- if (IS_GEN(engine->i915, 11)) {
+ if (GRAPHICS_VER(engine->i915) == 11) {
/*
* We only need subslice count so it doesn't matter which ones
* we select - just turn off low bits in the amount of half of
@@ -2864,7 +2864,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
}
if (!(props->sample_flags & SAMPLE_OA_REPORT) &&
- (INTEL_GEN(perf->i915) < 12 || !stream->ctx)) {
+ (GRAPHICS_VER(perf->i915) < 12 || !stream->ctx)) {
DRM_DEBUG("Only OA report sampling supported\n");
return -EINVAL;
}
@@ -3006,7 +3006,7 @@ void i915_oa_init_reg_state(const struct intel_context *ce,
/* perf.exclusive_stream serialised by lrc_configure_all_contexts() */
stream = READ_ONCE(engine->i915->perf.exclusive_stream);
- if (stream && INTEL_GEN(stream->perf->i915) < 12)
+ if (stream && GRAPHICS_VER(stream->perf->i915) < 12)
gen8_update_reg_state_unlocked(ce, stream);
}
@@ -3443,7 +3443,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
*/
if (IS_HASWELL(perf->i915) && specific_ctx)
privileged_op = false;
- else if (IS_GEN(perf->i915, 12) && specific_ctx &&
+ else if (GRAPHICS_VER(perf->i915) == 12 && specific_ctx &&
(props->sample_flags & SAMPLE_OA_REPORT) == 0)
privileged_op = false;
@@ -4119,7 +4119,7 @@ int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
}
oa_config->b_counter_regs = regs;
- if (INTEL_GEN(perf->i915) < 8) {
+ if (GRAPHICS_VER(perf->i915) < 8) {
if (args->n_flex_regs != 0) {
err = -EINVAL;
goto reg_err;
@@ -4365,7 +4365,7 @@ void i915_perf_init(struct drm_i915_private *i915)
*/
perf->ops.read = gen8_oa_read;
- if (IS_GEN_RANGE(i915, 8, 9)) {
+ if (IS_GRAPHICS_VER(i915, 8, 9)) {
perf->ops.is_valid_b_counter_reg =
gen7_is_valid_b_counter_addr;
perf->ops.is_valid_mux_reg =
@@ -4384,7 +4384,7 @@ void i915_perf_init(struct drm_i915_private *i915)
perf->ops.disable_metric_set = gen8_disable_metric_set;
perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
- if (IS_GEN(i915, 8)) {
+ if (GRAPHICS_VER(i915) == 8) {
perf->ctx_oactxctrl_offset = 0x120;
perf->ctx_flexeu0_offset = 0x2ce;
@@ -4395,7 +4395,7 @@ void i915_perf_init(struct drm_i915_private *i915)
perf->gen8_valid_ctx_bit = BIT(16);
}
- } else if (IS_GEN_RANGE(i915, 10, 11)) {
+ } else if (IS_GRAPHICS_VER(i915, 10, 11)) {
perf->ops.is_valid_b_counter_reg =
gen7_is_valid_b_counter_addr;
perf->ops.is_valid_mux_reg =
@@ -4409,7 +4409,7 @@ void i915_perf_init(struct drm_i915_private *i915)
perf->ops.disable_metric_set = gen10_disable_metric_set;
perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
- if (IS_GEN(i915, 10)) {
+ if (GRAPHICS_VER(i915) == 10) {
perf->ctx_oactxctrl_offset = 0x128;
perf->ctx_flexeu0_offset = 0x3de;
} else {
@@ -4417,7 +4417,7 @@ void i915_perf_init(struct drm_i915_private *i915)
perf->ctx_flexeu0_offset = 0x78e;
}
perf->gen8_valid_ctx_bit = BIT(16);
- } else if (IS_GEN(i915, 12)) {
+ } else if (GRAPHICS_VER(i915) == 12) {
perf->ops.is_valid_b_counter_reg =
gen12_is_valid_b_counter_addr;
perf->ops.is_valid_mux_reg =
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index a75cd1db320b..22c4d4178766 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -287,7 +287,7 @@ static bool exclusive_mmio_access(const struct drm_i915_private *i915)
* risk a machine hang. For a fun history lesson dig out the old
* userspace intel_gpu_top and run it on Ivybridge or Haswell!
*/
- return IS_GEN(i915, 7);
+ return GRAPHICS_VER(i915) == 7;
}
static void engine_sample(struct intel_engine_cs *engine, unsigned int period_ns)
@@ -463,7 +463,7 @@ engine_event_status(struct intel_engine_cs *engine,
case I915_SAMPLE_WAIT:
break;
case I915_SAMPLE_SEMA:
- if (INTEL_GEN(engine->i915) < 6)
+ if (GRAPHICS_VER(engine->i915) < 6)
return -ENODEV;
break;
default:
@@ -485,7 +485,7 @@ config_status(struct drm_i915_private *i915, u64 config)
return -ENODEV;
fallthrough;
case I915_PMU_REQUESTED_FREQUENCY:
- if (INTEL_GEN(i915) < 6)
+ if (GRAPHICS_VER(i915) < 6)
return -ENODEV;
break;
case I915_PMU_INTERRUPTS:
@@ -1147,7 +1147,7 @@ void i915_pmu_register(struct drm_i915_private *i915)
int ret = -ENOMEM;
- if (INTEL_GEN(i915) <= 2) {
+ if (GRAPHICS_VER(i915) <= 2) {
drm_info(&i915->drm, "PMU not supported for this GPU.");
return;
}
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 970d8f4986bb..a14ef8bbdc0b 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1176,12 +1176,12 @@ __emit_semaphore_wait(struct i915_request *to,
struct i915_request *from,
u32 seqno)
{
- const int has_token = INTEL_GEN(to->engine->i915) >= 12;
+ const int has_token = GRAPHICS_VER(to->engine->i915) >= 12;
u32 hwsp_offset;
int len, err;
u32 *cs;
- GEM_BUG_ON(INTEL_GEN(to->engine->i915) < 8);
+ GEM_BUG_ON(GRAPHICS_VER(to->engine->i915) < 8);
GEM_BUG_ON(i915_request_has_initial_breadcrumb(to));
/* We need to pin the signaler's HWSP until we are finished reading. */
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 5fcc32821e18..f7b55f34dba8 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -38,14 +38,14 @@ static void intel_save_swf(struct drm_i915_private *dev_priv)
int i;
/* Scratch space */
- if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
+ if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) {
for (i = 0; i < 7; i++) {
dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i));
dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
}
for (i = 0; i < 3; i++)
dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));
- } else if (IS_GEN(dev_priv, 2)) {
+ } else if (GRAPHICS_VER(dev_priv) == 2) {
for (i = 0; i < 7; i++)
dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
} else if (HAS_GMCH(dev_priv)) {
@@ -63,14 +63,14 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv)
int i;
/* Scratch space */
- if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
+ if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) {
for (i = 0; i < 7; i++) {
intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]);
intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
}
for (i = 0; i < 3; i++)
intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]);
- } else if (IS_GEN(dev_priv, 2)) {
+ } else if (GRAPHICS_VER(dev_priv) == 2) {
for (i = 0; i < 7; i++)
intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
} else if (HAS_GMCH(dev_priv)) {
@@ -91,10 +91,10 @@ void i915_save_display(struct drm_i915_private *dev_priv)
return;
/* Display arbitration control */
- if (INTEL_GEN(dev_priv) <= 4)
+ if (GRAPHICS_VER(dev_priv) <= 4)
dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB);
- if (IS_GEN(dev_priv, 4))
+ if (GRAPHICS_VER(dev_priv) == 4)
pci_read_config_word(pdev, GCDGMBUS,
&dev_priv->regfile.saveGCDGMBUS);
@@ -110,12 +110,12 @@ void i915_restore_display(struct drm_i915_private *dev_priv)
intel_restore_swf(dev_priv);
- if (IS_GEN(dev_priv, 4))
+ if (GRAPHICS_VER(dev_priv) == 4)
pci_write_config_word(pdev, GCDGMBUS,
dev_priv->regfile.saveGCDGMBUS);
/* Display arbitration */
- if (INTEL_GEN(dev_priv) <= 4)
+ if (GRAPHICS_VER(dev_priv) <= 4)
intel_de_write(dev_priv, DSPARB, dev_priv->regfile.saveDSPARB);
/* only restore FBC info on the platform that supports FBC*/
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 4c6b5d52b5ca..b099e09ccc32 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -595,7 +595,7 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
ret = 0;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
- else if (INTEL_GEN(dev_priv) >= 6)
+ else if (GRAPHICS_VER(dev_priv) >= 6)
ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
if (ret)
drm_err(&dev_priv->drm, "RPS sysfs setup failed\n");
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 172799277dd5..31a105bc1792 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -74,7 +74,7 @@ void intel_vgpu_detect(struct drm_i915_private *dev_priv)
* we do not support VGT on older gens, return early so we don't have
* to consider differently numbered or sized MMIO bars
*/
- if (INTEL_GEN(dev_priv) < 6)
+ if (GRAPHICS_VER(dev_priv) < 6)
return;
shared_area = pci_iomap_range(pdev, 0, VGT_PVINFO_PAGE, VGT_PVINFO_SIZE);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index e16599b67b83..7eaa92fee421 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -257,10 +257,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
for_each_pipe(dev_priv, pipe)
runtime->num_scalers[pipe] = 0;
- else if (INTEL_GEN(dev_priv) >= 10) {
+ else if (GRAPHICS_VER(dev_priv) >= 10) {
for_each_pipe(dev_priv, pipe)
runtime->num_scalers[pipe] = 2;
- } else if (IS_GEN(dev_priv, 9)) {
+ } else if (GRAPHICS_VER(dev_priv) == 9) {
runtime->num_scalers[PIPE_A] = 2;
runtime->num_scalers[PIPE_B] = 2;
runtime->num_scalers[PIPE_C] = 1;
@@ -271,10 +271,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 4;
- else if (INTEL_GEN(dev_priv) >= 11)
+ else if (GRAPHICS_VER(dev_priv) >= 11)
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 6;
- else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
+ else if (GRAPHICS_VER(dev_priv) == 10 || IS_GEMINILAKE(dev_priv))
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 3;
else if (IS_BROXTON(dev_priv)) {
@@ -293,12 +293,12 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 2;
- } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
+ } else if (GRAPHICS_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 1;
}
- if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) &&
+ if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
HAS_PCH_SPLIT(dev_priv)) {
u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
@@ -325,7 +325,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
info->pipe_mask &= ~BIT(PIPE_C);
info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
}
- } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
+ } else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) {
u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
@@ -340,7 +340,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
info->pipe_mask &= ~BIT(PIPE_C);
info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
}
- if (INTEL_GEN(dev_priv) >= 12 &&
+ if (GRAPHICS_VER(dev_priv) >= 12 &&
(dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
info->pipe_mask &= ~BIT(PIPE_D);
info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
@@ -352,15 +352,15 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
info->display.has_fbc = 0;
- if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
+ if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
info->display.has_dmc = 0;
- if (INTEL_GEN(dev_priv) >= 10 &&
+ if (GRAPHICS_VER(dev_priv) >= 10 &&
(dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
info->display.has_dsc = 0;
}
- if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
+ if (GRAPHICS_VER(dev_priv) == 6 && intel_vtd_active()) {
drm_info(&dev_priv->drm,
"Disabling ppGTT for VT-d support\n");
info->ppgtt_type = INTEL_PPGTT_NONE;
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 1e53c017c30d..50fdea84ba70 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -121,7 +121,7 @@ skl_dram_get_dimm_info(struct drm_i915_private *i915,
struct dram_dimm_info *dimm,
int channel, char dimm_name, u16 val)
{
- if (INTEL_GEN(i915) >= 10) {
+ if (GRAPHICS_VER(i915) >= 10) {
dimm->size = cnl_get_dimm_size(val);
dimm->width = cnl_get_dimm_width(val);
dimm->ranks = cnl_get_dimm_ranks(val);
@@ -422,7 +422,7 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
if (ret)
return ret;
- if (IS_GEN(dev_priv, 12)) {
+ if (GRAPHICS_VER(dev_priv) == 12) {
switch (val & 0xf) {
case 0:
dram_info->type = INTEL_DRAM_DDR4;
@@ -501,12 +501,12 @@ void intel_dram_detect(struct drm_i915_private *i915)
*/
dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);
- if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
+ if (GRAPHICS_VER(i915) < 9 || !HAS_DISPLAY(i915))
return;
- if (INTEL_GEN(i915) >= 12)
+ if (GRAPHICS_VER(i915) >= 12)
ret = gen12_get_dram_info(i915);
- else if (INTEL_GEN(i915) >= 11)
+ else if (GRAPHICS_VER(i915) >= 11)
ret = gen11_get_dram_info(i915);
else if (IS_GEN9_LP(i915))
ret = bxt_get_dram_info(i915);
@@ -535,7 +535,7 @@ void intel_dram_edram_detect(struct drm_i915_private *i915)
{
u32 edram_cap = 0;
- if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || INTEL_GEN(i915) >= 9))
+ if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9))
return;
edram_cap = __raw_uncore_read32(&i915->uncore, HSW_EDRAM_CAP);
@@ -549,7 +549,7 @@ void intel_dram_edram_detect(struct drm_i915_private *i915)
* The needed capability bits for size calculation are not there with
* pre gen9 so return 128MB always.
*/
- if (INTEL_GEN(i915) < 9)
+ if (GRAPHICS_VER(i915) < 9)
i915->edram_size_mb = 128;
else
i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index 98a17dd1bda4..4e92ae19189e 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -13,17 +13,17 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
switch (id) {
case INTEL_PCH_IBX_DEVICE_ID_TYPE:
drm_dbg_kms(&dev_priv->drm, "Found Ibex Peak PCH\n");
- drm_WARN_ON(&dev_priv->drm, !IS_GEN(dev_priv, 5));
+ drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) != 5);
return PCH_IBX;
case INTEL_PCH_CPT_DEVICE_ID_TYPE:
drm_dbg_kms(&dev_priv->drm, "Found CougarPoint PCH\n");
drm_WARN_ON(&dev_priv->drm,
- !IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
+ GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv));
return PCH_CPT;
case INTEL_PCH_PPT_DEVICE_ID_TYPE:
drm_dbg_kms(&dev_priv->drm, "Found PantherPoint PCH\n");
drm_WARN_ON(&dev_priv->drm,
- !IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
+ GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv));
/* PantherPoint is CPT compatible */
return PCH_CPT;
case INTEL_PCH_LPT_DEVICE_ID_TYPE:
@@ -181,9 +181,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv,
id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
- else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
+ else if (GRAPHICS_VER(dev_priv) == 6 || IS_IVYBRIDGE(dev_priv))
id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
- else if (IS_GEN(dev_priv, 5))
+ else if (GRAPHICS_VER(dev_priv) == 5)
id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
if (id)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 00f3dead20ad..74bbb05ce027 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7859,9 +7859,9 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.init_clock_gating = adlp_init_clock_gating;
else if (IS_DG1(dev_priv))
dev_priv->display.init_clock_gating = dg1_init_clock_gating;
- else if (IS_GEN(dev_priv, 12))
+ else if (GRAPHICS_VER(dev_priv) == 12)
dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
- else if (IS_GEN(dev_priv, 11))
+ else if (GRAPHICS_VER(dev_priv) == 11)
dev_priv->display.init_clock_gating = icl_init_clock_gating;
else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
@@ -7885,9 +7885,9 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.init_clock_gating = ivb_init_clock_gating;
else if (IS_VALLEYVIEW(dev_priv))
dev_priv->display.init_clock_gating = vlv_init_clock_gating;
- else if (IS_GEN(dev_priv, 6))
+ else if (GRAPHICS_VER(dev_priv) == 6)
dev_priv->display.init_clock_gating = gen6_init_clock_gating;
- else if (IS_GEN(dev_priv, 5))
+ else if (GRAPHICS_VER(dev_priv) == 5)
dev_priv->display.init_clock_gating = ilk_init_clock_gating;
else if (IS_G4X(dev_priv))
dev_priv->display.init_clock_gating = g4x_init_clock_gating;
@@ -7895,11 +7895,11 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
else if (IS_I965G(dev_priv))
dev_priv->display.init_clock_gating = i965g_init_clock_gating;
- else if (IS_GEN(dev_priv, 3))
+ else if (GRAPHICS_VER(dev_priv) == 3)
dev_priv->display.init_clock_gating = gen3_init_clock_gating;
else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
dev_priv->display.init_clock_gating = i85x_init_clock_gating;
- else if (IS_GEN(dev_priv, 2))
+ else if (GRAPHICS_VER(dev_priv) == 2)
dev_priv->display.init_clock_gating = i830_init_clock_gating;
else {
MISSING_CASE(INTEL_DEVID(dev_priv));
@@ -7913,7 +7913,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
/* For cxsr */
if (IS_PINEVIEW(dev_priv))
pnv_get_mem_freq(dev_priv);
- else if (IS_GEN(dev_priv, 5))
+ else if (GRAPHICS_VER(dev_priv) == 5)
ilk_get_mem_freq(dev_priv);
if (intel_has_sagv(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 0ec0cf191955..f0a82b37bd1a 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -430,7 +430,7 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
if (is_read && val1)
*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
- if (INTEL_GEN(i915) > 6)
+ if (GRAPHICS_VER(i915) > 6)
return gen7_check_mailbox_status(mbox);
else
return gen6_check_mailbox_status(mbox);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index b4aaf8b7109f..7178bc6f8556 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1635,7 +1635,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
#define fw_domain_init(uncore__, id__, set__, ack__) \
(ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__))))
- if (INTEL_GEN(i915) >= 11) {
+ if (GRAPHICS_VER(i915) >= 11) {
/* we'll prune the domains of missing engines later */
intel_engine_mask_t emask = INTEL_INFO(i915)->platform_engine_mask;
int i;
@@ -1665,7 +1665,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
FORCEWAKE_MEDIA_VEBOX_GEN11(i),
FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
}
- } else if (IS_GEN_RANGE(i915, 9, 10)) {
+ } else if (IS_GRAPHICS_VER(i915, 9, 10)) {
uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
uncore->funcs.force_wake_put = fw_domains_put;
fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
@@ -1733,7 +1733,7 @@ static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
FORCEWAKE, FORCEWAKE_ACK);
}
- } else if (IS_GEN(i915, 6)) {
+ } else if (GRAPHICS_VER(i915) == 6) {
uncore->funcs.force_wake_get =
fw_domains_get_with_thread_status;
uncore->funcs.force_wake_put = fw_domains_put;
@@ -1800,7 +1800,7 @@ static int uncore_mmio_setup(struct intel_uncore *uncore)
int mmio_bar;
int mmio_size;
- mmio_bar = IS_GEN(i915, 2) ? 1 : 0;
+ mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
/*
* Before gen4, the registers and the GTT are behind different BARs.
* However, from gen4 onwards, the registers and the GTT are shared
@@ -1810,7 +1810,7 @@ static int uncore_mmio_setup(struct intel_uncore *uncore)
* generations up to Ironlake.
* For dgfx chips register range is expanded to 4MB.
*/
- if (INTEL_GEN(i915) < 5)
+ if (GRAPHICS_VER(i915) < 5)
mmio_size = 512 * 1024;
else if (IS_DGFX(i915))
mmio_size = 4 * 1024 * 1024;
@@ -1849,7 +1849,7 @@ static void uncore_raw_init(struct intel_uncore *uncore)
if (intel_vgpu_active(uncore->i915)) {
ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu);
ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu);
- } else if (IS_GEN(uncore->i915, 5)) {
+ } else if (GRAPHICS_VER(uncore->i915) == 5) {
ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
} else {
@@ -1870,7 +1870,7 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
return ret;
forcewake_early_sanitize(uncore, 0);
- if (IS_GEN_RANGE(i915, 6, 7)) {
+ if (IS_GRAPHICS_VER(i915, 6, 7)) {
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
if (IS_VALLEYVIEW(i915)) {
@@ -1879,7 +1879,7 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
} else {
ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
}
- } else if (IS_GEN(i915, 8)) {
+ } else if (GRAPHICS_VER(i915) == 8) {
if (IS_CHERRYVIEW(i915)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
@@ -1888,11 +1888,11 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);
ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
}
- } else if (IS_GEN_RANGE(i915, 9, 10)) {
+ } else if (IS_GRAPHICS_VER(i915, 9, 10)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
- } else if (IS_GEN(i915, 11)) {
+ } else if (GRAPHICS_VER(i915) == 11) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges);
ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable);
ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
@@ -1929,7 +1929,7 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
return -ENODEV;
}
- if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
+ if (GRAPHICS_VER(i915) > 5 && !intel_vgpu_active(i915))
uncore->flags |= UNCORE_HAS_FORCEWAKE;
if (!intel_uncore_has_forcewake(uncore)) {
@@ -1952,7 +1952,7 @@ int intel_uncore_init_mmio(struct intel_uncore *uncore)
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED;
- if (IS_GEN_RANGE(i915, 6, 7))
+ if (IS_GRAPHICS_VER(i915, 6, 7))
uncore->flags |= UNCORE_HAS_FIFO;
/* clear out unclaimed reg detection bit */
@@ -1979,7 +1979,7 @@ void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
enum forcewake_domain_id domain_id;
int i;
- if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(uncore->i915) < 11)
+ if (!intel_uncore_has_forcewake(uncore) || GRAPHICS_VER(uncore->i915) < 11)
return;
for (i = 0; i < I915_MAX_VCS; i++) {
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
index ec776591e1cf..8309455f13ea 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -81,7 +81,7 @@ void intel_wopcm_init_early(struct intel_wopcm *wopcm)
if (!HAS_GT_UC(i915))
return;
- if (INTEL_GEN(i915) >= 11)
+ if (GRAPHICS_VER(i915) >= 11)
wopcm->size = GEN11_WOPCM_SIZE;
else
wopcm->size = GEN9_WOPCM_SIZE;
@@ -93,7 +93,7 @@ static u32 context_reserved_size(struct drm_i915_private *i915)
{
if (IS_GEN9_LP(i915))
return BXT_WOPCM_RC6_CTX_RESERVED;
- else if (INTEL_GEN(i915) >= 10)
+ else if (GRAPHICS_VER(i915) >= 10)
return CNL_WOPCM_HW_CTX_RESERVED;
else
return 0;
@@ -145,11 +145,11 @@ static bool check_hw_restrictions(struct drm_i915_private *i915,
u32 guc_wopcm_base, u32 guc_wopcm_size,
u32 huc_fw_size)
{
- if (IS_GEN(i915, 9) && !gen9_check_dword_gap(i915, guc_wopcm_base,
- guc_wopcm_size))
+ if (GRAPHICS_VER(i915) == 9 && !gen9_check_dword_gap(i915, guc_wopcm_base,
+ guc_wopcm_size))
return false;
- if (IS_GEN(i915, 9) &&
+ if (GRAPHICS_VER(i915) == 9 &&
!gen9_check_huc_fw_fits(i915, guc_wopcm_size, huc_fw_size))
return false;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 0a1472bb12bc..f843a5040706 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1884,9 +1884,9 @@ static int igt_cs_tlb(void *arg)
u32 *cs = batch + i * 64 / sizeof(*cs);
u64 addr = (vm->total - PAGE_SIZE) + i * sizeof(u32);
- GEM_BUG_ON(INTEL_GEN(i915) < 6);
+ GEM_BUG_ON(GRAPHICS_VER(i915) < 6);
cs[0] = MI_STORE_DWORD_IMM_GEN4;
- if (INTEL_GEN(i915) >= 8) {
+ if (GRAPHICS_VER(i915) >= 8) {
cs[1] = lower_32_bits(addr);
cs[2] = upper_32_bits(addr);
cs[3] = i;
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c
index bfb0290967a1..9e9a6cb1d9e5 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf.c
+++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
@@ -98,7 +98,7 @@ test_stream(struct i915_perf *perf)
I915_ENGINE_CLASS_RENDER,
0),
.sample_flags = SAMPLE_OA_REPORT,
- .oa_format = IS_GEN(perf->i915, 12) ?
+ .oa_format = GRAPHICS_VER(perf->i915) == 12 ?
I915_OA_FORMAT_A32u40_A4u32_B8_C8 : I915_OA_FORMAT_C4_B8,
};
struct i915_perf_stream *stream;
@@ -162,7 +162,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
return PTR_ERR(cs);
len = 5;
- if (INTEL_GEN(rq->engine->i915) >= 8)
+ if (GRAPHICS_VER(rq->engine->i915) >= 8)
len++;
*cs++ = GFX_OP_PIPE_CONTROL(len);
@@ -363,7 +363,7 @@ static int live_noa_gpr(void *arg)
}
cmd = MI_STORE_REGISTER_MEM;
- if (INTEL_GEN(i915) >= 8)
+ if (GRAPHICS_VER(i915) >= 8)
cmd++;
cmd |= MI_USE_GGTT;
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
index ee8e753d98ce..db367a6721c5 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -963,7 +963,7 @@ static int live_empty_request(void *arg)
static struct i915_vma *recursive_batch(struct drm_i915_private *i915)
{
struct drm_i915_gem_object *obj;
- const int gen = INTEL_GEN(i915);
+ const int ver = GRAPHICS_VER(i915);
struct i915_vma *vma;
u32 *cmd;
int err;
@@ -988,11 +988,11 @@ static struct i915_vma *recursive_batch(struct drm_i915_private *i915)
goto err;
}
- if (gen >= 8) {
+ if (ver >= 8) {
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
*cmd++ = lower_32_bits(vma->node.start);
*cmd++ = upper_32_bits(vma->node.start);
- } else if (gen >= 6) {
+ } else if (ver >= 6) {
*cmd++ = MI_BATCH_BUFFER_START | 1 << 8;
*cmd++ = lower_32_bits(vma->node.start);
} else {
@@ -2482,7 +2482,7 @@ static int perf_request_latency(void *arg)
struct pm_qos_request qos;
int err = 0;
- if (INTEL_GEN(i915) < 8) /* per-engine CS timestamp, semaphores */
+ if (GRAPHICS_VER(i915) < 8) /* per-engine CS timestamp, semaphores */
return 0;
cpu_latency_qos_add_request(&qos, 0); /* disable cstates */
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index 5fe397b7d1d9..24d87d0fc747 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -174,15 +174,15 @@ igt_spinner_create_request(struct igt_spinner *spin,
batch = spin->batch;
- if (INTEL_GEN(rq->engine->i915) >= 8) {
+ if (GRAPHICS_VER(rq->engine->i915) >= 8) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = lower_32_bits(hws_address(hws, rq));
*batch++ = upper_32_bits(hws_address(hws, rq));
- } else if (INTEL_GEN(rq->engine->i915) >= 6) {
+ } else if (GRAPHICS_VER(rq->engine->i915) >= 6) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = 0;
*batch++ = hws_address(hws, rq);
- } else if (INTEL_GEN(rq->engine->i915) >= 4) {
+ } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*batch++ = 0;
*batch++ = hws_address(hws, rq);
@@ -194,11 +194,11 @@ igt_spinner_create_request(struct igt_spinner *spin,
*batch++ = arbitration_command;
- if (INTEL_GEN(rq->engine->i915) >= 8)
+ if (GRAPHICS_VER(rq->engine->i915) >= 8)
*batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1;
else if (IS_HASWELL(rq->engine->i915))
*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW;
- else if (INTEL_GEN(rq->engine->i915) >= 6)
+ else if (GRAPHICS_VER(rq->engine->i915) >= 6)
*batch++ = MI_BATCH_BUFFER_START;
else
*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
@@ -216,7 +216,7 @@ igt_spinner_create_request(struct igt_spinner *spin,
}
flags = 0;
- if (INTEL_GEN(rq->engine->i915) <= 5)
+ if (GRAPHICS_VER(rq->engine->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index f76c9bcec735..8ef9e6a4ad05 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -321,7 +321,7 @@ static int live_fw_table(void *arg)
/* Confirm the table we load is still valid */
return intel_fw_table_check(gt->uncore->fw_domains_table,
gt->uncore->fw_domains_table_entries,
- INTEL_GEN(gt->i915) >= 9);
+ GRAPHICS_VER(gt->i915) >= 9);
}
int intel_uncore_live_selftests(struct drm_i915_private *i915)
--
2.31.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 6/7] drm/i915: Add remaining conversions to GRAPHICS_VER
2021-05-27 18:16 [Intel-gfx] [PATCH 0/7] Finish conversion to GRAPHICS_VER Lucas De Marchi
` (4 preceding siblings ...)
2021-05-27 18:16 ` [Intel-gfx] [PATCH 5/7] drm/i915: " Lucas De Marchi
@ 2021-05-27 18:16 ` Lucas De Marchi
2021-05-27 18:17 ` [Intel-gfx] [PATCH 7/7] drm/i915/display: replace IS_GEN() in commented code Lucas De Marchi
` (4 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2021-05-27 18:16 UTC (permalink / raw)
To: intel-gfx
For some reason coccinelle misses a few cases in header files with calls to
INTEL_GEN()/IS_GEN(). Do a manual conversion for those.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 35 ++++++++++++++++-----------------
drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++++++------------
2 files changed, 30 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0f6d27da69ac..ea8cc2656261 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1563,9 +1563,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_ALDERLAKE_P(__i915) && \
IS_GT_STEP(__i915, since, until))
-#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
-#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
-#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
+#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
+#define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
+#define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
@@ -1585,12 +1585,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
* The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
* All later gens can run the final buffer from the ppgtt
*/
-#define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
+#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
-#define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
+#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
#define HAS_WT(dev_priv) HAS_EDRAM(dev_priv)
#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
@@ -1623,7 +1623,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
- (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
+ (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
/* WaRsDisableCoarsePowerGating:skl,cnl */
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
@@ -1631,23 +1631,22 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SKL_GT3(dev_priv) || \
IS_SKL_GT4(dev_priv))
-#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
-#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
+#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
+#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \
IS_GEMINILAKE(dev_priv) || \
IS_KABYLAKE(dev_priv))
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming.
*/
-#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
- !(IS_I915G(dev_priv) || \
- IS_I915GM(dev_priv)))
+#define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
+ !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
-#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
+#define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2)
#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
-#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
+#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7)
#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
@@ -1658,7 +1657,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
#define HAS_PSR_HW_TRACKING(dev_priv) \
(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
-#define HAS_PSR2_SEL_FETCH(dev_priv) (INTEL_GEN(dev_priv) >= 12)
+#define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
#define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
@@ -1669,7 +1668,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc)
-#define HAS_MSO(i915) (INTEL_GEN(i915) >= 12)
+#define HAS_MSO(i915) (GRAPHICS_VER(i915) >= 12)
#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
@@ -1702,7 +1701,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
-#define HAS_VRR(i915) (INTEL_GEN(i915) >= 12)
+#define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 12)
/* Only valid when HAS_DISPLAY() is true */
#define INTEL_DISPLAY_ENABLED(dev_priv) \
@@ -1729,7 +1728,7 @@ static inline bool intel_vtd_active(void)
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
- return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
+ return GRAPHICS_VER(dev_priv) >= 6 && intel_vtd_active();
}
static inline bool
@@ -1947,7 +1946,7 @@ int remap_io_sg(struct vm_area_struct *vma,
static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) >= 10)
+ if (GRAPHICS_VER(i915) >= 10)
return CNL_HWS_CSB_WRITE_INDEX;
else
return I915_HWS_CSB_WRITE_INDEX;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 42f7909fc842..ba891c1ab6c7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9902,7 +9902,7 @@ enum skl_power_gate {
#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \
_TRANSB_HDCP_CONF)
#define HDCP_CONF(dev_priv, trans, port) \
- (INTEL_GEN(dev_priv) >= 12 ? \
+ (GRAPHICS_VER(dev_priv) >= 12 ? \
TRANS_HDCP_CONF(trans) : \
PORT_HDCP_CONF(port))
@@ -9915,7 +9915,7 @@ enum skl_power_gate {
_TRANSA_HDCP_ANINIT, \
_TRANSB_HDCP_ANINIT)
#define HDCP_ANINIT(dev_priv, trans, port) \
- (INTEL_GEN(dev_priv) >= 12 ? \
+ (GRAPHICS_VER(dev_priv) >= 12 ? \
TRANS_HDCP_ANINIT(trans) : \
PORT_HDCP_ANINIT(port))
@@ -9925,7 +9925,7 @@ enum skl_power_gate {
#define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \
_TRANSB_HDCP_ANLO)
#define HDCP_ANLO(dev_priv, trans, port) \
- (INTEL_GEN(dev_priv) >= 12 ? \
+ (GRAPHICS_VER(dev_priv) >= 12 ? \
TRANS_HDCP_ANLO(trans) : \
PORT_HDCP_ANLO(port))
@@ -9935,7 +9935,7 @@ enum skl_power_gate {
#define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \
_TRANSB_HDCP_ANHI)
#define HDCP_ANHI(dev_priv, trans, port) \
- (INTEL_GEN(dev_priv) >= 12 ? \
+ (GRAPHICS_VER(dev_priv) >= 12 ? \
TRANS_HDCP_ANHI(trans) : \
PORT_HDCP_ANHI(port))
@@ -9946,7 +9946,7 @@ enum skl_power_gate {
_TRANSA_HDCP_BKSVLO, \
_TRANSB_HDCP_BKSVLO)
#define HDCP_BKSVLO(dev_priv, trans, port) \
- (INTEL_GEN(dev_priv) >= 12 ? \
+ (GRAPHICS_VER(dev_priv) >= 12 ? \
TRANS_HDCP_BKSVLO(trans) : \
PORT_HDCP_BKSVLO(port))
@@ -9957,7 +9957,7 @@ enum skl_power_gate {
_TRANSA_HDCP_BKSVHI, \
_TRANSB_HDCP_BKSVHI)
#define HDCP_BKSVHI(dev_priv, trans, port) \
- (INTEL_GEN(dev_priv) >= 12 ? \
+ (GRAPHICS_VER(dev_priv) >= 12 ? \
TRANS_HDCP_BKSVHI(trans) : \
PORT_HDCP_BKSVHI(port))
@@ -9968,7 +9968,7 @@ enum skl_power_gate {
_TRANSA_HDCP_RPRIME, \
_TRANSB_HDCP_RPRIME)
#define HDCP_RPRIME(dev_priv, trans, port) \
- (INTEL_GEN(dev_priv) >= 12 ? \
+ (GRAPHICS_VER(dev_priv) >= 12 ? \
TRANS_HDCP_RPRIME(trans) : \
PORT_HDCP_RPRIME(port))
@@ -9979,7 +9979,7 @@ enum skl_power_gate {
_TRANSA_HDCP_STATUS, \
_TRANSB_HDCP_STATUS)
#define HDCP_STATUS(dev_priv, trans, port) \
- (INTEL_GEN(dev_priv) >= 12 ? \
+ (GRAPHICS_VER(dev_priv) >= 12 ? \
TRANS_HDCP_STATUS(trans) : \
PORT_HDCP_STATUS(port))
@@ -10020,7 +10020,7 @@ enum skl_power_gate {
#define AUTH_FORCE_CLR_INPUTCTR BIT(19)
#define AUTH_CLR_KEYS BIT(18)
#define HDCP2_AUTH(dev_priv, trans, port) \
- (INTEL_GEN(dev_priv) >= 12 ? \
+ (GRAPHICS_VER(dev_priv) >= 12 ? \
TRANS_HDCP2_AUTH(trans) : \
PORT_HDCP2_AUTH(port))
@@ -10031,7 +10031,7 @@ enum skl_power_gate {
_TRANSB_HDCP2_CTL)
#define CTL_LINK_ENCRYPTION_REQ BIT(31)
#define HDCP2_CTL(dev_priv, trans, port) \
- (INTEL_GEN(dev_priv) >= 12 ? \
+ (GRAPHICS_VER(dev_priv) >= 12 ? \
TRANS_HDCP2_CTL(trans) : \
PORT_HDCP2_CTL(port))
@@ -10045,7 +10045,7 @@ enum skl_power_gate {
#define LINK_AUTH_STATUS BIT(21)
#define LINK_ENCRYPTION_STATUS BIT(20)
#define HDCP2_STATUS(dev_priv, trans, port) \
- (INTEL_GEN(dev_priv) >= 12 ? \
+ (GRAPHICS_VER(dev_priv) >= 12 ? \
TRANS_HDCP2_STATUS(trans) : \
PORT_HDCP2_STATUS(port))
@@ -10067,7 +10067,7 @@ enum skl_power_gate {
#define STREAM_ENCRYPTION_STATUS BIT(31)
#define STREAM_TYPE_STATUS BIT(30)
#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
- (INTEL_GEN(dev_priv) >= 12 ? \
+ (GRAPHICS_VER(dev_priv) >= 12 ? \
TRANS_HDCP2_STREAM_STATUS(trans) : \
PIPE_HDCP2_STREAM_STATUS(pipe))
@@ -10083,7 +10083,7 @@ enum skl_power_gate {
_TRANSB_HDCP2_AUTH_STREAM)
#define AUTH_STREAM_TYPE BIT(31)
#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
- (INTEL_GEN(dev_priv) >= 12 ? \
+ (GRAPHICS_VER(dev_priv) >= 12 ? \
TRANS_HDCP2_AUTH_STREAM(trans) : \
PORT_HDCP2_AUTH_STREAM(port))
--
2.31.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 7/7] drm/i915/display: replace IS_GEN() in commented code
2021-05-27 18:16 [Intel-gfx] [PATCH 0/7] Finish conversion to GRAPHICS_VER Lucas De Marchi
` (5 preceding siblings ...)
2021-05-27 18:16 ` [Intel-gfx] [PATCH 6/7] drm/i915: Add remaining conversions to GRAPHICS_VER Lucas De Marchi
@ 2021-05-27 18:17 ` Lucas De Marchi
2021-05-27 21:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Finish conversion to GRAPHICS_VER Patchwork
` (3 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2021-05-27 18:17 UTC (permalink / raw)
To: intel-gfx
Since we are replacing IS_GEN() with GRAPHICS_VER(), make sure we take
care of the comments as well.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_tv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
index ce73ebdfc669..aa52af7891f0 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -1307,7 +1307,7 @@ intel_tv_compute_config(struct intel_encoder *encoder,
* the active portion. Hence following this formula seems
* more trouble that it's worth.
*
- * if (IS_GEN(dev_priv, 4)) {
+ * if (GRAPHICS_VER(dev_priv) == 4) {
* num = cdclk * (tv_mode->oversample >> !tv_mode->progressive);
* den = tv_mode->clock;
* } else {
--
2.31.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Finish conversion to GRAPHICS_VER
2021-05-27 18:16 [Intel-gfx] [PATCH 0/7] Finish conversion to GRAPHICS_VER Lucas De Marchi
` (6 preceding siblings ...)
2021-05-27 18:17 ` [Intel-gfx] [PATCH 7/7] drm/i915/display: replace IS_GEN() in commented code Lucas De Marchi
@ 2021-05-27 21:25 ` Patchwork
2021-05-27 21:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2021-05-27 21:25 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Finish conversion to GRAPHICS_VER
URL : https://patchwork.freedesktop.org/series/90693/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c7eb65fd23b6 drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
-:2316: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#2316: FILE: drivers/gpu/drm/i915/gt/selftest_llc.c:47:
+ intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
-:2325: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#2325: FILE: drivers/gpu/drm/i915/gt/selftest_llc.c:57:
+ intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
total: 0 errors, 2 warnings, 0 checks, 2252 lines checked
dc0babe0e3f4 drm/i915/gt: Add remaining conversions to GRAPHICS_VER
bf349477ef65 drm/i915/gem: replace IS_GEN and friends with IS_GRAPHICS_VER
5f5511830f0a drm/i915/gvt: replace IS_GEN and friends with IS_GRAPHICS_VER
e466a8d9d7b2 drm/i915: replace IS_GEN and friends with IS_GRAPHICS_VER
-:149: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#149: FILE: drivers/gpu/drm/i915/i915_debugfs.c:500:
+ (gt_perf_status & (GRAPHICS_VER(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
total: 0 errors, 1 warnings, 0 checks, 1352 lines checked
39f44ce0df3a drm/i915: Add remaining conversions to GRAPHICS_VER
-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#23: FILE: drivers/gpu/drm/i915/i915_drv.h:1567:
+#define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/i915_drv.h:1568:
+#define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
-:59: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#59: FILE: drivers/gpu/drm/i915/i915_drv.h:1635:
+#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \
IS_GEMINILAKE(dev_priv) || \
IS_KABYLAKE(dev_priv))
-:69: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#69: FILE: drivers/gpu/drm/i915/i915_drv.h:1642:
+#define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
+ !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
-:78: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#78: FILE: drivers/gpu/drm/i915/i915_drv.h:1649:
+#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7)
total: 0 errors, 0 warnings, 5 checks, 207 lines checked
473d823e7205 drm/i915/display: replace IS_GEN() in commented code
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Finish conversion to GRAPHICS_VER
2021-05-27 18:16 [Intel-gfx] [PATCH 0/7] Finish conversion to GRAPHICS_VER Lucas De Marchi
` (7 preceding siblings ...)
2021-05-27 21:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Finish conversion to GRAPHICS_VER Patchwork
@ 2021-05-27 21:27 ` Patchwork
2021-05-27 21:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-28 19:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
10 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2021-05-27 21:27 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: Finish conversion to GRAPHICS_VER
URL : https://patchwork.freedesktop.org/series/90693/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1893:21: expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1893:21: got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1893:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1207:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Finish conversion to GRAPHICS_VER
2021-05-27 18:16 [Intel-gfx] [PATCH 0/7] Finish conversion to GRAPHICS_VER Lucas De Marchi
` (8 preceding siblings ...)
2021-05-27 21:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-05-27 21:55 ` Patchwork
2021-05-28 19:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
10 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2021-05-27 21:55 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4109 bytes --]
== Series Details ==
Series: Finish conversion to GRAPHICS_VER
URL : https://patchwork.freedesktop.org/series/90693/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10145 -> Patchwork_20228
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/index.html
Known issues
------------
Here are the changes found in Patchwork_20228 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- fi-bsw-n3050: NOTRUN -> [SKIP][1] ([fdo#109271])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/fi-bsw-n3050/igt@gem_exec_gttfill@basic.html
* igt@gem_exec_suspend@basic-s3:
- fi-bsw-n3050: NOTRUN -> [INCOMPLETE][2] ([i915#3159])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/fi-bsw-n3050/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-skl-6700k2: [PASS][3] -> [DMESG-FAIL][4] ([i915#2291] / [i915#541])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/fi-skl-6700k2/igt@i915_selftest@live@gt_heartbeat.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/fi-skl-6700k2/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][5] -> [INCOMPLETE][6] ([i915#2782])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
#### Warnings ####
* igt@i915_selftest@live@execlists:
- fi-tgl-u2: [INCOMPLETE][7] ([i915#3462]) -> [DMESG-FAIL][8] ([i915#3462])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/fi-tgl-u2/igt@i915_selftest@live@execlists.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/fi-tgl-u2/igt@i915_selftest@live@execlists.html
* igt@runner@aborted:
- fi-bdw-5557u: [FAIL][9] ([i915#3462]) -> [FAIL][10] ([i915#1602] / [i915#2029])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/fi-bdw-5557u/igt@runner@aborted.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/fi-bdw-5557u/igt@runner@aborted.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#3159]: https://gitlab.freedesktop.org/drm/intel/issues/3159
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (43 -> 40)
------------------------------
Additional (1): fi-bsw-n3050
Missing (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_10145 -> Patchwork_20228
CI-20190529: 20190529
CI_DRM_10145: 1b8b25e48b6d72ccd335a79d30c7e6641befb17b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6095: 5c7b7a8e441577a00cc4e71ec0ae57af640eb92a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20228: 473d823e72053a189d32c2758ea5589ede97af85 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
473d823e7205 drm/i915/display: replace IS_GEN() in commented code
39f44ce0df3a drm/i915: Add remaining conversions to GRAPHICS_VER
e466a8d9d7b2 drm/i915: replace IS_GEN and friends with IS_GRAPHICS_VER
5f5511830f0a drm/i915/gvt: replace IS_GEN and friends with IS_GRAPHICS_VER
bf349477ef65 drm/i915/gem: replace IS_GEN and friends with IS_GRAPHICS_VER
dc0babe0e3f4 drm/i915/gt: Add remaining conversions to GRAPHICS_VER
c7eb65fd23b6 drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/index.html
[-- Attachment #1.2: Type: text/html, Size: 5023 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Finish conversion to GRAPHICS_VER
2021-05-27 18:16 [Intel-gfx] [PATCH 0/7] Finish conversion to GRAPHICS_VER Lucas De Marchi
` (9 preceding siblings ...)
2021-05-27 21:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-05-28 19:55 ` Patchwork
10 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2021-05-28 19:55 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30256 bytes --]
== Series Details ==
Series: Finish conversion to GRAPHICS_VER
URL : https://patchwork.freedesktop.org/series/90693/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10145_full -> Patchwork_20228_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20228_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20228_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20228_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_eio@hibernate:
- shard-glk: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-glk6/igt@gem_eio@hibernate.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-glk2/igt@gem_eio@hibernate.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-kbl: NOTRUN -> [TIMEOUT][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl3/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
Known issues
------------
Here are the changes found in Patchwork_20228_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-clear:
- shard-snb: [PASS][4] -> [INCOMPLETE][5] ([i915#2405] / [i915#2502])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-snb6/igt@gem_create@create-clear.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-snb7/igt@gem_create@create-clear.html
* igt@gem_create@create-massive:
- shard-skl: NOTRUN -> [DMESG-WARN][6] ([i915#3002])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl5/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +4 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-snb6/igt@gem_ctx_persistence@legacy-engines-mixed.html
* igt@gem_eio@in-flight-suspend:
- shard-apl: NOTRUN -> [DMESG-WARN][8] ([i915#180]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl1/igt@gem_eio@in-flight-suspend.html
* igt@gem_eio@unwedge-stress:
- shard-snb: NOTRUN -> [FAIL][9] ([i915#3354])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-snb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][10] ([i915#2846])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl1/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl1/igt@gem_exec_fair@basic-none@vecs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-tglb2/igt@gem_exec_fair@basic-pace@vcs1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb7/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_params@no-vebox:
- shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271]) +37 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl7/igt@gem_exec_params@no-vebox.html
* igt@gem_mmap_gtt@coherency:
- shard-tglb: NOTRUN -> [SKIP][16] ([fdo#111656])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb8/igt@gem_mmap_gtt@coherency.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy:
- shard-glk: [PASS][17] -> [INCOMPLETE][18] ([i915#2055] / [i915#3468])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-glk6/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-glk6/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
- shard-apl: NOTRUN -> [INCOMPLETE][19] ([i915#3468]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl6/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
- shard-skl: [PASS][20] -> [INCOMPLETE][21] ([i915#198] / [i915#3468])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-skl3/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl9/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
- shard-snb: NOTRUN -> [INCOMPLETE][22] ([i915#2055]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-snb2/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
- shard-tglb: [PASS][23] -> [INCOMPLETE][24] ([i915#3468])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-tglb6/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb5/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
- shard-apl: [PASS][25] -> [INCOMPLETE][26] ([i915#3468])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-apl3/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl3/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
* igt@gem_mmap_gtt@cpuset-medium-copy-xy:
- shard-iclb: [PASS][27] -> [INCOMPLETE][28] ([i915#3468])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-iclb6/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-iclb3/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html
* igt@gem_mmap_gtt@fault-concurrent:
- shard-kbl: NOTRUN -> [INCOMPLETE][29] ([i915#3468])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl3/igt@gem_mmap_gtt@fault-concurrent.html
* igt@gem_mmap_gtt@fault-concurrent-y:
- shard-skl: NOTRUN -> [INCOMPLETE][30] ([i915#3468] / [i915#3523])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl2/igt@gem_mmap_gtt@fault-concurrent-y.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3323])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl3/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@input-checking:
- shard-kbl: NOTRUN -> [DMESG-WARN][32] ([i915#3002])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl4/igt@gem_userptr_blits@input-checking.html
* igt@gen9_exec_parse@allowed-single:
- shard-tglb: NOTRUN -> [SKIP][33] ([fdo#112306])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb8/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-snb: NOTRUN -> [SKIP][34] ([fdo#109271]) +467 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-snb6/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@bb-large:
- shard-tglb: NOTRUN -> [SKIP][35] ([i915#2527])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb8/igt@gen9_exec_parse@bb-large.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-skl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#658])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl7/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_lpsp@screens-disabled:
- shard-tglb: NOTRUN -> [SKIP][37] ([i915#1902])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb8/igt@i915_pm_lpsp@screens-disabled.html
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [PASS][38] -> [INCOMPLETE][39] ([i915#151])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-skl8/igt@i915_pm_rpm@system-suspend.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl8/igt@i915_pm_rpm@system-suspend.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][40] ([fdo#111614])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb8/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_joiner@invalid-modeset:
- shard-kbl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#2705])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl7/igt@kms_big_joiner@invalid-modeset.html
- shard-apl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#2705])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl3/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_chamelium@hdmi-crc-nonplanar-formats:
- shard-glk: NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +4 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-glk5/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +12 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl4/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-a-ctm-0-25:
- shard-snb: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +27 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-snb2/igt@kms_color_chamelium@pipe-a-ctm-0-25.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +16 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl1/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-tglb: NOTRUN -> [SKIP][47] ([fdo#109284] / [fdo#111827]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb8/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
* igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes:
- shard-skl: NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +2 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl7/igt@kms_color_chamelium@pipe-invalid-degamma-lut-sizes.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][49] ([i915#1319])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl3/igt@kms_content_protection@lic.html
* igt@kms_content_protection@srm:
- shard-kbl: NOTRUN -> [TIMEOUT][50] ([i915#1319])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl3/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding:
- shard-tglb: NOTRUN -> [SKIP][51] ([i915#3319])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-512x170-sliding:
- shard-tglb: NOTRUN -> [SKIP][52] ([fdo#109279] / [i915#3359])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb8/igt@kms_cursor_crc@pipe-b-cursor-512x170-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][53] ([i915#180])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-128x42-random:
- shard-apl: NOTRUN -> [FAIL][54] ([i915#3444])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-128x42-random.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-skl: [PASS][55] -> [FAIL][56] ([i915#2346])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_dp_dsc@basic-dsc-enable-dp:
- shard-tglb: NOTRUN -> [SKIP][57] ([fdo#109349])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb8/igt@kms_dp_dsc@basic-dsc-enable-dp.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-tglb: NOTRUN -> [SKIP][58] ([fdo#111825]) +6 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb8/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend@b-edp1:
- shard-skl: [PASS][59] -> [INCOMPLETE][60] ([i915#198])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-skl2/igt@kms_flip@flip-vs-suspend@b-edp1.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl3/igt@kms_flip@flip-vs-suspend@b-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][61] -> [FAIL][62] ([i915#2122])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-skl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#2642])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#2672])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2672])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][66] -> [DMESG-WARN][67] ([i915#180]) +4 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render:
- shard-glk: NOTRUN -> [SKIP][68] ([fdo#109271]) +33 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-glk5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
- shard-skl: [PASS][69] -> [FAIL][70] ([i915#53]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-skl1/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl3/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][71] ([fdo#108145] / [i915#265])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][72] ([i915#265])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][73] ([fdo#108145] / [i915#265]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl3/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-glk: NOTRUN -> [FAIL][74] ([fdo#108145] / [i915#265])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-glk5/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-glk: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2733])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-glk5/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-apl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#658]) +3 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5:
- shard-tglb: NOTRUN -> [SKIP][77] ([i915#2920])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#658]) +3 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl4/igt@kms_psr2_sf@plane-move-sf-dmg-area-1.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
- shard-glk: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#658])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-glk5/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-tglb: NOTRUN -> [FAIL][80] ([i915#132] / [i915#3467])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb8/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][81] -> [SKIP][82] ([fdo#109441])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][83] ([fdo#109271]) +96 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl2/igt@kms_universal_plane@disable-primary-vs-flip-pipe-d.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][84] ([i915#180] / [i915#295])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#533]) +2 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl3/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-fb-id:
- shard-kbl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#2437])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl4/igt@kms_writeback@writeback-fb-id.html
* igt@nouveau_crc@pipe-a-source-rg:
- shard-tglb: NOTRUN -> [SKIP][87] ([i915#2530])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb8/igt@nouveau_crc@pipe-a-source-rg.html
* igt@perf@polling-parameterized:
- shard-glk: [PASS][88] -> [FAIL][89] ([i915#1542])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-glk9/igt@perf@polling-parameterized.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-glk5/igt@perf@polling-parameterized.html
* igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
- shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271]) +174 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl3/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
* igt@sysfs_clients@sema-10:
- shard-apl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2994]) +2 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl3/igt@sysfs_clients@sema-10.html
* igt@sysfs_clients@split-25:
- shard-kbl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#2994]) +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl3/igt@sysfs_clients@split-25.html
* igt@tools_test@sysfs_l3_parity:
- shard-tglb: NOTRUN -> [SKIP][93] ([fdo#109307])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb8/igt@tools_test@sysfs_l3_parity.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [DMESG-WARN][94] ([i915#180]) -> [PASS][95] +11 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [FAIL][96] ([i915#2842]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk: [FAIL][98] ([i915#2842]) -> [PASS][99] +1 similar issue
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-glk2/igt@gem_exec_fair@basic-pace@vecs0.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-glk8/igt@gem_exec_fair@basic-pace@vecs0.html
- shard-tglb: [FAIL][100] ([i915#2842]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-tglb2/igt@gem_exec_fair@basic-pace@vecs0.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb7/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
- shard-skl: [INCOMPLETE][102] ([i915#198] / [i915#3468]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-skl3/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl7/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
- shard-kbl: [INCOMPLETE][104] ([i915#3468]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl3/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl3/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
* igt@gem_mmap_gtt@cpuset-medium-copy-xy:
- shard-tglb: [INCOMPLETE][106] ([i915#3468] / [i915#750]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-tglb5/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-tglb8/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html
* igt@gem_tiled_wb:
- shard-glk: [DMESG-WARN][108] ([i915#118] / [i915#95]) -> [PASS][109] +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-glk9/igt@gem_tiled_wb.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-glk9/igt@gem_tiled_wb.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [DMESG-WARN][110] ([i915#180]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-apl1/igt@gem_workarounds@suspend-resume.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-apl8/igt@gem_workarounds@suspend-resume.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][112] ([i915#1188]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][114] ([fdo#108145] / [i915#265]) -> [PASS][115] +2 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [SKIP][116] ([fdo#109441]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-iclb8/igt@kms_psr@psr2_cursor_plane_move.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
* igt@sysfs_preempt_timeout@timeout@vcs0:
- shard-skl: [FAIL][118] ([i915#2821]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-skl3/igt@sysfs_preempt_timeout@timeout@vcs0.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-skl9/igt@sysfs_preempt_timeout@timeout@vcs0.html
#### Warnings ####
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [CRASH][120] ([i915#3494]) -> [SKIP][121] ([fdo#109349])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-iclb7/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled:
- shard-glk: [FAIL][122] -> [DMESG-FAIL][123] ([i915#118] / [i915#95])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-glk8/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-glk1/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-iclb: [SKIP][124] ([i915#2920]) -> [SKIP][125] ([i915#658]) +1 similar issue
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-iclb7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2722] / [i915#3002] / [i915#3363] / [i915#602] / [i915#92]) -> ([FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160], [FAIL][161], [FAIL][162]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#2292] / [i915#2722] / [i915#3002] / [i915#3363] / [i915#602] / [i915#92])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl7/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl1/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl3/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl7/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl4/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl3/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl2/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl1/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl4/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl3/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl7/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl7/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl2/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl4/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl4/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl2/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl3/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl1/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10145/shard-kbl4/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl1/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl2/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/shard-kbl
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20228/index.html
[-- Attachment #1.2: Type: text/html, Size: 33943 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
2021-05-27 18:16 ` [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER Lucas De Marchi
@ 2021-06-01 16:58 ` Matt Roper
2021-06-01 17:15 ` Lucas De Marchi
0 siblings, 1 reply; 20+ messages in thread
From: Matt Roper @ 2021-06-01 16:58 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Thu, May 27, 2021 at 11:16:54AM -0700, Lucas De Marchi wrote:
> This was done by the following semantic patch:
Is the commit message here out-of-date? The cocci doesn't appear to
match the diff anymore. IS_GRAPHICS_VER() is the range macro now and
IS_GEN is being replaced with a direct "==" comparison.
Matt
>
> @@ expression dev_priv, E; @@
> - INTEL_GEN(dev_priv) == E
> + IS_GRAPHICS_VER(dev_priv, E)
>
> @@ expression dev_priv; @@
> - INTEL_GEN(dev_priv)
> + GRAPHICS_VER(dev_priv)
>
> @@ expression dev_priv; expression E; @@
> - IS_GEN(dev_priv, E)
> + IS_GRAPHICS_VER(dev_priv, E)
>
> @@
> expression dev_priv;
> expression from, until;
> @@
> - IS_GEN_RANGE(dev_priv, from, until)
> + IS_GRAPHICS_RANGE(dev_priv, from, until)
>
> @def@
> expression E;
> identifier id =~ "^gen$";
> @@
> - id = GRAPHICS_VER(E)
> + ver = GRAPHICS_VER(E)
>
> @@
> identifier def.id;
> @@
> - id
> + ver
>
> It also takes care of renaming the variable we assign to GRAPHICS_VER()
> so to use "ver" rather than "gen".
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 38 +++++------
> drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 54 +++++++--------
> .../drm/i915/gt/intel_execlists_submission.c | 18 ++---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 18 ++---
> drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 34 +++++-----
> drivers/gpu/drm/i915/gt/intel_gt.c | 27 ++++----
> .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 12 ++--
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 10 +--
> drivers/gpu/drm/i915/gt/intel_gtt.c | 14 ++--
> drivers/gpu/drm/i915/gt/intel_llc.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 46 ++++++-------
> drivers/gpu/drm/i915/gt/intel_mocs.c | 8 +--
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_rc6.c | 16 ++---
> drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_reset.c | 12 ++--
> .../gpu/drm/i915/gt/intel_ring_submission.c | 64 +++++++++---------
> drivers/gpu/drm/i915/gt/intel_rps.c | 60 ++++++++---------
> drivers/gpu/drm/i915/gt/intel_sseu.c | 14 ++--
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +++++++++----------
> drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 6 +-
> drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_execlists.c | 4 +-
> drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +--
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 +--
> drivers/gpu/drm/i915/gt/selftest_llc.c | 4 +-
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 8 +--
> drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_rc6.c | 4 +-
> .../drm/i915/gt/selftest_ring_submission.c | 6 +-
> drivers/gpu/drm/i915/gt/selftest_rps.c | 16 ++---
> drivers/gpu/drm/i915/gt/selftest_timeline.c | 6 +-
> .../gpu/drm/i915/gt/selftest_workarounds.c | 8 +--
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +--
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
> 44 files changed, 323 insertions(+), 322 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> index d4f4452ce5ed..0389bceebd06 100644
> --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> @@ -85,14 +85,14 @@ static int gen6_drpc(struct seq_file *m)
> gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
>
> rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
> - if (INTEL_GEN(i915) >= 9) {
> + if (GRAPHICS_VER(i915) >= 9) {
> gen9_powergate_enable =
> intel_uncore_read(uncore, GEN9_PG_ENABLE);
> gen9_powergate_status =
> intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
> }
>
> - if (INTEL_GEN(i915) <= 7)
> + if (GRAPHICS_VER(i915) <= 7)
> sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
> &rc6vids, NULL);
>
> @@ -100,7 +100,7 @@ static int gen6_drpc(struct seq_file *m)
> yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
> seq_printf(m, "RC6 Enabled: %s\n",
> yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
> - if (INTEL_GEN(i915) >= 9) {
> + if (GRAPHICS_VER(i915) >= 9) {
> seq_printf(m, "Render Well Gating Enabled: %s\n",
> yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
> seq_printf(m, "Media Well Gating Enabled: %s\n",
> @@ -134,7 +134,7 @@ static int gen6_drpc(struct seq_file *m)
>
> seq_printf(m, "Core Power Down: %s\n",
> yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
> - if (INTEL_GEN(i915) >= 9) {
> + if (GRAPHICS_VER(i915) >= 9) {
> seq_printf(m, "Render Power Well: %s\n",
> (gen9_powergate_status &
> GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
> @@ -150,7 +150,7 @@ static int gen6_drpc(struct seq_file *m)
> print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
> print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
>
> - if (INTEL_GEN(i915) <= 7) {
> + if (GRAPHICS_VER(i915) <= 7) {
> seq_printf(m, "RC6 voltage: %dmV\n",
> GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
> seq_printf(m, "RC6+ voltage: %dmV\n",
> @@ -250,7 +250,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>
> wakeref = intel_runtime_pm_get(uncore->rpm);
>
> - if (IS_GEN(i915, 5)) {
> + if (GRAPHICS_VER(i915) == 5) {
> u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
> u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
>
> @@ -296,7 +296,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>
> seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
> intel_gpu_freq(rps, rps->efficient_freq));
> - } else if (INTEL_GEN(i915) >= 6) {
> + } else if (GRAPHICS_VER(i915) >= 6) {
> u32 rp_state_limits;
> u32 gt_perf_status;
> u32 rp_state_cap;
> @@ -321,7 +321,7 @@ static int frequency_show(struct seq_file *m, void *unused)
> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>
> reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
> - if (INTEL_GEN(i915) >= 9) {
> + if (GRAPHICS_VER(i915) >= 9) {
> reqf >>= 23;
> } else {
> reqf &= ~GEN6_TURBO_DISABLE;
> @@ -354,7 +354,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>
> intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>
> - if (INTEL_GEN(i915) >= 11) {
> + if (GRAPHICS_VER(i915) >= 11) {
> pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
> pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
> /*
> @@ -363,7 +363,7 @@ static int frequency_show(struct seq_file *m, void *unused)
> */
> pm_isr = 0;
> pm_iir = 0;
> - } else if (INTEL_GEN(i915) >= 8) {
> + } else if (GRAPHICS_VER(i915) >= 8) {
> pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
> pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
> pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
> @@ -386,14 +386,14 @@ static int frequency_show(struct seq_file *m, void *unused)
>
> seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
> pm_ier, pm_imr, pm_mask);
> - if (INTEL_GEN(i915) <= 10)
> + if (GRAPHICS_VER(i915) <= 10)
> seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
> pm_isr, pm_iir);
> seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
> rps->pm_intrmsk_mbz);
> seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> seq_printf(m, "Render p-state ratio: %d\n",
> - (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> + (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> seq_printf(m, "Render p-state VID: %d\n",
> gt_perf_status & 0xff);
> seq_printf(m, "Render p-state limit: %d\n",
> @@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void *unused)
> max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
> rp_state_cap >> 16) & 0xff;
> max_freq *= (IS_GEN9_BC(i915) ||
> - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
> intel_gpu_freq(rps, max_freq));
>
> max_freq = (rp_state_cap & 0xff00) >> 8;
> max_freq *= (IS_GEN9_BC(i915) ||
> - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
> intel_gpu_freq(rps, max_freq));
>
> max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
> rp_state_cap >> 0) & 0xff;
> max_freq *= (IS_GEN9_BC(i915) ||
> - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
> intel_gpu_freq(rps, max_freq));
> seq_printf(m, "Max overclocked frequency: %dMHz\n",
> @@ -488,7 +488,7 @@ static int llc_show(struct seq_file *m, void *data)
> {
> struct intel_gt *gt = m->private;
> struct drm_i915_private *i915 = gt->i915;
> - const bool edram = INTEL_GEN(i915) > 8;
> + const bool edram = GRAPHICS_VER(i915) > 8;
> struct intel_rps *rps = >->rps;
> unsigned int max_gpu_freq, min_gpu_freq;
> intel_wakeref_t wakeref;
> @@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data)
>
> min_gpu_freq = rps->min_freq;
> max_gpu_freq = rps->max_freq;
> - if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
> + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
> /* Convert GT frequency to 50 HZ units */
> min_gpu_freq /= GEN9_FREQ_SCALER;
> max_gpu_freq /= GEN9_FREQ_SCALER;
> @@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data)
> intel_gpu_freq(rps,
> (gpu_freq *
> (IS_GEN9_BC(i915) ||
> - INTEL_GEN(i915) >= 10 ?
> + GRAPHICS_VER(i915) >= 10 ?
> GEN9_FREQ_SCALER : 1))),
> ((ia_freq >> 0) & 0xff) * 100,
> ((ia_freq >> 8) & 0xff) * 100);
> @@ -580,7 +580,7 @@ static int rps_boost_show(struct seq_file *m, void *data)
>
> seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
>
> - if (INTEL_GEN(i915) >= 6 && intel_rps_is_active(rps)) {
> + if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) {
> struct intel_uncore *uncore = gt->uncore;
> u32 rpup, rpupei;
> u32 rpdown, rpdownei;
> diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> index 9646200d2792..61383830505e 100644
> --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> @@ -74,7 +74,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
> cmd = MI_FLUSH;
> if (mode & EMIT_INVALIDATE) {
> cmd |= MI_EXE_FLUSH;
> - if (IS_G4X(rq->engine->i915) || IS_GEN(rq->engine->i915, 5))
> + if (IS_G4X(rq->engine->i915) || GRAPHICS_VER(rq->engine->i915) == 5)
> cmd |= MI_INVALIDATE_ISP;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 732c2ed1d933..94e0a5669f90 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -38,7 +38,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
> * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
> * pipe control.
> */
> - if (IS_GEN(rq->engine->i915, 9))
> + if (GRAPHICS_VER(rq->engine->i915) == 9)
> vf_flush_wa = true;
>
> /* WaForGAMHang:kbl */
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index e3a8924d2286..21c8b7350b7a 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -709,7 +709,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> *
> * Gen12 has inherited the same read-only fault issue from gen11.
> */
> - ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12);
> + ppgtt->vm.has_read_only = !IS_GRAPHICS_VER(gt->i915, 11, 12);
>
> if (HAS_LMEM(gt->i915))
> ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;
> diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
> index 8dfd8f656aaa..e86d8255feec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
> @@ -76,7 +76,7 @@ intel_context_reconfigure_sseu(struct intel_context *ce,
> {
> int ret;
>
> - GEM_BUG_ON(INTEL_GEN(ce->engine->i915) < 8);
> + GEM_BUG_ON(GRAPHICS_VER(ce->engine->i915) < 8);
>
> ret = intel_context_lock_pinned(ce);
> if (ret)
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 3f9a811eb02b..54baf17b81b6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -240,10 +240,10 @@ void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
> * Though they added more rings on g4x/ilk, they did not add
> * per-engine HWSTAM until gen6.
> */
> - if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS)
> + if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)
> return;
>
> - if (INTEL_GEN(engine->i915) >= 3)
> + if (GRAPHICS_VER(engine->i915) >= 3)
> ENGINE_WRITE(engine, RING_HWSTAM, mask);
> else
> ENGINE_WRITE16(engine, RING_HWSTAM, mask);
> @@ -315,7 +315,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
> CONFIG_DRM_I915_TIMESLICE_DURATION;
>
> /* Override to uninterruptible for OpenCL workloads. */
> - if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS)
> + if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
> engine->props.preempt_timeout_ms = 0;
>
> engine->defaults = engine->props; /* never to change again */
> @@ -352,8 +352,8 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
> * HEVC support is present on first engine instance
> * before Gen11 and on all instances afterwards.
> */
> - if (INTEL_GEN(i915) >= 11 ||
> - (INTEL_GEN(i915) >= 9 && engine->instance == 0))
> + if (GRAPHICS_VER(i915) >= 11 ||
> + (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
> engine->uabi_capabilities |=
> I915_VIDEO_CLASS_CAPABILITY_HEVC;
>
> @@ -361,14 +361,14 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
> * SFC block is present only on even logical engine
> * instances.
> */
> - if ((INTEL_GEN(i915) >= 11 &&
> + if ((GRAPHICS_VER(i915) >= 11 &&
> (engine->gt->info.vdbox_sfc_access &
> BIT(engine->instance))) ||
> - (INTEL_GEN(i915) >= 9 && engine->instance == 0))
> + (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
> engine->uabi_capabilities |=
> I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
> } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
> - if (INTEL_GEN(i915) >= 9)
> + if (GRAPHICS_VER(i915) >= 9)
> engine->uabi_capabilities |=
> I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
> }
> @@ -466,7 +466,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>
> info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
>
> - if (INTEL_GEN(i915) < 11)
> + if (GRAPHICS_VER(i915) < 11)
> return info->engine_mask;
>
> media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> @@ -492,7 +492,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> * hooked up to an SFC (Scaler & Format Converter) unit.
> * In TGL each VDBOX has access to an SFC.
> */
> - if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
> + if (GRAPHICS_VER(i915) >= 12 || logical_vdbox++ % 2 == 0)
> gt->info.vdbox_sfc_access |= BIT(i);
> }
> drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
> @@ -729,7 +729,7 @@ static int engine_setup_common(struct intel_engine_cs *engine)
> intel_engine_init_whitelist(engine);
> intel_engine_init_ctx_wa(engine);
>
> - if (INTEL_GEN(engine->i915) >= 12)
> + if (GRAPHICS_VER(engine->i915) >= 12)
> engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
>
> return 0;
> @@ -997,9 +997,9 @@ u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
>
> u64 acthd;
>
> - if (INTEL_GEN(i915) >= 8)
> + if (GRAPHICS_VER(i915) >= 8)
> acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
> - else if (INTEL_GEN(i915) >= 4)
> + else if (GRAPHICS_VER(i915) >= 4)
> acthd = ENGINE_READ(engine, RING_ACTHD);
> else
> acthd = ENGINE_READ(engine, ACTHD);
> @@ -1011,7 +1011,7 @@ u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
> {
> u64 bbaddr;
>
> - if (INTEL_GEN(engine->i915) >= 8)
> + if (GRAPHICS_VER(engine->i915) >= 8)
> bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
> else
> bbaddr = ENGINE_READ(engine, RING_BBADDR);
> @@ -1058,7 +1058,7 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
> {
> int err = 0;
>
> - if (INTEL_GEN(engine->i915) < 3)
> + if (GRAPHICS_VER(engine->i915) < 3)
> return -ENODEV;
>
> ENGINE_TRACE(engine, "\n");
> @@ -1108,7 +1108,7 @@ read_subslice_reg(const struct intel_engine_cs *engine,
> u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
> enum forcewake_domains fw_domains;
>
> - if (INTEL_GEN(i915) >= 11) {
> + if (GRAPHICS_VER(i915) >= 11) {
> mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
> mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
> } else {
> @@ -1157,7 +1157,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
>
> memset(instdone, 0, sizeof(*instdone));
>
> - switch (INTEL_GEN(i915)) {
> + switch (GRAPHICS_VER(i915)) {
> default:
> instdone->instdone =
> intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
> @@ -1167,7 +1167,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
>
> instdone->slice_common =
> intel_uncore_read(uncore, GEN7_SC_INSTDONE);
> - if (INTEL_GEN(i915) >= 12) {
> + if (GRAPHICS_VER(i915) >= 12) {
> instdone->slice_common_extra[0] =
> intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
> instdone->slice_common_extra[1] =
> @@ -1230,7 +1230,7 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
> idle = false;
>
> /* No bit for gen2, so assume the CS parser is idle */
> - if (INTEL_GEN(engine->i915) > 2 &&
> + if (GRAPHICS_VER(engine->i915) > 2 &&
> !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
> idle = false;
>
> @@ -1327,7 +1327,7 @@ void intel_engines_reset_default_submission(struct intel_gt *gt)
>
> bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
> {
> - switch (INTEL_GEN(engine->i915)) {
> + switch (GRAPHICS_VER(engine->i915)) {
> case 2:
> return false; /* uses physical not virtual addresses */
> case 3:
> @@ -1432,7 +1432,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
> struct intel_engine_execlists * const execlists = &engine->execlists;
> u64 addr;
>
> - if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
> + if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7))
> drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
> if (HAS_EXECLISTS(dev_priv)) {
> drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
> @@ -1449,13 +1449,13 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
> drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
> ENGINE_READ(engine, RING_CTL),
> ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
> - if (INTEL_GEN(engine->i915) > 2) {
> + if (GRAPHICS_VER(engine->i915) > 2) {
> drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
> ENGINE_READ(engine, RING_MI_MODE),
> ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
> }
>
> - if (INTEL_GEN(dev_priv) >= 6) {
> + if (GRAPHICS_VER(dev_priv) >= 6) {
> drm_printf(m, "\tRING_IMR: 0x%08x\n",
> ENGINE_READ(engine, RING_IMR));
> drm_printf(m, "\tRING_ESR: 0x%08x\n",
> @@ -1472,15 +1472,15 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
> addr = intel_engine_get_last_batch_head(engine);
> drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
> upper_32_bits(addr), lower_32_bits(addr));
> - if (INTEL_GEN(dev_priv) >= 8)
> + if (GRAPHICS_VER(dev_priv) >= 8)
> addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
> - else if (INTEL_GEN(dev_priv) >= 4)
> + else if (GRAPHICS_VER(dev_priv) >= 4)
> addr = ENGINE_READ(engine, RING_DMA_FADD);
> else
> addr = ENGINE_READ(engine, DMA_FADD_I8XX);
> drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
> upper_32_bits(addr), lower_32_bits(addr));
> - if (INTEL_GEN(dev_priv) >= 4) {
> + if (GRAPHICS_VER(dev_priv) >= 4) {
> drm_printf(m, "\tIPEIR: 0x%08x\n",
> ENGINE_READ(engine, RING_IPEIR));
> drm_printf(m, "\tIPEHR: 0x%08x\n",
> @@ -1559,7 +1559,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
> }
> rcu_read_unlock();
> execlists_active_unlock_bh(execlists);
> - } else if (INTEL_GEN(dev_priv) > 6) {
> + } else if (GRAPHICS_VER(dev_priv) > 6) {
> drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
> ENGINE_READ(engine, RING_PP_DIR_BASE));
> drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 8db200422950..fc77592d88a9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -1847,7 +1847,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
> ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n",
> head, upper_32_bits(csb), lower_32_bits(csb));
>
> - if (INTEL_GEN(engine->i915) >= 12)
> + if (GRAPHICS_VER(engine->i915) >= 12)
> promote = gen12_csb_parse(csb);
> else
> promote = gen8_csb_parse(csb);
> @@ -2772,7 +2772,7 @@ static void enable_execlists(struct intel_engine_cs *engine)
>
> intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
>
> - if (INTEL_GEN(engine->i915) >= 11)
> + if (GRAPHICS_VER(engine->i915) >= 11)
> mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
> else
> mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
> @@ -3103,7 +3103,7 @@ static void execlists_park(struct intel_engine_cs *engine)
>
> static bool can_preempt(struct intel_engine_cs *engine)
> {
> - if (INTEL_GEN(engine->i915) > 8)
> + if (GRAPHICS_VER(engine->i915) > 8)
> return true;
>
> /* GPGPU on bdw requires extra w/a; not implemented */
> @@ -3156,13 +3156,13 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> engine->emit_flush = gen8_emit_flush_xcs;
> engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
> engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
> - if (INTEL_GEN(engine->i915) >= 12) {
> + if (GRAPHICS_VER(engine->i915) >= 12) {
> engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;
> engine->emit_flush = gen12_emit_flush_xcs;
> }
> engine->set_default_submission = execlists_set_default_submission;
>
> - if (INTEL_GEN(engine->i915) < 11) {
> + if (GRAPHICS_VER(engine->i915) < 11) {
> engine->irq_enable = gen8_logical_ring_enable_irq;
> engine->irq_disable = gen8_logical_ring_disable_irq;
> } else {
> @@ -3195,7 +3195,7 @@ static void logical_ring_default_irqs(struct intel_engine_cs *engine)
> {
> unsigned int shift = 0;
>
> - if (INTEL_GEN(engine->i915) < 11) {
> + if (GRAPHICS_VER(engine->i915) < 11) {
> const u8 irq_shifts[] = {
> [RCS0] = GEN8_RCS_IRQ_SHIFT,
> [BCS0] = GEN8_BCS_IRQ_SHIFT,
> @@ -3215,7 +3215,7 @@ static void logical_ring_default_irqs(struct intel_engine_cs *engine)
>
> static void rcs_submission_override(struct intel_engine_cs *engine)
> {
> - switch (INTEL_GEN(engine->i915)) {
> + switch (GRAPHICS_VER(engine->i915)) {
> case 12:
> engine->emit_flush = gen12_emit_flush_rcs;
> engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
> @@ -3266,13 +3266,13 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
> execlists->csb_write =
> &engine->status_page.addr[intel_hws_csb_write_index(i915)];
>
> - if (INTEL_GEN(i915) < 11)
> + if (GRAPHICS_VER(i915) < 11)
> execlists->csb_size = GEN8_CSB_ENTRIES;
> else
> execlists->csb_size = GEN11_CSB_ENTRIES;
>
> engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);
> - if (INTEL_GEN(engine->i915) >= 11) {
> + if (GRAPHICS_VER(engine->i915) >= 11) {
> execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
> execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 35069ca5d7de..19bd8856ce84 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -107,10 +107,10 @@ static bool needs_idle_maps(struct drm_i915_private *i915)
> if (!intel_vtd_active())
> return false;
>
> - if (IS_GEN(i915, 5) && IS_MOBILE(i915))
> + if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
> return true;
>
> - if (IS_GEN(i915, 12))
> + if (GRAPHICS_VER(i915) == 12)
> return true; /* XXX DMAR fault reason 7 */
>
> return false;
> @@ -176,7 +176,7 @@ static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
>
> gen8_ggtt_invalidate(ggtt);
>
> - if (INTEL_GEN(i915) >= 12)
> + if (GRAPHICS_VER(i915) >= 12)
> intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
> GEN12_GUC_TLB_INV_CR_INVALIDATE);
> else
> @@ -820,7 +820,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
> * resort to an uncached mapping. The WC issue is easily caught by the
> * readback check when writing GTT PTE entries.
> */
> - if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
> + if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 10)
> ggtt->gsm = ioremap(phys_addr, size);
> else
> ggtt->gsm = ioremap_wc(phys_addr, size);
> @@ -1065,7 +1065,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
> ggtt->vm.pte_encode = hsw_pte_encode;
> else if (IS_VALLEYVIEW(i915))
> ggtt->vm.pte_encode = byt_pte_encode;
> - else if (INTEL_GEN(i915) >= 7)
> + else if (GRAPHICS_VER(i915) >= 7)
> ggtt->vm.pte_encode = ivb_pte_encode;
> else
> ggtt->vm.pte_encode = snb_pte_encode;
> @@ -1137,9 +1137,9 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
> ggtt->vm.dma = i915->drm.dev;
> dma_resv_init(&ggtt->vm.resv);
>
> - if (INTEL_GEN(i915) <= 5)
> + if (GRAPHICS_VER(i915) <= 5)
> ret = i915_gmch_probe(ggtt);
> - else if (INTEL_GEN(i915) < 8)
> + else if (GRAPHICS_VER(i915) < 8)
> ret = gen6_gmch_probe(ggtt);
> else
> ret = gen8_gmch_probe(ggtt);
> @@ -1196,7 +1196,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
>
> int i915_ggtt_enable_hw(struct drm_i915_private *i915)
> {
> - if (INTEL_GEN(i915) < 6 && !intel_enable_gtt())
> + if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
> return -EIO;
>
> return 0;
> @@ -1261,7 +1261,7 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt)
> if (flush)
> wbinvd_on_all_cpus();
>
> - if (INTEL_GEN(ggtt->vm.i915) >= 8)
> + if (GRAPHICS_VER(ggtt->vm.i915) >= 8)
> setup_private_pat(ggtt->vm.gt->uncore);
>
> intel_ggtt_restore_fences(ggtt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> index 7bf84cd21543..cac7f3f44642 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> @@ -56,7 +56,7 @@ static void i965_write_fence_reg(struct i915_fence_reg *fence)
> int fence_pitch_shift;
> u64 val;
>
> - if (INTEL_GEN(fence_to_i915(fence)) >= 6) {
> + if (GRAPHICS_VER(fence_to_i915(fence)) >= 6) {
> fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
> fence_reg_hi = FENCE_REG_GEN6_HI(fence->id);
> fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
> @@ -173,9 +173,9 @@ static void fence_write(struct i915_fence_reg *fence)
> * and explicitly managed for internal users.
> */
>
> - if (IS_GEN(i915, 2))
> + if (GRAPHICS_VER(i915) == 2)
> i830_write_fence_reg(fence);
> - else if (IS_GEN(i915, 3))
> + else if (GRAPHICS_VER(i915) == 3)
> i915_write_fence_reg(fence);
> else
> i965_write_fence_reg(fence);
> @@ -188,7 +188,7 @@ static void fence_write(struct i915_fence_reg *fence)
>
> static bool gpu_uses_fence_registers(struct i915_fence_reg *fence)
> {
> - return INTEL_GEN(fence_to_i915(fence)) < 4;
> + return GRAPHICS_VER(fence_to_i915(fence)) < 4;
> }
>
> static int fence_update(struct i915_fence_reg *fence,
> @@ -569,7 +569,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>
> - if (INTEL_GEN(i915) >= 8 || IS_VALLEYVIEW(i915)) {
> + if (GRAPHICS_VER(i915) >= 8 || IS_VALLEYVIEW(i915)) {
> /*
> * On BDW+, swizzling is not used. We leave the CPU memory
> * controller in charge of optimizing memory accesses without
> @@ -579,7 +579,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> */
> swizzle_x = I915_BIT_6_SWIZZLE_NONE;
> swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> - } else if (INTEL_GEN(i915) >= 6) {
> + } else if (GRAPHICS_VER(i915) >= 6) {
> if (i915->preserve_bios_swizzle) {
> if (intel_uncore_read(uncore, DISP_ARB_CTL) &
> DISP_TILE_SURFACE_SWIZZLING) {
> @@ -611,14 +611,14 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> }
> }
> - } else if (IS_GEN(i915, 5)) {
> + } else if (GRAPHICS_VER(i915) == 5) {
> /*
> * On Ironlake whatever DRAM config, GPU always do
> * same swizzling setup.
> */
> swizzle_x = I915_BIT_6_SWIZZLE_9_10;
> swizzle_y = I915_BIT_6_SWIZZLE_9;
> - } else if (IS_GEN(i915, 2)) {
> + } else if (GRAPHICS_VER(i915) == 2) {
> /*
> * As far as we know, the 865 doesn't have these bit 6
> * swizzling issues.
> @@ -697,7 +697,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> }
>
> /* check for L-shaped memory aka modified enhanced addressing */
> - if (IS_GEN(i915, 4) &&
> + if (GRAPHICS_VER(i915) == 4 &&
> !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
> swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> @@ -844,10 +844,10 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
>
> if (!i915_ggtt_has_aperture(ggtt))
> num_fences = 0;
> - else if (INTEL_GEN(i915) >= 7 &&
> + else if (GRAPHICS_VER(i915) >= 7 &&
> !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
> num_fences = 32;
> - else if (INTEL_GEN(i915) >= 4 ||
> + else if (GRAPHICS_VER(i915) >= 4 ||
> IS_I945G(i915) || IS_I945GM(i915) ||
> IS_G33(i915) || IS_PINEVIEW(i915))
> num_fences = 16;
> @@ -895,29 +895,29 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
> struct drm_i915_private *i915 = gt->i915;
> struct intel_uncore *uncore = gt->uncore;
>
> - if (INTEL_GEN(i915) < 5 ||
> + if (GRAPHICS_VER(i915) < 5 ||
> i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
> return;
>
> intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
>
> - if (IS_GEN(i915, 5))
> + if (GRAPHICS_VER(i915) == 5)
> return;
>
> intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL);
>
> - if (IS_GEN(i915, 6))
> + if (GRAPHICS_VER(i915) == 6)
> intel_uncore_write(uncore,
> ARB_MODE,
> _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
> - else if (IS_GEN(i915, 7))
> + else if (GRAPHICS_VER(i915) == 7)
> intel_uncore_write(uncore,
> ARB_MODE,
> _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
> - else if (IS_GEN(i915, 8))
> + else if (GRAPHICS_VER(i915) == 8)
> intel_uncore_write(uncore,
> GAMTARBMODE,
> _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
> else
> - MISSING_CASE(INTEL_GEN(i915));
> + MISSING_CASE(GRAPHICS_VER(i915));
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 8d77dcbad059..7f24301cef18 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -115,10 +115,10 @@ static void init_unused_rings(struct intel_gt *gt)
> init_unused_ring(gt, SRB1_BASE);
> init_unused_ring(gt, SRB2_BASE);
> init_unused_ring(gt, SRB3_BASE);
> - } else if (IS_GEN(i915, 2)) {
> + } else if (GRAPHICS_VER(i915) == 2) {
> init_unused_ring(gt, SRB0_BASE);
> init_unused_ring(gt, SRB1_BASE);
> - } else if (IS_GEN(i915, 3)) {
> + } else if (GRAPHICS_VER(i915) == 3) {
> init_unused_ring(gt, PRB1_BASE);
> init_unused_ring(gt, PRB2_BASE);
> }
> @@ -135,7 +135,7 @@ int intel_gt_init_hw(struct intel_gt *gt)
> /* Double layer security blanket, see i915_gem_init() */
> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>
> - if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
> + if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
> intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
>
> if (IS_HASWELL(i915))
> @@ -208,10 +208,10 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
> struct intel_uncore *uncore = gt->uncore;
> u32 eir;
>
> - if (!IS_GEN(i915, 2))
> + if (GRAPHICS_VER(i915) != 2)
> clear_register(uncore, PGTBL_ER);
>
> - if (INTEL_GEN(i915) < 4)
> + if (GRAPHICS_VER(i915) < 4)
> clear_register(uncore, IPEIR(RENDER_RING_BASE));
> else
> clear_register(uncore, IPEIR_I965);
> @@ -229,13 +229,13 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
> I915_MASTER_ERROR_INTERRUPT);
> }
>
> - if (INTEL_GEN(i915) >= 12) {
> + if (GRAPHICS_VER(i915) >= 12) {
> rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
> intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
> - } else if (INTEL_GEN(i915) >= 8) {
> + } else if (GRAPHICS_VER(i915) >= 8) {
> rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
> intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
> - } else if (INTEL_GEN(i915) >= 6) {
> + } else if (GRAPHICS_VER(i915) >= 6) {
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
>
> @@ -273,7 +273,7 @@ static void gen8_check_faults(struct intel_gt *gt)
> i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
> u32 fault;
>
> - if (INTEL_GEN(gt->i915) >= 12) {
> + if (GRAPHICS_VER(gt->i915) >= 12) {
> fault_reg = GEN12_RING_FAULT_REG;
> fault_data0_reg = GEN12_FAULT_TLB_DATA0;
> fault_data1_reg = GEN12_FAULT_TLB_DATA1;
> @@ -313,9 +313,9 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
> struct drm_i915_private *i915 = gt->i915;
>
> /* From GEN8 onwards we only have one 'All Engine Fault Register' */
> - if (INTEL_GEN(i915) >= 8)
> + if (GRAPHICS_VER(i915) >= 8)
> gen8_check_faults(gt);
> - else if (INTEL_GEN(i915) >= 6)
> + else if (GRAPHICS_VER(i915) >= 6)
> gen6_check_faults(gt);
> else
> return;
> @@ -367,7 +367,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
> void intel_gt_chipset_flush(struct intel_gt *gt)
> {
> wmb();
> - if (INTEL_GEN(gt->i915) < 6)
> + if (GRAPHICS_VER(gt->i915) < 6)
> intel_gtt_chipset_flush();
> }
>
> @@ -591,7 +591,8 @@ int intel_gt_init(struct intel_gt *gt)
> */
> intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
>
> - err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K);
> + err = intel_gt_init_scratch(gt,
> + GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
> if (err)
> goto out_fw;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> index 582fcaee11aa..9f0e729d2d15 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> @@ -76,7 +76,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> u32 f19_2_mhz = 19200000;
> u32 f24_mhz = 24000000;
>
> - if (INTEL_GEN(uncore->i915) <= 4) {
> + if (GRAPHICS_VER(uncore->i915) <= 4) {
> /*
> * PRMs say:
> *
> @@ -85,7 +85,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> * (“CLKCFG”) MCHBAR register)
> */
> return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
> - } else if (INTEL_GEN(uncore->i915) <= 8) {
> + } else if (GRAPHICS_VER(uncore->i915) <= 8) {
> /*
> * PRMs say:
> *
> @@ -94,7 +94,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> * rolling over every 1.5 hours).
> */
> return f12_5_mhz;
> - } else if (INTEL_GEN(uncore->i915) <= 9) {
> + } else if (GRAPHICS_VER(uncore->i915) <= 9) {
> u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> u32 freq = 0;
>
> @@ -113,7 +113,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> }
>
> return freq;
> - } else if (INTEL_GEN(uncore->i915) <= 12) {
> + } else if (GRAPHICS_VER(uncore->i915) <= 12) {
> u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> u32 freq = 0;
>
> @@ -128,7 +128,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> } else {
> u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
>
> - if (INTEL_GEN(uncore->i915) <= 10)
> + if (GRAPHICS_VER(uncore->i915) <= 10)
> freq = gen10_get_crystal_clock_freq(uncore, c0);
> else
> freq = gen11_get_crystal_clock_freq(uncore, c0);
> @@ -211,7 +211,7 @@ u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns)
> * frozen machine.
> */
> val = div_u64_roundup(intel_gt_ns_to_clock_interval(gt, ns), 16);
> - if (IS_GEN(gt->i915, 6))
> + if (GRAPHICS_VER(gt->i915) == 6)
> val = div_u64_roundup(val, 25) * 25;
>
> return val;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index d29126c458ba..1ec63cceabf6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -395,7 +395,7 @@ void gen5_gt_irq_reset(struct intel_gt *gt)
> struct intel_uncore *uncore = gt->uncore;
>
> GEN3_IRQ_RESET(uncore, GT);
> - if (INTEL_GEN(gt->i915) >= 6)
> + if (GRAPHICS_VER(gt->i915) >= 6)
> GEN3_IRQ_RESET(uncore, GEN6_PM);
> }
>
> @@ -413,14 +413,14 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt)
> }
>
> gt_irqs |= GT_RENDER_USER_INTERRUPT;
> - if (IS_GEN(gt->i915, 5))
> + if (GRAPHICS_VER(gt->i915) == 5)
> gt_irqs |= ILK_BSD_USER_INTERRUPT;
> else
> gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
>
> GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs);
>
> - if (INTEL_GEN(gt->i915) >= 6) {
> + if (GRAPHICS_VER(gt->i915) >= 6) {
> /*
> * RPS interrupts will get enabled/disabled on demand when RPS
> * itself is enabled/disabled.
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
> index 811a11ed181c..fe51f894b073 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
> @@ -16,10 +16,10 @@ static void write_pm_imr(struct intel_gt *gt)
> u32 mask = gt->pm_imr;
> i915_reg_t reg;
>
> - if (INTEL_GEN(i915) >= 11) {
> + if (GRAPHICS_VER(i915) >= 11) {
> reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
> mask <<= 16; /* pm is in upper half */
> - } else if (INTEL_GEN(i915) >= 8) {
> + } else if (GRAPHICS_VER(i915) >= 8) {
> reg = GEN8_GT_IMR(2);
> } else {
> reg = GEN6_PMIMR;
> @@ -61,7 +61,7 @@ void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask)
> void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)
> {
> struct intel_uncore *uncore = gt->uncore;
> - i915_reg_t reg = INTEL_GEN(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
> + i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
>
> lockdep_assert_held(>->irq_lock);
>
> @@ -77,10 +77,10 @@ static void write_pm_ier(struct intel_gt *gt)
> u32 mask = gt->pm_ier;
> i915_reg_t reg;
>
> - if (INTEL_GEN(i915) >= 11) {
> + if (GRAPHICS_VER(i915) >= 11) {
> reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
> mask <<= 16; /* pm is in upper half */
> - } else if (INTEL_GEN(i915) >= 8) {
> + } else if (GRAPHICS_VER(i915) >= 8) {
> reg = GEN8_GT_IER(2);
> } else {
> reg = GEN6_PMIER;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 9b98f9d9faa3..b9c9993573ec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -327,7 +327,7 @@ void gtt_write_workarounds(struct intel_gt *gt)
> intel_uncore_write(uncore,
> GEN8_L3_LRA_1_GPGPU,
> GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> - else if (INTEL_GEN(i915) >= 9 && INTEL_GEN(i915) <= 11)
> + else if (GRAPHICS_VER(i915) >= 9 && GRAPHICS_VER(i915) <= 11)
> intel_uncore_write(uncore,
> GEN8_L3_LRA_1_GPGPU,
> GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> @@ -344,13 +344,13 @@ void gtt_write_workarounds(struct intel_gt *gt)
> * driver.
> */
> if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
> - INTEL_GEN(i915) <= 10)
> + GRAPHICS_VER(i915) <= 10)
> intel_uncore_rmw(uncore,
> GEN8_GAMW_ECO_DEV_RW_IA,
> 0,
> GAMW_ECO_ENABLE_64K_IPS_FIELD);
>
> - if (IS_GEN_RANGE(i915, 8, 11)) {
> + if (IS_GRAPHICS_VER(i915, 8, 11)) {
> bool can_use_gtt_cache = true;
>
> /*
> @@ -432,7 +432,7 @@ static void bdw_setup_private_ppat(struct intel_uncore *uncore)
> GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
>
> /* for scanout with eLLC */
> - if (INTEL_GEN(i915) >= 9)
> + if (GRAPHICS_VER(i915) >= 9)
> pat |= GEN8_PPAT(2, GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE);
> else
> pat |= GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
> @@ -481,11 +481,11 @@ void setup_private_pat(struct intel_uncore *uncore)
> {
> struct drm_i915_private *i915 = uncore->i915;
>
> - GEM_BUG_ON(INTEL_GEN(i915) < 8);
> + GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
>
> - if (INTEL_GEN(i915) >= 12)
> + if (GRAPHICS_VER(i915) >= 12)
> tgl_setup_private_ppat(uncore);
> - else if (INTEL_GEN(i915) >= 10)
> + else if (GRAPHICS_VER(i915) >= 10)
> cnl_setup_private_ppat(uncore);
> else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))
> chv_setup_private_ppat(uncore);
> diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
> index 075d741644ae..eb1a15deed22 100644
> --- a/drivers/gpu/drm/i915/gt/intel_llc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_llc.c
> @@ -64,7 +64,7 @@ static bool get_ia_constants(struct intel_llc *llc,
>
> consts->min_gpu_freq = rps->min_freq;
> consts->max_gpu_freq = rps->max_freq;
> - if (INTEL_GEN(i915) >= 9) {
> + if (GRAPHICS_VER(i915) >= 9) {
> /* Convert GT frequency to 50 HZ units */
> consts->min_gpu_freq /= GEN9_FREQ_SCALER;
> consts->max_gpu_freq /= GEN9_FREQ_SCALER;
> @@ -83,13 +83,13 @@ static void calc_ia_freq(struct intel_llc *llc,
> const int diff = consts->max_gpu_freq - gpu_freq;
> unsigned int ia_freq = 0, ring_freq = 0;
>
> - if (INTEL_GEN(i915) >= 9) {
> + if (GRAPHICS_VER(i915) >= 9) {
> /*
> * ring_freq = 2 * GT. ring_freq is in 100MHz units
> * No floor required for ring frequency on SKL.
> */
> ring_freq = gpu_freq;
> - } else if (INTEL_GEN(i915) >= 8) {
> + } else if (GRAPHICS_VER(i915) >= 8) {
> /* max(2 * GT, DDR). NB: GT is 50MHz units */
> ring_freq = max(consts->min_ring_freq, gpu_freq);
> } else if (IS_HASWELL(i915)) {
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index aafe2a4df496..a27bac0a4bfb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -47,7 +47,7 @@ static void set_offsets(u32 *regs,
> *regs = MI_LOAD_REGISTER_IMM(count);
> if (flags & POSTED)
> *regs |= MI_LRI_FORCE_POSTED;
> - if (INTEL_GEN(engine->i915) >= 11)
> + if (GRAPHICS_VER(engine->i915) >= 11)
> *regs |= MI_LRI_LRM_CS_MMIO;
> regs++;
>
> @@ -70,7 +70,7 @@ static void set_offsets(u32 *regs,
> if (close) {
> /* Close the batch; used mainly by live_lrc_layout() */
> *regs = MI_BATCH_BUFFER_END;
> - if (INTEL_GEN(engine->i915) >= 10)
> + if (GRAPHICS_VER(engine->i915) >= 10)
> *regs |= BIT(0);
> }
> }
> @@ -498,22 +498,22 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> * addressing to automatic fixup the register state between the
> * physical engines for virtual engine.
> */
> - GEM_BUG_ON(INTEL_GEN(engine->i915) >= 12 &&
> + GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
> !intel_engine_has_relative_mmio(engine));
>
> if (engine->class == RENDER_CLASS) {
> - if (INTEL_GEN(engine->i915) >= 12)
> + if (GRAPHICS_VER(engine->i915) >= 12)
> return gen12_rcs_offsets;
> - else if (INTEL_GEN(engine->i915) >= 11)
> + else if (GRAPHICS_VER(engine->i915) >= 11)
> return gen11_rcs_offsets;
> - else if (INTEL_GEN(engine->i915) >= 9)
> + else if (GRAPHICS_VER(engine->i915) >= 9)
> return gen9_rcs_offsets;
> else
> return gen8_rcs_offsets;
> } else {
> - if (INTEL_GEN(engine->i915) >= 12)
> + if (GRAPHICS_VER(engine->i915) >= 12)
> return gen12_xcs_offsets;
> - else if (INTEL_GEN(engine->i915) >= 9)
> + else if (GRAPHICS_VER(engine->i915) >= 9)
> return gen9_xcs_offsets;
> else
> return gen8_xcs_offsets;
> @@ -522,9 +522,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
>
> static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
> {
> - if (INTEL_GEN(engine->i915) >= 12)
> + if (GRAPHICS_VER(engine->i915) >= 12)
> return 0x60;
> - else if (INTEL_GEN(engine->i915) >= 9)
> + else if (GRAPHICS_VER(engine->i915) >= 9)
> return 0x54;
> else if (engine->class == RENDER_CLASS)
> return 0x58;
> @@ -534,9 +534,9 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
>
> static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
> {
> - if (INTEL_GEN(engine->i915) >= 12)
> + if (GRAPHICS_VER(engine->i915) >= 12)
> return 0x74;
> - else if (INTEL_GEN(engine->i915) >= 9)
> + else if (GRAPHICS_VER(engine->i915) >= 9)
> return 0x68;
> else if (engine->class == RENDER_CLASS)
> return 0xd8;
> @@ -546,9 +546,9 @@ static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
>
> static int lrc_ring_wa_bb_per_ctx(const struct intel_engine_cs *engine)
> {
> - if (INTEL_GEN(engine->i915) >= 12)
> + if (GRAPHICS_VER(engine->i915) >= 12)
> return 0x12;
> - else if (INTEL_GEN(engine->i915) >= 9 || engine->class == RENDER_CLASS)
> + else if (GRAPHICS_VER(engine->i915) >= 9 || engine->class == RENDER_CLASS)
> return 0x18;
> else
> return -1;
> @@ -581,9 +581,9 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
> if (engine->class != RENDER_CLASS)
> return -1;
>
> - if (INTEL_GEN(engine->i915) >= 12)
> + if (GRAPHICS_VER(engine->i915) >= 12)
> return 0xb6;
> - else if (INTEL_GEN(engine->i915) >= 11)
> + else if (GRAPHICS_VER(engine->i915) >= 11)
> return 0xaa;
> else
> return -1;
> @@ -592,9 +592,9 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
> static u32
> lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
> {
> - switch (INTEL_GEN(engine->i915)) {
> + switch (GRAPHICS_VER(engine->i915)) {
> default:
> - MISSING_CASE(INTEL_GEN(engine->i915));
> + MISSING_CASE(GRAPHICS_VER(engine->i915));
> fallthrough;
> case 12:
> return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> @@ -637,7 +637,7 @@ static void init_common_regs(u32 * const regs,
> ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
> if (inhibit)
> ctl |= CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT;
> - if (INTEL_GEN(engine->i915) < 11)
> + if (GRAPHICS_VER(engine->i915) < 11)
> ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
> CTX_CTRL_RS_CTX_ENABLE);
> regs[CTX_CONTEXT_CONTROL] = ctl;
> @@ -805,7 +805,7 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
> if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> context_size += I915_GTT_PAGE_SIZE; /* for redzone */
>
> - if (INTEL_GEN(engine->i915) == 12) {
> + if (GRAPHICS_VER(engine->i915) == 12) {
> ce->wa_bb_page = context_size / PAGE_SIZE;
> context_size += PAGE_SIZE;
> }
> @@ -1114,7 +1114,7 @@ static u32 lrc_descriptor(const struct intel_context *ce)
> desc <<= GEN8_CTX_ADDRESSING_MODE_SHIFT;
>
> desc |= GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
> - if (IS_GEN(ce->vm->i915, 8))
> + if (GRAPHICS_VER(ce->vm->i915) == 8)
> desc |= GEN8_CTX_L3LLC_COHERENT;
>
> return i915_ggtt_offset(ce->state) | desc;
> @@ -1469,7 +1469,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
> if (engine->class != RENDER_CLASS)
> return;
>
> - switch (INTEL_GEN(engine->i915)) {
> + switch (GRAPHICS_VER(engine->i915)) {
> case 12:
> case 11:
> return;
> @@ -1486,7 +1486,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
> wa_bb_fn[1] = NULL;
> break;
> default:
> - MISSING_CASE(INTEL_GEN(engine->i915));
> + MISSING_CASE(GRAPHICS_VER(engine->i915));
> return;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index b14138fd505c..17848807f111 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -344,11 +344,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> table->size = ARRAY_SIZE(dg1_mocs_table);
> table->table = dg1_mocs_table;
> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> - } else if (INTEL_GEN(i915) >= 12) {
> + } else if (GRAPHICS_VER(i915) >= 12) {
> table->size = ARRAY_SIZE(tgl_mocs_table);
> table->table = tgl_mocs_table;
> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> - } else if (IS_GEN(i915, 11)) {
> + } else if (GRAPHICS_VER(i915) == 11) {
> table->size = ARRAY_SIZE(icl_mocs_table);
> table->table = icl_mocs_table;
> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> @@ -361,7 +361,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> table->table = broxton_mocs_table;
> } else {
> - drm_WARN_ONCE(&i915->drm, INTEL_GEN(i915) >= 9,
> + drm_WARN_ONCE(&i915->drm, GRAPHICS_VER(i915) >= 9,
> "Platform that should have a MOCS table does not.\n");
> return 0;
> }
> @@ -370,7 +370,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> return 0;
>
> /* WaDisableSkipCaching:skl,bxt,kbl,glk */
> - if (IS_GEN(i915, 9)) {
> + if (GRAPHICS_VER(i915) == 9) {
> int i;
>
> for (i = 0; i < table->size; i++)
> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> index 4e3d80c2295c..3891c078906e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> @@ -146,9 +146,9 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
>
> gtt_write_workarounds(gt);
>
> - if (IS_GEN(i915, 6))
> + if (GRAPHICS_VER(i915) == 6)
> gen6_ppgtt_enable(gt);
> - else if (IS_GEN(i915, 7))
> + else if (GRAPHICS_VER(i915) == 7)
> gen7_ppgtt_enable(gt);
>
> return 0;
> @@ -157,7 +157,7 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
> static struct i915_ppgtt *
> __ppgtt_create(struct intel_gt *gt)
> {
> - if (INTEL_GEN(gt->i915) < 8)
> + if (GRAPHICS_VER(gt->i915) < 8)
> return gen6_ppgtt_create(gt);
> else
> return gen8_ppgtt_create(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 3b7e62debe7e..259d7eb4e165 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -109,7 +109,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
> GEN9_MEDIA_PG_ENABLE |
> GEN11_MEDIA_SAMPLER_PG_ENABLE;
>
> - if (INTEL_GEN(gt->i915) >= 12) {
> + if (GRAPHICS_VER(gt->i915) >= 12) {
> for (i = 0; i < I915_MAX_VCS; i++)
> if (HAS_ENGINE(gt, _VCS(i)))
> pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
> @@ -126,7 +126,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
> enum intel_engine_id id;
>
> /* 2b: Program RC6 thresholds.*/
> - if (INTEL_GEN(rc6_to_i915(rc6)) >= 10) {
> + if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 10) {
> set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
> } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
> @@ -249,9 +249,9 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
> rc6vids = 0;
> ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
> &rc6vids, NULL);
> - if (IS_GEN(i915, 6) && ret) {
> + if (GRAPHICS_VER(i915) == 6 && ret) {
> drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
> - } else if (IS_GEN(i915, 6) &&
> + } else if (GRAPHICS_VER(i915) == 6 &&
> (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
> drm_dbg(&i915->drm,
> "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
> @@ -515,7 +515,7 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
> struct intel_uncore *uncore = rc6_to_uncore(rc6);
>
> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> - if (INTEL_GEN(i915) >= 9)
> + if (GRAPHICS_VER(i915) >= 9)
> set(uncore, GEN9_PG_ENABLE, 0);
> set(uncore, GEN6_RC_CONTROL, 0);
> set(uncore, GEN6_RC_STATE, 0);
> @@ -575,13 +575,13 @@ void intel_rc6_enable(struct intel_rc6 *rc6)
> chv_rc6_enable(rc6);
> else if (IS_VALLEYVIEW(i915))
> vlv_rc6_enable(rc6);
> - else if (INTEL_GEN(i915) >= 11)
> + else if (GRAPHICS_VER(i915) >= 11)
> gen11_rc6_enable(rc6);
> - else if (INTEL_GEN(i915) >= 9)
> + else if (GRAPHICS_VER(i915) >= 9)
> gen9_rc6_enable(rc6);
> else if (IS_BROADWELL(i915))
> gen8_rc6_enable(rc6);
> - else if (INTEL_GEN(i915) >= 6)
> + else if (GRAPHICS_VER(i915) >= 6)
> gen6_rc6_enable(rc6);
>
> rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE;
> diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
> index b03e197b1d99..b575cd6e0b7a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
> @@ -15,7 +15,7 @@ render_state_get_rodata(const struct intel_engine_cs *engine)
> if (engine->class != RENDER_CLASS)
> return NULL;
>
> - switch (INTEL_GEN(engine->i915)) {
> + switch (GRAPHICS_VER(engine->i915)) {
> case 6:
> return &gen6_null_state;
> case 7:
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index d5094be6d90f..27315d7f8935 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -565,7 +565,7 @@ static int gen8_reset_engines(struct intel_gt *gt,
> */
> }
>
> - if (INTEL_GEN(gt->i915) >= 11)
> + if (GRAPHICS_VER(gt->i915) >= 11)
> ret = gen11_reset_engines(gt, engine_mask, retry);
> else
> ret = gen6_reset_engines(gt, engine_mask, retry);
> @@ -594,17 +594,17 @@ static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
>
> if (is_mock_gt(gt))
> return mock_reset;
> - else if (INTEL_GEN(i915) >= 8)
> + else if (GRAPHICS_VER(i915) >= 8)
> return gen8_reset_engines;
> - else if (INTEL_GEN(i915) >= 6)
> + else if (GRAPHICS_VER(i915) >= 6)
> return gen6_reset_engines;
> - else if (INTEL_GEN(i915) >= 5)
> + else if (GRAPHICS_VER(i915) >= 5)
> return ilk_do_reset;
> else if (IS_G4X(i915))
> return g4x_do_reset;
> else if (IS_G33(i915) || IS_PINEVIEW(i915))
> return g33_do_reset;
> - else if (INTEL_GEN(i915) >= 3)
> + else if (GRAPHICS_VER(i915) >= 3)
> return i915_do_reset;
> else
> return NULL;
> @@ -656,7 +656,7 @@ bool intel_has_reset_engine(const struct intel_gt *gt)
> int intel_reset_guc(struct intel_gt *gt)
> {
> u32 guc_domain =
> - INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
> + GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
> int ret;
>
> GEM_BUG_ON(!HAS_GT_UC(gt->i915));
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 2b6dffcc2262..0c423f096e2b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -29,7 +29,7 @@ static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
> * lost interrupts following a reset.
> */
> if (engine->class == RENDER_CLASS) {
> - if (INTEL_GEN(engine->i915) >= 6)
> + if (GRAPHICS_VER(engine->i915) >= 6)
> mask &= ~BIT(0);
> else
> mask &= ~I915_USER_INTERRUPT;
> @@ -43,7 +43,7 @@ static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
> u32 addr;
>
> addr = lower_32_bits(phys);
> - if (INTEL_GEN(engine->i915) >= 4)
> + if (GRAPHICS_VER(engine->i915) >= 4)
> addr |= (phys >> 28) & 0xf0;
>
> intel_uncore_write(engine->uncore, HWS_PGA, addr);
> @@ -71,7 +71,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
> * The ring status page addresses are no longer next to the rest of
> * the ring registers as of gen7.
> */
> - if (IS_GEN(engine->i915, 7)) {
> + if (GRAPHICS_VER(engine->i915) == 7) {
> switch (engine->id) {
> /*
> * No more rings exist on Gen7. Default case is only to shut up
> @@ -93,7 +93,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
> hwsp = VEBOX_HWS_PGA_GEN7;
> break;
> }
> - } else if (IS_GEN(engine->i915, 6)) {
> + } else if (GRAPHICS_VER(engine->i915) == 6) {
> hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
> } else {
> hwsp = RING_HWS_PGA(engine->mmio_base);
> @@ -105,7 +105,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
>
> static void flush_cs_tlb(struct intel_engine_cs *engine)
> {
> - if (!IS_GEN_RANGE(engine->i915, 6, 7))
> + if (!IS_GRAPHICS_VER(engine->i915, 6, 7))
> return;
>
> /* ring should be idle before issuing a sync flush*/
> @@ -153,7 +153,7 @@ static void set_pp_dir(struct intel_engine_cs *engine)
> ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
> ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm));
>
> - if (INTEL_GEN(engine->i915) >= 7) {
> + if (GRAPHICS_VER(engine->i915) >= 7) {
> ENGINE_WRITE_FW(engine,
> RING_MODE_GEN7,
> _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> @@ -229,7 +229,7 @@ static int xcs_resume(struct intel_engine_cs *engine)
> 5000, 0, NULL))
> goto err;
>
> - if (INTEL_GEN(engine->i915) > 2)
> + if (GRAPHICS_VER(engine->i915) > 2)
> ENGINE_WRITE_FW(engine,
> RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
>
> @@ -646,9 +646,9 @@ static int mi_set_context(struct i915_request *rq,
> u32 *cs;
>
> len = 4;
> - if (IS_GEN(i915, 7))
> + if (GRAPHICS_VER(i915) == 7)
> len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
> - else if (IS_GEN(i915, 5))
> + else if (GRAPHICS_VER(i915) == 5)
> len += 2;
> if (flags & MI_FORCE_RESTORE) {
> GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
> @@ -662,7 +662,7 @@ static int mi_set_context(struct i915_request *rq,
> return PTR_ERR(cs);
>
> /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
> - if (IS_GEN(i915, 7)) {
> + if (GRAPHICS_VER(i915) == 7) {
> *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> if (num_engines) {
> struct intel_engine_cs *signaller;
> @@ -678,7 +678,7 @@ static int mi_set_context(struct i915_request *rq,
> GEN6_PSMI_SLEEP_MSG_DISABLE);
> }
> }
> - } else if (IS_GEN(i915, 5)) {
> + } else if (GRAPHICS_VER(i915) == 5) {
> /*
> * This w/a is only listed for pre-production ilk a/b steppings,
> * but is also mentioned for programming the powerctx. To be
> @@ -716,7 +716,7 @@ static int mi_set_context(struct i915_request *rq,
> */
> *cs++ = MI_NOOP;
>
> - if (IS_GEN(i915, 7)) {
> + if (GRAPHICS_VER(i915) == 7) {
> if (num_engines) {
> struct intel_engine_cs *signaller;
> i915_reg_t last_reg = {}; /* keep gcc quiet */
> @@ -740,7 +740,7 @@ static int mi_set_context(struct i915_request *rq,
> *cs++ = MI_NOOP;
> }
> *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
> - } else if (IS_GEN(i915, 5)) {
> + } else if (GRAPHICS_VER(i915) == 5) {
> *cs++ = MI_SUSPEND_FLUSH;
> }
>
> @@ -1001,7 +1001,7 @@ static void ring_release(struct intel_engine_cs *engine)
> {
> struct drm_i915_private *dev_priv = engine->i915;
>
> - drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) > 2 &&
> + drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) > 2 &&
> (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
>
> intel_engine_cleanup_common(engine);
> @@ -1029,13 +1029,13 @@ static void setup_irq(struct intel_engine_cs *engine)
>
> intel_engine_set_irq_handler(engine, irq_handler);
>
> - if (INTEL_GEN(i915) >= 6) {
> + if (GRAPHICS_VER(i915) >= 6) {
> engine->irq_enable = gen6_irq_enable;
> engine->irq_disable = gen6_irq_disable;
> - } else if (INTEL_GEN(i915) >= 5) {
> + } else if (GRAPHICS_VER(i915) >= 5) {
> engine->irq_enable = gen5_irq_enable;
> engine->irq_disable = gen5_irq_disable;
> - } else if (INTEL_GEN(i915) >= 3) {
> + } else if (GRAPHICS_VER(i915) >= 3) {
> engine->irq_enable = gen3_irq_enable;
> engine->irq_disable = gen3_irq_disable;
> } else {
> @@ -1049,7 +1049,7 @@ static void setup_common(struct intel_engine_cs *engine)
> struct drm_i915_private *i915 = engine->i915;
>
> /* gen8+ are only supported with execlists */
> - GEM_BUG_ON(INTEL_GEN(i915) >= 8);
> + GEM_BUG_ON(GRAPHICS_VER(i915) >= 8);
>
> setup_irq(engine);
>
> @@ -1070,14 +1070,14 @@ static void setup_common(struct intel_engine_cs *engine)
> * engine->emit_init_breadcrumb().
> */
> engine->emit_fini_breadcrumb = gen3_emit_breadcrumb;
> - if (IS_GEN(i915, 5))
> + if (GRAPHICS_VER(i915) == 5)
> engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
>
> engine->set_default_submission = i9xx_set_default_submission;
>
> - if (INTEL_GEN(i915) >= 6)
> + if (GRAPHICS_VER(i915) >= 6)
> engine->emit_bb_start = gen6_emit_bb_start;
> - else if (INTEL_GEN(i915) >= 4)
> + else if (GRAPHICS_VER(i915) >= 4)
> engine->emit_bb_start = gen4_emit_bb_start;
> else if (IS_I830(i915) || IS_I845G(i915))
> engine->emit_bb_start = i830_emit_bb_start;
> @@ -1094,16 +1094,16 @@ static void setup_rcs(struct intel_engine_cs *engine)
>
> engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
>
> - if (INTEL_GEN(i915) >= 7) {
> + if (GRAPHICS_VER(i915) >= 7) {
> engine->emit_flush = gen7_emit_flush_rcs;
> engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs;
> - } else if (IS_GEN(i915, 6)) {
> + } else if (GRAPHICS_VER(i915) == 6) {
> engine->emit_flush = gen6_emit_flush_rcs;
> engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs;
> - } else if (IS_GEN(i915, 5)) {
> + } else if (GRAPHICS_VER(i915) == 5) {
> engine->emit_flush = gen4_emit_flush_rcs;
> } else {
> - if (INTEL_GEN(i915) < 4)
> + if (GRAPHICS_VER(i915) < 4)
> engine->emit_flush = gen2_emit_flush;
> else
> engine->emit_flush = gen4_emit_flush_rcs;
> @@ -1118,20 +1118,20 @@ static void setup_vcs(struct intel_engine_cs *engine)
> {
> struct drm_i915_private *i915 = engine->i915;
>
> - if (INTEL_GEN(i915) >= 6) {
> + if (GRAPHICS_VER(i915) >= 6) {
> /* gen6 bsd needs a special wa for tail updates */
> - if (IS_GEN(i915, 6))
> + if (GRAPHICS_VER(i915) == 6)
> engine->set_default_submission = gen6_bsd_set_default_submission;
> engine->emit_flush = gen6_emit_flush_vcs;
> engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
>
> - if (IS_GEN(i915, 6))
> + if (GRAPHICS_VER(i915) == 6)
> engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
> else
> engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
> } else {
> engine->emit_flush = gen4_emit_flush_vcs;
> - if (IS_GEN(i915, 5))
> + if (GRAPHICS_VER(i915) == 5)
> engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
> else
> engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
> @@ -1145,7 +1145,7 @@ static void setup_bcs(struct intel_engine_cs *engine)
> engine->emit_flush = gen6_emit_flush_xcs;
> engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
>
> - if (IS_GEN(i915, 6))
> + if (GRAPHICS_VER(i915) == 6)
> engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
> else
> engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
> @@ -1155,7 +1155,7 @@ static void setup_vecs(struct intel_engine_cs *engine)
> {
> struct drm_i915_private *i915 = engine->i915;
>
> - GEM_BUG_ON(INTEL_GEN(i915) < 7);
> + GEM_BUG_ON(GRAPHICS_VER(i915) < 7);
>
> engine->emit_flush = gen6_emit_flush_xcs;
> engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
> @@ -1203,7 +1203,7 @@ static struct i915_vma *gen7_ctx_vma(struct intel_engine_cs *engine)
> struct i915_vma *vma;
> int size, err;
>
> - if (!IS_GEN(engine->i915, 7) || engine->class != RENDER_CLASS)
> + if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS)
> return 0;
>
> err = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */);
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 97cab1b99871..06e9a8ed4e03 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -196,7 +196,7 @@ static void rps_reset_interrupts(struct intel_rps *rps)
> struct intel_gt *gt = rps_to_gt(rps);
>
> spin_lock_irq(>->irq_lock);
> - if (INTEL_GEN(gt->i915) >= 11)
> + if (GRAPHICS_VER(gt->i915) >= 11)
> gen11_rps_reset_interrupts(rps);
> else
> gen6_rps_reset_interrupts(rps);
> @@ -630,7 +630,7 @@ static u32 rps_limits(struct intel_rps *rps, u8 val)
> * frequency, if the down threshold expires in that window we will not
> * receive a down interrupt.
> */
> - if (INTEL_GEN(rps_to_i915(rps)) >= 9) {
> + if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) {
> limits = rps->max_freq_softlimit << 23;
> if (val <= rps->min_freq_softlimit)
> limits |= rps->min_freq_softlimit << 14;
> @@ -697,7 +697,7 @@ static void rps_set_power(struct intel_rps *rps, int new_power)
> intel_gt_ns_to_pm_interval(gt, ei_down * threshold_down * 10));
>
> set(uncore, GEN6_RP_CONTROL,
> - (INTEL_GEN(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
> + (GRAPHICS_VER(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
> GEN6_RP_MEDIA_HW_NORMAL_MODE |
> GEN6_RP_MEDIA_IS_GFX |
> GEN6_RP_ENABLE |
> @@ -771,7 +771,7 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val)
> struct drm_i915_private *i915 = rps_to_i915(rps);
> u32 swreq;
>
> - if (INTEL_GEN(i915) >= 9)
> + if (GRAPHICS_VER(i915) >= 9)
> swreq = GEN9_FREQUENCY(val);
> else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> swreq = HSW_FREQUENCY(val);
> @@ -812,14 +812,14 @@ static int rps_set(struct intel_rps *rps, u8 val, bool update)
>
> if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> err = vlv_rps_set(rps, val);
> - else if (INTEL_GEN(i915) >= 6)
> + else if (GRAPHICS_VER(i915) >= 6)
> err = gen6_rps_set(rps, val);
> else
> err = gen5_rps_set(rps, val);
> if (err)
> return err;
>
> - if (update && INTEL_GEN(i915) >= 6)
> + if (update && GRAPHICS_VER(i915) >= 6)
> gen6_rps_set_thresholds(rps, val);
> rps->last_freq = val;
>
> @@ -853,7 +853,7 @@ void intel_rps_unpark(struct intel_rps *rps)
> if (intel_rps_uses_timer(rps))
> rps_start_timer(rps);
>
> - if (IS_GEN(rps_to_i915(rps), 5))
> + if (GRAPHICS_VER(rps_to_i915(rps)) == 5)
> gen5_rps_update(rps);
> }
>
> @@ -999,7 +999,7 @@ static void gen6_rps_init(struct intel_rps *rps)
>
> rps->efficient_freq = rps->rp1_freq;
> if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
> - IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
> + IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
> u32 ddcc_status = 0;
>
> if (sandybridge_pcode_read(i915,
> @@ -1012,7 +1012,7 @@ static void gen6_rps_init(struct intel_rps *rps)
> rps->max_freq);
> }
>
> - if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
> + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
> /* Store the frequency values in 16.66 MHZ units, which is
> * the natural hardware unit for SKL
> */
> @@ -1048,7 +1048,7 @@ static bool gen9_rps_enable(struct intel_rps *rps)
> struct intel_uncore *uncore = gt->uncore;
>
> /* Program defaults and thresholds for RPS */
> - if (IS_GEN(gt->i915, 9))
> + if (GRAPHICS_VER(gt->i915) == 9)
> intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ,
> GEN9_FREQUENCY(rps->rp1_freq));
>
> @@ -1365,16 +1365,16 @@ void intel_rps_enable(struct intel_rps *rps)
> enabled = chv_rps_enable(rps);
> else if (IS_VALLEYVIEW(i915))
> enabled = vlv_rps_enable(rps);
> - else if (INTEL_GEN(i915) >= 9)
> + else if (GRAPHICS_VER(i915) >= 9)
> enabled = gen9_rps_enable(rps);
> - else if (INTEL_GEN(i915) >= 8)
> + else if (GRAPHICS_VER(i915) >= 8)
> enabled = gen8_rps_enable(rps);
> - else if (INTEL_GEN(i915) >= 6)
> + else if (GRAPHICS_VER(i915) >= 6)
> enabled = gen6_rps_enable(rps);
> else if (IS_IRONLAKE_M(i915))
> enabled = gen5_rps_enable(rps);
> else
> - MISSING_CASE(INTEL_GEN(i915));
> + MISSING_CASE(GRAPHICS_VER(i915));
> intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> if (!enabled)
> return;
> @@ -1393,7 +1393,7 @@ void intel_rps_enable(struct intel_rps *rps)
>
> if (has_busy_stats(rps))
> intel_rps_set_timer(rps);
> - else if (INTEL_GEN(i915) >= 6)
> + else if (GRAPHICS_VER(i915) >= 6)
> intel_rps_set_interrupts(rps);
> else
> /* Ironlake currently uses intel_ips.ko */ {}
> @@ -1414,7 +1414,7 @@ void intel_rps_disable(struct intel_rps *rps)
> intel_rps_clear_interrupts(rps);
> intel_rps_clear_timer(rps);
>
> - if (INTEL_GEN(i915) >= 6)
> + if (GRAPHICS_VER(i915) >= 6)
> gen6_rps_disable(rps);
> else if (IS_IRONLAKE_M(i915))
> gen5_rps_disable(rps);
> @@ -1453,14 +1453,14 @@ int intel_gpu_freq(struct intel_rps *rps, int val)
> {
> struct drm_i915_private *i915 = rps_to_i915(rps);
>
> - if (INTEL_GEN(i915) >= 9)
> + if (GRAPHICS_VER(i915) >= 9)
> return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
> GEN9_FREQ_SCALER);
> else if (IS_CHERRYVIEW(i915))
> return chv_gpu_freq(rps, val);
> else if (IS_VALLEYVIEW(i915))
> return byt_gpu_freq(rps, val);
> - else if (INTEL_GEN(i915) >= 6)
> + else if (GRAPHICS_VER(i915) >= 6)
> return val * GT_FREQUENCY_MULTIPLIER;
> else
> return val;
> @@ -1470,14 +1470,14 @@ int intel_freq_opcode(struct intel_rps *rps, int val)
> {
> struct drm_i915_private *i915 = rps_to_i915(rps);
>
> - if (INTEL_GEN(i915) >= 9)
> + if (GRAPHICS_VER(i915) >= 9)
> return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
> GT_FREQUENCY_MULTIPLIER);
> else if (IS_CHERRYVIEW(i915))
> return chv_freq_opcode(rps, val);
> else if (IS_VALLEYVIEW(i915))
> return byt_freq_opcode(rps, val);
> - else if (INTEL_GEN(i915) >= 6)
> + else if (GRAPHICS_VER(i915) >= 6)
> return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
> else
> return val;
> @@ -1770,7 +1770,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
> spin_unlock(>->irq_lock);
> }
>
> - if (INTEL_GEN(gt->i915) >= 8)
> + if (GRAPHICS_VER(gt->i915) >= 8)
> return;
>
> if (pm_iir & PM_VEBOX_USER_INTERRUPT)
> @@ -1833,7 +1833,7 @@ void intel_rps_init(struct intel_rps *rps)
> chv_rps_init(rps);
> else if (IS_VALLEYVIEW(i915))
> vlv_rps_init(rps);
> - else if (INTEL_GEN(i915) >= 6)
> + else if (GRAPHICS_VER(i915) >= 6)
> gen6_rps_init(rps);
> else if (IS_IRONLAKE_M(i915))
> gen5_rps_init(rps);
> @@ -1843,7 +1843,7 @@ void intel_rps_init(struct intel_rps *rps)
> rps->min_freq_softlimit = rps->min_freq;
>
> /* After setting max-softlimit, find the overclock max freq */
> - if (IS_GEN(i915, 6) || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
> + if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
> u32 params = 0;
>
> sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS,
> @@ -1872,16 +1872,16 @@ void intel_rps_init(struct intel_rps *rps)
> *
> * TODO: verify if this can be reproduced on VLV,CHV.
> */
> - if (INTEL_GEN(i915) <= 7)
> + if (GRAPHICS_VER(i915) <= 7)
> rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
>
> - if (INTEL_GEN(i915) >= 8 && INTEL_GEN(i915) < 11)
> + if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) < 11)
> rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
> }
>
> void intel_rps_sanitize(struct intel_rps *rps)
> {
> - if (INTEL_GEN(rps_to_i915(rps)) >= 6)
> + if (GRAPHICS_VER(rps_to_i915(rps)) >= 6)
> rps_disable_interrupts(rps);
> }
>
> @@ -1892,11 +1892,11 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
>
> if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> cagf = (rpstat >> 8) & 0xff;
> - else if (INTEL_GEN(i915) >= 9)
> + else if (GRAPHICS_VER(i915) >= 9)
> cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
> - else if (INTEL_GEN(i915) >= 6)
> + else if (GRAPHICS_VER(i915) >= 6)
> cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
> else
> cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >>
> @@ -1915,7 +1915,7 @@ static u32 read_cagf(struct intel_rps *rps)
> vlv_punit_get(i915);
> freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
> vlv_punit_put(i915);
> - } else if (INTEL_GEN(i915) >= 6) {
> + } else if (GRAPHICS_VER(i915) >= 6) {
> freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
> } else {
> freq = intel_uncore_read(uncore, MEMSTAT_ILK);
> @@ -1968,7 +1968,7 @@ void intel_rps_driver_register(struct intel_rps *rps)
> * We only register the i915 ips part with intel-ips once everything is
> * set up, to avoid intel-ips sneaking in and reading bogus values.
> */
> - if (IS_GEN(gt->i915, 5)) {
> + if (GRAPHICS_VER(gt->i915) == 5) {
> GEM_BUG_ON(ips_mchdev);
> rcu_assign_pointer(ips_mchdev, gt->i915);
> ips_ping_for_i915_load();
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 0d9f74aec8fe..367fd44b81c8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -590,13 +590,13 @@ void intel_sseu_info_init(struct intel_gt *gt)
> cherryview_sseu_info_init(gt);
> else if (IS_BROADWELL(i915))
> bdw_sseu_info_init(gt);
> - else if (IS_GEN(i915, 9))
> + else if (GRAPHICS_VER(i915) == 9)
> gen9_sseu_info_init(gt);
> - else if (IS_GEN(i915, 10))
> + else if (GRAPHICS_VER(i915) == 10)
> gen10_sseu_info_init(gt);
> - else if (IS_GEN(i915, 11))
> + else if (GRAPHICS_VER(i915) == 11)
> gen11_sseu_info_init(gt);
> - else if (INTEL_GEN(i915) >= 12)
> + else if (GRAPHICS_VER(i915) >= 12)
> gen12_sseu_info_init(gt);
> }
>
> @@ -613,7 +613,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> * No explicit RPCS request is needed to ensure full
> * slice/subslice/EU enablement prior to Gen9.
> */
> - if (INTEL_GEN(i915) < 9)
> + if (GRAPHICS_VER(i915) < 9)
> return 0;
>
> /*
> @@ -651,7 +651,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> * subslices are enabled, or a count between one and four on the first
> * slice.
> */
> - if (IS_GEN(i915, 11) &&
> + if (GRAPHICS_VER(i915) == 11 &&
> slices == 1 &&
> subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
> GEM_BUG_ON(subslices & 1);
> @@ -669,7 +669,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> if (sseu->has_slice_pg) {
> u32 mask, val = slices;
>
> - if (INTEL_GEN(i915) >= 11) {
> + if (GRAPHICS_VER(i915) >= 11) {
> mask = GEN11_RPCS_S_CNT_MASK;
> val <<= GEN11_RPCS_S_CNT_SHIFT;
> } else {
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 62cb9ee5bfc3..b62d1e31a645 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -699,9 +699,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>
> if (IS_DG1(i915))
> dg1_ctx_workarounds_init(engine, wal);
> - else if (IS_GEN(i915, 12))
> + else if (GRAPHICS_VER(i915) == 12)
> gen12_ctx_workarounds_init(engine, wal);
> - else if (IS_GEN(i915, 11))
> + else if (GRAPHICS_VER(i915) == 11)
> icl_ctx_workarounds_init(engine, wal);
> else if (IS_CANNONLAKE(i915))
> cnl_ctx_workarounds_init(engine, wal);
> @@ -719,14 +719,14 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> chv_ctx_workarounds_init(engine, wal);
> else if (IS_BROADWELL(i915))
> bdw_ctx_workarounds_init(engine, wal);
> - else if (IS_GEN(i915, 7))
> + else if (GRAPHICS_VER(i915) == 7)
> gen7_ctx_workarounds_init(engine, wal);
> - else if (IS_GEN(i915, 6))
> + else if (GRAPHICS_VER(i915) == 6)
> gen6_ctx_workarounds_init(engine, wal);
> - else if (INTEL_GEN(i915) < 8)
> + else if (GRAPHICS_VER(i915) < 8)
> ;
> else
> - MISSING_CASE(INTEL_GEN(i915));
> + MISSING_CASE(GRAPHICS_VER(i915));
>
> wa_init_finish(wal);
> }
> @@ -950,7 +950,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> unsigned int slice, subslice;
> u32 l3_en, mcr, mcr_mask;
>
> - GEM_BUG_ON(INTEL_GEN(i915) < 10);
> + GEM_BUG_ON(GRAPHICS_VER(i915) < 10);
>
> /*
> * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
> @@ -980,7 +980,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> * of every MMIO read.
> */
>
> - if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
> + if (GRAPHICS_VER(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
> u32 l3_fuse =
> intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
> GEN10_L3BANK_MASK;
> @@ -1002,7 +1002,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> }
> subslice--;
>
> - if (INTEL_GEN(i915) >= 11) {
> + if (GRAPHICS_VER(i915) >= 11) {
> mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
> mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
> } else {
> @@ -1171,9 +1171,9 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> dg1_gt_workarounds_init(i915, wal);
> else if (IS_TIGERLAKE(i915))
> tgl_gt_workarounds_init(i915, wal);
> - else if (IS_GEN(i915, 12))
> + else if (GRAPHICS_VER(i915) == 12)
> gen12_gt_workarounds_init(i915, wal);
> - else if (IS_GEN(i915, 11))
> + else if (GRAPHICS_VER(i915) == 11)
> icl_gt_workarounds_init(i915, wal);
> else if (IS_CANNONLAKE(i915))
> cnl_gt_workarounds_init(i915, wal);
> @@ -1193,18 +1193,18 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> vlv_gt_workarounds_init(i915, wal);
> else if (IS_IVYBRIDGE(i915))
> ivb_gt_workarounds_init(i915, wal);
> - else if (IS_GEN(i915, 6))
> + else if (GRAPHICS_VER(i915) == 6)
> snb_gt_workarounds_init(i915, wal);
> - else if (IS_GEN(i915, 5))
> + else if (GRAPHICS_VER(i915) == 5)
> ilk_gt_workarounds_init(i915, wal);
> else if (IS_G4X(i915))
> g4x_gt_workarounds_init(i915, wal);
> - else if (IS_GEN(i915, 4))
> + else if (GRAPHICS_VER(i915) == 4)
> gen4_gt_workarounds_init(i915, wal);
> - else if (INTEL_GEN(i915) <= 8)
> + else if (GRAPHICS_VER(i915) <= 8)
> ;
> else
> - MISSING_CASE(INTEL_GEN(i915));
> + MISSING_CASE(GRAPHICS_VER(i915));
> }
>
> void intel_gt_init_workarounds(struct drm_i915_private *i915)
> @@ -1558,9 +1558,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>
> if (IS_DG1(i915))
> dg1_whitelist_build(engine);
> - else if (IS_GEN(i915, 12))
> + else if (GRAPHICS_VER(i915) == 12)
> tgl_whitelist_build(engine);
> - else if (IS_GEN(i915, 11))
> + else if (GRAPHICS_VER(i915) == 11)
> icl_whitelist_build(engine);
> else if (IS_CANNONLAKE(i915))
> cnl_whitelist_build(engine);
> @@ -1576,10 +1576,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> bxt_whitelist_build(engine);
> else if (IS_SKYLAKE(i915))
> skl_whitelist_build(engine);
> - else if (INTEL_GEN(i915) <= 8)
> + else if (GRAPHICS_VER(i915) <= 8)
> ;
> else
> - MISSING_CASE(INTEL_GEN(i915));
> + MISSING_CASE(GRAPHICS_VER(i915));
>
> wa_init_finish(w);
> }
> @@ -1695,7 +1695,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> ENABLE_SMALLPL);
> }
>
> - if (IS_GEN(i915, 11)) {
> + if (GRAPHICS_VER(i915) == 11) {
> /* This is not an Wa. Enable for better image quality */
> wa_masked_en(wal,
> _3D_CHICKEN3,
> @@ -1793,7 +1793,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> FF_DOP_CLOCK_GATE_DISABLE);
> }
>
> - if (IS_GEN_RANGE(i915, 9, 12)) {
> + if (IS_GRAPHICS_VER(i915, 9, 12)) {
> /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
> wa_masked_en(wal,
> GEN7_FF_SLICE_CS_CHICKEN1,
> @@ -1817,7 +1817,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
> }
>
> - if (IS_GEN(i915, 9)) {
> + if (GRAPHICS_VER(i915) == 9) {
> /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
> wa_masked_en(wal,
> GEN9_CSFE_CHICKEN1_RCS,
> @@ -1921,7 +1921,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
> }
>
> - if (IS_GEN(i915, 7)) {
> + if (GRAPHICS_VER(i915) == 7) {
> /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
> wa_masked_en(wal,
> GFX_MODE_GEN7,
> @@ -1953,7 +1953,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> GEN6_WIZ_HASHING_16x4);
> }
>
> - if (IS_GEN_RANGE(i915, 6, 7))
> + if (IS_GRAPHICS_VER(i915, 6, 7))
> /*
> * We need to disable the AsyncFlip performance optimisations in
> * order to use MI_WAIT_FOR_EVENT within the CS. It should
> @@ -1965,7 +1965,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> MI_MODE,
> ASYNC_FLIP_PERF_DISABLE);
>
> - if (IS_GEN(i915, 6)) {
> + if (GRAPHICS_VER(i915) == 6) {
> /*
> * Required for the hardware to program scanline values for
> * waiting
> @@ -2019,14 +2019,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> CM0_STC_EVICT_DISABLE_LRA_SNB);
> }
>
> - if (IS_GEN_RANGE(i915, 4, 6))
> + if (IS_GRAPHICS_VER(i915, 4, 6))
> /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
> wa_add(wal, MI_MODE,
> 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
> /* XXX bit doesn't stick on Broadwater */
> IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
>
> - if (IS_GEN(i915, 4))
> + if (GRAPHICS_VER(i915) == 4)
> /*
> * Disable CONSTANT_BUFFER before it is loaded from the context
> * image. For as it is loaded, it is executed and the stored
> @@ -2058,7 +2058,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> static void
> engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> {
> - if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4))
> + if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4))
> return;
>
> if (engine->class == RENDER_CLASS)
> @@ -2071,7 +2071,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
> {
> struct i915_wa_list *wal = &engine->wa_list;
>
> - if (INTEL_GEN(engine->i915) < 4)
> + if (GRAPHICS_VER(engine->i915) < 4)
> return;
>
> wa_init_start(wal, "engine", engine->name);
> @@ -2112,9 +2112,9 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
> const struct mcr_range *mcr_ranges;
> int i;
>
> - if (INTEL_GEN(i915) >= 12)
> + if (GRAPHICS_VER(i915) >= 12)
> mcr_ranges = mcr_ranges_gen12;
> - else if (INTEL_GEN(i915) >= 8)
> + else if (GRAPHICS_VER(i915) >= 8)
> mcr_ranges = mcr_ranges_gen8;
> else
> return false;
> @@ -2143,7 +2143,7 @@ wa_list_srm(struct i915_request *rq,
> u32 srm, *cs;
>
> srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
> - if (INTEL_GEN(i915) >= 8)
> + if (GRAPHICS_VER(i915) >= 8)
> srm++;
>
> for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> index 3453eb77c498..64abf5feabfa 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> @@ -52,7 +52,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
> return PTR_ERR(cs);
>
> cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
> - if (INTEL_GEN(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->engine->i915) >= 8)
> cmd++;
> *cs++ = cmd;
> *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
> @@ -125,7 +125,7 @@ static int perf_mi_bb_start(void *arg)
> enum intel_engine_id id;
> int err = 0;
>
> - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
> + if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
> return 0;
>
> perf_begin(gt);
> @@ -249,7 +249,7 @@ static int perf_mi_noop(void *arg)
> enum intel_engine_id id;
> int err = 0;
>
> - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
> + if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
> return 0;
>
> perf_begin(gt);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> index 2c898622bdfb..72cca3f0da21 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> @@ -198,7 +198,7 @@ static int live_engine_timestamps(void *arg)
> * the same CS clock.
> */
>
> - if (INTEL_GEN(gt->i915) < 8)
> + if (GRAPHICS_VER(gt->i915) < 8)
> return 0;
>
> for_each_engine(engine, gt, id) {
> diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> index 1f93591a8c69..ea2203af0764 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> @@ -3269,7 +3269,7 @@ static int live_preempt_user(void *arg)
> if (!intel_engine_has_preemption(engine))
> continue;
>
> - if (IS_GEN(gt->i915, 8) && engine->class != RENDER_CLASS)
> + if (GRAPHICS_VER(gt->i915) == 8 && engine->class != RENDER_CLASS)
> continue; /* we need per-context GPR */
>
> if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {
> @@ -4293,7 +4293,7 @@ static int live_virtual_preserved(void *arg)
> return 0;
>
> /* As we use CS_GPR we cannot run before they existed on all engines. */
> - if (INTEL_GEN(gt->i915) < 9)
> + if (GRAPHICS_VER(gt->i915) < 9)
> return 0;
>
> for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
> diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> index c0845bf72dd3..b9441217ca3d 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> @@ -74,10 +74,10 @@ static int live_gt_clocks(void *arg)
> return 0;
> }
>
> - if (INTEL_GEN(gt->i915) < 4) /* Any CS_TIMESTAMP? */
> + if (GRAPHICS_VER(gt->i915) < 4) /* Any CS_TIMESTAMP? */
> return 0;
>
> - if (IS_GEN(gt->i915, 5))
> + if (GRAPHICS_VER(gt->i915) == 5)
> /*
> * XXX CS_TIMESTAMP low dword is dysfunctional?
> *
> @@ -86,7 +86,7 @@ static int live_gt_clocks(void *arg)
> */
> return 0;
>
> - if (IS_GEN(gt->i915, 4))
> + if (GRAPHICS_VER(gt->i915) == 4)
> /*
> * XXX CS_TIMESTAMP appears gibberish
> *
> @@ -105,7 +105,7 @@ static int live_gt_clocks(void *arg)
> u64 time;
> u64 dt;
>
> - if (INTEL_GEN(engine->i915) < 7 && engine->id != RCS0)
> + if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0)
> continue;
>
> measure_clocks(engine, &cycles, &dt);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> index 5b63d4df8c93..853246fad05f 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> @@ -180,7 +180,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> goto cancel_rq;
>
> batch = h->batch;
> - if (INTEL_GEN(gt->i915) >= 8) {
> + if (GRAPHICS_VER(gt->i915) >= 8) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4;
> *batch++ = lower_32_bits(hws_address(hws, rq));
> *batch++ = upper_32_bits(hws_address(hws, rq));
> @@ -194,7 +194,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
> *batch++ = lower_32_bits(vma->node.start);
> *batch++ = upper_32_bits(vma->node.start);
> - } else if (INTEL_GEN(gt->i915) >= 6) {
> + } else if (GRAPHICS_VER(gt->i915) >= 6) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4;
> *batch++ = 0;
> *batch++ = lower_32_bits(hws_address(hws, rq));
> @@ -207,7 +207,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> *batch++ = MI_NOOP;
> *batch++ = MI_BATCH_BUFFER_START | 1 << 8;
> *batch++ = lower_32_bits(vma->node.start);
> - } else if (INTEL_GEN(gt->i915) >= 4) {
> + } else if (GRAPHICS_VER(gt->i915) >= 4) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *batch++ = 0;
> *batch++ = lower_32_bits(hws_address(hws, rq));
> @@ -243,7 +243,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> }
>
> flags = 0;
> - if (INTEL_GEN(gt->i915) <= 5)
> + if (GRAPHICS_VER(gt->i915) <= 5)
> flags |= I915_DISPATCH_SECURE;
>
> err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
> index 94006f117bbd..459b775f163a 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_llc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
> @@ -44,7 +44,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
> if (found != ia_freq) {
> pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected CPU freq, found %d, expected %d\n",
> gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
> - intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
> + intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
> found, ia_freq);
> err = -EINVAL;
> break;
> @@ -54,7 +54,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
> if (found != ring_freq) {
> pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected ring freq, found %d, expected %d\n",
> gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
> - intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
> + intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
> found, ring_freq);
> err = -EINVAL;
> break;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> index d8f6623524e8..3119016d9910 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> @@ -584,7 +584,7 @@ static int __live_lrc_gpr(struct intel_engine_cs *engine,
> int err;
> int n;
>
> - if (INTEL_GEN(engine->i915) < 9 && engine->class != RENDER_CLASS)
> + if (GRAPHICS_VER(engine->i915) < 9 && engine->class != RENDER_CLASS)
> return 0; /* GPR only on rcs0 for gen8 */
>
> err = gpr_make_dirty(engine->kernel_context);
> @@ -1389,10 +1389,10 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
>
> static bool skip_isolation(const struct intel_engine_cs *engine)
> {
> - if (engine->class == COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) == 9)
> + if (engine->class == COPY_ENGINE_CLASS && GRAPHICS_VER(engine->i915) == 9)
> return true;
>
> - if (engine->class == RENDER_CLASS && INTEL_GEN(engine->i915) == 11)
> + if (engine->class == RENDER_CLASS && GRAPHICS_VER(engine->i915) == 11)
> return true;
>
> return false;
> @@ -1551,7 +1551,7 @@ static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)
> /* We use the already reserved extra page in context state */
> if (!a->wa_bb_page) {
> GEM_BUG_ON(b->wa_bb_page);
> - GEM_BUG_ON(INTEL_GEN(engine->i915) == 12);
> + GEM_BUG_ON(GRAPHICS_VER(engine->i915) == 12);
> goto unpin_b;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> index e55a887d11e2..b9bb0e6e97f7 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> @@ -183,7 +183,7 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
> * which only controls CPU initiated MMIO. Routing does not
> * work for CS access so we cannot verify them on this path.
> */
> - return INTEL_GEN(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
> + return GRAPHICS_VER(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
> }
>
> static int check_l3cc_table(struct intel_engine_cs *engine,
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> index 710f825f6e5a..8c70b7e12074 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> @@ -140,7 +140,7 @@ static const u32 *__live_rc6_ctx(struct intel_context *ce)
> }
>
> cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
> - if (INTEL_GEN(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->engine->i915) >= 8)
> cmd++;
>
> *cs++ = cmd;
> @@ -193,7 +193,7 @@ int live_rc6_ctx_wa(void *arg)
> int err = 0;
>
> /* A read of CTX_INFO upsets rc6. Poke the bear! */
> - if (INTEL_GEN(gt->i915) < 8)
> + if (GRAPHICS_VER(gt->i915) < 8)
> return 0;
>
> engines = randomised_engines(gt, &prng, &count);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
> index c12e74171b63..041954408d0f 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
> @@ -41,10 +41,10 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
> return ERR_CAST(cs);
> }
>
> - if (INTEL_GEN(engine->i915) >= 6) {
> + if (GRAPHICS_VER(engine->i915) >= 6) {
> *cs++ = MI_STORE_DWORD_IMM_GEN4;
> *cs++ = 0;
> - } else if (INTEL_GEN(engine->i915) >= 4) {
> + } else if (GRAPHICS_VER(engine->i915) >= 4) {
> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *cs++ = 0;
> } else {
> @@ -266,7 +266,7 @@ static int live_ctx_switch_wa(void *arg)
> if (!intel_engine_can_store_dword(engine))
> continue;
>
> - if (IS_GEN_RANGE(gt->i915, 4, 5))
> + if (IS_GRAPHICS_VER(gt->i915, 4, 5))
> continue; /* MI_STORE_DWORD is privileged! */
>
> saved_wa = fetch_and_zero(&engine->wa_ctx.vma);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
> index 3ca1bd5793c3..7ee2513e15f9 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rps.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
> @@ -204,7 +204,7 @@ static void show_pstate_limits(struct intel_rps *rps)
> i915_mmio_reg_offset(BXT_RP_STATE_CAP),
> intel_uncore_read(rps_to_uncore(rps),
> BXT_RP_STATE_CAP));
> - } else if (IS_GEN(i915, 9)) {
> + } else if (GRAPHICS_VER(i915) == 9) {
> pr_info("P_STATE_LIMITS[%x]: 0x%08x\n",
> i915_mmio_reg_offset(GEN9_RP_STATE_LIMITS),
> intel_uncore_read(rps_to_uncore(rps),
> @@ -222,7 +222,7 @@ int live_rps_clock_interval(void *arg)
> struct igt_spinner spin;
> int err = 0;
>
> - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
> + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
> return 0;
>
> if (igt_spinner_init(&spin, gt))
> @@ -506,7 +506,7 @@ static void show_pcu_config(struct intel_rps *rps)
>
> min_gpu_freq = rps->min_freq;
> max_gpu_freq = rps->max_freq;
> - if (INTEL_GEN(i915) >= 9) {
> + if (GRAPHICS_VER(i915) >= 9) {
> /* Convert GT frequency to 50 HZ units */
> min_gpu_freq /= GEN9_FREQ_SCALER;
> max_gpu_freq /= GEN9_FREQ_SCALER;
> @@ -614,7 +614,7 @@ int live_rps_frequency_cs(void *arg)
> if (!intel_rps_is_enabled(rps))
> return 0;
>
> - if (INTEL_GEN(gt->i915) < 8) /* for CS simplicity */
> + if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
> return 0;
>
> if (CPU_LATENCY >= 0)
> @@ -755,7 +755,7 @@ int live_rps_frequency_srm(void *arg)
> if (!intel_rps_is_enabled(rps))
> return 0;
>
> - if (INTEL_GEN(gt->i915) < 8) /* for CS simplicity */
> + if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
> return 0;
>
> if (CPU_LATENCY >= 0)
> @@ -1031,7 +1031,7 @@ int live_rps_interrupt(void *arg)
> * First, let's check whether or not we are receiving interrupts.
> */
>
> - if (!intel_rps_has_interrupts(rps) || INTEL_GEN(gt->i915) < 6)
> + if (!intel_rps_has_interrupts(rps) || GRAPHICS_VER(gt->i915) < 6)
> return 0;
>
> intel_gt_pm_get(gt);
> @@ -1136,7 +1136,7 @@ int live_rps_power(void *arg)
> * that theory.
> */
>
> - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
> + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
> return 0;
>
> if (!librapl_supported(gt->i915))
> @@ -1240,7 +1240,7 @@ int live_rps_dynamic(void *arg)
> * moving parts into dynamic reclocking based on load.
> */
>
> - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
> + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
> return 0;
>
> if (igt_spinner_init(&spin, gt))
> diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> index 9adbd9d147be..64da0c91dec1 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> @@ -457,12 +457,12 @@ static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
> if (IS_ERR(cs))
> return PTR_ERR(cs);
>
> - if (INTEL_GEN(rq->engine->i915) >= 8) {
> + if (GRAPHICS_VER(rq->engine->i915) >= 8) {
> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *cs++ = addr;
> *cs++ = 0;
> *cs++ = value;
> - } else if (INTEL_GEN(rq->engine->i915) >= 4) {
> + } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *cs++ = 0;
> *cs++ = addr;
> @@ -992,7 +992,7 @@ static int live_hwsp_read(void *arg)
> * even across multiple wraps.
> */
>
> - if (INTEL_GEN(gt->i915) < 8) /* CS convenience [SRM/LRM] */
> + if (GRAPHICS_VER(gt->i915) < 8) /* CS convenience [SRM/LRM] */
> return 0;
>
> tl = intel_timeline_create(gt);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> index 64937ec3f2dc..c30754daf4b1 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> @@ -145,7 +145,7 @@ read_nonprivs(struct intel_context *ce)
> goto err_req;
>
> srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
> - if (INTEL_GEN(engine->i915) >= 8)
> + if (GRAPHICS_VER(engine->i915) >= 8)
> srm++;
>
> cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
> @@ -546,7 +546,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
>
> srm = MI_STORE_REGISTER_MEM;
> lrm = MI_LOAD_REGISTER_MEM;
> - if (INTEL_GEN(engine->i915) >= 8)
> + if (GRAPHICS_VER(engine->i915) >= 8)
> lrm++, srm++;
>
> pr_debug("%s: Writing garbage to %x\n",
> @@ -749,7 +749,7 @@ static int live_dirty_whitelist(void *arg)
>
> /* Can the user write to the whitelisted registers? */
>
> - if (INTEL_GEN(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */
> + if (GRAPHICS_VER(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */
> return 0;
>
> for_each_engine(engine, gt, id) {
> @@ -829,7 +829,7 @@ static int read_whitelisted_registers(struct intel_context *ce,
> goto err_req;
>
> srm = MI_STORE_REGISTER_MEM;
> - if (INTEL_GEN(engine->i915) >= 8)
> + if (GRAPHICS_VER(engine->i915) >= 8)
> srm++;
>
> cs = intel_ring_begin(rq, 4 * engine->whitelist.count);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index adae04c47aab..84f806911370 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -60,7 +60,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
> enum forcewake_domains fw_domains = 0;
> unsigned int i;
>
> - if (INTEL_GEN(gt->i915) >= 11) {
> + if (GRAPHICS_VER(gt->i915) >= 11) {
> guc->send_regs.base =
> i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
> guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
> @@ -176,7 +176,7 @@ void intel_guc_init_early(struct intel_guc *guc)
>
> mutex_init(&guc->send_mutex);
> spin_lock_init(&guc->irq_lock);
> - if (INTEL_GEN(i915) >= 11) {
> + if (GRAPHICS_VER(i915) >= 11) {
> guc->notify_reg = GEN11_GUC_HOST_INTERRUPT;
> guc->interrupts.reset = gen11_reset_guc_interrupts;
> guc->interrupts.enable = gen11_enable_guc_interrupts;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 17526717368c..b32fafba2a90 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -162,7 +162,7 @@ static void __guc_ads_init(struct intel_guc *guc)
> blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK] =
> gt->info.vdbox_sfc_access;
>
> - if (INTEL_GEN(i915) >= 12 && !IS_DGFX(i915)) {
> + if (GRAPHICS_VER(i915) >= 12 && !IS_DGFX(i915)) {
> u32 distdbreg = intel_uncore_read(gt->uncore,
> GEN12_DIST_DBS_POPULATED);
> blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI] =
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> index 2270d6b3b272..76fe766ad1bc 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> @@ -30,7 +30,7 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
> else
> intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
>
> - if (IS_GEN(uncore->i915, 9)) {
> + if (GRAPHICS_VER(uncore->i915) == 9) {
> /* DOP Clock Gating Enable for GuC clocks */
> intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
> 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 335719f17490..541f6da1ec47 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -438,7 +438,7 @@ static void guc_interrupts_capture(struct intel_gt *gt)
> u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
> u32 dmask = irqs << 16 | irqs;
>
> - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
> + GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
>
> /* Don't handle the ctx switch interrupt in GuC submission mode */
> intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask, 0);
> @@ -451,7 +451,7 @@ static void guc_interrupts_release(struct intel_gt *gt)
> u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
> u32 dmask = irqs << 16 | irqs;
>
> - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
> + GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
>
> /* Handle ctx switch interrupts again */
> intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0, dmask);
> @@ -648,7 +648,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
> engine->emit_flush = gen8_emit_flush_xcs;
> engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
> engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
> - if (INTEL_GEN(engine->i915) >= 12) {
> + if (GRAPHICS_VER(engine->i915) >= 12) {
> engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;
> engine->emit_flush = gen12_emit_flush_xcs;
> }
> @@ -670,7 +670,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>
> static void rcs_submission_override(struct intel_engine_cs *engine)
> {
> - switch (INTEL_GEN(engine->i915)) {
> + switch (GRAPHICS_VER(engine->i915)) {
> case 12:
> engine->emit_flush = gen12_emit_flush_rcs;
> engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
> @@ -700,7 +700,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
> * The setup relies on several assumptions (e.g. irqs always enabled)
> * that are only valid on gen11+
> */
> - GEM_BUG_ON(INTEL_GEN(i915) < 11);
> + GEM_BUG_ON(GRAPHICS_VER(i915) < 11);
>
> tasklet_setup(&engine->execlists.tasklet, guc_submission_tasklet);
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index 56d2144dc6a0..fc5387b410a2 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -43,7 +43,7 @@ void intel_huc_init_early(struct intel_huc *huc)
>
> intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC);
>
> - if (INTEL_GEN(i915) >= 11) {
> + if (GRAPHICS_VER(i915) >= 11) {
> huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
> huc->status.mask = HUC_LOAD_SUCCESSFUL;
> huc->status.value = HUC_LOAD_SUCCESSFUL;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 6abb8f2dc33d..6c2bf4b6bc10 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -23,7 +23,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
> return;
>
> /* Don't enable GuC/HuC on pre-Gen12 */
> - if (INTEL_GEN(i915) < 12) {
> + if (GRAPHICS_VER(i915) < 12) {
> i915->params.enable_guc = 0;
> return;
> }
> @@ -467,7 +467,7 @@ static int __uc_init_hw(struct intel_uc *uc)
>
> /* WaEnableuKernelHeaderValidFix:skl */
> /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
> - if (IS_GEN(i915, 9))
> + if (GRAPHICS_VER(i915) == 9)
> attempts = 3;
> else
> attempts = 1;
> --
> 2.31.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
2021-06-01 16:58 ` Matt Roper
@ 2021-06-01 17:15 ` Lucas De Marchi
2021-06-01 17:30 ` Matt Roper
0 siblings, 1 reply; 20+ messages in thread
From: Lucas De Marchi @ 2021-06-01 17:15 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Tue, Jun 01, 2021 at 09:58:34AM -0700, Matt Roper wrote:
>On Thu, May 27, 2021 at 11:16:54AM -0700, Lucas De Marchi wrote:
>> This was done by the following semantic patch:
>
>Is the commit message here out-of-date? The cocci doesn't appear to
>match the diff anymore. IS_GRAPHICS_VER() is the range macro now and
>IS_GEN is being replaced with a direct "==" comparison.
not necessarily, it's included in "and friends...". Maybe rewording to
something like "replace gen-based macros with new ver-based ones" would
make it clearer?
Lucas De Marchi
>
>
>Matt
>
>>
>> @@ expression dev_priv, E; @@
>> - INTEL_GEN(dev_priv) == E
>> + IS_GRAPHICS_VER(dev_priv, E)
>>
>> @@ expression dev_priv; @@
>> - INTEL_GEN(dev_priv)
>> + GRAPHICS_VER(dev_priv)
>>
>> @@ expression dev_priv; expression E; @@
>> - IS_GEN(dev_priv, E)
>> + IS_GRAPHICS_VER(dev_priv, E)
>>
>> @@
>> expression dev_priv;
>> expression from, until;
>> @@
>> - IS_GEN_RANGE(dev_priv, from, until)
>> + IS_GRAPHICS_RANGE(dev_priv, from, until)
>>
>> @def@
>> expression E;
>> identifier id =~ "^gen$";
>> @@
>> - id = GRAPHICS_VER(E)
>> + ver = GRAPHICS_VER(E)
>>
>> @@
>> identifier def.id;
>> @@
>> - id
>> + ver
>>
>> It also takes care of renaming the variable we assign to GRAPHICS_VER()
>> so to use "ver" rather than "gen".
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 38 +++++------
>> drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
>> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 54 +++++++--------
>> .../drm/i915/gt/intel_execlists_submission.c | 18 ++---
>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 18 ++---
>> drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 34 +++++-----
>> drivers/gpu/drm/i915/gt/intel_gt.c | 27 ++++----
>> .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 12 ++--
>> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 6 +-
>> drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 10 +--
>> drivers/gpu/drm/i915/gt/intel_gtt.c | 14 ++--
>> drivers/gpu/drm/i915/gt/intel_llc.c | 6 +-
>> drivers/gpu/drm/i915/gt/intel_lrc.c | 46 ++++++-------
>> drivers/gpu/drm/i915/gt/intel_mocs.c | 8 +--
>> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 6 +-
>> drivers/gpu/drm/i915/gt/intel_rc6.c | 16 ++---
>> drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_reset.c | 12 ++--
>> .../gpu/drm/i915/gt/intel_ring_submission.c | 64 +++++++++---------
>> drivers/gpu/drm/i915/gt/intel_rps.c | 60 ++++++++---------
>> drivers/gpu/drm/i915/gt/intel_sseu.c | 14 ++--
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +++++++++----------
>> drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 6 +-
>> drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 +-
>> drivers/gpu/drm/i915/gt/selftest_execlists.c | 4 +-
>> drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +--
>> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 +--
>> drivers/gpu/drm/i915/gt/selftest_llc.c | 4 +-
>> drivers/gpu/drm/i915/gt/selftest_lrc.c | 8 +--
>> drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
>> drivers/gpu/drm/i915/gt/selftest_rc6.c | 4 +-
>> .../drm/i915/gt/selftest_ring_submission.c | 6 +-
>> drivers/gpu/drm/i915/gt/selftest_rps.c | 16 ++---
>> drivers/gpu/drm/i915/gt/selftest_timeline.c | 6 +-
>> .../gpu/drm/i915/gt/selftest_workarounds.c | 8 +--
>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +-
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
>> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +--
>> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
>> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
>> 44 files changed, 323 insertions(+), 322 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
>> index d4f4452ce5ed..0389bceebd06 100644
>> --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
>> +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
>> @@ -85,14 +85,14 @@ static int gen6_drpc(struct seq_file *m)
>> gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
>>
>> rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
>> - if (INTEL_GEN(i915) >= 9) {
>> + if (GRAPHICS_VER(i915) >= 9) {
>> gen9_powergate_enable =
>> intel_uncore_read(uncore, GEN9_PG_ENABLE);
>> gen9_powergate_status =
>> intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
>> }
>>
>> - if (INTEL_GEN(i915) <= 7)
>> + if (GRAPHICS_VER(i915) <= 7)
>> sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
>> &rc6vids, NULL);
>>
>> @@ -100,7 +100,7 @@ static int gen6_drpc(struct seq_file *m)
>> yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
>> seq_printf(m, "RC6 Enabled: %s\n",
>> yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
>> - if (INTEL_GEN(i915) >= 9) {
>> + if (GRAPHICS_VER(i915) >= 9) {
>> seq_printf(m, "Render Well Gating Enabled: %s\n",
>> yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
>> seq_printf(m, "Media Well Gating Enabled: %s\n",
>> @@ -134,7 +134,7 @@ static int gen6_drpc(struct seq_file *m)
>>
>> seq_printf(m, "Core Power Down: %s\n",
>> yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
>> - if (INTEL_GEN(i915) >= 9) {
>> + if (GRAPHICS_VER(i915) >= 9) {
>> seq_printf(m, "Render Power Well: %s\n",
>> (gen9_powergate_status &
>> GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
>> @@ -150,7 +150,7 @@ static int gen6_drpc(struct seq_file *m)
>> print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
>> print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
>>
>> - if (INTEL_GEN(i915) <= 7) {
>> + if (GRAPHICS_VER(i915) <= 7) {
>> seq_printf(m, "RC6 voltage: %dmV\n",
>> GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
>> seq_printf(m, "RC6+ voltage: %dmV\n",
>> @@ -250,7 +250,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>>
>> wakeref = intel_runtime_pm_get(uncore->rpm);
>>
>> - if (IS_GEN(i915, 5)) {
>> + if (GRAPHICS_VER(i915) == 5) {
>> u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
>> u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
>>
>> @@ -296,7 +296,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>>
>> seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
>> intel_gpu_freq(rps, rps->efficient_freq));
>> - } else if (INTEL_GEN(i915) >= 6) {
>> + } else if (GRAPHICS_VER(i915) >= 6) {
>> u32 rp_state_limits;
>> u32 gt_perf_status;
>> u32 rp_state_cap;
>> @@ -321,7 +321,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>>
>> reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
>> - if (INTEL_GEN(i915) >= 9) {
>> + if (GRAPHICS_VER(i915) >= 9) {
>> reqf >>= 23;
>> } else {
>> reqf &= ~GEN6_TURBO_DISABLE;
>> @@ -354,7 +354,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>>
>> intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>>
>> - if (INTEL_GEN(i915) >= 11) {
>> + if (GRAPHICS_VER(i915) >= 11) {
>> pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
>> pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
>> /*
>> @@ -363,7 +363,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>> */
>> pm_isr = 0;
>> pm_iir = 0;
>> - } else if (INTEL_GEN(i915) >= 8) {
>> + } else if (GRAPHICS_VER(i915) >= 8) {
>> pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
>> pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
>> pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
>> @@ -386,14 +386,14 @@ static int frequency_show(struct seq_file *m, void *unused)
>>
>> seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
>> pm_ier, pm_imr, pm_mask);
>> - if (INTEL_GEN(i915) <= 10)
>> + if (GRAPHICS_VER(i915) <= 10)
>> seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
>> pm_isr, pm_iir);
>> seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
>> rps->pm_intrmsk_mbz);
>> seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
>> seq_printf(m, "Render p-state ratio: %d\n",
>> - (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
>> + (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
>> seq_printf(m, "Render p-state VID: %d\n",
>> gt_perf_status & 0xff);
>> seq_printf(m, "Render p-state limit: %d\n",
>> @@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void *unused)
>> max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
>> rp_state_cap >> 16) & 0xff;
>> max_freq *= (IS_GEN9_BC(i915) ||
>> - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
>> intel_gpu_freq(rps, max_freq));
>>
>> max_freq = (rp_state_cap & 0xff00) >> 8;
>> max_freq *= (IS_GEN9_BC(i915) ||
>> - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
>> intel_gpu_freq(rps, max_freq));
>>
>> max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
>> rp_state_cap >> 0) & 0xff;
>> max_freq *= (IS_GEN9_BC(i915) ||
>> - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
>> intel_gpu_freq(rps, max_freq));
>> seq_printf(m, "Max overclocked frequency: %dMHz\n",
>> @@ -488,7 +488,7 @@ static int llc_show(struct seq_file *m, void *data)
>> {
>> struct intel_gt *gt = m->private;
>> struct drm_i915_private *i915 = gt->i915;
>> - const bool edram = INTEL_GEN(i915) > 8;
>> + const bool edram = GRAPHICS_VER(i915) > 8;
>> struct intel_rps *rps = >->rps;
>> unsigned int max_gpu_freq, min_gpu_freq;
>> intel_wakeref_t wakeref;
>> @@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data)
>>
>> min_gpu_freq = rps->min_freq;
>> max_gpu_freq = rps->max_freq;
>> - if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
>> + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
>> /* Convert GT frequency to 50 HZ units */
>> min_gpu_freq /= GEN9_FREQ_SCALER;
>> max_gpu_freq /= GEN9_FREQ_SCALER;
>> @@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data)
>> intel_gpu_freq(rps,
>> (gpu_freq *
>> (IS_GEN9_BC(i915) ||
>> - INTEL_GEN(i915) >= 10 ?
>> + GRAPHICS_VER(i915) >= 10 ?
>> GEN9_FREQ_SCALER : 1))),
>> ((ia_freq >> 0) & 0xff) * 100,
>> ((ia_freq >> 8) & 0xff) * 100);
>> @@ -580,7 +580,7 @@ static int rps_boost_show(struct seq_file *m, void *data)
>>
>> seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
>>
>> - if (INTEL_GEN(i915) >= 6 && intel_rps_is_active(rps)) {
>> + if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) {
>> struct intel_uncore *uncore = gt->uncore;
>> u32 rpup, rpupei;
>> u32 rpdown, rpdownei;
>> diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> index 9646200d2792..61383830505e 100644
>> --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> @@ -74,7 +74,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
>> cmd = MI_FLUSH;
>> if (mode & EMIT_INVALIDATE) {
>> cmd |= MI_EXE_FLUSH;
>> - if (IS_G4X(rq->engine->i915) || IS_GEN(rq->engine->i915, 5))
>> + if (IS_G4X(rq->engine->i915) || GRAPHICS_VER(rq->engine->i915) == 5)
>> cmd |= MI_INVALIDATE_ISP;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> index 732c2ed1d933..94e0a5669f90 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> @@ -38,7 +38,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
>> * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
>> * pipe control.
>> */
>> - if (IS_GEN(rq->engine->i915, 9))
>> + if (GRAPHICS_VER(rq->engine->i915) == 9)
>> vf_flush_wa = true;
>>
>> /* WaForGAMHang:kbl */
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> index e3a8924d2286..21c8b7350b7a 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> @@ -709,7 +709,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
>> *
>> * Gen12 has inherited the same read-only fault issue from gen11.
>> */
>> - ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12);
>> + ppgtt->vm.has_read_only = !IS_GRAPHICS_VER(gt->i915, 11, 12);
>>
>> if (HAS_LMEM(gt->i915))
>> ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
>> index 8dfd8f656aaa..e86d8255feec 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
>> @@ -76,7 +76,7 @@ intel_context_reconfigure_sseu(struct intel_context *ce,
>> {
>> int ret;
>>
>> - GEM_BUG_ON(INTEL_GEN(ce->engine->i915) < 8);
>> + GEM_BUG_ON(GRAPHICS_VER(ce->engine->i915) < 8);
>>
>> ret = intel_context_lock_pinned(ce);
>> if (ret)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> index 3f9a811eb02b..54baf17b81b6 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> @@ -240,10 +240,10 @@ void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
>> * Though they added more rings on g4x/ilk, they did not add
>> * per-engine HWSTAM until gen6.
>> */
>> - if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS)
>> + if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)
>> return;
>>
>> - if (INTEL_GEN(engine->i915) >= 3)
>> + if (GRAPHICS_VER(engine->i915) >= 3)
>> ENGINE_WRITE(engine, RING_HWSTAM, mask);
>> else
>> ENGINE_WRITE16(engine, RING_HWSTAM, mask);
>> @@ -315,7 +315,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
>> CONFIG_DRM_I915_TIMESLICE_DURATION;
>>
>> /* Override to uninterruptible for OpenCL workloads. */
>> - if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS)
>> + if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
>> engine->props.preempt_timeout_ms = 0;
>>
>> engine->defaults = engine->props; /* never to change again */
>> @@ -352,8 +352,8 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
>> * HEVC support is present on first engine instance
>> * before Gen11 and on all instances afterwards.
>> */
>> - if (INTEL_GEN(i915) >= 11 ||
>> - (INTEL_GEN(i915) >= 9 && engine->instance == 0))
>> + if (GRAPHICS_VER(i915) >= 11 ||
>> + (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
>> engine->uabi_capabilities |=
>> I915_VIDEO_CLASS_CAPABILITY_HEVC;
>>
>> @@ -361,14 +361,14 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
>> * SFC block is present only on even logical engine
>> * instances.
>> */
>> - if ((INTEL_GEN(i915) >= 11 &&
>> + if ((GRAPHICS_VER(i915) >= 11 &&
>> (engine->gt->info.vdbox_sfc_access &
>> BIT(engine->instance))) ||
>> - (INTEL_GEN(i915) >= 9 && engine->instance == 0))
>> + (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
>> engine->uabi_capabilities |=
>> I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
>> } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
>> - if (INTEL_GEN(i915) >= 9)
>> + if (GRAPHICS_VER(i915) >= 9)
>> engine->uabi_capabilities |=
>> I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
>> }
>> @@ -466,7 +466,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>>
>> info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
>>
>> - if (INTEL_GEN(i915) < 11)
>> + if (GRAPHICS_VER(i915) < 11)
>> return info->engine_mask;
>>
>> media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
>> @@ -492,7 +492,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>> * hooked up to an SFC (Scaler & Format Converter) unit.
>> * In TGL each VDBOX has access to an SFC.
>> */
>> - if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
>> + if (GRAPHICS_VER(i915) >= 12 || logical_vdbox++ % 2 == 0)
>> gt->info.vdbox_sfc_access |= BIT(i);
>> }
>> drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
>> @@ -729,7 +729,7 @@ static int engine_setup_common(struct intel_engine_cs *engine)
>> intel_engine_init_whitelist(engine);
>> intel_engine_init_ctx_wa(engine);
>>
>> - if (INTEL_GEN(engine->i915) >= 12)
>> + if (GRAPHICS_VER(engine->i915) >= 12)
>> engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
>>
>> return 0;
>> @@ -997,9 +997,9 @@ u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
>>
>> u64 acthd;
>>
>> - if (INTEL_GEN(i915) >= 8)
>> + if (GRAPHICS_VER(i915) >= 8)
>> acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
>> - else if (INTEL_GEN(i915) >= 4)
>> + else if (GRAPHICS_VER(i915) >= 4)
>> acthd = ENGINE_READ(engine, RING_ACTHD);
>> else
>> acthd = ENGINE_READ(engine, ACTHD);
>> @@ -1011,7 +1011,7 @@ u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
>> {
>> u64 bbaddr;
>>
>> - if (INTEL_GEN(engine->i915) >= 8)
>> + if (GRAPHICS_VER(engine->i915) >= 8)
>> bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
>> else
>> bbaddr = ENGINE_READ(engine, RING_BBADDR);
>> @@ -1058,7 +1058,7 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
>> {
>> int err = 0;
>>
>> - if (INTEL_GEN(engine->i915) < 3)
>> + if (GRAPHICS_VER(engine->i915) < 3)
>> return -ENODEV;
>>
>> ENGINE_TRACE(engine, "\n");
>> @@ -1108,7 +1108,7 @@ read_subslice_reg(const struct intel_engine_cs *engine,
>> u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
>> enum forcewake_domains fw_domains;
>>
>> - if (INTEL_GEN(i915) >= 11) {
>> + if (GRAPHICS_VER(i915) >= 11) {
>> mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
>> mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
>> } else {
>> @@ -1157,7 +1157,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
>>
>> memset(instdone, 0, sizeof(*instdone));
>>
>> - switch (INTEL_GEN(i915)) {
>> + switch (GRAPHICS_VER(i915)) {
>> default:
>> instdone->instdone =
>> intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
>> @@ -1167,7 +1167,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
>>
>> instdone->slice_common =
>> intel_uncore_read(uncore, GEN7_SC_INSTDONE);
>> - if (INTEL_GEN(i915) >= 12) {
>> + if (GRAPHICS_VER(i915) >= 12) {
>> instdone->slice_common_extra[0] =
>> intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
>> instdone->slice_common_extra[1] =
>> @@ -1230,7 +1230,7 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
>> idle = false;
>>
>> /* No bit for gen2, so assume the CS parser is idle */
>> - if (INTEL_GEN(engine->i915) > 2 &&
>> + if (GRAPHICS_VER(engine->i915) > 2 &&
>> !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
>> idle = false;
>>
>> @@ -1327,7 +1327,7 @@ void intel_engines_reset_default_submission(struct intel_gt *gt)
>>
>> bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
>> {
>> - switch (INTEL_GEN(engine->i915)) {
>> + switch (GRAPHICS_VER(engine->i915)) {
>> case 2:
>> return false; /* uses physical not virtual addresses */
>> case 3:
>> @@ -1432,7 +1432,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
>> struct intel_engine_execlists * const execlists = &engine->execlists;
>> u64 addr;
>>
>> - if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
>> + if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7))
>> drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
>> if (HAS_EXECLISTS(dev_priv)) {
>> drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
>> @@ -1449,13 +1449,13 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
>> drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
>> ENGINE_READ(engine, RING_CTL),
>> ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
>> - if (INTEL_GEN(engine->i915) > 2) {
>> + if (GRAPHICS_VER(engine->i915) > 2) {
>> drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
>> ENGINE_READ(engine, RING_MI_MODE),
>> ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
>> }
>>
>> - if (INTEL_GEN(dev_priv) >= 6) {
>> + if (GRAPHICS_VER(dev_priv) >= 6) {
>> drm_printf(m, "\tRING_IMR: 0x%08x\n",
>> ENGINE_READ(engine, RING_IMR));
>> drm_printf(m, "\tRING_ESR: 0x%08x\n",
>> @@ -1472,15 +1472,15 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
>> addr = intel_engine_get_last_batch_head(engine);
>> drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
>> upper_32_bits(addr), lower_32_bits(addr));
>> - if (INTEL_GEN(dev_priv) >= 8)
>> + if (GRAPHICS_VER(dev_priv) >= 8)
>> addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
>> - else if (INTEL_GEN(dev_priv) >= 4)
>> + else if (GRAPHICS_VER(dev_priv) >= 4)
>> addr = ENGINE_READ(engine, RING_DMA_FADD);
>> else
>> addr = ENGINE_READ(engine, DMA_FADD_I8XX);
>> drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
>> upper_32_bits(addr), lower_32_bits(addr));
>> - if (INTEL_GEN(dev_priv) >= 4) {
>> + if (GRAPHICS_VER(dev_priv) >= 4) {
>> drm_printf(m, "\tIPEIR: 0x%08x\n",
>> ENGINE_READ(engine, RING_IPEIR));
>> drm_printf(m, "\tIPEHR: 0x%08x\n",
>> @@ -1559,7 +1559,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
>> }
>> rcu_read_unlock();
>> execlists_active_unlock_bh(execlists);
>> - } else if (INTEL_GEN(dev_priv) > 6) {
>> + } else if (GRAPHICS_VER(dev_priv) > 6) {
>> drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
>> ENGINE_READ(engine, RING_PP_DIR_BASE));
>> drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> index 8db200422950..fc77592d88a9 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> @@ -1847,7 +1847,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
>> ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n",
>> head, upper_32_bits(csb), lower_32_bits(csb));
>>
>> - if (INTEL_GEN(engine->i915) >= 12)
>> + if (GRAPHICS_VER(engine->i915) >= 12)
>> promote = gen12_csb_parse(csb);
>> else
>> promote = gen8_csb_parse(csb);
>> @@ -2772,7 +2772,7 @@ static void enable_execlists(struct intel_engine_cs *engine)
>>
>> intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
>>
>> - if (INTEL_GEN(engine->i915) >= 11)
>> + if (GRAPHICS_VER(engine->i915) >= 11)
>> mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
>> else
>> mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
>> @@ -3103,7 +3103,7 @@ static void execlists_park(struct intel_engine_cs *engine)
>>
>> static bool can_preempt(struct intel_engine_cs *engine)
>> {
>> - if (INTEL_GEN(engine->i915) > 8)
>> + if (GRAPHICS_VER(engine->i915) > 8)
>> return true;
>>
>> /* GPGPU on bdw requires extra w/a; not implemented */
>> @@ -3156,13 +3156,13 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
>> engine->emit_flush = gen8_emit_flush_xcs;
>> engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
>> engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
>> - if (INTEL_GEN(engine->i915) >= 12) {
>> + if (GRAPHICS_VER(engine->i915) >= 12) {
>> engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;
>> engine->emit_flush = gen12_emit_flush_xcs;
>> }
>> engine->set_default_submission = execlists_set_default_submission;
>>
>> - if (INTEL_GEN(engine->i915) < 11) {
>> + if (GRAPHICS_VER(engine->i915) < 11) {
>> engine->irq_enable = gen8_logical_ring_enable_irq;
>> engine->irq_disable = gen8_logical_ring_disable_irq;
>> } else {
>> @@ -3195,7 +3195,7 @@ static void logical_ring_default_irqs(struct intel_engine_cs *engine)
>> {
>> unsigned int shift = 0;
>>
>> - if (INTEL_GEN(engine->i915) < 11) {
>> + if (GRAPHICS_VER(engine->i915) < 11) {
>> const u8 irq_shifts[] = {
>> [RCS0] = GEN8_RCS_IRQ_SHIFT,
>> [BCS0] = GEN8_BCS_IRQ_SHIFT,
>> @@ -3215,7 +3215,7 @@ static void logical_ring_default_irqs(struct intel_engine_cs *engine)
>>
>> static void rcs_submission_override(struct intel_engine_cs *engine)
>> {
>> - switch (INTEL_GEN(engine->i915)) {
>> + switch (GRAPHICS_VER(engine->i915)) {
>> case 12:
>> engine->emit_flush = gen12_emit_flush_rcs;
>> engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
>> @@ -3266,13 +3266,13 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
>> execlists->csb_write =
>> &engine->status_page.addr[intel_hws_csb_write_index(i915)];
>>
>> - if (INTEL_GEN(i915) < 11)
>> + if (GRAPHICS_VER(i915) < 11)
>> execlists->csb_size = GEN8_CSB_ENTRIES;
>> else
>> execlists->csb_size = GEN11_CSB_ENTRIES;
>>
>> engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);
>> - if (INTEL_GEN(engine->i915) >= 11) {
>> + if (GRAPHICS_VER(engine->i915) >= 11) {
>> execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
>> execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> index 35069ca5d7de..19bd8856ce84 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> @@ -107,10 +107,10 @@ static bool needs_idle_maps(struct drm_i915_private *i915)
>> if (!intel_vtd_active())
>> return false;
>>
>> - if (IS_GEN(i915, 5) && IS_MOBILE(i915))
>> + if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
>> return true;
>>
>> - if (IS_GEN(i915, 12))
>> + if (GRAPHICS_VER(i915) == 12)
>> return true; /* XXX DMAR fault reason 7 */
>>
>> return false;
>> @@ -176,7 +176,7 @@ static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
>>
>> gen8_ggtt_invalidate(ggtt);
>>
>> - if (INTEL_GEN(i915) >= 12)
>> + if (GRAPHICS_VER(i915) >= 12)
>> intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
>> GEN12_GUC_TLB_INV_CR_INVALIDATE);
>> else
>> @@ -820,7 +820,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
>> * resort to an uncached mapping. The WC issue is easily caught by the
>> * readback check when writing GTT PTE entries.
>> */
>> - if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
>> + if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 10)
>> ggtt->gsm = ioremap(phys_addr, size);
>> else
>> ggtt->gsm = ioremap_wc(phys_addr, size);
>> @@ -1065,7 +1065,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
>> ggtt->vm.pte_encode = hsw_pte_encode;
>> else if (IS_VALLEYVIEW(i915))
>> ggtt->vm.pte_encode = byt_pte_encode;
>> - else if (INTEL_GEN(i915) >= 7)
>> + else if (GRAPHICS_VER(i915) >= 7)
>> ggtt->vm.pte_encode = ivb_pte_encode;
>> else
>> ggtt->vm.pte_encode = snb_pte_encode;
>> @@ -1137,9 +1137,9 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
>> ggtt->vm.dma = i915->drm.dev;
>> dma_resv_init(&ggtt->vm.resv);
>>
>> - if (INTEL_GEN(i915) <= 5)
>> + if (GRAPHICS_VER(i915) <= 5)
>> ret = i915_gmch_probe(ggtt);
>> - else if (INTEL_GEN(i915) < 8)
>> + else if (GRAPHICS_VER(i915) < 8)
>> ret = gen6_gmch_probe(ggtt);
>> else
>> ret = gen8_gmch_probe(ggtt);
>> @@ -1196,7 +1196,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
>>
>> int i915_ggtt_enable_hw(struct drm_i915_private *i915)
>> {
>> - if (INTEL_GEN(i915) < 6 && !intel_enable_gtt())
>> + if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
>> return -EIO;
>>
>> return 0;
>> @@ -1261,7 +1261,7 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt)
>> if (flush)
>> wbinvd_on_all_cpus();
>>
>> - if (INTEL_GEN(ggtt->vm.i915) >= 8)
>> + if (GRAPHICS_VER(ggtt->vm.i915) >= 8)
>> setup_private_pat(ggtt->vm.gt->uncore);
>>
>> intel_ggtt_restore_fences(ggtt);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
>> index 7bf84cd21543..cac7f3f44642 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
>> @@ -56,7 +56,7 @@ static void i965_write_fence_reg(struct i915_fence_reg *fence)
>> int fence_pitch_shift;
>> u64 val;
>>
>> - if (INTEL_GEN(fence_to_i915(fence)) >= 6) {
>> + if (GRAPHICS_VER(fence_to_i915(fence)) >= 6) {
>> fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
>> fence_reg_hi = FENCE_REG_GEN6_HI(fence->id);
>> fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
>> @@ -173,9 +173,9 @@ static void fence_write(struct i915_fence_reg *fence)
>> * and explicitly managed for internal users.
>> */
>>
>> - if (IS_GEN(i915, 2))
>> + if (GRAPHICS_VER(i915) == 2)
>> i830_write_fence_reg(fence);
>> - else if (IS_GEN(i915, 3))
>> + else if (GRAPHICS_VER(i915) == 3)
>> i915_write_fence_reg(fence);
>> else
>> i965_write_fence_reg(fence);
>> @@ -188,7 +188,7 @@ static void fence_write(struct i915_fence_reg *fence)
>>
>> static bool gpu_uses_fence_registers(struct i915_fence_reg *fence)
>> {
>> - return INTEL_GEN(fence_to_i915(fence)) < 4;
>> + return GRAPHICS_VER(fence_to_i915(fence)) < 4;
>> }
>>
>> static int fence_update(struct i915_fence_reg *fence,
>> @@ -569,7 +569,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
>> u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
>> u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>>
>> - if (INTEL_GEN(i915) >= 8 || IS_VALLEYVIEW(i915)) {
>> + if (GRAPHICS_VER(i915) >= 8 || IS_VALLEYVIEW(i915)) {
>> /*
>> * On BDW+, swizzling is not used. We leave the CPU memory
>> * controller in charge of optimizing memory accesses without
>> @@ -579,7 +579,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
>> */
>> swizzle_x = I915_BIT_6_SWIZZLE_NONE;
>> swizzle_y = I915_BIT_6_SWIZZLE_NONE;
>> - } else if (INTEL_GEN(i915) >= 6) {
>> + } else if (GRAPHICS_VER(i915) >= 6) {
>> if (i915->preserve_bios_swizzle) {
>> if (intel_uncore_read(uncore, DISP_ARB_CTL) &
>> DISP_TILE_SURFACE_SWIZZLING) {
>> @@ -611,14 +611,14 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
>> swizzle_y = I915_BIT_6_SWIZZLE_NONE;
>> }
>> }
>> - } else if (IS_GEN(i915, 5)) {
>> + } else if (GRAPHICS_VER(i915) == 5) {
>> /*
>> * On Ironlake whatever DRAM config, GPU always do
>> * same swizzling setup.
>> */
>> swizzle_x = I915_BIT_6_SWIZZLE_9_10;
>> swizzle_y = I915_BIT_6_SWIZZLE_9;
>> - } else if (IS_GEN(i915, 2)) {
>> + } else if (GRAPHICS_VER(i915) == 2) {
>> /*
>> * As far as we know, the 865 doesn't have these bit 6
>> * swizzling issues.
>> @@ -697,7 +697,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
>> }
>>
>> /* check for L-shaped memory aka modified enhanced addressing */
>> - if (IS_GEN(i915, 4) &&
>> + if (GRAPHICS_VER(i915) == 4 &&
>> !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
>> swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
>> swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>> @@ -844,10 +844,10 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
>>
>> if (!i915_ggtt_has_aperture(ggtt))
>> num_fences = 0;
>> - else if (INTEL_GEN(i915) >= 7 &&
>> + else if (GRAPHICS_VER(i915) >= 7 &&
>> !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
>> num_fences = 32;
>> - else if (INTEL_GEN(i915) >= 4 ||
>> + else if (GRAPHICS_VER(i915) >= 4 ||
>> IS_I945G(i915) || IS_I945GM(i915) ||
>> IS_G33(i915) || IS_PINEVIEW(i915))
>> num_fences = 16;
>> @@ -895,29 +895,29 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
>> struct drm_i915_private *i915 = gt->i915;
>> struct intel_uncore *uncore = gt->uncore;
>>
>> - if (INTEL_GEN(i915) < 5 ||
>> + if (GRAPHICS_VER(i915) < 5 ||
>> i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
>> return;
>>
>> intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
>>
>> - if (IS_GEN(i915, 5))
>> + if (GRAPHICS_VER(i915) == 5)
>> return;
>>
>> intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL);
>>
>> - if (IS_GEN(i915, 6))
>> + if (GRAPHICS_VER(i915) == 6)
>> intel_uncore_write(uncore,
>> ARB_MODE,
>> _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
>> - else if (IS_GEN(i915, 7))
>> + else if (GRAPHICS_VER(i915) == 7)
>> intel_uncore_write(uncore,
>> ARB_MODE,
>> _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
>> - else if (IS_GEN(i915, 8))
>> + else if (GRAPHICS_VER(i915) == 8)
>> intel_uncore_write(uncore,
>> GAMTARBMODE,
>> _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
>> else
>> - MISSING_CASE(INTEL_GEN(i915));
>> + MISSING_CASE(GRAPHICS_VER(i915));
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>> index 8d77dcbad059..7f24301cef18 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> @@ -115,10 +115,10 @@ static void init_unused_rings(struct intel_gt *gt)
>> init_unused_ring(gt, SRB1_BASE);
>> init_unused_ring(gt, SRB2_BASE);
>> init_unused_ring(gt, SRB3_BASE);
>> - } else if (IS_GEN(i915, 2)) {
>> + } else if (GRAPHICS_VER(i915) == 2) {
>> init_unused_ring(gt, SRB0_BASE);
>> init_unused_ring(gt, SRB1_BASE);
>> - } else if (IS_GEN(i915, 3)) {
>> + } else if (GRAPHICS_VER(i915) == 3) {
>> init_unused_ring(gt, PRB1_BASE);
>> init_unused_ring(gt, PRB2_BASE);
>> }
>> @@ -135,7 +135,7 @@ int intel_gt_init_hw(struct intel_gt *gt)
>> /* Double layer security blanket, see i915_gem_init() */
>> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>>
>> - if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
>> + if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
>> intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
>>
>> if (IS_HASWELL(i915))
>> @@ -208,10 +208,10 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
>> struct intel_uncore *uncore = gt->uncore;
>> u32 eir;
>>
>> - if (!IS_GEN(i915, 2))
>> + if (GRAPHICS_VER(i915) != 2)
>> clear_register(uncore, PGTBL_ER);
>>
>> - if (INTEL_GEN(i915) < 4)
>> + if (GRAPHICS_VER(i915) < 4)
>> clear_register(uncore, IPEIR(RENDER_RING_BASE));
>> else
>> clear_register(uncore, IPEIR_I965);
>> @@ -229,13 +229,13 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
>> I915_MASTER_ERROR_INTERRUPT);
>> }
>>
>> - if (INTEL_GEN(i915) >= 12) {
>> + if (GRAPHICS_VER(i915) >= 12) {
>> rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
>> intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
>> - } else if (INTEL_GEN(i915) >= 8) {
>> + } else if (GRAPHICS_VER(i915) >= 8) {
>> rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
>> intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
>> - } else if (INTEL_GEN(i915) >= 6) {
>> + } else if (GRAPHICS_VER(i915) >= 6) {
>> struct intel_engine_cs *engine;
>> enum intel_engine_id id;
>>
>> @@ -273,7 +273,7 @@ static void gen8_check_faults(struct intel_gt *gt)
>> i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
>> u32 fault;
>>
>> - if (INTEL_GEN(gt->i915) >= 12) {
>> + if (GRAPHICS_VER(gt->i915) >= 12) {
>> fault_reg = GEN12_RING_FAULT_REG;
>> fault_data0_reg = GEN12_FAULT_TLB_DATA0;
>> fault_data1_reg = GEN12_FAULT_TLB_DATA1;
>> @@ -313,9 +313,9 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
>> struct drm_i915_private *i915 = gt->i915;
>>
>> /* From GEN8 onwards we only have one 'All Engine Fault Register' */
>> - if (INTEL_GEN(i915) >= 8)
>> + if (GRAPHICS_VER(i915) >= 8)
>> gen8_check_faults(gt);
>> - else if (INTEL_GEN(i915) >= 6)
>> + else if (GRAPHICS_VER(i915) >= 6)
>> gen6_check_faults(gt);
>> else
>> return;
>> @@ -367,7 +367,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
>> void intel_gt_chipset_flush(struct intel_gt *gt)
>> {
>> wmb();
>> - if (INTEL_GEN(gt->i915) < 6)
>> + if (GRAPHICS_VER(gt->i915) < 6)
>> intel_gtt_chipset_flush();
>> }
>>
>> @@ -591,7 +591,8 @@ int intel_gt_init(struct intel_gt *gt)
>> */
>> intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
>>
>> - err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K);
>> + err = intel_gt_init_scratch(gt,
>> + GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
>> if (err)
>> goto out_fw;
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
>> index 582fcaee11aa..9f0e729d2d15 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
>> @@ -76,7 +76,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> u32 f19_2_mhz = 19200000;
>> u32 f24_mhz = 24000000;
>>
>> - if (INTEL_GEN(uncore->i915) <= 4) {
>> + if (GRAPHICS_VER(uncore->i915) <= 4) {
>> /*
>> * PRMs say:
>> *
>> @@ -85,7 +85,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> * (“CLKCFG”) MCHBAR register)
>> */
>> return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
>> - } else if (INTEL_GEN(uncore->i915) <= 8) {
>> + } else if (GRAPHICS_VER(uncore->i915) <= 8) {
>> /*
>> * PRMs say:
>> *
>> @@ -94,7 +94,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> * rolling over every 1.5 hours).
>> */
>> return f12_5_mhz;
>> - } else if (INTEL_GEN(uncore->i915) <= 9) {
>> + } else if (GRAPHICS_VER(uncore->i915) <= 9) {
>> u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
>> u32 freq = 0;
>>
>> @@ -113,7 +113,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> }
>>
>> return freq;
>> - } else if (INTEL_GEN(uncore->i915) <= 12) {
>> + } else if (GRAPHICS_VER(uncore->i915) <= 12) {
>> u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
>> u32 freq = 0;
>>
>> @@ -128,7 +128,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> } else {
>> u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
>>
>> - if (INTEL_GEN(uncore->i915) <= 10)
>> + if (GRAPHICS_VER(uncore->i915) <= 10)
>> freq = gen10_get_crystal_clock_freq(uncore, c0);
>> else
>> freq = gen11_get_crystal_clock_freq(uncore, c0);
>> @@ -211,7 +211,7 @@ u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns)
>> * frozen machine.
>> */
>> val = div_u64_roundup(intel_gt_ns_to_clock_interval(gt, ns), 16);
>> - if (IS_GEN(gt->i915, 6))
>> + if (GRAPHICS_VER(gt->i915) == 6)
>> val = div_u64_roundup(val, 25) * 25;
>>
>> return val;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> index d29126c458ba..1ec63cceabf6 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> @@ -395,7 +395,7 @@ void gen5_gt_irq_reset(struct intel_gt *gt)
>> struct intel_uncore *uncore = gt->uncore;
>>
>> GEN3_IRQ_RESET(uncore, GT);
>> - if (INTEL_GEN(gt->i915) >= 6)
>> + if (GRAPHICS_VER(gt->i915) >= 6)
>> GEN3_IRQ_RESET(uncore, GEN6_PM);
>> }
>>
>> @@ -413,14 +413,14 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt)
>> }
>>
>> gt_irqs |= GT_RENDER_USER_INTERRUPT;
>> - if (IS_GEN(gt->i915, 5))
>> + if (GRAPHICS_VER(gt->i915) == 5)
>> gt_irqs |= ILK_BSD_USER_INTERRUPT;
>> else
>> gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
>>
>> GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs);
>>
>> - if (INTEL_GEN(gt->i915) >= 6) {
>> + if (GRAPHICS_VER(gt->i915) >= 6) {
>> /*
>> * RPS interrupts will get enabled/disabled on demand when RPS
>> * itself is enabled/disabled.
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
>> index 811a11ed181c..fe51f894b073 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
>> @@ -16,10 +16,10 @@ static void write_pm_imr(struct intel_gt *gt)
>> u32 mask = gt->pm_imr;
>> i915_reg_t reg;
>>
>> - if (INTEL_GEN(i915) >= 11) {
>> + if (GRAPHICS_VER(i915) >= 11) {
>> reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
>> mask <<= 16; /* pm is in upper half */
>> - } else if (INTEL_GEN(i915) >= 8) {
>> + } else if (GRAPHICS_VER(i915) >= 8) {
>> reg = GEN8_GT_IMR(2);
>> } else {
>> reg = GEN6_PMIMR;
>> @@ -61,7 +61,7 @@ void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask)
>> void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)
>> {
>> struct intel_uncore *uncore = gt->uncore;
>> - i915_reg_t reg = INTEL_GEN(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
>> + i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
>>
>> lockdep_assert_held(>->irq_lock);
>>
>> @@ -77,10 +77,10 @@ static void write_pm_ier(struct intel_gt *gt)
>> u32 mask = gt->pm_ier;
>> i915_reg_t reg;
>>
>> - if (INTEL_GEN(i915) >= 11) {
>> + if (GRAPHICS_VER(i915) >= 11) {
>> reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
>> mask <<= 16; /* pm is in upper half */
>> - } else if (INTEL_GEN(i915) >= 8) {
>> + } else if (GRAPHICS_VER(i915) >= 8) {
>> reg = GEN8_GT_IER(2);
>> } else {
>> reg = GEN6_PMIER;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
>> index 9b98f9d9faa3..b9c9993573ec 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
>> @@ -327,7 +327,7 @@ void gtt_write_workarounds(struct intel_gt *gt)
>> intel_uncore_write(uncore,
>> GEN8_L3_LRA_1_GPGPU,
>> GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
>> - else if (INTEL_GEN(i915) >= 9 && INTEL_GEN(i915) <= 11)
>> + else if (GRAPHICS_VER(i915) >= 9 && GRAPHICS_VER(i915) <= 11)
>> intel_uncore_write(uncore,
>> GEN8_L3_LRA_1_GPGPU,
>> GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>> @@ -344,13 +344,13 @@ void gtt_write_workarounds(struct intel_gt *gt)
>> * driver.
>> */
>> if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
>> - INTEL_GEN(i915) <= 10)
>> + GRAPHICS_VER(i915) <= 10)
>> intel_uncore_rmw(uncore,
>> GEN8_GAMW_ECO_DEV_RW_IA,
>> 0,
>> GAMW_ECO_ENABLE_64K_IPS_FIELD);
>>
>> - if (IS_GEN_RANGE(i915, 8, 11)) {
>> + if (IS_GRAPHICS_VER(i915, 8, 11)) {
>> bool can_use_gtt_cache = true;
>>
>> /*
>> @@ -432,7 +432,7 @@ static void bdw_setup_private_ppat(struct intel_uncore *uncore)
>> GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
>>
>> /* for scanout with eLLC */
>> - if (INTEL_GEN(i915) >= 9)
>> + if (GRAPHICS_VER(i915) >= 9)
>> pat |= GEN8_PPAT(2, GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE);
>> else
>> pat |= GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
>> @@ -481,11 +481,11 @@ void setup_private_pat(struct intel_uncore *uncore)
>> {
>> struct drm_i915_private *i915 = uncore->i915;
>>
>> - GEM_BUG_ON(INTEL_GEN(i915) < 8);
>> + GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
>>
>> - if (INTEL_GEN(i915) >= 12)
>> + if (GRAPHICS_VER(i915) >= 12)
>> tgl_setup_private_ppat(uncore);
>> - else if (INTEL_GEN(i915) >= 10)
>> + else if (GRAPHICS_VER(i915) >= 10)
>> cnl_setup_private_ppat(uncore);
>> else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))
>> chv_setup_private_ppat(uncore);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
>> index 075d741644ae..eb1a15deed22 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_llc.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_llc.c
>> @@ -64,7 +64,7 @@ static bool get_ia_constants(struct intel_llc *llc,
>>
>> consts->min_gpu_freq = rps->min_freq;
>> consts->max_gpu_freq = rps->max_freq;
>> - if (INTEL_GEN(i915) >= 9) {
>> + if (GRAPHICS_VER(i915) >= 9) {
>> /* Convert GT frequency to 50 HZ units */
>> consts->min_gpu_freq /= GEN9_FREQ_SCALER;
>> consts->max_gpu_freq /= GEN9_FREQ_SCALER;
>> @@ -83,13 +83,13 @@ static void calc_ia_freq(struct intel_llc *llc,
>> const int diff = consts->max_gpu_freq - gpu_freq;
>> unsigned int ia_freq = 0, ring_freq = 0;
>>
>> - if (INTEL_GEN(i915) >= 9) {
>> + if (GRAPHICS_VER(i915) >= 9) {
>> /*
>> * ring_freq = 2 * GT. ring_freq is in 100MHz units
>> * No floor required for ring frequency on SKL.
>> */
>> ring_freq = gpu_freq;
>> - } else if (INTEL_GEN(i915) >= 8) {
>> + } else if (GRAPHICS_VER(i915) >= 8) {
>> /* max(2 * GT, DDR). NB: GT is 50MHz units */
>> ring_freq = max(consts->min_ring_freq, gpu_freq);
>> } else if (IS_HASWELL(i915)) {
>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> index aafe2a4df496..a27bac0a4bfb 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> @@ -47,7 +47,7 @@ static void set_offsets(u32 *regs,
>> *regs = MI_LOAD_REGISTER_IMM(count);
>> if (flags & POSTED)
>> *regs |= MI_LRI_FORCE_POSTED;
>> - if (INTEL_GEN(engine->i915) >= 11)
>> + if (GRAPHICS_VER(engine->i915) >= 11)
>> *regs |= MI_LRI_LRM_CS_MMIO;
>> regs++;
>>
>> @@ -70,7 +70,7 @@ static void set_offsets(u32 *regs,
>> if (close) {
>> /* Close the batch; used mainly by live_lrc_layout() */
>> *regs = MI_BATCH_BUFFER_END;
>> - if (INTEL_GEN(engine->i915) >= 10)
>> + if (GRAPHICS_VER(engine->i915) >= 10)
>> *regs |= BIT(0);
>> }
>> }
>> @@ -498,22 +498,22 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
>> * addressing to automatic fixup the register state between the
>> * physical engines for virtual engine.
>> */
>> - GEM_BUG_ON(INTEL_GEN(engine->i915) >= 12 &&
>> + GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
>> !intel_engine_has_relative_mmio(engine));
>>
>> if (engine->class == RENDER_CLASS) {
>> - if (INTEL_GEN(engine->i915) >= 12)
>> + if (GRAPHICS_VER(engine->i915) >= 12)
>> return gen12_rcs_offsets;
>> - else if (INTEL_GEN(engine->i915) >= 11)
>> + else if (GRAPHICS_VER(engine->i915) >= 11)
>> return gen11_rcs_offsets;
>> - else if (INTEL_GEN(engine->i915) >= 9)
>> + else if (GRAPHICS_VER(engine->i915) >= 9)
>> return gen9_rcs_offsets;
>> else
>> return gen8_rcs_offsets;
>> } else {
>> - if (INTEL_GEN(engine->i915) >= 12)
>> + if (GRAPHICS_VER(engine->i915) >= 12)
>> return gen12_xcs_offsets;
>> - else if (INTEL_GEN(engine->i915) >= 9)
>> + else if (GRAPHICS_VER(engine->i915) >= 9)
>> return gen9_xcs_offsets;
>> else
>> return gen8_xcs_offsets;
>> @@ -522,9 +522,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
>>
>> static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
>> {
>> - if (INTEL_GEN(engine->i915) >= 12)
>> + if (GRAPHICS_VER(engine->i915) >= 12)
>> return 0x60;
>> - else if (INTEL_GEN(engine->i915) >= 9)
>> + else if (GRAPHICS_VER(engine->i915) >= 9)
>> return 0x54;
>> else if (engine->class == RENDER_CLASS)
>> return 0x58;
>> @@ -534,9 +534,9 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
>>
>> static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
>> {
>> - if (INTEL_GEN(engine->i915) >= 12)
>> + if (GRAPHICS_VER(engine->i915) >= 12)
>> return 0x74;
>> - else if (INTEL_GEN(engine->i915) >= 9)
>> + else if (GRAPHICS_VER(engine->i915) >= 9)
>> return 0x68;
>> else if (engine->class == RENDER_CLASS)
>> return 0xd8;
>> @@ -546,9 +546,9 @@ static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
>>
>> static int lrc_ring_wa_bb_per_ctx(const struct intel_engine_cs *engine)
>> {
>> - if (INTEL_GEN(engine->i915) >= 12)
>> + if (GRAPHICS_VER(engine->i915) >= 12)
>> return 0x12;
>> - else if (INTEL_GEN(engine->i915) >= 9 || engine->class == RENDER_CLASS)
>> + else if (GRAPHICS_VER(engine->i915) >= 9 || engine->class == RENDER_CLASS)
>> return 0x18;
>> else
>> return -1;
>> @@ -581,9 +581,9 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
>> if (engine->class != RENDER_CLASS)
>> return -1;
>>
>> - if (INTEL_GEN(engine->i915) >= 12)
>> + if (GRAPHICS_VER(engine->i915) >= 12)
>> return 0xb6;
>> - else if (INTEL_GEN(engine->i915) >= 11)
>> + else if (GRAPHICS_VER(engine->i915) >= 11)
>> return 0xaa;
>> else
>> return -1;
>> @@ -592,9 +592,9 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
>> static u32
>> lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
>> {
>> - switch (INTEL_GEN(engine->i915)) {
>> + switch (GRAPHICS_VER(engine->i915)) {
>> default:
>> - MISSING_CASE(INTEL_GEN(engine->i915));
>> + MISSING_CASE(GRAPHICS_VER(engine->i915));
>> fallthrough;
>> case 12:
>> return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
>> @@ -637,7 +637,7 @@ static void init_common_regs(u32 * const regs,
>> ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
>> if (inhibit)
>> ctl |= CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT;
>> - if (INTEL_GEN(engine->i915) < 11)
>> + if (GRAPHICS_VER(engine->i915) < 11)
>> ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
>> CTX_CTRL_RS_CTX_ENABLE);
>> regs[CTX_CONTEXT_CONTROL] = ctl;
>> @@ -805,7 +805,7 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
>> if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
>> context_size += I915_GTT_PAGE_SIZE; /* for redzone */
>>
>> - if (INTEL_GEN(engine->i915) == 12) {
>> + if (GRAPHICS_VER(engine->i915) == 12) {
>> ce->wa_bb_page = context_size / PAGE_SIZE;
>> context_size += PAGE_SIZE;
>> }
>> @@ -1114,7 +1114,7 @@ static u32 lrc_descriptor(const struct intel_context *ce)
>> desc <<= GEN8_CTX_ADDRESSING_MODE_SHIFT;
>>
>> desc |= GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
>> - if (IS_GEN(ce->vm->i915, 8))
>> + if (GRAPHICS_VER(ce->vm->i915) == 8)
>> desc |= GEN8_CTX_L3LLC_COHERENT;
>>
>> return i915_ggtt_offset(ce->state) | desc;
>> @@ -1469,7 +1469,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
>> if (engine->class != RENDER_CLASS)
>> return;
>>
>> - switch (INTEL_GEN(engine->i915)) {
>> + switch (GRAPHICS_VER(engine->i915)) {
>> case 12:
>> case 11:
>> return;
>> @@ -1486,7 +1486,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
>> wa_bb_fn[1] = NULL;
>> break;
>> default:
>> - MISSING_CASE(INTEL_GEN(engine->i915));
>> + MISSING_CASE(GRAPHICS_VER(engine->i915));
>> return;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
>> index b14138fd505c..17848807f111 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
>> @@ -344,11 +344,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>> table->size = ARRAY_SIZE(dg1_mocs_table);
>> table->table = dg1_mocs_table;
>> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>> - } else if (INTEL_GEN(i915) >= 12) {
>> + } else if (GRAPHICS_VER(i915) >= 12) {
>> table->size = ARRAY_SIZE(tgl_mocs_table);
>> table->table = tgl_mocs_table;
>> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>> - } else if (IS_GEN(i915, 11)) {
>> + } else if (GRAPHICS_VER(i915) == 11) {
>> table->size = ARRAY_SIZE(icl_mocs_table);
>> table->table = icl_mocs_table;
>> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>> @@ -361,7 +361,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>> table->table = broxton_mocs_table;
>> } else {
>> - drm_WARN_ONCE(&i915->drm, INTEL_GEN(i915) >= 9,
>> + drm_WARN_ONCE(&i915->drm, GRAPHICS_VER(i915) >= 9,
>> "Platform that should have a MOCS table does not.\n");
>> return 0;
>> }
>> @@ -370,7 +370,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>> return 0;
>>
>> /* WaDisableSkipCaching:skl,bxt,kbl,glk */
>> - if (IS_GEN(i915, 9)) {
>> + if (GRAPHICS_VER(i915) == 9) {
>> int i;
>>
>> for (i = 0; i < table->size; i++)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>> index 4e3d80c2295c..3891c078906e 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>> @@ -146,9 +146,9 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
>>
>> gtt_write_workarounds(gt);
>>
>> - if (IS_GEN(i915, 6))
>> + if (GRAPHICS_VER(i915) == 6)
>> gen6_ppgtt_enable(gt);
>> - else if (IS_GEN(i915, 7))
>> + else if (GRAPHICS_VER(i915) == 7)
>> gen7_ppgtt_enable(gt);
>>
>> return 0;
>> @@ -157,7 +157,7 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
>> static struct i915_ppgtt *
>> __ppgtt_create(struct intel_gt *gt)
>> {
>> - if (INTEL_GEN(gt->i915) < 8)
>> + if (GRAPHICS_VER(gt->i915) < 8)
>> return gen6_ppgtt_create(gt);
>> else
>> return gen8_ppgtt_create(gt);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
>> index 3b7e62debe7e..259d7eb4e165 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>> @@ -109,7 +109,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
>> GEN9_MEDIA_PG_ENABLE |
>> GEN11_MEDIA_SAMPLER_PG_ENABLE;
>>
>> - if (INTEL_GEN(gt->i915) >= 12) {
>> + if (GRAPHICS_VER(gt->i915) >= 12) {
>> for (i = 0; i < I915_MAX_VCS; i++)
>> if (HAS_ENGINE(gt, _VCS(i)))
>> pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
>> @@ -126,7 +126,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
>> enum intel_engine_id id;
>>
>> /* 2b: Program RC6 thresholds.*/
>> - if (INTEL_GEN(rc6_to_i915(rc6)) >= 10) {
>> + if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 10) {
>> set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
>> set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
>> } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
>> @@ -249,9 +249,9 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
>> rc6vids = 0;
>> ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
>> &rc6vids, NULL);
>> - if (IS_GEN(i915, 6) && ret) {
>> + if (GRAPHICS_VER(i915) == 6 && ret) {
>> drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
>> - } else if (IS_GEN(i915, 6) &&
>> + } else if (GRAPHICS_VER(i915) == 6 &&
>> (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
>> drm_dbg(&i915->drm,
>> "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
>> @@ -515,7 +515,7 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
>> struct intel_uncore *uncore = rc6_to_uncore(rc6);
>>
>> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>> - if (INTEL_GEN(i915) >= 9)
>> + if (GRAPHICS_VER(i915) >= 9)
>> set(uncore, GEN9_PG_ENABLE, 0);
>> set(uncore, GEN6_RC_CONTROL, 0);
>> set(uncore, GEN6_RC_STATE, 0);
>> @@ -575,13 +575,13 @@ void intel_rc6_enable(struct intel_rc6 *rc6)
>> chv_rc6_enable(rc6);
>> else if (IS_VALLEYVIEW(i915))
>> vlv_rc6_enable(rc6);
>> - else if (INTEL_GEN(i915) >= 11)
>> + else if (GRAPHICS_VER(i915) >= 11)
>> gen11_rc6_enable(rc6);
>> - else if (INTEL_GEN(i915) >= 9)
>> + else if (GRAPHICS_VER(i915) >= 9)
>> gen9_rc6_enable(rc6);
>> else if (IS_BROADWELL(i915))
>> gen8_rc6_enable(rc6);
>> - else if (INTEL_GEN(i915) >= 6)
>> + else if (GRAPHICS_VER(i915) >= 6)
>> gen6_rc6_enable(rc6);
>>
>> rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
>> index b03e197b1d99..b575cd6e0b7a 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
>> @@ -15,7 +15,7 @@ render_state_get_rodata(const struct intel_engine_cs *engine)
>> if (engine->class != RENDER_CLASS)
>> return NULL;
>>
>> - switch (INTEL_GEN(engine->i915)) {
>> + switch (GRAPHICS_VER(engine->i915)) {
>> case 6:
>> return &gen6_null_state;
>> case 7:
>> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
>> index d5094be6d90f..27315d7f8935 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>> @@ -565,7 +565,7 @@ static int gen8_reset_engines(struct intel_gt *gt,
>> */
>> }
>>
>> - if (INTEL_GEN(gt->i915) >= 11)
>> + if (GRAPHICS_VER(gt->i915) >= 11)
>> ret = gen11_reset_engines(gt, engine_mask, retry);
>> else
>> ret = gen6_reset_engines(gt, engine_mask, retry);
>> @@ -594,17 +594,17 @@ static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
>>
>> if (is_mock_gt(gt))
>> return mock_reset;
>> - else if (INTEL_GEN(i915) >= 8)
>> + else if (GRAPHICS_VER(i915) >= 8)
>> return gen8_reset_engines;
>> - else if (INTEL_GEN(i915) >= 6)
>> + else if (GRAPHICS_VER(i915) >= 6)
>> return gen6_reset_engines;
>> - else if (INTEL_GEN(i915) >= 5)
>> + else if (GRAPHICS_VER(i915) >= 5)
>> return ilk_do_reset;
>> else if (IS_G4X(i915))
>> return g4x_do_reset;
>> else if (IS_G33(i915) || IS_PINEVIEW(i915))
>> return g33_do_reset;
>> - else if (INTEL_GEN(i915) >= 3)
>> + else if (GRAPHICS_VER(i915) >= 3)
>> return i915_do_reset;
>> else
>> return NULL;
>> @@ -656,7 +656,7 @@ bool intel_has_reset_engine(const struct intel_gt *gt)
>> int intel_reset_guc(struct intel_gt *gt)
>> {
>> u32 guc_domain =
>> - INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
>> + GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
>> int ret;
>>
>> GEM_BUG_ON(!HAS_GT_UC(gt->i915));
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> index 2b6dffcc2262..0c423f096e2b 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> @@ -29,7 +29,7 @@ static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
>> * lost interrupts following a reset.
>> */
>> if (engine->class == RENDER_CLASS) {
>> - if (INTEL_GEN(engine->i915) >= 6)
>> + if (GRAPHICS_VER(engine->i915) >= 6)
>> mask &= ~BIT(0);
>> else
>> mask &= ~I915_USER_INTERRUPT;
>> @@ -43,7 +43,7 @@ static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
>> u32 addr;
>>
>> addr = lower_32_bits(phys);
>> - if (INTEL_GEN(engine->i915) >= 4)
>> + if (GRAPHICS_VER(engine->i915) >= 4)
>> addr |= (phys >> 28) & 0xf0;
>>
>> intel_uncore_write(engine->uncore, HWS_PGA, addr);
>> @@ -71,7 +71,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
>> * The ring status page addresses are no longer next to the rest of
>> * the ring registers as of gen7.
>> */
>> - if (IS_GEN(engine->i915, 7)) {
>> + if (GRAPHICS_VER(engine->i915) == 7) {
>> switch (engine->id) {
>> /*
>> * No more rings exist on Gen7. Default case is only to shut up
>> @@ -93,7 +93,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
>> hwsp = VEBOX_HWS_PGA_GEN7;
>> break;
>> }
>> - } else if (IS_GEN(engine->i915, 6)) {
>> + } else if (GRAPHICS_VER(engine->i915) == 6) {
>> hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
>> } else {
>> hwsp = RING_HWS_PGA(engine->mmio_base);
>> @@ -105,7 +105,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
>>
>> static void flush_cs_tlb(struct intel_engine_cs *engine)
>> {
>> - if (!IS_GEN_RANGE(engine->i915, 6, 7))
>> + if (!IS_GRAPHICS_VER(engine->i915, 6, 7))
>> return;
>>
>> /* ring should be idle before issuing a sync flush*/
>> @@ -153,7 +153,7 @@ static void set_pp_dir(struct intel_engine_cs *engine)
>> ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
>> ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm));
>>
>> - if (INTEL_GEN(engine->i915) >= 7) {
>> + if (GRAPHICS_VER(engine->i915) >= 7) {
>> ENGINE_WRITE_FW(engine,
>> RING_MODE_GEN7,
>> _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
>> @@ -229,7 +229,7 @@ static int xcs_resume(struct intel_engine_cs *engine)
>> 5000, 0, NULL))
>> goto err;
>>
>> - if (INTEL_GEN(engine->i915) > 2)
>> + if (GRAPHICS_VER(engine->i915) > 2)
>> ENGINE_WRITE_FW(engine,
>> RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
>>
>> @@ -646,9 +646,9 @@ static int mi_set_context(struct i915_request *rq,
>> u32 *cs;
>>
>> len = 4;
>> - if (IS_GEN(i915, 7))
>> + if (GRAPHICS_VER(i915) == 7)
>> len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
>> - else if (IS_GEN(i915, 5))
>> + else if (GRAPHICS_VER(i915) == 5)
>> len += 2;
>> if (flags & MI_FORCE_RESTORE) {
>> GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
>> @@ -662,7 +662,7 @@ static int mi_set_context(struct i915_request *rq,
>> return PTR_ERR(cs);
>>
>> /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
>> - if (IS_GEN(i915, 7)) {
>> + if (GRAPHICS_VER(i915) == 7) {
>> *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
>> if (num_engines) {
>> struct intel_engine_cs *signaller;
>> @@ -678,7 +678,7 @@ static int mi_set_context(struct i915_request *rq,
>> GEN6_PSMI_SLEEP_MSG_DISABLE);
>> }
>> }
>> - } else if (IS_GEN(i915, 5)) {
>> + } else if (GRAPHICS_VER(i915) == 5) {
>> /*
>> * This w/a is only listed for pre-production ilk a/b steppings,
>> * but is also mentioned for programming the powerctx. To be
>> @@ -716,7 +716,7 @@ static int mi_set_context(struct i915_request *rq,
>> */
>> *cs++ = MI_NOOP;
>>
>> - if (IS_GEN(i915, 7)) {
>> + if (GRAPHICS_VER(i915) == 7) {
>> if (num_engines) {
>> struct intel_engine_cs *signaller;
>> i915_reg_t last_reg = {}; /* keep gcc quiet */
>> @@ -740,7 +740,7 @@ static int mi_set_context(struct i915_request *rq,
>> *cs++ = MI_NOOP;
>> }
>> *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
>> - } else if (IS_GEN(i915, 5)) {
>> + } else if (GRAPHICS_VER(i915) == 5) {
>> *cs++ = MI_SUSPEND_FLUSH;
>> }
>>
>> @@ -1001,7 +1001,7 @@ static void ring_release(struct intel_engine_cs *engine)
>> {
>> struct drm_i915_private *dev_priv = engine->i915;
>>
>> - drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) > 2 &&
>> + drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) > 2 &&
>> (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
>>
>> intel_engine_cleanup_common(engine);
>> @@ -1029,13 +1029,13 @@ static void setup_irq(struct intel_engine_cs *engine)
>>
>> intel_engine_set_irq_handler(engine, irq_handler);
>>
>> - if (INTEL_GEN(i915) >= 6) {
>> + if (GRAPHICS_VER(i915) >= 6) {
>> engine->irq_enable = gen6_irq_enable;
>> engine->irq_disable = gen6_irq_disable;
>> - } else if (INTEL_GEN(i915) >= 5) {
>> + } else if (GRAPHICS_VER(i915) >= 5) {
>> engine->irq_enable = gen5_irq_enable;
>> engine->irq_disable = gen5_irq_disable;
>> - } else if (INTEL_GEN(i915) >= 3) {
>> + } else if (GRAPHICS_VER(i915) >= 3) {
>> engine->irq_enable = gen3_irq_enable;
>> engine->irq_disable = gen3_irq_disable;
>> } else {
>> @@ -1049,7 +1049,7 @@ static void setup_common(struct intel_engine_cs *engine)
>> struct drm_i915_private *i915 = engine->i915;
>>
>> /* gen8+ are only supported with execlists */
>> - GEM_BUG_ON(INTEL_GEN(i915) >= 8);
>> + GEM_BUG_ON(GRAPHICS_VER(i915) >= 8);
>>
>> setup_irq(engine);
>>
>> @@ -1070,14 +1070,14 @@ static void setup_common(struct intel_engine_cs *engine)
>> * engine->emit_init_breadcrumb().
>> */
>> engine->emit_fini_breadcrumb = gen3_emit_breadcrumb;
>> - if (IS_GEN(i915, 5))
>> + if (GRAPHICS_VER(i915) == 5)
>> engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
>>
>> engine->set_default_submission = i9xx_set_default_submission;
>>
>> - if (INTEL_GEN(i915) >= 6)
>> + if (GRAPHICS_VER(i915) >= 6)
>> engine->emit_bb_start = gen6_emit_bb_start;
>> - else if (INTEL_GEN(i915) >= 4)
>> + else if (GRAPHICS_VER(i915) >= 4)
>> engine->emit_bb_start = gen4_emit_bb_start;
>> else if (IS_I830(i915) || IS_I845G(i915))
>> engine->emit_bb_start = i830_emit_bb_start;
>> @@ -1094,16 +1094,16 @@ static void setup_rcs(struct intel_engine_cs *engine)
>>
>> engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
>>
>> - if (INTEL_GEN(i915) >= 7) {
>> + if (GRAPHICS_VER(i915) >= 7) {
>> engine->emit_flush = gen7_emit_flush_rcs;
>> engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs;
>> - } else if (IS_GEN(i915, 6)) {
>> + } else if (GRAPHICS_VER(i915) == 6) {
>> engine->emit_flush = gen6_emit_flush_rcs;
>> engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs;
>> - } else if (IS_GEN(i915, 5)) {
>> + } else if (GRAPHICS_VER(i915) == 5) {
>> engine->emit_flush = gen4_emit_flush_rcs;
>> } else {
>> - if (INTEL_GEN(i915) < 4)
>> + if (GRAPHICS_VER(i915) < 4)
>> engine->emit_flush = gen2_emit_flush;
>> else
>> engine->emit_flush = gen4_emit_flush_rcs;
>> @@ -1118,20 +1118,20 @@ static void setup_vcs(struct intel_engine_cs *engine)
>> {
>> struct drm_i915_private *i915 = engine->i915;
>>
>> - if (INTEL_GEN(i915) >= 6) {
>> + if (GRAPHICS_VER(i915) >= 6) {
>> /* gen6 bsd needs a special wa for tail updates */
>> - if (IS_GEN(i915, 6))
>> + if (GRAPHICS_VER(i915) == 6)
>> engine->set_default_submission = gen6_bsd_set_default_submission;
>> engine->emit_flush = gen6_emit_flush_vcs;
>> engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
>>
>> - if (IS_GEN(i915, 6))
>> + if (GRAPHICS_VER(i915) == 6)
>> engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
>> else
>> engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
>> } else {
>> engine->emit_flush = gen4_emit_flush_vcs;
>> - if (IS_GEN(i915, 5))
>> + if (GRAPHICS_VER(i915) == 5)
>> engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
>> else
>> engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
>> @@ -1145,7 +1145,7 @@ static void setup_bcs(struct intel_engine_cs *engine)
>> engine->emit_flush = gen6_emit_flush_xcs;
>> engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
>>
>> - if (IS_GEN(i915, 6))
>> + if (GRAPHICS_VER(i915) == 6)
>> engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
>> else
>> engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
>> @@ -1155,7 +1155,7 @@ static void setup_vecs(struct intel_engine_cs *engine)
>> {
>> struct drm_i915_private *i915 = engine->i915;
>>
>> - GEM_BUG_ON(INTEL_GEN(i915) < 7);
>> + GEM_BUG_ON(GRAPHICS_VER(i915) < 7);
>>
>> engine->emit_flush = gen6_emit_flush_xcs;
>> engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
>> @@ -1203,7 +1203,7 @@ static struct i915_vma *gen7_ctx_vma(struct intel_engine_cs *engine)
>> struct i915_vma *vma;
>> int size, err;
>>
>> - if (!IS_GEN(engine->i915, 7) || engine->class != RENDER_CLASS)
>> + if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS)
>> return 0;
>>
>> err = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
>> index 97cab1b99871..06e9a8ed4e03 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
>> @@ -196,7 +196,7 @@ static void rps_reset_interrupts(struct intel_rps *rps)
>> struct intel_gt *gt = rps_to_gt(rps);
>>
>> spin_lock_irq(>->irq_lock);
>> - if (INTEL_GEN(gt->i915) >= 11)
>> + if (GRAPHICS_VER(gt->i915) >= 11)
>> gen11_rps_reset_interrupts(rps);
>> else
>> gen6_rps_reset_interrupts(rps);
>> @@ -630,7 +630,7 @@ static u32 rps_limits(struct intel_rps *rps, u8 val)
>> * frequency, if the down threshold expires in that window we will not
>> * receive a down interrupt.
>> */
>> - if (INTEL_GEN(rps_to_i915(rps)) >= 9) {
>> + if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) {
>> limits = rps->max_freq_softlimit << 23;
>> if (val <= rps->min_freq_softlimit)
>> limits |= rps->min_freq_softlimit << 14;
>> @@ -697,7 +697,7 @@ static void rps_set_power(struct intel_rps *rps, int new_power)
>> intel_gt_ns_to_pm_interval(gt, ei_down * threshold_down * 10));
>>
>> set(uncore, GEN6_RP_CONTROL,
>> - (INTEL_GEN(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
>> + (GRAPHICS_VER(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
>> GEN6_RP_MEDIA_HW_NORMAL_MODE |
>> GEN6_RP_MEDIA_IS_GFX |
>> GEN6_RP_ENABLE |
>> @@ -771,7 +771,7 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val)
>> struct drm_i915_private *i915 = rps_to_i915(rps);
>> u32 swreq;
>>
>> - if (INTEL_GEN(i915) >= 9)
>> + if (GRAPHICS_VER(i915) >= 9)
>> swreq = GEN9_FREQUENCY(val);
>> else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
>> swreq = HSW_FREQUENCY(val);
>> @@ -812,14 +812,14 @@ static int rps_set(struct intel_rps *rps, u8 val, bool update)
>>
>> if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
>> err = vlv_rps_set(rps, val);
>> - else if (INTEL_GEN(i915) >= 6)
>> + else if (GRAPHICS_VER(i915) >= 6)
>> err = gen6_rps_set(rps, val);
>> else
>> err = gen5_rps_set(rps, val);
>> if (err)
>> return err;
>>
>> - if (update && INTEL_GEN(i915) >= 6)
>> + if (update && GRAPHICS_VER(i915) >= 6)
>> gen6_rps_set_thresholds(rps, val);
>> rps->last_freq = val;
>>
>> @@ -853,7 +853,7 @@ void intel_rps_unpark(struct intel_rps *rps)
>> if (intel_rps_uses_timer(rps))
>> rps_start_timer(rps);
>>
>> - if (IS_GEN(rps_to_i915(rps), 5))
>> + if (GRAPHICS_VER(rps_to_i915(rps)) == 5)
>> gen5_rps_update(rps);
>> }
>>
>> @@ -999,7 +999,7 @@ static void gen6_rps_init(struct intel_rps *rps)
>>
>> rps->efficient_freq = rps->rp1_freq;
>> if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
>> - IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
>> + IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
>> u32 ddcc_status = 0;
>>
>> if (sandybridge_pcode_read(i915,
>> @@ -1012,7 +1012,7 @@ static void gen6_rps_init(struct intel_rps *rps)
>> rps->max_freq);
>> }
>>
>> - if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
>> + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
>> /* Store the frequency values in 16.66 MHZ units, which is
>> * the natural hardware unit for SKL
>> */
>> @@ -1048,7 +1048,7 @@ static bool gen9_rps_enable(struct intel_rps *rps)
>> struct intel_uncore *uncore = gt->uncore;
>>
>> /* Program defaults and thresholds for RPS */
>> - if (IS_GEN(gt->i915, 9))
>> + if (GRAPHICS_VER(gt->i915) == 9)
>> intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ,
>> GEN9_FREQUENCY(rps->rp1_freq));
>>
>> @@ -1365,16 +1365,16 @@ void intel_rps_enable(struct intel_rps *rps)
>> enabled = chv_rps_enable(rps);
>> else if (IS_VALLEYVIEW(i915))
>> enabled = vlv_rps_enable(rps);
>> - else if (INTEL_GEN(i915) >= 9)
>> + else if (GRAPHICS_VER(i915) >= 9)
>> enabled = gen9_rps_enable(rps);
>> - else if (INTEL_GEN(i915) >= 8)
>> + else if (GRAPHICS_VER(i915) >= 8)
>> enabled = gen8_rps_enable(rps);
>> - else if (INTEL_GEN(i915) >= 6)
>> + else if (GRAPHICS_VER(i915) >= 6)
>> enabled = gen6_rps_enable(rps);
>> else if (IS_IRONLAKE_M(i915))
>> enabled = gen5_rps_enable(rps);
>> else
>> - MISSING_CASE(INTEL_GEN(i915));
>> + MISSING_CASE(GRAPHICS_VER(i915));
>> intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>> if (!enabled)
>> return;
>> @@ -1393,7 +1393,7 @@ void intel_rps_enable(struct intel_rps *rps)
>>
>> if (has_busy_stats(rps))
>> intel_rps_set_timer(rps);
>> - else if (INTEL_GEN(i915) >= 6)
>> + else if (GRAPHICS_VER(i915) >= 6)
>> intel_rps_set_interrupts(rps);
>> else
>> /* Ironlake currently uses intel_ips.ko */ {}
>> @@ -1414,7 +1414,7 @@ void intel_rps_disable(struct intel_rps *rps)
>> intel_rps_clear_interrupts(rps);
>> intel_rps_clear_timer(rps);
>>
>> - if (INTEL_GEN(i915) >= 6)
>> + if (GRAPHICS_VER(i915) >= 6)
>> gen6_rps_disable(rps);
>> else if (IS_IRONLAKE_M(i915))
>> gen5_rps_disable(rps);
>> @@ -1453,14 +1453,14 @@ int intel_gpu_freq(struct intel_rps *rps, int val)
>> {
>> struct drm_i915_private *i915 = rps_to_i915(rps);
>>
>> - if (INTEL_GEN(i915) >= 9)
>> + if (GRAPHICS_VER(i915) >= 9)
>> return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
>> GEN9_FREQ_SCALER);
>> else if (IS_CHERRYVIEW(i915))
>> return chv_gpu_freq(rps, val);
>> else if (IS_VALLEYVIEW(i915))
>> return byt_gpu_freq(rps, val);
>> - else if (INTEL_GEN(i915) >= 6)
>> + else if (GRAPHICS_VER(i915) >= 6)
>> return val * GT_FREQUENCY_MULTIPLIER;
>> else
>> return val;
>> @@ -1470,14 +1470,14 @@ int intel_freq_opcode(struct intel_rps *rps, int val)
>> {
>> struct drm_i915_private *i915 = rps_to_i915(rps);
>>
>> - if (INTEL_GEN(i915) >= 9)
>> + if (GRAPHICS_VER(i915) >= 9)
>> return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
>> GT_FREQUENCY_MULTIPLIER);
>> else if (IS_CHERRYVIEW(i915))
>> return chv_freq_opcode(rps, val);
>> else if (IS_VALLEYVIEW(i915))
>> return byt_freq_opcode(rps, val);
>> - else if (INTEL_GEN(i915) >= 6)
>> + else if (GRAPHICS_VER(i915) >= 6)
>> return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
>> else
>> return val;
>> @@ -1770,7 +1770,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
>> spin_unlock(>->irq_lock);
>> }
>>
>> - if (INTEL_GEN(gt->i915) >= 8)
>> + if (GRAPHICS_VER(gt->i915) >= 8)
>> return;
>>
>> if (pm_iir & PM_VEBOX_USER_INTERRUPT)
>> @@ -1833,7 +1833,7 @@ void intel_rps_init(struct intel_rps *rps)
>> chv_rps_init(rps);
>> else if (IS_VALLEYVIEW(i915))
>> vlv_rps_init(rps);
>> - else if (INTEL_GEN(i915) >= 6)
>> + else if (GRAPHICS_VER(i915) >= 6)
>> gen6_rps_init(rps);
>> else if (IS_IRONLAKE_M(i915))
>> gen5_rps_init(rps);
>> @@ -1843,7 +1843,7 @@ void intel_rps_init(struct intel_rps *rps)
>> rps->min_freq_softlimit = rps->min_freq;
>>
>> /* After setting max-softlimit, find the overclock max freq */
>> - if (IS_GEN(i915, 6) || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
>> + if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
>> u32 params = 0;
>>
>> sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS,
>> @@ -1872,16 +1872,16 @@ void intel_rps_init(struct intel_rps *rps)
>> *
>> * TODO: verify if this can be reproduced on VLV,CHV.
>> */
>> - if (INTEL_GEN(i915) <= 7)
>> + if (GRAPHICS_VER(i915) <= 7)
>> rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
>>
>> - if (INTEL_GEN(i915) >= 8 && INTEL_GEN(i915) < 11)
>> + if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) < 11)
>> rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
>> }
>>
>> void intel_rps_sanitize(struct intel_rps *rps)
>> {
>> - if (INTEL_GEN(rps_to_i915(rps)) >= 6)
>> + if (GRAPHICS_VER(rps_to_i915(rps)) >= 6)
>> rps_disable_interrupts(rps);
>> }
>>
>> @@ -1892,11 +1892,11 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
>>
>> if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
>> cagf = (rpstat >> 8) & 0xff;
>> - else if (INTEL_GEN(i915) >= 9)
>> + else if (GRAPHICS_VER(i915) >= 9)
>> cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
>> else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
>> cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
>> - else if (INTEL_GEN(i915) >= 6)
>> + else if (GRAPHICS_VER(i915) >= 6)
>> cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
>> else
>> cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >>
>> @@ -1915,7 +1915,7 @@ static u32 read_cagf(struct intel_rps *rps)
>> vlv_punit_get(i915);
>> freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
>> vlv_punit_put(i915);
>> - } else if (INTEL_GEN(i915) >= 6) {
>> + } else if (GRAPHICS_VER(i915) >= 6) {
>> freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
>> } else {
>> freq = intel_uncore_read(uncore, MEMSTAT_ILK);
>> @@ -1968,7 +1968,7 @@ void intel_rps_driver_register(struct intel_rps *rps)
>> * We only register the i915 ips part with intel-ips once everything is
>> * set up, to avoid intel-ips sneaking in and reading bogus values.
>> */
>> - if (IS_GEN(gt->i915, 5)) {
>> + if (GRAPHICS_VER(gt->i915) == 5) {
>> GEM_BUG_ON(ips_mchdev);
>> rcu_assign_pointer(ips_mchdev, gt->i915);
>> ips_ping_for_i915_load();
>> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
>> index 0d9f74aec8fe..367fd44b81c8 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
>> @@ -590,13 +590,13 @@ void intel_sseu_info_init(struct intel_gt *gt)
>> cherryview_sseu_info_init(gt);
>> else if (IS_BROADWELL(i915))
>> bdw_sseu_info_init(gt);
>> - else if (IS_GEN(i915, 9))
>> + else if (GRAPHICS_VER(i915) == 9)
>> gen9_sseu_info_init(gt);
>> - else if (IS_GEN(i915, 10))
>> + else if (GRAPHICS_VER(i915) == 10)
>> gen10_sseu_info_init(gt);
>> - else if (IS_GEN(i915, 11))
>> + else if (GRAPHICS_VER(i915) == 11)
>> gen11_sseu_info_init(gt);
>> - else if (INTEL_GEN(i915) >= 12)
>> + else if (GRAPHICS_VER(i915) >= 12)
>> gen12_sseu_info_init(gt);
>> }
>>
>> @@ -613,7 +613,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
>> * No explicit RPCS request is needed to ensure full
>> * slice/subslice/EU enablement prior to Gen9.
>> */
>> - if (INTEL_GEN(i915) < 9)
>> + if (GRAPHICS_VER(i915) < 9)
>> return 0;
>>
>> /*
>> @@ -651,7 +651,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
>> * subslices are enabled, or a count between one and four on the first
>> * slice.
>> */
>> - if (IS_GEN(i915, 11) &&
>> + if (GRAPHICS_VER(i915) == 11 &&
>> slices == 1 &&
>> subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
>> GEM_BUG_ON(subslices & 1);
>> @@ -669,7 +669,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
>> if (sseu->has_slice_pg) {
>> u32 mask, val = slices;
>>
>> - if (INTEL_GEN(i915) >= 11) {
>> + if (GRAPHICS_VER(i915) >= 11) {
>> mask = GEN11_RPCS_S_CNT_MASK;
>> val <<= GEN11_RPCS_S_CNT_SHIFT;
>> } else {
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 62cb9ee5bfc3..b62d1e31a645 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -699,9 +699,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>>
>> if (IS_DG1(i915))
>> dg1_ctx_workarounds_init(engine, wal);
>> - else if (IS_GEN(i915, 12))
>> + else if (GRAPHICS_VER(i915) == 12)
>> gen12_ctx_workarounds_init(engine, wal);
>> - else if (IS_GEN(i915, 11))
>> + else if (GRAPHICS_VER(i915) == 11)
>> icl_ctx_workarounds_init(engine, wal);
>> else if (IS_CANNONLAKE(i915))
>> cnl_ctx_workarounds_init(engine, wal);
>> @@ -719,14 +719,14 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>> chv_ctx_workarounds_init(engine, wal);
>> else if (IS_BROADWELL(i915))
>> bdw_ctx_workarounds_init(engine, wal);
>> - else if (IS_GEN(i915, 7))
>> + else if (GRAPHICS_VER(i915) == 7)
>> gen7_ctx_workarounds_init(engine, wal);
>> - else if (IS_GEN(i915, 6))
>> + else if (GRAPHICS_VER(i915) == 6)
>> gen6_ctx_workarounds_init(engine, wal);
>> - else if (INTEL_GEN(i915) < 8)
>> + else if (GRAPHICS_VER(i915) < 8)
>> ;
>> else
>> - MISSING_CASE(INTEL_GEN(i915));
>> + MISSING_CASE(GRAPHICS_VER(i915));
>>
>> wa_init_finish(wal);
>> }
>> @@ -950,7 +950,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> unsigned int slice, subslice;
>> u32 l3_en, mcr, mcr_mask;
>>
>> - GEM_BUG_ON(INTEL_GEN(i915) < 10);
>> + GEM_BUG_ON(GRAPHICS_VER(i915) < 10);
>>
>> /*
>> * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
>> @@ -980,7 +980,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> * of every MMIO read.
>> */
>>
>> - if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
>> + if (GRAPHICS_VER(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
>> u32 l3_fuse =
>> intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
>> GEN10_L3BANK_MASK;
>> @@ -1002,7 +1002,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> }
>> subslice--;
>>
>> - if (INTEL_GEN(i915) >= 11) {
>> + if (GRAPHICS_VER(i915) >= 11) {
>> mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
>> mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
>> } else {
>> @@ -1171,9 +1171,9 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> dg1_gt_workarounds_init(i915, wal);
>> else if (IS_TIGERLAKE(i915))
>> tgl_gt_workarounds_init(i915, wal);
>> - else if (IS_GEN(i915, 12))
>> + else if (GRAPHICS_VER(i915) == 12)
>> gen12_gt_workarounds_init(i915, wal);
>> - else if (IS_GEN(i915, 11))
>> + else if (GRAPHICS_VER(i915) == 11)
>> icl_gt_workarounds_init(i915, wal);
>> else if (IS_CANNONLAKE(i915))
>> cnl_gt_workarounds_init(i915, wal);
>> @@ -1193,18 +1193,18 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> vlv_gt_workarounds_init(i915, wal);
>> else if (IS_IVYBRIDGE(i915))
>> ivb_gt_workarounds_init(i915, wal);
>> - else if (IS_GEN(i915, 6))
>> + else if (GRAPHICS_VER(i915) == 6)
>> snb_gt_workarounds_init(i915, wal);
>> - else if (IS_GEN(i915, 5))
>> + else if (GRAPHICS_VER(i915) == 5)
>> ilk_gt_workarounds_init(i915, wal);
>> else if (IS_G4X(i915))
>> g4x_gt_workarounds_init(i915, wal);
>> - else if (IS_GEN(i915, 4))
>> + else if (GRAPHICS_VER(i915) == 4)
>> gen4_gt_workarounds_init(i915, wal);
>> - else if (INTEL_GEN(i915) <= 8)
>> + else if (GRAPHICS_VER(i915) <= 8)
>> ;
>> else
>> - MISSING_CASE(INTEL_GEN(i915));
>> + MISSING_CASE(GRAPHICS_VER(i915));
>> }
>>
>> void intel_gt_init_workarounds(struct drm_i915_private *i915)
>> @@ -1558,9 +1558,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>>
>> if (IS_DG1(i915))
>> dg1_whitelist_build(engine);
>> - else if (IS_GEN(i915, 12))
>> + else if (GRAPHICS_VER(i915) == 12)
>> tgl_whitelist_build(engine);
>> - else if (IS_GEN(i915, 11))
>> + else if (GRAPHICS_VER(i915) == 11)
>> icl_whitelist_build(engine);
>> else if (IS_CANNONLAKE(i915))
>> cnl_whitelist_build(engine);
>> @@ -1576,10 +1576,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>> bxt_whitelist_build(engine);
>> else if (IS_SKYLAKE(i915))
>> skl_whitelist_build(engine);
>> - else if (INTEL_GEN(i915) <= 8)
>> + else if (GRAPHICS_VER(i915) <= 8)
>> ;
>> else
>> - MISSING_CASE(INTEL_GEN(i915));
>> + MISSING_CASE(GRAPHICS_VER(i915));
>>
>> wa_init_finish(w);
>> }
>> @@ -1695,7 +1695,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> ENABLE_SMALLPL);
>> }
>>
>> - if (IS_GEN(i915, 11)) {
>> + if (GRAPHICS_VER(i915) == 11) {
>> /* This is not an Wa. Enable for better image quality */
>> wa_masked_en(wal,
>> _3D_CHICKEN3,
>> @@ -1793,7 +1793,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> FF_DOP_CLOCK_GATE_DISABLE);
>> }
>>
>> - if (IS_GEN_RANGE(i915, 9, 12)) {
>> + if (IS_GRAPHICS_VER(i915, 9, 12)) {
>> /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
>> wa_masked_en(wal,
>> GEN7_FF_SLICE_CS_CHICKEN1,
>> @@ -1817,7 +1817,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
>> }
>>
>> - if (IS_GEN(i915, 9)) {
>> + if (GRAPHICS_VER(i915) == 9) {
>> /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
>> wa_masked_en(wal,
>> GEN9_CSFE_CHICKEN1_RCS,
>> @@ -1921,7 +1921,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
>> }
>>
>> - if (IS_GEN(i915, 7)) {
>> + if (GRAPHICS_VER(i915) == 7) {
>> /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
>> wa_masked_en(wal,
>> GFX_MODE_GEN7,
>> @@ -1953,7 +1953,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> GEN6_WIZ_HASHING_16x4);
>> }
>>
>> - if (IS_GEN_RANGE(i915, 6, 7))
>> + if (IS_GRAPHICS_VER(i915, 6, 7))
>> /*
>> * We need to disable the AsyncFlip performance optimisations in
>> * order to use MI_WAIT_FOR_EVENT within the CS. It should
>> @@ -1965,7 +1965,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> MI_MODE,
>> ASYNC_FLIP_PERF_DISABLE);
>>
>> - if (IS_GEN(i915, 6)) {
>> + if (GRAPHICS_VER(i915) == 6) {
>> /*
>> * Required for the hardware to program scanline values for
>> * waiting
>> @@ -2019,14 +2019,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> CM0_STC_EVICT_DISABLE_LRA_SNB);
>> }
>>
>> - if (IS_GEN_RANGE(i915, 4, 6))
>> + if (IS_GRAPHICS_VER(i915, 4, 6))
>> /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
>> wa_add(wal, MI_MODE,
>> 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
>> /* XXX bit doesn't stick on Broadwater */
>> IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
>>
>> - if (IS_GEN(i915, 4))
>> + if (GRAPHICS_VER(i915) == 4)
>> /*
>> * Disable CONSTANT_BUFFER before it is loaded from the context
>> * image. For as it is loaded, it is executed and the stored
>> @@ -2058,7 +2058,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> static void
>> engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> {
>> - if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4))
>> + if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4))
>> return;
>>
>> if (engine->class == RENDER_CLASS)
>> @@ -2071,7 +2071,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
>> {
>> struct i915_wa_list *wal = &engine->wa_list;
>>
>> - if (INTEL_GEN(engine->i915) < 4)
>> + if (GRAPHICS_VER(engine->i915) < 4)
>> return;
>>
>> wa_init_start(wal, "engine", engine->name);
>> @@ -2112,9 +2112,9 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
>> const struct mcr_range *mcr_ranges;
>> int i;
>>
>> - if (INTEL_GEN(i915) >= 12)
>> + if (GRAPHICS_VER(i915) >= 12)
>> mcr_ranges = mcr_ranges_gen12;
>> - else if (INTEL_GEN(i915) >= 8)
>> + else if (GRAPHICS_VER(i915) >= 8)
>> mcr_ranges = mcr_ranges_gen8;
>> else
>> return false;
>> @@ -2143,7 +2143,7 @@ wa_list_srm(struct i915_request *rq,
>> u32 srm, *cs;
>>
>> srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
>> - if (INTEL_GEN(i915) >= 8)
>> + if (GRAPHICS_VER(i915) >= 8)
>> srm++;
>>
>> for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>> index 3453eb77c498..64abf5feabfa 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>> @@ -52,7 +52,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
>> return PTR_ERR(cs);
>>
>> cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
>> - if (INTEL_GEN(rq->engine->i915) >= 8)
>> + if (GRAPHICS_VER(rq->engine->i915) >= 8)
>> cmd++;
>> *cs++ = cmd;
>> *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
>> @@ -125,7 +125,7 @@ static int perf_mi_bb_start(void *arg)
>> enum intel_engine_id id;
>> int err = 0;
>>
>> - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
>> + if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
>> return 0;
>>
>> perf_begin(gt);
>> @@ -249,7 +249,7 @@ static int perf_mi_noop(void *arg)
>> enum intel_engine_id id;
>> int err = 0;
>>
>> - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
>> + if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
>> return 0;
>>
>> perf_begin(gt);
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
>> index 2c898622bdfb..72cca3f0da21 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
>> @@ -198,7 +198,7 @@ static int live_engine_timestamps(void *arg)
>> * the same CS clock.
>> */
>>
>> - if (INTEL_GEN(gt->i915) < 8)
>> + if (GRAPHICS_VER(gt->i915) < 8)
>> return 0;
>>
>> for_each_engine(engine, gt, id) {
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
>> index 1f93591a8c69..ea2203af0764 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
>> @@ -3269,7 +3269,7 @@ static int live_preempt_user(void *arg)
>> if (!intel_engine_has_preemption(engine))
>> continue;
>>
>> - if (IS_GEN(gt->i915, 8) && engine->class != RENDER_CLASS)
>> + if (GRAPHICS_VER(gt->i915) == 8 && engine->class != RENDER_CLASS)
>> continue; /* we need per-context GPR */
>>
>> if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {
>> @@ -4293,7 +4293,7 @@ static int live_virtual_preserved(void *arg)
>> return 0;
>>
>> /* As we use CS_GPR we cannot run before they existed on all engines. */
>> - if (INTEL_GEN(gt->i915) < 9)
>> + if (GRAPHICS_VER(gt->i915) < 9)
>> return 0;
>>
>> for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
>> index c0845bf72dd3..b9441217ca3d 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
>> @@ -74,10 +74,10 @@ static int live_gt_clocks(void *arg)
>> return 0;
>> }
>>
>> - if (INTEL_GEN(gt->i915) < 4) /* Any CS_TIMESTAMP? */
>> + if (GRAPHICS_VER(gt->i915) < 4) /* Any CS_TIMESTAMP? */
>> return 0;
>>
>> - if (IS_GEN(gt->i915, 5))
>> + if (GRAPHICS_VER(gt->i915) == 5)
>> /*
>> * XXX CS_TIMESTAMP low dword is dysfunctional?
>> *
>> @@ -86,7 +86,7 @@ static int live_gt_clocks(void *arg)
>> */
>> return 0;
>>
>> - if (IS_GEN(gt->i915, 4))
>> + if (GRAPHICS_VER(gt->i915) == 4)
>> /*
>> * XXX CS_TIMESTAMP appears gibberish
>> *
>> @@ -105,7 +105,7 @@ static int live_gt_clocks(void *arg)
>> u64 time;
>> u64 dt;
>>
>> - if (INTEL_GEN(engine->i915) < 7 && engine->id != RCS0)
>> + if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0)
>> continue;
>>
>> measure_clocks(engine, &cycles, &dt);
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
>> index 5b63d4df8c93..853246fad05f 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
>> @@ -180,7 +180,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>> goto cancel_rq;
>>
>> batch = h->batch;
>> - if (INTEL_GEN(gt->i915) >= 8) {
>> + if (GRAPHICS_VER(gt->i915) >= 8) {
>> *batch++ = MI_STORE_DWORD_IMM_GEN4;
>> *batch++ = lower_32_bits(hws_address(hws, rq));
>> *batch++ = upper_32_bits(hws_address(hws, rq));
>> @@ -194,7 +194,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>> *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
>> *batch++ = lower_32_bits(vma->node.start);
>> *batch++ = upper_32_bits(vma->node.start);
>> - } else if (INTEL_GEN(gt->i915) >= 6) {
>> + } else if (GRAPHICS_VER(gt->i915) >= 6) {
>> *batch++ = MI_STORE_DWORD_IMM_GEN4;
>> *batch++ = 0;
>> *batch++ = lower_32_bits(hws_address(hws, rq));
>> @@ -207,7 +207,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>> *batch++ = MI_NOOP;
>> *batch++ = MI_BATCH_BUFFER_START | 1 << 8;
>> *batch++ = lower_32_bits(vma->node.start);
>> - } else if (INTEL_GEN(gt->i915) >= 4) {
>> + } else if (GRAPHICS_VER(gt->i915) >= 4) {
>> *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> *batch++ = 0;
>> *batch++ = lower_32_bits(hws_address(hws, rq));
>> @@ -243,7 +243,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>> }
>>
>> flags = 0;
>> - if (INTEL_GEN(gt->i915) <= 5)
>> + if (GRAPHICS_VER(gt->i915) <= 5)
>> flags |= I915_DISPATCH_SECURE;
>>
>> err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
>> index 94006f117bbd..459b775f163a 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_llc.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
>> @@ -44,7 +44,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
>> if (found != ia_freq) {
>> pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected CPU freq, found %d, expected %d\n",
>> gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
>> - intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
>> + intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
>> found, ia_freq);
>> err = -EINVAL;
>> break;
>> @@ -54,7 +54,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
>> if (found != ring_freq) {
>> pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected ring freq, found %d, expected %d\n",
>> gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
>> - intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
>> + intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
>> found, ring_freq);
>> err = -EINVAL;
>> break;
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> index d8f6623524e8..3119016d9910 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> @@ -584,7 +584,7 @@ static int __live_lrc_gpr(struct intel_engine_cs *engine,
>> int err;
>> int n;
>>
>> - if (INTEL_GEN(engine->i915) < 9 && engine->class != RENDER_CLASS)
>> + if (GRAPHICS_VER(engine->i915) < 9 && engine->class != RENDER_CLASS)
>> return 0; /* GPR only on rcs0 for gen8 */
>>
>> err = gpr_make_dirty(engine->kernel_context);
>> @@ -1389,10 +1389,10 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
>>
>> static bool skip_isolation(const struct intel_engine_cs *engine)
>> {
>> - if (engine->class == COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) == 9)
>> + if (engine->class == COPY_ENGINE_CLASS && GRAPHICS_VER(engine->i915) == 9)
>> return true;
>>
>> - if (engine->class == RENDER_CLASS && INTEL_GEN(engine->i915) == 11)
>> + if (engine->class == RENDER_CLASS && GRAPHICS_VER(engine->i915) == 11)
>> return true;
>>
>> return false;
>> @@ -1551,7 +1551,7 @@ static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)
>> /* We use the already reserved extra page in context state */
>> if (!a->wa_bb_page) {
>> GEM_BUG_ON(b->wa_bb_page);
>> - GEM_BUG_ON(INTEL_GEN(engine->i915) == 12);
>> + GEM_BUG_ON(GRAPHICS_VER(engine->i915) == 12);
>> goto unpin_b;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
>> index e55a887d11e2..b9bb0e6e97f7 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
>> @@ -183,7 +183,7 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
>> * which only controls CPU initiated MMIO. Routing does not
>> * work for CS access so we cannot verify them on this path.
>> */
>> - return INTEL_GEN(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
>> + return GRAPHICS_VER(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
>> }
>>
>> static int check_l3cc_table(struct intel_engine_cs *engine,
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
>> index 710f825f6e5a..8c70b7e12074 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
>> @@ -140,7 +140,7 @@ static const u32 *__live_rc6_ctx(struct intel_context *ce)
>> }
>>
>> cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
>> - if (INTEL_GEN(rq->engine->i915) >= 8)
>> + if (GRAPHICS_VER(rq->engine->i915) >= 8)
>> cmd++;
>>
>> *cs++ = cmd;
>> @@ -193,7 +193,7 @@ int live_rc6_ctx_wa(void *arg)
>> int err = 0;
>>
>> /* A read of CTX_INFO upsets rc6. Poke the bear! */
>> - if (INTEL_GEN(gt->i915) < 8)
>> + if (GRAPHICS_VER(gt->i915) < 8)
>> return 0;
>>
>> engines = randomised_engines(gt, &prng, &count);
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
>> index c12e74171b63..041954408d0f 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
>> @@ -41,10 +41,10 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
>> return ERR_CAST(cs);
>> }
>>
>> - if (INTEL_GEN(engine->i915) >= 6) {
>> + if (GRAPHICS_VER(engine->i915) >= 6) {
>> *cs++ = MI_STORE_DWORD_IMM_GEN4;
>> *cs++ = 0;
>> - } else if (INTEL_GEN(engine->i915) >= 4) {
>> + } else if (GRAPHICS_VER(engine->i915) >= 4) {
>> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> *cs++ = 0;
>> } else {
>> @@ -266,7 +266,7 @@ static int live_ctx_switch_wa(void *arg)
>> if (!intel_engine_can_store_dword(engine))
>> continue;
>>
>> - if (IS_GEN_RANGE(gt->i915, 4, 5))
>> + if (IS_GRAPHICS_VER(gt->i915, 4, 5))
>> continue; /* MI_STORE_DWORD is privileged! */
>>
>> saved_wa = fetch_and_zero(&engine->wa_ctx.vma);
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
>> index 3ca1bd5793c3..7ee2513e15f9 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_rps.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
>> @@ -204,7 +204,7 @@ static void show_pstate_limits(struct intel_rps *rps)
>> i915_mmio_reg_offset(BXT_RP_STATE_CAP),
>> intel_uncore_read(rps_to_uncore(rps),
>> BXT_RP_STATE_CAP));
>> - } else if (IS_GEN(i915, 9)) {
>> + } else if (GRAPHICS_VER(i915) == 9) {
>> pr_info("P_STATE_LIMITS[%x]: 0x%08x\n",
>> i915_mmio_reg_offset(GEN9_RP_STATE_LIMITS),
>> intel_uncore_read(rps_to_uncore(rps),
>> @@ -222,7 +222,7 @@ int live_rps_clock_interval(void *arg)
>> struct igt_spinner spin;
>> int err = 0;
>>
>> - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
>> + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
>> return 0;
>>
>> if (igt_spinner_init(&spin, gt))
>> @@ -506,7 +506,7 @@ static void show_pcu_config(struct intel_rps *rps)
>>
>> min_gpu_freq = rps->min_freq;
>> max_gpu_freq = rps->max_freq;
>> - if (INTEL_GEN(i915) >= 9) {
>> + if (GRAPHICS_VER(i915) >= 9) {
>> /* Convert GT frequency to 50 HZ units */
>> min_gpu_freq /= GEN9_FREQ_SCALER;
>> max_gpu_freq /= GEN9_FREQ_SCALER;
>> @@ -614,7 +614,7 @@ int live_rps_frequency_cs(void *arg)
>> if (!intel_rps_is_enabled(rps))
>> return 0;
>>
>> - if (INTEL_GEN(gt->i915) < 8) /* for CS simplicity */
>> + if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
>> return 0;
>>
>> if (CPU_LATENCY >= 0)
>> @@ -755,7 +755,7 @@ int live_rps_frequency_srm(void *arg)
>> if (!intel_rps_is_enabled(rps))
>> return 0;
>>
>> - if (INTEL_GEN(gt->i915) < 8) /* for CS simplicity */
>> + if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
>> return 0;
>>
>> if (CPU_LATENCY >= 0)
>> @@ -1031,7 +1031,7 @@ int live_rps_interrupt(void *arg)
>> * First, let's check whether or not we are receiving interrupts.
>> */
>>
>> - if (!intel_rps_has_interrupts(rps) || INTEL_GEN(gt->i915) < 6)
>> + if (!intel_rps_has_interrupts(rps) || GRAPHICS_VER(gt->i915) < 6)
>> return 0;
>>
>> intel_gt_pm_get(gt);
>> @@ -1136,7 +1136,7 @@ int live_rps_power(void *arg)
>> * that theory.
>> */
>>
>> - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
>> + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
>> return 0;
>>
>> if (!librapl_supported(gt->i915))
>> @@ -1240,7 +1240,7 @@ int live_rps_dynamic(void *arg)
>> * moving parts into dynamic reclocking based on load.
>> */
>>
>> - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
>> + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
>> return 0;
>>
>> if (igt_spinner_init(&spin, gt))
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> index 9adbd9d147be..64da0c91dec1 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> @@ -457,12 +457,12 @@ static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
>> if (IS_ERR(cs))
>> return PTR_ERR(cs);
>>
>> - if (INTEL_GEN(rq->engine->i915) >= 8) {
>> + if (GRAPHICS_VER(rq->engine->i915) >= 8) {
>> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> *cs++ = addr;
>> *cs++ = 0;
>> *cs++ = value;
>> - } else if (INTEL_GEN(rq->engine->i915) >= 4) {
>> + } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
>> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> *cs++ = 0;
>> *cs++ = addr;
>> @@ -992,7 +992,7 @@ static int live_hwsp_read(void *arg)
>> * even across multiple wraps.
>> */
>>
>> - if (INTEL_GEN(gt->i915) < 8) /* CS convenience [SRM/LRM] */
>> + if (GRAPHICS_VER(gt->i915) < 8) /* CS convenience [SRM/LRM] */
>> return 0;
>>
>> tl = intel_timeline_create(gt);
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
>> index 64937ec3f2dc..c30754daf4b1 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
>> @@ -145,7 +145,7 @@ read_nonprivs(struct intel_context *ce)
>> goto err_req;
>>
>> srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
>> - if (INTEL_GEN(engine->i915) >= 8)
>> + if (GRAPHICS_VER(engine->i915) >= 8)
>> srm++;
>>
>> cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
>> @@ -546,7 +546,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
>>
>> srm = MI_STORE_REGISTER_MEM;
>> lrm = MI_LOAD_REGISTER_MEM;
>> - if (INTEL_GEN(engine->i915) >= 8)
>> + if (GRAPHICS_VER(engine->i915) >= 8)
>> lrm++, srm++;
>>
>> pr_debug("%s: Writing garbage to %x\n",
>> @@ -749,7 +749,7 @@ static int live_dirty_whitelist(void *arg)
>>
>> /* Can the user write to the whitelisted registers? */
>>
>> - if (INTEL_GEN(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */
>> + if (GRAPHICS_VER(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */
>> return 0;
>>
>> for_each_engine(engine, gt, id) {
>> @@ -829,7 +829,7 @@ static int read_whitelisted_registers(struct intel_context *ce,
>> goto err_req;
>>
>> srm = MI_STORE_REGISTER_MEM;
>> - if (INTEL_GEN(engine->i915) >= 8)
>> + if (GRAPHICS_VER(engine->i915) >= 8)
>> srm++;
>>
>> cs = intel_ring_begin(rq, 4 * engine->whitelist.count);
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> index adae04c47aab..84f806911370 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> @@ -60,7 +60,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
>> enum forcewake_domains fw_domains = 0;
>> unsigned int i;
>>
>> - if (INTEL_GEN(gt->i915) >= 11) {
>> + if (GRAPHICS_VER(gt->i915) >= 11) {
>> guc->send_regs.base =
>> i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
>> guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
>> @@ -176,7 +176,7 @@ void intel_guc_init_early(struct intel_guc *guc)
>>
>> mutex_init(&guc->send_mutex);
>> spin_lock_init(&guc->irq_lock);
>> - if (INTEL_GEN(i915) >= 11) {
>> + if (GRAPHICS_VER(i915) >= 11) {
>> guc->notify_reg = GEN11_GUC_HOST_INTERRUPT;
>> guc->interrupts.reset = gen11_reset_guc_interrupts;
>> guc->interrupts.enable = gen11_enable_guc_interrupts;
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> index 17526717368c..b32fafba2a90 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> @@ -162,7 +162,7 @@ static void __guc_ads_init(struct intel_guc *guc)
>> blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK] =
>> gt->info.vdbox_sfc_access;
>>
>> - if (INTEL_GEN(i915) >= 12 && !IS_DGFX(i915)) {
>> + if (GRAPHICS_VER(i915) >= 12 && !IS_DGFX(i915)) {
>> u32 distdbreg = intel_uncore_read(gt->uncore,
>> GEN12_DIST_DBS_POPULATED);
>> blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI] =
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> index 2270d6b3b272..76fe766ad1bc 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> @@ -30,7 +30,7 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
>> else
>> intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
>>
>> - if (IS_GEN(uncore->i915, 9)) {
>> + if (GRAPHICS_VER(uncore->i915) == 9) {
>> /* DOP Clock Gating Enable for GuC clocks */
>> intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
>> 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> index 335719f17490..541f6da1ec47 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> @@ -438,7 +438,7 @@ static void guc_interrupts_capture(struct intel_gt *gt)
>> u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
>> u32 dmask = irqs << 16 | irqs;
>>
>> - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
>> + GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
>>
>> /* Don't handle the ctx switch interrupt in GuC submission mode */
>> intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask, 0);
>> @@ -451,7 +451,7 @@ static void guc_interrupts_release(struct intel_gt *gt)
>> u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
>> u32 dmask = irqs << 16 | irqs;
>>
>> - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
>> + GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
>>
>> /* Handle ctx switch interrupts again */
>> intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0, dmask);
>> @@ -648,7 +648,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>> engine->emit_flush = gen8_emit_flush_xcs;
>> engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
>> engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
>> - if (INTEL_GEN(engine->i915) >= 12) {
>> + if (GRAPHICS_VER(engine->i915) >= 12) {
>> engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;
>> engine->emit_flush = gen12_emit_flush_xcs;
>> }
>> @@ -670,7 +670,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>>
>> static void rcs_submission_override(struct intel_engine_cs *engine)
>> {
>> - switch (INTEL_GEN(engine->i915)) {
>> + switch (GRAPHICS_VER(engine->i915)) {
>> case 12:
>> engine->emit_flush = gen12_emit_flush_rcs;
>> engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
>> @@ -700,7 +700,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
>> * The setup relies on several assumptions (e.g. irqs always enabled)
>> * that are only valid on gen11+
>> */
>> - GEM_BUG_ON(INTEL_GEN(i915) < 11);
>> + GEM_BUG_ON(GRAPHICS_VER(i915) < 11);
>>
>> tasklet_setup(&engine->execlists.tasklet, guc_submission_tasklet);
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>> index 56d2144dc6a0..fc5387b410a2 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>> @@ -43,7 +43,7 @@ void intel_huc_init_early(struct intel_huc *huc)
>>
>> intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC);
>>
>> - if (INTEL_GEN(i915) >= 11) {
>> + if (GRAPHICS_VER(i915) >= 11) {
>> huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
>> huc->status.mask = HUC_LOAD_SUCCESSFUL;
>> huc->status.value = HUC_LOAD_SUCCESSFUL;
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> index 6abb8f2dc33d..6c2bf4b6bc10 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> @@ -23,7 +23,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
>> return;
>>
>> /* Don't enable GuC/HuC on pre-Gen12 */
>> - if (INTEL_GEN(i915) < 12) {
>> + if (GRAPHICS_VER(i915) < 12) {
>> i915->params.enable_guc = 0;
>> return;
>> }
>> @@ -467,7 +467,7 @@ static int __uc_init_hw(struct intel_uc *uc)
>>
>> /* WaEnableuKernelHeaderValidFix:skl */
>> /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
>> - if (IS_GEN(i915, 9))
>> + if (GRAPHICS_VER(i915) == 9)
>> attempts = 3;
>> else
>> attempts = 1;
>> --
>> 2.31.1
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
2021-06-01 17:15 ` Lucas De Marchi
@ 2021-06-01 17:30 ` Matt Roper
2021-06-01 19:13 ` Lucas De Marchi
0 siblings, 1 reply; 20+ messages in thread
From: Matt Roper @ 2021-06-01 17:30 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, Jun 01, 2021 at 10:15:14AM -0700, Lucas De Marchi wrote:
> On Tue, Jun 01, 2021 at 09:58:34AM -0700, Matt Roper wrote:
> > On Thu, May 27, 2021 at 11:16:54AM -0700, Lucas De Marchi wrote:
> > > This was done by the following semantic patch:
> >
> > Is the commit message here out-of-date? The cocci doesn't appear to
> > match the diff anymore. IS_GRAPHICS_VER() is the range macro now and
> > IS_GEN is being replaced with a direct "==" comparison.
>
> not necessarily, it's included in "and friends...". Maybe rewording to
> something like "replace gen-based macros with new ver-based ones" would
> make it clearer?
I mean that running the coccinelle rules below through spatch won't
generate the code diff here; it would generate a completely different
patch (that I don't think would build properly either).
Matt
>
> Lucas De Marchi
>
> >
> >
> > Matt
> >
> > >
> > > @@ expression dev_priv, E; @@
> > > - INTEL_GEN(dev_priv) == E
> > > + IS_GRAPHICS_VER(dev_priv, E)
> > >
> > > @@ expression dev_priv; @@
> > > - INTEL_GEN(dev_priv)
> > > + GRAPHICS_VER(dev_priv)
> > >
> > > @@ expression dev_priv; expression E; @@
> > > - IS_GEN(dev_priv, E)
> > > + IS_GRAPHICS_VER(dev_priv, E)
> > >
> > > @@
> > > expression dev_priv;
> > > expression from, until;
> > > @@
> > > - IS_GEN_RANGE(dev_priv, from, until)
> > > + IS_GRAPHICS_RANGE(dev_priv, from, until)
> > >
> > > @def@
> > > expression E;
> > > identifier id =~ "^gen$";
> > > @@
> > > - id = GRAPHICS_VER(E)
> > > + ver = GRAPHICS_VER(E)
> > >
> > > @@
> > > identifier def.id;
> > > @@
> > > - id
> > > + ver
> > >
> > > It also takes care of renaming the variable we assign to GRAPHICS_VER()
> > > so to use "ver" rather than "gen".
> > >
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 38 +++++------
> > > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
> > > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
> > > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 +-
> > > drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
> > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 54 +++++++--------
> > > .../drm/i915/gt/intel_execlists_submission.c | 18 ++---
> > > drivers/gpu/drm/i915/gt/intel_ggtt.c | 18 ++---
> > > drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 34 +++++-----
> > > drivers/gpu/drm/i915/gt/intel_gt.c | 27 ++++----
> > > .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 12 ++--
> > > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 6 +-
> > > drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 10 +--
> > > drivers/gpu/drm/i915/gt/intel_gtt.c | 14 ++--
> > > drivers/gpu/drm/i915/gt/intel_llc.c | 6 +-
> > > drivers/gpu/drm/i915/gt/intel_lrc.c | 46 ++++++-------
> > > drivers/gpu/drm/i915/gt/intel_mocs.c | 8 +--
> > > drivers/gpu/drm/i915/gt/intel_ppgtt.c | 6 +-
> > > drivers/gpu/drm/i915/gt/intel_rc6.c | 16 ++---
> > > drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
> > > drivers/gpu/drm/i915/gt/intel_reset.c | 12 ++--
> > > .../gpu/drm/i915/gt/intel_ring_submission.c | 64 +++++++++---------
> > > drivers/gpu/drm/i915/gt/intel_rps.c | 60 ++++++++---------
> > > drivers/gpu/drm/i915/gt/intel_sseu.c | 14 ++--
> > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +++++++++----------
> > > drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 6 +-
> > > drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 +-
> > > drivers/gpu/drm/i915/gt/selftest_execlists.c | 4 +-
> > > drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +--
> > > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 +--
> > > drivers/gpu/drm/i915/gt/selftest_llc.c | 4 +-
> > > drivers/gpu/drm/i915/gt/selftest_lrc.c | 8 +--
> > > drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
> > > drivers/gpu/drm/i915/gt/selftest_rc6.c | 4 +-
> > > .../drm/i915/gt/selftest_ring_submission.c | 6 +-
> > > drivers/gpu/drm/i915/gt/selftest_rps.c | 16 ++---
> > > drivers/gpu/drm/i915/gt/selftest_timeline.c | 6 +-
> > > .../gpu/drm/i915/gt/selftest_workarounds.c | 8 +--
> > > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +-
> > > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
> > > drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
> > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +--
> > > drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
> > > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
> > > 44 files changed, 323 insertions(+), 322 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> > > index d4f4452ce5ed..0389bceebd06 100644
> > > --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> > > +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> > > @@ -85,14 +85,14 @@ static int gen6_drpc(struct seq_file *m)
> > > gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
> > >
> > > rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
> > > - if (INTEL_GEN(i915) >= 9) {
> > > + if (GRAPHICS_VER(i915) >= 9) {
> > > gen9_powergate_enable =
> > > intel_uncore_read(uncore, GEN9_PG_ENABLE);
> > > gen9_powergate_status =
> > > intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
> > > }
> > >
> > > - if (INTEL_GEN(i915) <= 7)
> > > + if (GRAPHICS_VER(i915) <= 7)
> > > sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
> > > &rc6vids, NULL);
> > >
> > > @@ -100,7 +100,7 @@ static int gen6_drpc(struct seq_file *m)
> > > yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
> > > seq_printf(m, "RC6 Enabled: %s\n",
> > > yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
> > > - if (INTEL_GEN(i915) >= 9) {
> > > + if (GRAPHICS_VER(i915) >= 9) {
> > > seq_printf(m, "Render Well Gating Enabled: %s\n",
> > > yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
> > > seq_printf(m, "Media Well Gating Enabled: %s\n",
> > > @@ -134,7 +134,7 @@ static int gen6_drpc(struct seq_file *m)
> > >
> > > seq_printf(m, "Core Power Down: %s\n",
> > > yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
> > > - if (INTEL_GEN(i915) >= 9) {
> > > + if (GRAPHICS_VER(i915) >= 9) {
> > > seq_printf(m, "Render Power Well: %s\n",
> > > (gen9_powergate_status &
> > > GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
> > > @@ -150,7 +150,7 @@ static int gen6_drpc(struct seq_file *m)
> > > print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
> > > print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
> > >
> > > - if (INTEL_GEN(i915) <= 7) {
> > > + if (GRAPHICS_VER(i915) <= 7) {
> > > seq_printf(m, "RC6 voltage: %dmV\n",
> > > GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
> > > seq_printf(m, "RC6+ voltage: %dmV\n",
> > > @@ -250,7 +250,7 @@ static int frequency_show(struct seq_file *m, void *unused)
> > >
> > > wakeref = intel_runtime_pm_get(uncore->rpm);
> > >
> > > - if (IS_GEN(i915, 5)) {
> > > + if (GRAPHICS_VER(i915) == 5) {
> > > u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
> > > u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
> > >
> > > @@ -296,7 +296,7 @@ static int frequency_show(struct seq_file *m, void *unused)
> > >
> > > seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
> > > intel_gpu_freq(rps, rps->efficient_freq));
> > > - } else if (INTEL_GEN(i915) >= 6) {
> > > + } else if (GRAPHICS_VER(i915) >= 6) {
> > > u32 rp_state_limits;
> > > u32 gt_perf_status;
> > > u32 rp_state_cap;
> > > @@ -321,7 +321,7 @@ static int frequency_show(struct seq_file *m, void *unused)
> > > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> > >
> > > reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
> > > - if (INTEL_GEN(i915) >= 9) {
> > > + if (GRAPHICS_VER(i915) >= 9) {
> > > reqf >>= 23;
> > > } else {
> > > reqf &= ~GEN6_TURBO_DISABLE;
> > > @@ -354,7 +354,7 @@ static int frequency_show(struct seq_file *m, void *unused)
> > >
> > > intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> > >
> > > - if (INTEL_GEN(i915) >= 11) {
> > > + if (GRAPHICS_VER(i915) >= 11) {
> > > pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
> > > pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
> > > /*
> > > @@ -363,7 +363,7 @@ static int frequency_show(struct seq_file *m, void *unused)
> > > */
> > > pm_isr = 0;
> > > pm_iir = 0;
> > > - } else if (INTEL_GEN(i915) >= 8) {
> > > + } else if (GRAPHICS_VER(i915) >= 8) {
> > > pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
> > > pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
> > > pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
> > > @@ -386,14 +386,14 @@ static int frequency_show(struct seq_file *m, void *unused)
> > >
> > > seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
> > > pm_ier, pm_imr, pm_mask);
> > > - if (INTEL_GEN(i915) <= 10)
> > > + if (GRAPHICS_VER(i915) <= 10)
> > > seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
> > > pm_isr, pm_iir);
> > > seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
> > > rps->pm_intrmsk_mbz);
> > > seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> > > seq_printf(m, "Render p-state ratio: %d\n",
> > > - (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> > > + (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> > > seq_printf(m, "Render p-state VID: %d\n",
> > > gt_perf_status & 0xff);
> > > seq_printf(m, "Render p-state limit: %d\n",
> > > @@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void *unused)
> > > max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
> > > rp_state_cap >> 16) & 0xff;
> > > max_freq *= (IS_GEN9_BC(i915) ||
> > > - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> > > + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> > > seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
> > > intel_gpu_freq(rps, max_freq));
> > >
> > > max_freq = (rp_state_cap & 0xff00) >> 8;
> > > max_freq *= (IS_GEN9_BC(i915) ||
> > > - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> > > + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> > > seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
> > > intel_gpu_freq(rps, max_freq));
> > >
> > > max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
> > > rp_state_cap >> 0) & 0xff;
> > > max_freq *= (IS_GEN9_BC(i915) ||
> > > - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> > > + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> > > seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
> > > intel_gpu_freq(rps, max_freq));
> > > seq_printf(m, "Max overclocked frequency: %dMHz\n",
> > > @@ -488,7 +488,7 @@ static int llc_show(struct seq_file *m, void *data)
> > > {
> > > struct intel_gt *gt = m->private;
> > > struct drm_i915_private *i915 = gt->i915;
> > > - const bool edram = INTEL_GEN(i915) > 8;
> > > + const bool edram = GRAPHICS_VER(i915) > 8;
> > > struct intel_rps *rps = >->rps;
> > > unsigned int max_gpu_freq, min_gpu_freq;
> > > intel_wakeref_t wakeref;
> > > @@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data)
> > >
> > > min_gpu_freq = rps->min_freq;
> > > max_gpu_freq = rps->max_freq;
> > > - if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
> > > + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
> > > /* Convert GT frequency to 50 HZ units */
> > > min_gpu_freq /= GEN9_FREQ_SCALER;
> > > max_gpu_freq /= GEN9_FREQ_SCALER;
> > > @@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data)
> > > intel_gpu_freq(rps,
> > > (gpu_freq *
> > > (IS_GEN9_BC(i915) ||
> > > - INTEL_GEN(i915) >= 10 ?
> > > + GRAPHICS_VER(i915) >= 10 ?
> > > GEN9_FREQ_SCALER : 1))),
> > > ((ia_freq >> 0) & 0xff) * 100,
> > > ((ia_freq >> 8) & 0xff) * 100);
> > > @@ -580,7 +580,7 @@ static int rps_boost_show(struct seq_file *m, void *data)
> > >
> > > seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
> > >
> > > - if (INTEL_GEN(i915) >= 6 && intel_rps_is_active(rps)) {
> > > + if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) {
> > > struct intel_uncore *uncore = gt->uncore;
> > > u32 rpup, rpupei;
> > > u32 rpdown, rpdownei;
> > > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> > > index 9646200d2792..61383830505e 100644
> > > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> > > @@ -74,7 +74,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
> > > cmd = MI_FLUSH;
> > > if (mode & EMIT_INVALIDATE) {
> > > cmd |= MI_EXE_FLUSH;
> > > - if (IS_G4X(rq->engine->i915) || IS_GEN(rq->engine->i915, 5))
> > > + if (IS_G4X(rq->engine->i915) || GRAPHICS_VER(rq->engine->i915) == 5)
> > > cmd |= MI_INVALIDATE_ISP;
> > > }
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > index 732c2ed1d933..94e0a5669f90 100644
> > > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > @@ -38,7 +38,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
> > > * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
> > > * pipe control.
> > > */
> > > - if (IS_GEN(rq->engine->i915, 9))
> > > + if (GRAPHICS_VER(rq->engine->i915) == 9)
> > > vf_flush_wa = true;
> > >
> > > /* WaForGAMHang:kbl */
> > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > > index e3a8924d2286..21c8b7350b7a 100644
> > > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > > @@ -709,7 +709,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> > > *
> > > * Gen12 has inherited the same read-only fault issue from gen11.
> > > */
> > > - ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12);
> > > + ppgtt->vm.has_read_only = !IS_GRAPHICS_VER(gt->i915, 11, 12);
> > >
> > > if (HAS_LMEM(gt->i915))
> > > ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
> > > index 8dfd8f656aaa..e86d8255feec 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
> > > @@ -76,7 +76,7 @@ intel_context_reconfigure_sseu(struct intel_context *ce,
> > > {
> > > int ret;
> > >
> > > - GEM_BUG_ON(INTEL_GEN(ce->engine->i915) < 8);
> > > + GEM_BUG_ON(GRAPHICS_VER(ce->engine->i915) < 8);
> > >
> > > ret = intel_context_lock_pinned(ce);
> > > if (ret)
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > index 3f9a811eb02b..54baf17b81b6 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > @@ -240,10 +240,10 @@ void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
> > > * Though they added more rings on g4x/ilk, they did not add
> > > * per-engine HWSTAM until gen6.
> > > */
> > > - if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS)
> > > + if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)
> > > return;
> > >
> > > - if (INTEL_GEN(engine->i915) >= 3)
> > > + if (GRAPHICS_VER(engine->i915) >= 3)
> > > ENGINE_WRITE(engine, RING_HWSTAM, mask);
> > > else
> > > ENGINE_WRITE16(engine, RING_HWSTAM, mask);
> > > @@ -315,7 +315,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
> > > CONFIG_DRM_I915_TIMESLICE_DURATION;
> > >
> > > /* Override to uninterruptible for OpenCL workloads. */
> > > - if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS)
> > > + if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
> > > engine->props.preempt_timeout_ms = 0;
> > >
> > > engine->defaults = engine->props; /* never to change again */
> > > @@ -352,8 +352,8 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
> > > * HEVC support is present on first engine instance
> > > * before Gen11 and on all instances afterwards.
> > > */
> > > - if (INTEL_GEN(i915) >= 11 ||
> > > - (INTEL_GEN(i915) >= 9 && engine->instance == 0))
> > > + if (GRAPHICS_VER(i915) >= 11 ||
> > > + (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
> > > engine->uabi_capabilities |=
> > > I915_VIDEO_CLASS_CAPABILITY_HEVC;
> > >
> > > @@ -361,14 +361,14 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
> > > * SFC block is present only on even logical engine
> > > * instances.
> > > */
> > > - if ((INTEL_GEN(i915) >= 11 &&
> > > + if ((GRAPHICS_VER(i915) >= 11 &&
> > > (engine->gt->info.vdbox_sfc_access &
> > > BIT(engine->instance))) ||
> > > - (INTEL_GEN(i915) >= 9 && engine->instance == 0))
> > > + (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
> > > engine->uabi_capabilities |=
> > > I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
> > > } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
> > > - if (INTEL_GEN(i915) >= 9)
> > > + if (GRAPHICS_VER(i915) >= 9)
> > > engine->uabi_capabilities |=
> > > I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
> > > }
> > > @@ -466,7 +466,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> > >
> > > info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
> > >
> > > - if (INTEL_GEN(i915) < 11)
> > > + if (GRAPHICS_VER(i915) < 11)
> > > return info->engine_mask;
> > >
> > > media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> > > @@ -492,7 +492,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> > > * hooked up to an SFC (Scaler & Format Converter) unit.
> > > * In TGL each VDBOX has access to an SFC.
> > > */
> > > - if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
> > > + if (GRAPHICS_VER(i915) >= 12 || logical_vdbox++ % 2 == 0)
> > > gt->info.vdbox_sfc_access |= BIT(i);
> > > }
> > > drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
> > > @@ -729,7 +729,7 @@ static int engine_setup_common(struct intel_engine_cs *engine)
> > > intel_engine_init_whitelist(engine);
> > > intel_engine_init_ctx_wa(engine);
> > >
> > > - if (INTEL_GEN(engine->i915) >= 12)
> > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
> > >
> > > return 0;
> > > @@ -997,9 +997,9 @@ u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
> > >
> > > u64 acthd;
> > >
> > > - if (INTEL_GEN(i915) >= 8)
> > > + if (GRAPHICS_VER(i915) >= 8)
> > > acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
> > > - else if (INTEL_GEN(i915) >= 4)
> > > + else if (GRAPHICS_VER(i915) >= 4)
> > > acthd = ENGINE_READ(engine, RING_ACTHD);
> > > else
> > > acthd = ENGINE_READ(engine, ACTHD);
> > > @@ -1011,7 +1011,7 @@ u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
> > > {
> > > u64 bbaddr;
> > >
> > > - if (INTEL_GEN(engine->i915) >= 8)
> > > + if (GRAPHICS_VER(engine->i915) >= 8)
> > > bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
> > > else
> > > bbaddr = ENGINE_READ(engine, RING_BBADDR);
> > > @@ -1058,7 +1058,7 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
> > > {
> > > int err = 0;
> > >
> > > - if (INTEL_GEN(engine->i915) < 3)
> > > + if (GRAPHICS_VER(engine->i915) < 3)
> > > return -ENODEV;
> > >
> > > ENGINE_TRACE(engine, "\n");
> > > @@ -1108,7 +1108,7 @@ read_subslice_reg(const struct intel_engine_cs *engine,
> > > u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
> > > enum forcewake_domains fw_domains;
> > >
> > > - if (INTEL_GEN(i915) >= 11) {
> > > + if (GRAPHICS_VER(i915) >= 11) {
> > > mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
> > > mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
> > > } else {
> > > @@ -1157,7 +1157,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
> > >
> > > memset(instdone, 0, sizeof(*instdone));
> > >
> > > - switch (INTEL_GEN(i915)) {
> > > + switch (GRAPHICS_VER(i915)) {
> > > default:
> > > instdone->instdone =
> > > intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
> > > @@ -1167,7 +1167,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
> > >
> > > instdone->slice_common =
> > > intel_uncore_read(uncore, GEN7_SC_INSTDONE);
> > > - if (INTEL_GEN(i915) >= 12) {
> > > + if (GRAPHICS_VER(i915) >= 12) {
> > > instdone->slice_common_extra[0] =
> > > intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
> > > instdone->slice_common_extra[1] =
> > > @@ -1230,7 +1230,7 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
> > > idle = false;
> > >
> > > /* No bit for gen2, so assume the CS parser is idle */
> > > - if (INTEL_GEN(engine->i915) > 2 &&
> > > + if (GRAPHICS_VER(engine->i915) > 2 &&
> > > !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
> > > idle = false;
> > >
> > > @@ -1327,7 +1327,7 @@ void intel_engines_reset_default_submission(struct intel_gt *gt)
> > >
> > > bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
> > > {
> > > - switch (INTEL_GEN(engine->i915)) {
> > > + switch (GRAPHICS_VER(engine->i915)) {
> > > case 2:
> > > return false; /* uses physical not virtual addresses */
> > > case 3:
> > > @@ -1432,7 +1432,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
> > > struct intel_engine_execlists * const execlists = &engine->execlists;
> > > u64 addr;
> > >
> > > - if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
> > > + if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7))
> > > drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
> > > if (HAS_EXECLISTS(dev_priv)) {
> > > drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
> > > @@ -1449,13 +1449,13 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
> > > drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
> > > ENGINE_READ(engine, RING_CTL),
> > > ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
> > > - if (INTEL_GEN(engine->i915) > 2) {
> > > + if (GRAPHICS_VER(engine->i915) > 2) {
> > > drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
> > > ENGINE_READ(engine, RING_MI_MODE),
> > > ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
> > > }
> > >
> > > - if (INTEL_GEN(dev_priv) >= 6) {
> > > + if (GRAPHICS_VER(dev_priv) >= 6) {
> > > drm_printf(m, "\tRING_IMR: 0x%08x\n",
> > > ENGINE_READ(engine, RING_IMR));
> > > drm_printf(m, "\tRING_ESR: 0x%08x\n",
> > > @@ -1472,15 +1472,15 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
> > > addr = intel_engine_get_last_batch_head(engine);
> > > drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
> > > upper_32_bits(addr), lower_32_bits(addr));
> > > - if (INTEL_GEN(dev_priv) >= 8)
> > > + if (GRAPHICS_VER(dev_priv) >= 8)
> > > addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
> > > - else if (INTEL_GEN(dev_priv) >= 4)
> > > + else if (GRAPHICS_VER(dev_priv) >= 4)
> > > addr = ENGINE_READ(engine, RING_DMA_FADD);
> > > else
> > > addr = ENGINE_READ(engine, DMA_FADD_I8XX);
> > > drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
> > > upper_32_bits(addr), lower_32_bits(addr));
> > > - if (INTEL_GEN(dev_priv) >= 4) {
> > > + if (GRAPHICS_VER(dev_priv) >= 4) {
> > > drm_printf(m, "\tIPEIR: 0x%08x\n",
> > > ENGINE_READ(engine, RING_IPEIR));
> > > drm_printf(m, "\tIPEHR: 0x%08x\n",
> > > @@ -1559,7 +1559,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
> > > }
> > > rcu_read_unlock();
> > > execlists_active_unlock_bh(execlists);
> > > - } else if (INTEL_GEN(dev_priv) > 6) {
> > > + } else if (GRAPHICS_VER(dev_priv) > 6) {
> > > drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
> > > ENGINE_READ(engine, RING_PP_DIR_BASE));
> > > drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > index 8db200422950..fc77592d88a9 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > @@ -1847,7 +1847,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
> > > ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n",
> > > head, upper_32_bits(csb), lower_32_bits(csb));
> > >
> > > - if (INTEL_GEN(engine->i915) >= 12)
> > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > promote = gen12_csb_parse(csb);
> > > else
> > > promote = gen8_csb_parse(csb);
> > > @@ -2772,7 +2772,7 @@ static void enable_execlists(struct intel_engine_cs *engine)
> > >
> > > intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
> > >
> > > - if (INTEL_GEN(engine->i915) >= 11)
> > > + if (GRAPHICS_VER(engine->i915) >= 11)
> > > mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
> > > else
> > > mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
> > > @@ -3103,7 +3103,7 @@ static void execlists_park(struct intel_engine_cs *engine)
> > >
> > > static bool can_preempt(struct intel_engine_cs *engine)
> > > {
> > > - if (INTEL_GEN(engine->i915) > 8)
> > > + if (GRAPHICS_VER(engine->i915) > 8)
> > > return true;
> > >
> > > /* GPGPU on bdw requires extra w/a; not implemented */
> > > @@ -3156,13 +3156,13 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> > > engine->emit_flush = gen8_emit_flush_xcs;
> > > engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
> > > engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
> > > - if (INTEL_GEN(engine->i915) >= 12) {
> > > + if (GRAPHICS_VER(engine->i915) >= 12) {
> > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;
> > > engine->emit_flush = gen12_emit_flush_xcs;
> > > }
> > > engine->set_default_submission = execlists_set_default_submission;
> > >
> > > - if (INTEL_GEN(engine->i915) < 11) {
> > > + if (GRAPHICS_VER(engine->i915) < 11) {
> > > engine->irq_enable = gen8_logical_ring_enable_irq;
> > > engine->irq_disable = gen8_logical_ring_disable_irq;
> > > } else {
> > > @@ -3195,7 +3195,7 @@ static void logical_ring_default_irqs(struct intel_engine_cs *engine)
> > > {
> > > unsigned int shift = 0;
> > >
> > > - if (INTEL_GEN(engine->i915) < 11) {
> > > + if (GRAPHICS_VER(engine->i915) < 11) {
> > > const u8 irq_shifts[] = {
> > > [RCS0] = GEN8_RCS_IRQ_SHIFT,
> > > [BCS0] = GEN8_BCS_IRQ_SHIFT,
> > > @@ -3215,7 +3215,7 @@ static void logical_ring_default_irqs(struct intel_engine_cs *engine)
> > >
> > > static void rcs_submission_override(struct intel_engine_cs *engine)
> > > {
> > > - switch (INTEL_GEN(engine->i915)) {
> > > + switch (GRAPHICS_VER(engine->i915)) {
> > > case 12:
> > > engine->emit_flush = gen12_emit_flush_rcs;
> > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
> > > @@ -3266,13 +3266,13 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
> > > execlists->csb_write =
> > > &engine->status_page.addr[intel_hws_csb_write_index(i915)];
> > >
> > > - if (INTEL_GEN(i915) < 11)
> > > + if (GRAPHICS_VER(i915) < 11)
> > > execlists->csb_size = GEN8_CSB_ENTRIES;
> > > else
> > > execlists->csb_size = GEN11_CSB_ENTRIES;
> > >
> > > engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);
> > > - if (INTEL_GEN(engine->i915) >= 11) {
> > > + if (GRAPHICS_VER(engine->i915) >= 11) {
> > > execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
> > > execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
> > > }
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > index 35069ca5d7de..19bd8856ce84 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > @@ -107,10 +107,10 @@ static bool needs_idle_maps(struct drm_i915_private *i915)
> > > if (!intel_vtd_active())
> > > return false;
> > >
> > > - if (IS_GEN(i915, 5) && IS_MOBILE(i915))
> > > + if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
> > > return true;
> > >
> > > - if (IS_GEN(i915, 12))
> > > + if (GRAPHICS_VER(i915) == 12)
> > > return true; /* XXX DMAR fault reason 7 */
> > >
> > > return false;
> > > @@ -176,7 +176,7 @@ static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
> > >
> > > gen8_ggtt_invalidate(ggtt);
> > >
> > > - if (INTEL_GEN(i915) >= 12)
> > > + if (GRAPHICS_VER(i915) >= 12)
> > > intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
> > > GEN12_GUC_TLB_INV_CR_INVALIDATE);
> > > else
> > > @@ -820,7 +820,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
> > > * resort to an uncached mapping. The WC issue is easily caught by the
> > > * readback check when writing GTT PTE entries.
> > > */
> > > - if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
> > > + if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 10)
> > > ggtt->gsm = ioremap(phys_addr, size);
> > > else
> > > ggtt->gsm = ioremap_wc(phys_addr, size);
> > > @@ -1065,7 +1065,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
> > > ggtt->vm.pte_encode = hsw_pte_encode;
> > > else if (IS_VALLEYVIEW(i915))
> > > ggtt->vm.pte_encode = byt_pte_encode;
> > > - else if (INTEL_GEN(i915) >= 7)
> > > + else if (GRAPHICS_VER(i915) >= 7)
> > > ggtt->vm.pte_encode = ivb_pte_encode;
> > > else
> > > ggtt->vm.pte_encode = snb_pte_encode;
> > > @@ -1137,9 +1137,9 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
> > > ggtt->vm.dma = i915->drm.dev;
> > > dma_resv_init(&ggtt->vm.resv);
> > >
> > > - if (INTEL_GEN(i915) <= 5)
> > > + if (GRAPHICS_VER(i915) <= 5)
> > > ret = i915_gmch_probe(ggtt);
> > > - else if (INTEL_GEN(i915) < 8)
> > > + else if (GRAPHICS_VER(i915) < 8)
> > > ret = gen6_gmch_probe(ggtt);
> > > else
> > > ret = gen8_gmch_probe(ggtt);
> > > @@ -1196,7 +1196,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
> > >
> > > int i915_ggtt_enable_hw(struct drm_i915_private *i915)
> > > {
> > > - if (INTEL_GEN(i915) < 6 && !intel_enable_gtt())
> > > + if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
> > > return -EIO;
> > >
> > > return 0;
> > > @@ -1261,7 +1261,7 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt)
> > > if (flush)
> > > wbinvd_on_all_cpus();
> > >
> > > - if (INTEL_GEN(ggtt->vm.i915) >= 8)
> > > + if (GRAPHICS_VER(ggtt->vm.i915) >= 8)
> > > setup_private_pat(ggtt->vm.gt->uncore);
> > >
> > > intel_ggtt_restore_fences(ggtt);
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > > index 7bf84cd21543..cac7f3f44642 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > > @@ -56,7 +56,7 @@ static void i965_write_fence_reg(struct i915_fence_reg *fence)
> > > int fence_pitch_shift;
> > > u64 val;
> > >
> > > - if (INTEL_GEN(fence_to_i915(fence)) >= 6) {
> > > + if (GRAPHICS_VER(fence_to_i915(fence)) >= 6) {
> > > fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
> > > fence_reg_hi = FENCE_REG_GEN6_HI(fence->id);
> > > fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
> > > @@ -173,9 +173,9 @@ static void fence_write(struct i915_fence_reg *fence)
> > > * and explicitly managed for internal users.
> > > */
> > >
> > > - if (IS_GEN(i915, 2))
> > > + if (GRAPHICS_VER(i915) == 2)
> > > i830_write_fence_reg(fence);
> > > - else if (IS_GEN(i915, 3))
> > > + else if (GRAPHICS_VER(i915) == 3)
> > > i915_write_fence_reg(fence);
> > > else
> > > i965_write_fence_reg(fence);
> > > @@ -188,7 +188,7 @@ static void fence_write(struct i915_fence_reg *fence)
> > >
> > > static bool gpu_uses_fence_registers(struct i915_fence_reg *fence)
> > > {
> > > - return INTEL_GEN(fence_to_i915(fence)) < 4;
> > > + return GRAPHICS_VER(fence_to_i915(fence)) < 4;
> > > }
> > >
> > > static int fence_update(struct i915_fence_reg *fence,
> > > @@ -569,7 +569,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> > > u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> > > u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> > >
> > > - if (INTEL_GEN(i915) >= 8 || IS_VALLEYVIEW(i915)) {
> > > + if (GRAPHICS_VER(i915) >= 8 || IS_VALLEYVIEW(i915)) {
> > > /*
> > > * On BDW+, swizzling is not used. We leave the CPU memory
> > > * controller in charge of optimizing memory accesses without
> > > @@ -579,7 +579,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> > > */
> > > swizzle_x = I915_BIT_6_SWIZZLE_NONE;
> > > swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> > > - } else if (INTEL_GEN(i915) >= 6) {
> > > + } else if (GRAPHICS_VER(i915) >= 6) {
> > > if (i915->preserve_bios_swizzle) {
> > > if (intel_uncore_read(uncore, DISP_ARB_CTL) &
> > > DISP_TILE_SURFACE_SWIZZLING) {
> > > @@ -611,14 +611,14 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> > > swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> > > }
> > > }
> > > - } else if (IS_GEN(i915, 5)) {
> > > + } else if (GRAPHICS_VER(i915) == 5) {
> > > /*
> > > * On Ironlake whatever DRAM config, GPU always do
> > > * same swizzling setup.
> > > */
> > > swizzle_x = I915_BIT_6_SWIZZLE_9_10;
> > > swizzle_y = I915_BIT_6_SWIZZLE_9;
> > > - } else if (IS_GEN(i915, 2)) {
> > > + } else if (GRAPHICS_VER(i915) == 2) {
> > > /*
> > > * As far as we know, the 865 doesn't have these bit 6
> > > * swizzling issues.
> > > @@ -697,7 +697,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> > > }
> > >
> > > /* check for L-shaped memory aka modified enhanced addressing */
> > > - if (IS_GEN(i915, 4) &&
> > > + if (GRAPHICS_VER(i915) == 4 &&
> > > !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
> > > swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> > > swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> > > @@ -844,10 +844,10 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
> > >
> > > if (!i915_ggtt_has_aperture(ggtt))
> > > num_fences = 0;
> > > - else if (INTEL_GEN(i915) >= 7 &&
> > > + else if (GRAPHICS_VER(i915) >= 7 &&
> > > !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
> > > num_fences = 32;
> > > - else if (INTEL_GEN(i915) >= 4 ||
> > > + else if (GRAPHICS_VER(i915) >= 4 ||
> > > IS_I945G(i915) || IS_I945GM(i915) ||
> > > IS_G33(i915) || IS_PINEVIEW(i915))
> > > num_fences = 16;
> > > @@ -895,29 +895,29 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
> > > struct drm_i915_private *i915 = gt->i915;
> > > struct intel_uncore *uncore = gt->uncore;
> > >
> > > - if (INTEL_GEN(i915) < 5 ||
> > > + if (GRAPHICS_VER(i915) < 5 ||
> > > i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
> > > return;
> > >
> > > intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
> > >
> > > - if (IS_GEN(i915, 5))
> > > + if (GRAPHICS_VER(i915) == 5)
> > > return;
> > >
> > > intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL);
> > >
> > > - if (IS_GEN(i915, 6))
> > > + if (GRAPHICS_VER(i915) == 6)
> > > intel_uncore_write(uncore,
> > > ARB_MODE,
> > > _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
> > > - else if (IS_GEN(i915, 7))
> > > + else if (GRAPHICS_VER(i915) == 7)
> > > intel_uncore_write(uncore,
> > > ARB_MODE,
> > > _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
> > > - else if (IS_GEN(i915, 8))
> > > + else if (GRAPHICS_VER(i915) == 8)
> > > intel_uncore_write(uncore,
> > > GAMTARBMODE,
> > > _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
> > > else
> > > - MISSING_CASE(INTEL_GEN(i915));
> > > + MISSING_CASE(GRAPHICS_VER(i915));
> > > }
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > index 8d77dcbad059..7f24301cef18 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > @@ -115,10 +115,10 @@ static void init_unused_rings(struct intel_gt *gt)
> > > init_unused_ring(gt, SRB1_BASE);
> > > init_unused_ring(gt, SRB2_BASE);
> > > init_unused_ring(gt, SRB3_BASE);
> > > - } else if (IS_GEN(i915, 2)) {
> > > + } else if (GRAPHICS_VER(i915) == 2) {
> > > init_unused_ring(gt, SRB0_BASE);
> > > init_unused_ring(gt, SRB1_BASE);
> > > - } else if (IS_GEN(i915, 3)) {
> > > + } else if (GRAPHICS_VER(i915) == 3) {
> > > init_unused_ring(gt, PRB1_BASE);
> > > init_unused_ring(gt, PRB2_BASE);
> > > }
> > > @@ -135,7 +135,7 @@ int intel_gt_init_hw(struct intel_gt *gt)
> > > /* Double layer security blanket, see i915_gem_init() */
> > > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> > >
> > > - if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
> > > + if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
> > > intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
> > >
> > > if (IS_HASWELL(i915))
> > > @@ -208,10 +208,10 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
> > > struct intel_uncore *uncore = gt->uncore;
> > > u32 eir;
> > >
> > > - if (!IS_GEN(i915, 2))
> > > + if (GRAPHICS_VER(i915) != 2)
> > > clear_register(uncore, PGTBL_ER);
> > >
> > > - if (INTEL_GEN(i915) < 4)
> > > + if (GRAPHICS_VER(i915) < 4)
> > > clear_register(uncore, IPEIR(RENDER_RING_BASE));
> > > else
> > > clear_register(uncore, IPEIR_I965);
> > > @@ -229,13 +229,13 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
> > > I915_MASTER_ERROR_INTERRUPT);
> > > }
> > >
> > > - if (INTEL_GEN(i915) >= 12) {
> > > + if (GRAPHICS_VER(i915) >= 12) {
> > > rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
> > > intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
> > > - } else if (INTEL_GEN(i915) >= 8) {
> > > + } else if (GRAPHICS_VER(i915) >= 8) {
> > > rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
> > > intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
> > > - } else if (INTEL_GEN(i915) >= 6) {
> > > + } else if (GRAPHICS_VER(i915) >= 6) {
> > > struct intel_engine_cs *engine;
> > > enum intel_engine_id id;
> > >
> > > @@ -273,7 +273,7 @@ static void gen8_check_faults(struct intel_gt *gt)
> > > i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
> > > u32 fault;
> > >
> > > - if (INTEL_GEN(gt->i915) >= 12) {
> > > + if (GRAPHICS_VER(gt->i915) >= 12) {
> > > fault_reg = GEN12_RING_FAULT_REG;
> > > fault_data0_reg = GEN12_FAULT_TLB_DATA0;
> > > fault_data1_reg = GEN12_FAULT_TLB_DATA1;
> > > @@ -313,9 +313,9 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
> > > struct drm_i915_private *i915 = gt->i915;
> > >
> > > /* From GEN8 onwards we only have one 'All Engine Fault Register' */
> > > - if (INTEL_GEN(i915) >= 8)
> > > + if (GRAPHICS_VER(i915) >= 8)
> > > gen8_check_faults(gt);
> > > - else if (INTEL_GEN(i915) >= 6)
> > > + else if (GRAPHICS_VER(i915) >= 6)
> > > gen6_check_faults(gt);
> > > else
> > > return;
> > > @@ -367,7 +367,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
> > > void intel_gt_chipset_flush(struct intel_gt *gt)
> > > {
> > > wmb();
> > > - if (INTEL_GEN(gt->i915) < 6)
> > > + if (GRAPHICS_VER(gt->i915) < 6)
> > > intel_gtt_chipset_flush();
> > > }
> > >
> > > @@ -591,7 +591,8 @@ int intel_gt_init(struct intel_gt *gt)
> > > */
> > > intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
> > >
> > > - err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K);
> > > + err = intel_gt_init_scratch(gt,
> > > + GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
> > > if (err)
> > > goto out_fw;
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> > > index 582fcaee11aa..9f0e729d2d15 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> > > @@ -76,7 +76,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> > > u32 f19_2_mhz = 19200000;
> > > u32 f24_mhz = 24000000;
> > >
> > > - if (INTEL_GEN(uncore->i915) <= 4) {
> > > + if (GRAPHICS_VER(uncore->i915) <= 4) {
> > > /*
> > > * PRMs say:
> > > *
> > > @@ -85,7 +85,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> > > * (“CLKCFG”) MCHBAR register)
> > > */
> > > return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
> > > - } else if (INTEL_GEN(uncore->i915) <= 8) {
> > > + } else if (GRAPHICS_VER(uncore->i915) <= 8) {
> > > /*
> > > * PRMs say:
> > > *
> > > @@ -94,7 +94,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> > > * rolling over every 1.5 hours).
> > > */
> > > return f12_5_mhz;
> > > - } else if (INTEL_GEN(uncore->i915) <= 9) {
> > > + } else if (GRAPHICS_VER(uncore->i915) <= 9) {
> > > u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> > > u32 freq = 0;
> > >
> > > @@ -113,7 +113,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> > > }
> > >
> > > return freq;
> > > - } else if (INTEL_GEN(uncore->i915) <= 12) {
> > > + } else if (GRAPHICS_VER(uncore->i915) <= 12) {
> > > u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> > > u32 freq = 0;
> > >
> > > @@ -128,7 +128,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> > > } else {
> > > u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
> > >
> > > - if (INTEL_GEN(uncore->i915) <= 10)
> > > + if (GRAPHICS_VER(uncore->i915) <= 10)
> > > freq = gen10_get_crystal_clock_freq(uncore, c0);
> > > else
> > > freq = gen11_get_crystal_clock_freq(uncore, c0);
> > > @@ -211,7 +211,7 @@ u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns)
> > > * frozen machine.
> > > */
> > > val = div_u64_roundup(intel_gt_ns_to_clock_interval(gt, ns), 16);
> > > - if (IS_GEN(gt->i915, 6))
> > > + if (GRAPHICS_VER(gt->i915) == 6)
> > > val = div_u64_roundup(val, 25) * 25;
> > >
> > > return val;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> > > index d29126c458ba..1ec63cceabf6 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> > > @@ -395,7 +395,7 @@ void gen5_gt_irq_reset(struct intel_gt *gt)
> > > struct intel_uncore *uncore = gt->uncore;
> > >
> > > GEN3_IRQ_RESET(uncore, GT);
> > > - if (INTEL_GEN(gt->i915) >= 6)
> > > + if (GRAPHICS_VER(gt->i915) >= 6)
> > > GEN3_IRQ_RESET(uncore, GEN6_PM);
> > > }
> > >
> > > @@ -413,14 +413,14 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt)
> > > }
> > >
> > > gt_irqs |= GT_RENDER_USER_INTERRUPT;
> > > - if (IS_GEN(gt->i915, 5))
> > > + if (GRAPHICS_VER(gt->i915) == 5)
> > > gt_irqs |= ILK_BSD_USER_INTERRUPT;
> > > else
> > > gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
> > >
> > > GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs);
> > >
> > > - if (INTEL_GEN(gt->i915) >= 6) {
> > > + if (GRAPHICS_VER(gt->i915) >= 6) {
> > > /*
> > > * RPS interrupts will get enabled/disabled on demand when RPS
> > > * itself is enabled/disabled.
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
> > > index 811a11ed181c..fe51f894b073 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
> > > @@ -16,10 +16,10 @@ static void write_pm_imr(struct intel_gt *gt)
> > > u32 mask = gt->pm_imr;
> > > i915_reg_t reg;
> > >
> > > - if (INTEL_GEN(i915) >= 11) {
> > > + if (GRAPHICS_VER(i915) >= 11) {
> > > reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
> > > mask <<= 16; /* pm is in upper half */
> > > - } else if (INTEL_GEN(i915) >= 8) {
> > > + } else if (GRAPHICS_VER(i915) >= 8) {
> > > reg = GEN8_GT_IMR(2);
> > > } else {
> > > reg = GEN6_PMIMR;
> > > @@ -61,7 +61,7 @@ void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask)
> > > void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)
> > > {
> > > struct intel_uncore *uncore = gt->uncore;
> > > - i915_reg_t reg = INTEL_GEN(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
> > > + i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
> > >
> > > lockdep_assert_held(>->irq_lock);
> > >
> > > @@ -77,10 +77,10 @@ static void write_pm_ier(struct intel_gt *gt)
> > > u32 mask = gt->pm_ier;
> > > i915_reg_t reg;
> > >
> > > - if (INTEL_GEN(i915) >= 11) {
> > > + if (GRAPHICS_VER(i915) >= 11) {
> > > reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
> > > mask <<= 16; /* pm is in upper half */
> > > - } else if (INTEL_GEN(i915) >= 8) {
> > > + } else if (GRAPHICS_VER(i915) >= 8) {
> > > reg = GEN8_GT_IER(2);
> > > } else {
> > > reg = GEN6_PMIER;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > index 9b98f9d9faa3..b9c9993573ec 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > @@ -327,7 +327,7 @@ void gtt_write_workarounds(struct intel_gt *gt)
> > > intel_uncore_write(uncore,
> > > GEN8_L3_LRA_1_GPGPU,
> > > GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> > > - else if (INTEL_GEN(i915) >= 9 && INTEL_GEN(i915) <= 11)
> > > + else if (GRAPHICS_VER(i915) >= 9 && GRAPHICS_VER(i915) <= 11)
> > > intel_uncore_write(uncore,
> > > GEN8_L3_LRA_1_GPGPU,
> > > GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> > > @@ -344,13 +344,13 @@ void gtt_write_workarounds(struct intel_gt *gt)
> > > * driver.
> > > */
> > > if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
> > > - INTEL_GEN(i915) <= 10)
> > > + GRAPHICS_VER(i915) <= 10)
> > > intel_uncore_rmw(uncore,
> > > GEN8_GAMW_ECO_DEV_RW_IA,
> > > 0,
> > > GAMW_ECO_ENABLE_64K_IPS_FIELD);
> > >
> > > - if (IS_GEN_RANGE(i915, 8, 11)) {
> > > + if (IS_GRAPHICS_VER(i915, 8, 11)) {
> > > bool can_use_gtt_cache = true;
> > >
> > > /*
> > > @@ -432,7 +432,7 @@ static void bdw_setup_private_ppat(struct intel_uncore *uncore)
> > > GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
> > >
> > > /* for scanout with eLLC */
> > > - if (INTEL_GEN(i915) >= 9)
> > > + if (GRAPHICS_VER(i915) >= 9)
> > > pat |= GEN8_PPAT(2, GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE);
> > > else
> > > pat |= GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
> > > @@ -481,11 +481,11 @@ void setup_private_pat(struct intel_uncore *uncore)
> > > {
> > > struct drm_i915_private *i915 = uncore->i915;
> > >
> > > - GEM_BUG_ON(INTEL_GEN(i915) < 8);
> > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
> > >
> > > - if (INTEL_GEN(i915) >= 12)
> > > + if (GRAPHICS_VER(i915) >= 12)
> > > tgl_setup_private_ppat(uncore);
> > > - else if (INTEL_GEN(i915) >= 10)
> > > + else if (GRAPHICS_VER(i915) >= 10)
> > > cnl_setup_private_ppat(uncore);
> > > else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))
> > > chv_setup_private_ppat(uncore);
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
> > > index 075d741644ae..eb1a15deed22 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_llc.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_llc.c
> > > @@ -64,7 +64,7 @@ static bool get_ia_constants(struct intel_llc *llc,
> > >
> > > consts->min_gpu_freq = rps->min_freq;
> > > consts->max_gpu_freq = rps->max_freq;
> > > - if (INTEL_GEN(i915) >= 9) {
> > > + if (GRAPHICS_VER(i915) >= 9) {
> > > /* Convert GT frequency to 50 HZ units */
> > > consts->min_gpu_freq /= GEN9_FREQ_SCALER;
> > > consts->max_gpu_freq /= GEN9_FREQ_SCALER;
> > > @@ -83,13 +83,13 @@ static void calc_ia_freq(struct intel_llc *llc,
> > > const int diff = consts->max_gpu_freq - gpu_freq;
> > > unsigned int ia_freq = 0, ring_freq = 0;
> > >
> > > - if (INTEL_GEN(i915) >= 9) {
> > > + if (GRAPHICS_VER(i915) >= 9) {
> > > /*
> > > * ring_freq = 2 * GT. ring_freq is in 100MHz units
> > > * No floor required for ring frequency on SKL.
> > > */
> > > ring_freq = gpu_freq;
> > > - } else if (INTEL_GEN(i915) >= 8) {
> > > + } else if (GRAPHICS_VER(i915) >= 8) {
> > > /* max(2 * GT, DDR). NB: GT is 50MHz units */
> > > ring_freq = max(consts->min_ring_freq, gpu_freq);
> > > } else if (IS_HASWELL(i915)) {
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > index aafe2a4df496..a27bac0a4bfb 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > @@ -47,7 +47,7 @@ static void set_offsets(u32 *regs,
> > > *regs = MI_LOAD_REGISTER_IMM(count);
> > > if (flags & POSTED)
> > > *regs |= MI_LRI_FORCE_POSTED;
> > > - if (INTEL_GEN(engine->i915) >= 11)
> > > + if (GRAPHICS_VER(engine->i915) >= 11)
> > > *regs |= MI_LRI_LRM_CS_MMIO;
> > > regs++;
> > >
> > > @@ -70,7 +70,7 @@ static void set_offsets(u32 *regs,
> > > if (close) {
> > > /* Close the batch; used mainly by live_lrc_layout() */
> > > *regs = MI_BATCH_BUFFER_END;
> > > - if (INTEL_GEN(engine->i915) >= 10)
> > > + if (GRAPHICS_VER(engine->i915) >= 10)
> > > *regs |= BIT(0);
> > > }
> > > }
> > > @@ -498,22 +498,22 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> > > * addressing to automatic fixup the register state between the
> > > * physical engines for virtual engine.
> > > */
> > > - GEM_BUG_ON(INTEL_GEN(engine->i915) >= 12 &&
> > > + GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
> > > !intel_engine_has_relative_mmio(engine));
> > >
> > > if (engine->class == RENDER_CLASS) {
> > > - if (INTEL_GEN(engine->i915) >= 12)
> > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > return gen12_rcs_offsets;
> > > - else if (INTEL_GEN(engine->i915) >= 11)
> > > + else if (GRAPHICS_VER(engine->i915) >= 11)
> > > return gen11_rcs_offsets;
> > > - else if (INTEL_GEN(engine->i915) >= 9)
> > > + else if (GRAPHICS_VER(engine->i915) >= 9)
> > > return gen9_rcs_offsets;
> > > else
> > > return gen8_rcs_offsets;
> > > } else {
> > > - if (INTEL_GEN(engine->i915) >= 12)
> > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > return gen12_xcs_offsets;
> > > - else if (INTEL_GEN(engine->i915) >= 9)
> > > + else if (GRAPHICS_VER(engine->i915) >= 9)
> > > return gen9_xcs_offsets;
> > > else
> > > return gen8_xcs_offsets;
> > > @@ -522,9 +522,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> > >
> > > static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
> > > {
> > > - if (INTEL_GEN(engine->i915) >= 12)
> > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > return 0x60;
> > > - else if (INTEL_GEN(engine->i915) >= 9)
> > > + else if (GRAPHICS_VER(engine->i915) >= 9)
> > > return 0x54;
> > > else if (engine->class == RENDER_CLASS)
> > > return 0x58;
> > > @@ -534,9 +534,9 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
> > >
> > > static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
> > > {
> > > - if (INTEL_GEN(engine->i915) >= 12)
> > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > return 0x74;
> > > - else if (INTEL_GEN(engine->i915) >= 9)
> > > + else if (GRAPHICS_VER(engine->i915) >= 9)
> > > return 0x68;
> > > else if (engine->class == RENDER_CLASS)
> > > return 0xd8;
> > > @@ -546,9 +546,9 @@ static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
> > >
> > > static int lrc_ring_wa_bb_per_ctx(const struct intel_engine_cs *engine)
> > > {
> > > - if (INTEL_GEN(engine->i915) >= 12)
> > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > return 0x12;
> > > - else if (INTEL_GEN(engine->i915) >= 9 || engine->class == RENDER_CLASS)
> > > + else if (GRAPHICS_VER(engine->i915) >= 9 || engine->class == RENDER_CLASS)
> > > return 0x18;
> > > else
> > > return -1;
> > > @@ -581,9 +581,9 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
> > > if (engine->class != RENDER_CLASS)
> > > return -1;
> > >
> > > - if (INTEL_GEN(engine->i915) >= 12)
> > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > return 0xb6;
> > > - else if (INTEL_GEN(engine->i915) >= 11)
> > > + else if (GRAPHICS_VER(engine->i915) >= 11)
> > > return 0xaa;
> > > else
> > > return -1;
> > > @@ -592,9 +592,9 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
> > > static u32
> > > lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
> > > {
> > > - switch (INTEL_GEN(engine->i915)) {
> > > + switch (GRAPHICS_VER(engine->i915)) {
> > > default:
> > > - MISSING_CASE(INTEL_GEN(engine->i915));
> > > + MISSING_CASE(GRAPHICS_VER(engine->i915));
> > > fallthrough;
> > > case 12:
> > > return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> > > @@ -637,7 +637,7 @@ static void init_common_regs(u32 * const regs,
> > > ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
> > > if (inhibit)
> > > ctl |= CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT;
> > > - if (INTEL_GEN(engine->i915) < 11)
> > > + if (GRAPHICS_VER(engine->i915) < 11)
> > > ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
> > > CTX_CTRL_RS_CTX_ENABLE);
> > > regs[CTX_CONTEXT_CONTROL] = ctl;
> > > @@ -805,7 +805,7 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
> > > if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> > > context_size += I915_GTT_PAGE_SIZE; /* for redzone */
> > >
> > > - if (INTEL_GEN(engine->i915) == 12) {
> > > + if (GRAPHICS_VER(engine->i915) == 12) {
> > > ce->wa_bb_page = context_size / PAGE_SIZE;
> > > context_size += PAGE_SIZE;
> > > }
> > > @@ -1114,7 +1114,7 @@ static u32 lrc_descriptor(const struct intel_context *ce)
> > > desc <<= GEN8_CTX_ADDRESSING_MODE_SHIFT;
> > >
> > > desc |= GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
> > > - if (IS_GEN(ce->vm->i915, 8))
> > > + if (GRAPHICS_VER(ce->vm->i915) == 8)
> > > desc |= GEN8_CTX_L3LLC_COHERENT;
> > >
> > > return i915_ggtt_offset(ce->state) | desc;
> > > @@ -1469,7 +1469,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
> > > if (engine->class != RENDER_CLASS)
> > > return;
> > >
> > > - switch (INTEL_GEN(engine->i915)) {
> > > + switch (GRAPHICS_VER(engine->i915)) {
> > > case 12:
> > > case 11:
> > > return;
> > > @@ -1486,7 +1486,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
> > > wa_bb_fn[1] = NULL;
> > > break;
> > > default:
> > > - MISSING_CASE(INTEL_GEN(engine->i915));
> > > + MISSING_CASE(GRAPHICS_VER(engine->i915));
> > > return;
> > > }
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > > index b14138fd505c..17848807f111 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > > @@ -344,11 +344,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> > > table->size = ARRAY_SIZE(dg1_mocs_table);
> > > table->table = dg1_mocs_table;
> > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> > > - } else if (INTEL_GEN(i915) >= 12) {
> > > + } else if (GRAPHICS_VER(i915) >= 12) {
> > > table->size = ARRAY_SIZE(tgl_mocs_table);
> > > table->table = tgl_mocs_table;
> > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> > > - } else if (IS_GEN(i915, 11)) {
> > > + } else if (GRAPHICS_VER(i915) == 11) {
> > > table->size = ARRAY_SIZE(icl_mocs_table);
> > > table->table = icl_mocs_table;
> > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> > > @@ -361,7 +361,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> > > table->table = broxton_mocs_table;
> > > } else {
> > > - drm_WARN_ONCE(&i915->drm, INTEL_GEN(i915) >= 9,
> > > + drm_WARN_ONCE(&i915->drm, GRAPHICS_VER(i915) >= 9,
> > > "Platform that should have a MOCS table does not.\n");
> > > return 0;
> > > }
> > > @@ -370,7 +370,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> > > return 0;
> > >
> > > /* WaDisableSkipCaching:skl,bxt,kbl,glk */
> > > - if (IS_GEN(i915, 9)) {
> > > + if (GRAPHICS_VER(i915) == 9) {
> > > int i;
> > >
> > > for (i = 0; i < table->size; i++)
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> > > index 4e3d80c2295c..3891c078906e 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> > > @@ -146,9 +146,9 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
> > >
> > > gtt_write_workarounds(gt);
> > >
> > > - if (IS_GEN(i915, 6))
> > > + if (GRAPHICS_VER(i915) == 6)
> > > gen6_ppgtt_enable(gt);
> > > - else if (IS_GEN(i915, 7))
> > > + else if (GRAPHICS_VER(i915) == 7)
> > > gen7_ppgtt_enable(gt);
> > >
> > > return 0;
> > > @@ -157,7 +157,7 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
> > > static struct i915_ppgtt *
> > > __ppgtt_create(struct intel_gt *gt)
> > > {
> > > - if (INTEL_GEN(gt->i915) < 8)
> > > + if (GRAPHICS_VER(gt->i915) < 8)
> > > return gen6_ppgtt_create(gt);
> > > else
> > > return gen8_ppgtt_create(gt);
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> > > index 3b7e62debe7e..259d7eb4e165 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> > > @@ -109,7 +109,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
> > > GEN9_MEDIA_PG_ENABLE |
> > > GEN11_MEDIA_SAMPLER_PG_ENABLE;
> > >
> > > - if (INTEL_GEN(gt->i915) >= 12) {
> > > + if (GRAPHICS_VER(gt->i915) >= 12) {
> > > for (i = 0; i < I915_MAX_VCS; i++)
> > > if (HAS_ENGINE(gt, _VCS(i)))
> > > pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
> > > @@ -126,7 +126,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
> > > enum intel_engine_id id;
> > >
> > > /* 2b: Program RC6 thresholds.*/
> > > - if (INTEL_GEN(rc6_to_i915(rc6)) >= 10) {
> > > + if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 10) {
> > > set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> > > set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
> > > } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
> > > @@ -249,9 +249,9 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
> > > rc6vids = 0;
> > > ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
> > > &rc6vids, NULL);
> > > - if (IS_GEN(i915, 6) && ret) {
> > > + if (GRAPHICS_VER(i915) == 6 && ret) {
> > > drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
> > > - } else if (IS_GEN(i915, 6) &&
> > > + } else if (GRAPHICS_VER(i915) == 6 &&
> > > (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
> > > drm_dbg(&i915->drm,
> > > "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
> > > @@ -515,7 +515,7 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
> > > struct intel_uncore *uncore = rc6_to_uncore(rc6);
> > >
> > > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> > > - if (INTEL_GEN(i915) >= 9)
> > > + if (GRAPHICS_VER(i915) >= 9)
> > > set(uncore, GEN9_PG_ENABLE, 0);
> > > set(uncore, GEN6_RC_CONTROL, 0);
> > > set(uncore, GEN6_RC_STATE, 0);
> > > @@ -575,13 +575,13 @@ void intel_rc6_enable(struct intel_rc6 *rc6)
> > > chv_rc6_enable(rc6);
> > > else if (IS_VALLEYVIEW(i915))
> > > vlv_rc6_enable(rc6);
> > > - else if (INTEL_GEN(i915) >= 11)
> > > + else if (GRAPHICS_VER(i915) >= 11)
> > > gen11_rc6_enable(rc6);
> > > - else if (INTEL_GEN(i915) >= 9)
> > > + else if (GRAPHICS_VER(i915) >= 9)
> > > gen9_rc6_enable(rc6);
> > > else if (IS_BROADWELL(i915))
> > > gen8_rc6_enable(rc6);
> > > - else if (INTEL_GEN(i915) >= 6)
> > > + else if (GRAPHICS_VER(i915) >= 6)
> > > gen6_rc6_enable(rc6);
> > >
> > > rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
> > > index b03e197b1d99..b575cd6e0b7a 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
> > > @@ -15,7 +15,7 @@ render_state_get_rodata(const struct intel_engine_cs *engine)
> > > if (engine->class != RENDER_CLASS)
> > > return NULL;
> > >
> > > - switch (INTEL_GEN(engine->i915)) {
> > > + switch (GRAPHICS_VER(engine->i915)) {
> > > case 6:
> > > return &gen6_null_state;
> > > case 7:
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> > > index d5094be6d90f..27315d7f8935 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > > @@ -565,7 +565,7 @@ static int gen8_reset_engines(struct intel_gt *gt,
> > > */
> > > }
> > >
> > > - if (INTEL_GEN(gt->i915) >= 11)
> > > + if (GRAPHICS_VER(gt->i915) >= 11)
> > > ret = gen11_reset_engines(gt, engine_mask, retry);
> > > else
> > > ret = gen6_reset_engines(gt, engine_mask, retry);
> > > @@ -594,17 +594,17 @@ static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
> > >
> > > if (is_mock_gt(gt))
> > > return mock_reset;
> > > - else if (INTEL_GEN(i915) >= 8)
> > > + else if (GRAPHICS_VER(i915) >= 8)
> > > return gen8_reset_engines;
> > > - else if (INTEL_GEN(i915) >= 6)
> > > + else if (GRAPHICS_VER(i915) >= 6)
> > > return gen6_reset_engines;
> > > - else if (INTEL_GEN(i915) >= 5)
> > > + else if (GRAPHICS_VER(i915) >= 5)
> > > return ilk_do_reset;
> > > else if (IS_G4X(i915))
> > > return g4x_do_reset;
> > > else if (IS_G33(i915) || IS_PINEVIEW(i915))
> > > return g33_do_reset;
> > > - else if (INTEL_GEN(i915) >= 3)
> > > + else if (GRAPHICS_VER(i915) >= 3)
> > > return i915_do_reset;
> > > else
> > > return NULL;
> > > @@ -656,7 +656,7 @@ bool intel_has_reset_engine(const struct intel_gt *gt)
> > > int intel_reset_guc(struct intel_gt *gt)
> > > {
> > > u32 guc_domain =
> > > - INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
> > > + GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
> > > int ret;
> > >
> > > GEM_BUG_ON(!HAS_GT_UC(gt->i915));
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > > index 2b6dffcc2262..0c423f096e2b 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > > @@ -29,7 +29,7 @@ static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
> > > * lost interrupts following a reset.
> > > */
> > > if (engine->class == RENDER_CLASS) {
> > > - if (INTEL_GEN(engine->i915) >= 6)
> > > + if (GRAPHICS_VER(engine->i915) >= 6)
> > > mask &= ~BIT(0);
> > > else
> > > mask &= ~I915_USER_INTERRUPT;
> > > @@ -43,7 +43,7 @@ static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
> > > u32 addr;
> > >
> > > addr = lower_32_bits(phys);
> > > - if (INTEL_GEN(engine->i915) >= 4)
> > > + if (GRAPHICS_VER(engine->i915) >= 4)
> > > addr |= (phys >> 28) & 0xf0;
> > >
> > > intel_uncore_write(engine->uncore, HWS_PGA, addr);
> > > @@ -71,7 +71,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
> > > * The ring status page addresses are no longer next to the rest of
> > > * the ring registers as of gen7.
> > > */
> > > - if (IS_GEN(engine->i915, 7)) {
> > > + if (GRAPHICS_VER(engine->i915) == 7) {
> > > switch (engine->id) {
> > > /*
> > > * No more rings exist on Gen7. Default case is only to shut up
> > > @@ -93,7 +93,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
> > > hwsp = VEBOX_HWS_PGA_GEN7;
> > > break;
> > > }
> > > - } else if (IS_GEN(engine->i915, 6)) {
> > > + } else if (GRAPHICS_VER(engine->i915) == 6) {
> > > hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
> > > } else {
> > > hwsp = RING_HWS_PGA(engine->mmio_base);
> > > @@ -105,7 +105,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
> > >
> > > static void flush_cs_tlb(struct intel_engine_cs *engine)
> > > {
> > > - if (!IS_GEN_RANGE(engine->i915, 6, 7))
> > > + if (!IS_GRAPHICS_VER(engine->i915, 6, 7))
> > > return;
> > >
> > > /* ring should be idle before issuing a sync flush*/
> > > @@ -153,7 +153,7 @@ static void set_pp_dir(struct intel_engine_cs *engine)
> > > ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
> > > ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm));
> > >
> > > - if (INTEL_GEN(engine->i915) >= 7) {
> > > + if (GRAPHICS_VER(engine->i915) >= 7) {
> > > ENGINE_WRITE_FW(engine,
> > > RING_MODE_GEN7,
> > > _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> > > @@ -229,7 +229,7 @@ static int xcs_resume(struct intel_engine_cs *engine)
> > > 5000, 0, NULL))
> > > goto err;
> > >
> > > - if (INTEL_GEN(engine->i915) > 2)
> > > + if (GRAPHICS_VER(engine->i915) > 2)
> > > ENGINE_WRITE_FW(engine,
> > > RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
> > >
> > > @@ -646,9 +646,9 @@ static int mi_set_context(struct i915_request *rq,
> > > u32 *cs;
> > >
> > > len = 4;
> > > - if (IS_GEN(i915, 7))
> > > + if (GRAPHICS_VER(i915) == 7)
> > > len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
> > > - else if (IS_GEN(i915, 5))
> > > + else if (GRAPHICS_VER(i915) == 5)
> > > len += 2;
> > > if (flags & MI_FORCE_RESTORE) {
> > > GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
> > > @@ -662,7 +662,7 @@ static int mi_set_context(struct i915_request *rq,
> > > return PTR_ERR(cs);
> > >
> > > /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
> > > - if (IS_GEN(i915, 7)) {
> > > + if (GRAPHICS_VER(i915) == 7) {
> > > *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> > > if (num_engines) {
> > > struct intel_engine_cs *signaller;
> > > @@ -678,7 +678,7 @@ static int mi_set_context(struct i915_request *rq,
> > > GEN6_PSMI_SLEEP_MSG_DISABLE);
> > > }
> > > }
> > > - } else if (IS_GEN(i915, 5)) {
> > > + } else if (GRAPHICS_VER(i915) == 5) {
> > > /*
> > > * This w/a is only listed for pre-production ilk a/b steppings,
> > > * but is also mentioned for programming the powerctx. To be
> > > @@ -716,7 +716,7 @@ static int mi_set_context(struct i915_request *rq,
> > > */
> > > *cs++ = MI_NOOP;
> > >
> > > - if (IS_GEN(i915, 7)) {
> > > + if (GRAPHICS_VER(i915) == 7) {
> > > if (num_engines) {
> > > struct intel_engine_cs *signaller;
> > > i915_reg_t last_reg = {}; /* keep gcc quiet */
> > > @@ -740,7 +740,7 @@ static int mi_set_context(struct i915_request *rq,
> > > *cs++ = MI_NOOP;
> > > }
> > > *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
> > > - } else if (IS_GEN(i915, 5)) {
> > > + } else if (GRAPHICS_VER(i915) == 5) {
> > > *cs++ = MI_SUSPEND_FLUSH;
> > > }
> > >
> > > @@ -1001,7 +1001,7 @@ static void ring_release(struct intel_engine_cs *engine)
> > > {
> > > struct drm_i915_private *dev_priv = engine->i915;
> > >
> > > - drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) > 2 &&
> > > + drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) > 2 &&
> > > (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
> > >
> > > intel_engine_cleanup_common(engine);
> > > @@ -1029,13 +1029,13 @@ static void setup_irq(struct intel_engine_cs *engine)
> > >
> > > intel_engine_set_irq_handler(engine, irq_handler);
> > >
> > > - if (INTEL_GEN(i915) >= 6) {
> > > + if (GRAPHICS_VER(i915) >= 6) {
> > > engine->irq_enable = gen6_irq_enable;
> > > engine->irq_disable = gen6_irq_disable;
> > > - } else if (INTEL_GEN(i915) >= 5) {
> > > + } else if (GRAPHICS_VER(i915) >= 5) {
> > > engine->irq_enable = gen5_irq_enable;
> > > engine->irq_disable = gen5_irq_disable;
> > > - } else if (INTEL_GEN(i915) >= 3) {
> > > + } else if (GRAPHICS_VER(i915) >= 3) {
> > > engine->irq_enable = gen3_irq_enable;
> > > engine->irq_disable = gen3_irq_disable;
> > > } else {
> > > @@ -1049,7 +1049,7 @@ static void setup_common(struct intel_engine_cs *engine)
> > > struct drm_i915_private *i915 = engine->i915;
> > >
> > > /* gen8+ are only supported with execlists */
> > > - GEM_BUG_ON(INTEL_GEN(i915) >= 8);
> > > + GEM_BUG_ON(GRAPHICS_VER(i915) >= 8);
> > >
> > > setup_irq(engine);
> > >
> > > @@ -1070,14 +1070,14 @@ static void setup_common(struct intel_engine_cs *engine)
> > > * engine->emit_init_breadcrumb().
> > > */
> > > engine->emit_fini_breadcrumb = gen3_emit_breadcrumb;
> > > - if (IS_GEN(i915, 5))
> > > + if (GRAPHICS_VER(i915) == 5)
> > > engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
> > >
> > > engine->set_default_submission = i9xx_set_default_submission;
> > >
> > > - if (INTEL_GEN(i915) >= 6)
> > > + if (GRAPHICS_VER(i915) >= 6)
> > > engine->emit_bb_start = gen6_emit_bb_start;
> > > - else if (INTEL_GEN(i915) >= 4)
> > > + else if (GRAPHICS_VER(i915) >= 4)
> > > engine->emit_bb_start = gen4_emit_bb_start;
> > > else if (IS_I830(i915) || IS_I845G(i915))
> > > engine->emit_bb_start = i830_emit_bb_start;
> > > @@ -1094,16 +1094,16 @@ static void setup_rcs(struct intel_engine_cs *engine)
> > >
> > > engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
> > >
> > > - if (INTEL_GEN(i915) >= 7) {
> > > + if (GRAPHICS_VER(i915) >= 7) {
> > > engine->emit_flush = gen7_emit_flush_rcs;
> > > engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs;
> > > - } else if (IS_GEN(i915, 6)) {
> > > + } else if (GRAPHICS_VER(i915) == 6) {
> > > engine->emit_flush = gen6_emit_flush_rcs;
> > > engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs;
> > > - } else if (IS_GEN(i915, 5)) {
> > > + } else if (GRAPHICS_VER(i915) == 5) {
> > > engine->emit_flush = gen4_emit_flush_rcs;
> > > } else {
> > > - if (INTEL_GEN(i915) < 4)
> > > + if (GRAPHICS_VER(i915) < 4)
> > > engine->emit_flush = gen2_emit_flush;
> > > else
> > > engine->emit_flush = gen4_emit_flush_rcs;
> > > @@ -1118,20 +1118,20 @@ static void setup_vcs(struct intel_engine_cs *engine)
> > > {
> > > struct drm_i915_private *i915 = engine->i915;
> > >
> > > - if (INTEL_GEN(i915) >= 6) {
> > > + if (GRAPHICS_VER(i915) >= 6) {
> > > /* gen6 bsd needs a special wa for tail updates */
> > > - if (IS_GEN(i915, 6))
> > > + if (GRAPHICS_VER(i915) == 6)
> > > engine->set_default_submission = gen6_bsd_set_default_submission;
> > > engine->emit_flush = gen6_emit_flush_vcs;
> > > engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
> > >
> > > - if (IS_GEN(i915, 6))
> > > + if (GRAPHICS_VER(i915) == 6)
> > > engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
> > > else
> > > engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
> > > } else {
> > > engine->emit_flush = gen4_emit_flush_vcs;
> > > - if (IS_GEN(i915, 5))
> > > + if (GRAPHICS_VER(i915) == 5)
> > > engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
> > > else
> > > engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
> > > @@ -1145,7 +1145,7 @@ static void setup_bcs(struct intel_engine_cs *engine)
> > > engine->emit_flush = gen6_emit_flush_xcs;
> > > engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
> > >
> > > - if (IS_GEN(i915, 6))
> > > + if (GRAPHICS_VER(i915) == 6)
> > > engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
> > > else
> > > engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
> > > @@ -1155,7 +1155,7 @@ static void setup_vecs(struct intel_engine_cs *engine)
> > > {
> > > struct drm_i915_private *i915 = engine->i915;
> > >
> > > - GEM_BUG_ON(INTEL_GEN(i915) < 7);
> > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 7);
> > >
> > > engine->emit_flush = gen6_emit_flush_xcs;
> > > engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
> > > @@ -1203,7 +1203,7 @@ static struct i915_vma *gen7_ctx_vma(struct intel_engine_cs *engine)
> > > struct i915_vma *vma;
> > > int size, err;
> > >
> > > - if (!IS_GEN(engine->i915, 7) || engine->class != RENDER_CLASS)
> > > + if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS)
> > > return 0;
> > >
> > > err = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */);
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> > > index 97cab1b99871..06e9a8ed4e03 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> > > @@ -196,7 +196,7 @@ static void rps_reset_interrupts(struct intel_rps *rps)
> > > struct intel_gt *gt = rps_to_gt(rps);
> > >
> > > spin_lock_irq(>->irq_lock);
> > > - if (INTEL_GEN(gt->i915) >= 11)
> > > + if (GRAPHICS_VER(gt->i915) >= 11)
> > > gen11_rps_reset_interrupts(rps);
> > > else
> > > gen6_rps_reset_interrupts(rps);
> > > @@ -630,7 +630,7 @@ static u32 rps_limits(struct intel_rps *rps, u8 val)
> > > * frequency, if the down threshold expires in that window we will not
> > > * receive a down interrupt.
> > > */
> > > - if (INTEL_GEN(rps_to_i915(rps)) >= 9) {
> > > + if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) {
> > > limits = rps->max_freq_softlimit << 23;
> > > if (val <= rps->min_freq_softlimit)
> > > limits |= rps->min_freq_softlimit << 14;
> > > @@ -697,7 +697,7 @@ static void rps_set_power(struct intel_rps *rps, int new_power)
> > > intel_gt_ns_to_pm_interval(gt, ei_down * threshold_down * 10));
> > >
> > > set(uncore, GEN6_RP_CONTROL,
> > > - (INTEL_GEN(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
> > > + (GRAPHICS_VER(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
> > > GEN6_RP_MEDIA_HW_NORMAL_MODE |
> > > GEN6_RP_MEDIA_IS_GFX |
> > > GEN6_RP_ENABLE |
> > > @@ -771,7 +771,7 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val)
> > > struct drm_i915_private *i915 = rps_to_i915(rps);
> > > u32 swreq;
> > >
> > > - if (INTEL_GEN(i915) >= 9)
> > > + if (GRAPHICS_VER(i915) >= 9)
> > > swreq = GEN9_FREQUENCY(val);
> > > else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> > > swreq = HSW_FREQUENCY(val);
> > > @@ -812,14 +812,14 @@ static int rps_set(struct intel_rps *rps, u8 val, bool update)
> > >
> > > if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > > err = vlv_rps_set(rps, val);
> > > - else if (INTEL_GEN(i915) >= 6)
> > > + else if (GRAPHICS_VER(i915) >= 6)
> > > err = gen6_rps_set(rps, val);
> > > else
> > > err = gen5_rps_set(rps, val);
> > > if (err)
> > > return err;
> > >
> > > - if (update && INTEL_GEN(i915) >= 6)
> > > + if (update && GRAPHICS_VER(i915) >= 6)
> > > gen6_rps_set_thresholds(rps, val);
> > > rps->last_freq = val;
> > >
> > > @@ -853,7 +853,7 @@ void intel_rps_unpark(struct intel_rps *rps)
> > > if (intel_rps_uses_timer(rps))
> > > rps_start_timer(rps);
> > >
> > > - if (IS_GEN(rps_to_i915(rps), 5))
> > > + if (GRAPHICS_VER(rps_to_i915(rps)) == 5)
> > > gen5_rps_update(rps);
> > > }
> > >
> > > @@ -999,7 +999,7 @@ static void gen6_rps_init(struct intel_rps *rps)
> > >
> > > rps->efficient_freq = rps->rp1_freq;
> > > if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
> > > - IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
> > > + IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
> > > u32 ddcc_status = 0;
> > >
> > > if (sandybridge_pcode_read(i915,
> > > @@ -1012,7 +1012,7 @@ static void gen6_rps_init(struct intel_rps *rps)
> > > rps->max_freq);
> > > }
> > >
> > > - if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
> > > + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
> > > /* Store the frequency values in 16.66 MHZ units, which is
> > > * the natural hardware unit for SKL
> > > */
> > > @@ -1048,7 +1048,7 @@ static bool gen9_rps_enable(struct intel_rps *rps)
> > > struct intel_uncore *uncore = gt->uncore;
> > >
> > > /* Program defaults and thresholds for RPS */
> > > - if (IS_GEN(gt->i915, 9))
> > > + if (GRAPHICS_VER(gt->i915) == 9)
> > > intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ,
> > > GEN9_FREQUENCY(rps->rp1_freq));
> > >
> > > @@ -1365,16 +1365,16 @@ void intel_rps_enable(struct intel_rps *rps)
> > > enabled = chv_rps_enable(rps);
> > > else if (IS_VALLEYVIEW(i915))
> > > enabled = vlv_rps_enable(rps);
> > > - else if (INTEL_GEN(i915) >= 9)
> > > + else if (GRAPHICS_VER(i915) >= 9)
> > > enabled = gen9_rps_enable(rps);
> > > - else if (INTEL_GEN(i915) >= 8)
> > > + else if (GRAPHICS_VER(i915) >= 8)
> > > enabled = gen8_rps_enable(rps);
> > > - else if (INTEL_GEN(i915) >= 6)
> > > + else if (GRAPHICS_VER(i915) >= 6)
> > > enabled = gen6_rps_enable(rps);
> > > else if (IS_IRONLAKE_M(i915))
> > > enabled = gen5_rps_enable(rps);
> > > else
> > > - MISSING_CASE(INTEL_GEN(i915));
> > > + MISSING_CASE(GRAPHICS_VER(i915));
> > > intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> > > if (!enabled)
> > > return;
> > > @@ -1393,7 +1393,7 @@ void intel_rps_enable(struct intel_rps *rps)
> > >
> > > if (has_busy_stats(rps))
> > > intel_rps_set_timer(rps);
> > > - else if (INTEL_GEN(i915) >= 6)
> > > + else if (GRAPHICS_VER(i915) >= 6)
> > > intel_rps_set_interrupts(rps);
> > > else
> > > /* Ironlake currently uses intel_ips.ko */ {}
> > > @@ -1414,7 +1414,7 @@ void intel_rps_disable(struct intel_rps *rps)
> > > intel_rps_clear_interrupts(rps);
> > > intel_rps_clear_timer(rps);
> > >
> > > - if (INTEL_GEN(i915) >= 6)
> > > + if (GRAPHICS_VER(i915) >= 6)
> > > gen6_rps_disable(rps);
> > > else if (IS_IRONLAKE_M(i915))
> > > gen5_rps_disable(rps);
> > > @@ -1453,14 +1453,14 @@ int intel_gpu_freq(struct intel_rps *rps, int val)
> > > {
> > > struct drm_i915_private *i915 = rps_to_i915(rps);
> > >
> > > - if (INTEL_GEN(i915) >= 9)
> > > + if (GRAPHICS_VER(i915) >= 9)
> > > return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
> > > GEN9_FREQ_SCALER);
> > > else if (IS_CHERRYVIEW(i915))
> > > return chv_gpu_freq(rps, val);
> > > else if (IS_VALLEYVIEW(i915))
> > > return byt_gpu_freq(rps, val);
> > > - else if (INTEL_GEN(i915) >= 6)
> > > + else if (GRAPHICS_VER(i915) >= 6)
> > > return val * GT_FREQUENCY_MULTIPLIER;
> > > else
> > > return val;
> > > @@ -1470,14 +1470,14 @@ int intel_freq_opcode(struct intel_rps *rps, int val)
> > > {
> > > struct drm_i915_private *i915 = rps_to_i915(rps);
> > >
> > > - if (INTEL_GEN(i915) >= 9)
> > > + if (GRAPHICS_VER(i915) >= 9)
> > > return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
> > > GT_FREQUENCY_MULTIPLIER);
> > > else if (IS_CHERRYVIEW(i915))
> > > return chv_freq_opcode(rps, val);
> > > else if (IS_VALLEYVIEW(i915))
> > > return byt_freq_opcode(rps, val);
> > > - else if (INTEL_GEN(i915) >= 6)
> > > + else if (GRAPHICS_VER(i915) >= 6)
> > > return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
> > > else
> > > return val;
> > > @@ -1770,7 +1770,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
> > > spin_unlock(>->irq_lock);
> > > }
> > >
> > > - if (INTEL_GEN(gt->i915) >= 8)
> > > + if (GRAPHICS_VER(gt->i915) >= 8)
> > > return;
> > >
> > > if (pm_iir & PM_VEBOX_USER_INTERRUPT)
> > > @@ -1833,7 +1833,7 @@ void intel_rps_init(struct intel_rps *rps)
> > > chv_rps_init(rps);
> > > else if (IS_VALLEYVIEW(i915))
> > > vlv_rps_init(rps);
> > > - else if (INTEL_GEN(i915) >= 6)
> > > + else if (GRAPHICS_VER(i915) >= 6)
> > > gen6_rps_init(rps);
> > > else if (IS_IRONLAKE_M(i915))
> > > gen5_rps_init(rps);
> > > @@ -1843,7 +1843,7 @@ void intel_rps_init(struct intel_rps *rps)
> > > rps->min_freq_softlimit = rps->min_freq;
> > >
> > > /* After setting max-softlimit, find the overclock max freq */
> > > - if (IS_GEN(i915, 6) || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
> > > + if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
> > > u32 params = 0;
> > >
> > > sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS,
> > > @@ -1872,16 +1872,16 @@ void intel_rps_init(struct intel_rps *rps)
> > > *
> > > * TODO: verify if this can be reproduced on VLV,CHV.
> > > */
> > > - if (INTEL_GEN(i915) <= 7)
> > > + if (GRAPHICS_VER(i915) <= 7)
> > > rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
> > >
> > > - if (INTEL_GEN(i915) >= 8 && INTEL_GEN(i915) < 11)
> > > + if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) < 11)
> > > rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
> > > }
> > >
> > > void intel_rps_sanitize(struct intel_rps *rps)
> > > {
> > > - if (INTEL_GEN(rps_to_i915(rps)) >= 6)
> > > + if (GRAPHICS_VER(rps_to_i915(rps)) >= 6)
> > > rps_disable_interrupts(rps);
> > > }
> > >
> > > @@ -1892,11 +1892,11 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
> > >
> > > if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > > cagf = (rpstat >> 8) & 0xff;
> > > - else if (INTEL_GEN(i915) >= 9)
> > > + else if (GRAPHICS_VER(i915) >= 9)
> > > cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> > > else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> > > cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
> > > - else if (INTEL_GEN(i915) >= 6)
> > > + else if (GRAPHICS_VER(i915) >= 6)
> > > cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
> > > else
> > > cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >>
> > > @@ -1915,7 +1915,7 @@ static u32 read_cagf(struct intel_rps *rps)
> > > vlv_punit_get(i915);
> > > freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
> > > vlv_punit_put(i915);
> > > - } else if (INTEL_GEN(i915) >= 6) {
> > > + } else if (GRAPHICS_VER(i915) >= 6) {
> > > freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
> > > } else {
> > > freq = intel_uncore_read(uncore, MEMSTAT_ILK);
> > > @@ -1968,7 +1968,7 @@ void intel_rps_driver_register(struct intel_rps *rps)
> > > * We only register the i915 ips part with intel-ips once everything is
> > > * set up, to avoid intel-ips sneaking in and reading bogus values.
> > > */
> > > - if (IS_GEN(gt->i915, 5)) {
> > > + if (GRAPHICS_VER(gt->i915) == 5) {
> > > GEM_BUG_ON(ips_mchdev);
> > > rcu_assign_pointer(ips_mchdev, gt->i915);
> > > ips_ping_for_i915_load();
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > > index 0d9f74aec8fe..367fd44b81c8 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > > @@ -590,13 +590,13 @@ void intel_sseu_info_init(struct intel_gt *gt)
> > > cherryview_sseu_info_init(gt);
> > > else if (IS_BROADWELL(i915))
> > > bdw_sseu_info_init(gt);
> > > - else if (IS_GEN(i915, 9))
> > > + else if (GRAPHICS_VER(i915) == 9)
> > > gen9_sseu_info_init(gt);
> > > - else if (IS_GEN(i915, 10))
> > > + else if (GRAPHICS_VER(i915) == 10)
> > > gen10_sseu_info_init(gt);
> > > - else if (IS_GEN(i915, 11))
> > > + else if (GRAPHICS_VER(i915) == 11)
> > > gen11_sseu_info_init(gt);
> > > - else if (INTEL_GEN(i915) >= 12)
> > > + else if (GRAPHICS_VER(i915) >= 12)
> > > gen12_sseu_info_init(gt);
> > > }
> > >
> > > @@ -613,7 +613,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> > > * No explicit RPCS request is needed to ensure full
> > > * slice/subslice/EU enablement prior to Gen9.
> > > */
> > > - if (INTEL_GEN(i915) < 9)
> > > + if (GRAPHICS_VER(i915) < 9)
> > > return 0;
> > >
> > > /*
> > > @@ -651,7 +651,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> > > * subslices are enabled, or a count between one and four on the first
> > > * slice.
> > > */
> > > - if (IS_GEN(i915, 11) &&
> > > + if (GRAPHICS_VER(i915) == 11 &&
> > > slices == 1 &&
> > > subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
> > > GEM_BUG_ON(subslices & 1);
> > > @@ -669,7 +669,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> > > if (sseu->has_slice_pg) {
> > > u32 mask, val = slices;
> > >
> > > - if (INTEL_GEN(i915) >= 11) {
> > > + if (GRAPHICS_VER(i915) >= 11) {
> > > mask = GEN11_RPCS_S_CNT_MASK;
> > > val <<= GEN11_RPCS_S_CNT_SHIFT;
> > > } else {
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index 62cb9ee5bfc3..b62d1e31a645 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -699,9 +699,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> > >
> > > if (IS_DG1(i915))
> > > dg1_ctx_workarounds_init(engine, wal);
> > > - else if (IS_GEN(i915, 12))
> > > + else if (GRAPHICS_VER(i915) == 12)
> > > gen12_ctx_workarounds_init(engine, wal);
> > > - else if (IS_GEN(i915, 11))
> > > + else if (GRAPHICS_VER(i915) == 11)
> > > icl_ctx_workarounds_init(engine, wal);
> > > else if (IS_CANNONLAKE(i915))
> > > cnl_ctx_workarounds_init(engine, wal);
> > > @@ -719,14 +719,14 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> > > chv_ctx_workarounds_init(engine, wal);
> > > else if (IS_BROADWELL(i915))
> > > bdw_ctx_workarounds_init(engine, wal);
> > > - else if (IS_GEN(i915, 7))
> > > + else if (GRAPHICS_VER(i915) == 7)
> > > gen7_ctx_workarounds_init(engine, wal);
> > > - else if (IS_GEN(i915, 6))
> > > + else if (GRAPHICS_VER(i915) == 6)
> > > gen6_ctx_workarounds_init(engine, wal);
> > > - else if (INTEL_GEN(i915) < 8)
> > > + else if (GRAPHICS_VER(i915) < 8)
> > > ;
> > > else
> > > - MISSING_CASE(INTEL_GEN(i915));
> > > + MISSING_CASE(GRAPHICS_VER(i915));
> > >
> > > wa_init_finish(wal);
> > > }
> > > @@ -950,7 +950,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > > unsigned int slice, subslice;
> > > u32 l3_en, mcr, mcr_mask;
> > >
> > > - GEM_BUG_ON(INTEL_GEN(i915) < 10);
> > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 10);
> > >
> > > /*
> > > * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
> > > @@ -980,7 +980,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > > * of every MMIO read.
> > > */
> > >
> > > - if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
> > > + if (GRAPHICS_VER(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
> > > u32 l3_fuse =
> > > intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
> > > GEN10_L3BANK_MASK;
> > > @@ -1002,7 +1002,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > > }
> > > subslice--;
> > >
> > > - if (INTEL_GEN(i915) >= 11) {
> > > + if (GRAPHICS_VER(i915) >= 11) {
> > > mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
> > > mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
> > > } else {
> > > @@ -1171,9 +1171,9 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > > dg1_gt_workarounds_init(i915, wal);
> > > else if (IS_TIGERLAKE(i915))
> > > tgl_gt_workarounds_init(i915, wal);
> > > - else if (IS_GEN(i915, 12))
> > > + else if (GRAPHICS_VER(i915) == 12)
> > > gen12_gt_workarounds_init(i915, wal);
> > > - else if (IS_GEN(i915, 11))
> > > + else if (GRAPHICS_VER(i915) == 11)
> > > icl_gt_workarounds_init(i915, wal);
> > > else if (IS_CANNONLAKE(i915))
> > > cnl_gt_workarounds_init(i915, wal);
> > > @@ -1193,18 +1193,18 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > > vlv_gt_workarounds_init(i915, wal);
> > > else if (IS_IVYBRIDGE(i915))
> > > ivb_gt_workarounds_init(i915, wal);
> > > - else if (IS_GEN(i915, 6))
> > > + else if (GRAPHICS_VER(i915) == 6)
> > > snb_gt_workarounds_init(i915, wal);
> > > - else if (IS_GEN(i915, 5))
> > > + else if (GRAPHICS_VER(i915) == 5)
> > > ilk_gt_workarounds_init(i915, wal);
> > > else if (IS_G4X(i915))
> > > g4x_gt_workarounds_init(i915, wal);
> > > - else if (IS_GEN(i915, 4))
> > > + else if (GRAPHICS_VER(i915) == 4)
> > > gen4_gt_workarounds_init(i915, wal);
> > > - else if (INTEL_GEN(i915) <= 8)
> > > + else if (GRAPHICS_VER(i915) <= 8)
> > > ;
> > > else
> > > - MISSING_CASE(INTEL_GEN(i915));
> > > + MISSING_CASE(GRAPHICS_VER(i915));
> > > }
> > >
> > > void intel_gt_init_workarounds(struct drm_i915_private *i915)
> > > @@ -1558,9 +1558,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> > >
> > > if (IS_DG1(i915))
> > > dg1_whitelist_build(engine);
> > > - else if (IS_GEN(i915, 12))
> > > + else if (GRAPHICS_VER(i915) == 12)
> > > tgl_whitelist_build(engine);
> > > - else if (IS_GEN(i915, 11))
> > > + else if (GRAPHICS_VER(i915) == 11)
> > > icl_whitelist_build(engine);
> > > else if (IS_CANNONLAKE(i915))
> > > cnl_whitelist_build(engine);
> > > @@ -1576,10 +1576,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> > > bxt_whitelist_build(engine);
> > > else if (IS_SKYLAKE(i915))
> > > skl_whitelist_build(engine);
> > > - else if (INTEL_GEN(i915) <= 8)
> > > + else if (GRAPHICS_VER(i915) <= 8)
> > > ;
> > > else
> > > - MISSING_CASE(INTEL_GEN(i915));
> > > + MISSING_CASE(GRAPHICS_VER(i915));
> > >
> > > wa_init_finish(w);
> > > }
> > > @@ -1695,7 +1695,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > ENABLE_SMALLPL);
> > > }
> > >
> > > - if (IS_GEN(i915, 11)) {
> > > + if (GRAPHICS_VER(i915) == 11) {
> > > /* This is not an Wa. Enable for better image quality */
> > > wa_masked_en(wal,
> > > _3D_CHICKEN3,
> > > @@ -1793,7 +1793,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > FF_DOP_CLOCK_GATE_DISABLE);
> > > }
> > >
> > > - if (IS_GEN_RANGE(i915, 9, 12)) {
> > > + if (IS_GRAPHICS_VER(i915, 9, 12)) {
> > > /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
> > > wa_masked_en(wal,
> > > GEN7_FF_SLICE_CS_CHICKEN1,
> > > @@ -1817,7 +1817,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
> > > }
> > >
> > > - if (IS_GEN(i915, 9)) {
> > > + if (GRAPHICS_VER(i915) == 9) {
> > > /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
> > > wa_masked_en(wal,
> > > GEN9_CSFE_CHICKEN1_RCS,
> > > @@ -1921,7 +1921,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
> > > }
> > >
> > > - if (IS_GEN(i915, 7)) {
> > > + if (GRAPHICS_VER(i915) == 7) {
> > > /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
> > > wa_masked_en(wal,
> > > GFX_MODE_GEN7,
> > > @@ -1953,7 +1953,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > GEN6_WIZ_HASHING_16x4);
> > > }
> > >
> > > - if (IS_GEN_RANGE(i915, 6, 7))
> > > + if (IS_GRAPHICS_VER(i915, 6, 7))
> > > /*
> > > * We need to disable the AsyncFlip performance optimisations in
> > > * order to use MI_WAIT_FOR_EVENT within the CS. It should
> > > @@ -1965,7 +1965,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > MI_MODE,
> > > ASYNC_FLIP_PERF_DISABLE);
> > >
> > > - if (IS_GEN(i915, 6)) {
> > > + if (GRAPHICS_VER(i915) == 6) {
> > > /*
> > > * Required for the hardware to program scanline values for
> > > * waiting
> > > @@ -2019,14 +2019,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > CM0_STC_EVICT_DISABLE_LRA_SNB);
> > > }
> > >
> > > - if (IS_GEN_RANGE(i915, 4, 6))
> > > + if (IS_GRAPHICS_VER(i915, 4, 6))
> > > /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
> > > wa_add(wal, MI_MODE,
> > > 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
> > > /* XXX bit doesn't stick on Broadwater */
> > > IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
> > >
> > > - if (IS_GEN(i915, 4))
> > > + if (GRAPHICS_VER(i915) == 4)
> > > /*
> > > * Disable CONSTANT_BUFFER before it is loaded from the context
> > > * image. For as it is loaded, it is executed and the stored
> > > @@ -2058,7 +2058,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > static void
> > > engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > {
> > > - if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4))
> > > + if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4))
> > > return;
> > >
> > > if (engine->class == RENDER_CLASS)
> > > @@ -2071,7 +2071,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
> > > {
> > > struct i915_wa_list *wal = &engine->wa_list;
> > >
> > > - if (INTEL_GEN(engine->i915) < 4)
> > > + if (GRAPHICS_VER(engine->i915) < 4)
> > > return;
> > >
> > > wa_init_start(wal, "engine", engine->name);
> > > @@ -2112,9 +2112,9 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
> > > const struct mcr_range *mcr_ranges;
> > > int i;
> > >
> > > - if (INTEL_GEN(i915) >= 12)
> > > + if (GRAPHICS_VER(i915) >= 12)
> > > mcr_ranges = mcr_ranges_gen12;
> > > - else if (INTEL_GEN(i915) >= 8)
> > > + else if (GRAPHICS_VER(i915) >= 8)
> > > mcr_ranges = mcr_ranges_gen8;
> > > else
> > > return false;
> > > @@ -2143,7 +2143,7 @@ wa_list_srm(struct i915_request *rq,
> > > u32 srm, *cs;
> > >
> > > srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
> > > - if (INTEL_GEN(i915) >= 8)
> > > + if (GRAPHICS_VER(i915) >= 8)
> > > srm++;
> > >
> > > for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> > > index 3453eb77c498..64abf5feabfa 100644
> > > --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> > > @@ -52,7 +52,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
> > > return PTR_ERR(cs);
> > >
> > > cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
> > > - if (INTEL_GEN(rq->engine->i915) >= 8)
> > > + if (GRAPHICS_VER(rq->engine->i915) >= 8)
> > > cmd++;
> > > *cs++ = cmd;
> > > *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
> > > @@ -125,7 +125,7 @@ static int perf_mi_bb_start(void *arg)
> > > enum intel_engine_id id;
> > > int err = 0;
> > >
> > > - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
> > > + if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
> > > return 0;
> > >
> > > perf_begin(gt);
> > > @@ -249,7 +249,7 @@ static int perf_mi_noop(void *arg)
> > > enum intel_engine_id id;
> > > int err = 0;
> > >
> > > - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
> > > + if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
> > > return 0;
> > >
> > > perf_begin(gt);
> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> > > index 2c898622bdfb..72cca3f0da21 100644
> > > --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> > > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> > > @@ -198,7 +198,7 @@ static int live_engine_timestamps(void *arg)
> > > * the same CS clock.
> > > */
> > >
> > > - if (INTEL_GEN(gt->i915) < 8)
> > > + if (GRAPHICS_VER(gt->i915) < 8)
> > > return 0;
> > >
> > > for_each_engine(engine, gt, id) {
> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> > > index 1f93591a8c69..ea2203af0764 100644
> > > --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
> > > +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> > > @@ -3269,7 +3269,7 @@ static int live_preempt_user(void *arg)
> > > if (!intel_engine_has_preemption(engine))
> > > continue;
> > >
> > > - if (IS_GEN(gt->i915, 8) && engine->class != RENDER_CLASS)
> > > + if (GRAPHICS_VER(gt->i915) == 8 && engine->class != RENDER_CLASS)
> > > continue; /* we need per-context GPR */
> > >
> > > if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {
> > > @@ -4293,7 +4293,7 @@ static int live_virtual_preserved(void *arg)
> > > return 0;
> > >
> > > /* As we use CS_GPR we cannot run before they existed on all engines. */
> > > - if (INTEL_GEN(gt->i915) < 9)
> > > + if (GRAPHICS_VER(gt->i915) < 9)
> > > return 0;
> > >
> > > for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> > > index c0845bf72dd3..b9441217ca3d 100644
> > > --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> > > +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> > > @@ -74,10 +74,10 @@ static int live_gt_clocks(void *arg)
> > > return 0;
> > > }
> > >
> > > - if (INTEL_GEN(gt->i915) < 4) /* Any CS_TIMESTAMP? */
> > > + if (GRAPHICS_VER(gt->i915) < 4) /* Any CS_TIMESTAMP? */
> > > return 0;
> > >
> > > - if (IS_GEN(gt->i915, 5))
> > > + if (GRAPHICS_VER(gt->i915) == 5)
> > > /*
> > > * XXX CS_TIMESTAMP low dword is dysfunctional?
> > > *
> > > @@ -86,7 +86,7 @@ static int live_gt_clocks(void *arg)
> > > */
> > > return 0;
> > >
> > > - if (IS_GEN(gt->i915, 4))
> > > + if (GRAPHICS_VER(gt->i915) == 4)
> > > /*
> > > * XXX CS_TIMESTAMP appears gibberish
> > > *
> > > @@ -105,7 +105,7 @@ static int live_gt_clocks(void *arg)
> > > u64 time;
> > > u64 dt;
> > >
> > > - if (INTEL_GEN(engine->i915) < 7 && engine->id != RCS0)
> > > + if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0)
> > > continue;
> > >
> > > measure_clocks(engine, &cycles, &dt);
> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> > > index 5b63d4df8c93..853246fad05f 100644
> > > --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> > > +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> > > @@ -180,7 +180,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> > > goto cancel_rq;
> > >
> > > batch = h->batch;
> > > - if (INTEL_GEN(gt->i915) >= 8) {
> > > + if (GRAPHICS_VER(gt->i915) >= 8) {
> > > *batch++ = MI_STORE_DWORD_IMM_GEN4;
> > > *batch++ = lower_32_bits(hws_address(hws, rq));
> > > *batch++ = upper_32_bits(hws_address(hws, rq));
> > > @@ -194,7 +194,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> > > *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
> > > *batch++ = lower_32_bits(vma->node.start);
> > > *batch++ = upper_32_bits(vma->node.start);
> > > - } else if (INTEL_GEN(gt->i915) >= 6) {
> > > + } else if (GRAPHICS_VER(gt->i915) >= 6) {
> > > *batch++ = MI_STORE_DWORD_IMM_GEN4;
> > > *batch++ = 0;
> > > *batch++ = lower_32_bits(hws_address(hws, rq));
> > > @@ -207,7 +207,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> > > *batch++ = MI_NOOP;
> > > *batch++ = MI_BATCH_BUFFER_START | 1 << 8;
> > > *batch++ = lower_32_bits(vma->node.start);
> > > - } else if (INTEL_GEN(gt->i915) >= 4) {
> > > + } else if (GRAPHICS_VER(gt->i915) >= 4) {
> > > *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> > > *batch++ = 0;
> > > *batch++ = lower_32_bits(hws_address(hws, rq));
> > > @@ -243,7 +243,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> > > }
> > >
> > > flags = 0;
> > > - if (INTEL_GEN(gt->i915) <= 5)
> > > + if (GRAPHICS_VER(gt->i915) <= 5)
> > > flags |= I915_DISPATCH_SECURE;
> > >
> > > err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
> > > index 94006f117bbd..459b775f163a 100644
> > > --- a/drivers/gpu/drm/i915/gt/selftest_llc.c
> > > +++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
> > > @@ -44,7 +44,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
> > > if (found != ia_freq) {
> > > pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected CPU freq, found %d, expected %d\n",
> > > gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
> > > - intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
> > > + intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
> > > found, ia_freq);
> > > err = -EINVAL;
> > > break;
> > > @@ -54,7 +54,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
> > > if (found != ring_freq) {
> > > pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected ring freq, found %d, expected %d\n",
> > > gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
> > > - intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
> > > + intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
> > > found, ring_freq);
> > > err = -EINVAL;
> > > break;
> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > > index d8f6623524e8..3119016d9910 100644
> > > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > > @@ -584,7 +584,7 @@ static int __live_lrc_gpr(struct intel_engine_cs *engine,
> > > int err;
> > > int n;
> > >
> > > - if (INTEL_GEN(engine->i915) < 9 && engine->class != RENDER_CLASS)
> > > + if (GRAPHICS_VER(engine->i915) < 9 && engine->class != RENDER_CLASS)
> > > return 0; /* GPR only on rcs0 for gen8 */
> > >
> > > err = gpr_make_dirty(engine->kernel_context);
> > > @@ -1389,10 +1389,10 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
> > >
> > > static bool skip_isolation(const struct intel_engine_cs *engine)
> > > {
> > > - if (engine->class == COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) == 9)
> > > + if (engine->class == COPY_ENGINE_CLASS && GRAPHICS_VER(engine->i915) == 9)
> > > return true;
> > >
> > > - if (engine->class == RENDER_CLASS && INTEL_GEN(engine->i915) == 11)
> > > + if (engine->class == RENDER_CLASS && GRAPHICS_VER(engine->i915) == 11)
> > > return true;
> > >
> > > return false;
> > > @@ -1551,7 +1551,7 @@ static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)
> > > /* We use the already reserved extra page in context state */
> > > if (!a->wa_bb_page) {
> > > GEM_BUG_ON(b->wa_bb_page);
> > > - GEM_BUG_ON(INTEL_GEN(engine->i915) == 12);
> > > + GEM_BUG_ON(GRAPHICS_VER(engine->i915) == 12);
> > > goto unpin_b;
> > > }
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> > > index e55a887d11e2..b9bb0e6e97f7 100644
> > > --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> > > +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> > > @@ -183,7 +183,7 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
> > > * which only controls CPU initiated MMIO. Routing does not
> > > * work for CS access so we cannot verify them on this path.
> > > */
> > > - return INTEL_GEN(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
> > > + return GRAPHICS_VER(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
> > > }
> > >
> > > static int check_l3cc_table(struct intel_engine_cs *engine,
> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> > > index 710f825f6e5a..8c70b7e12074 100644
> > > --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> > > +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> > > @@ -140,7 +140,7 @@ static const u32 *__live_rc6_ctx(struct intel_context *ce)
> > > }
> > >
> > > cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
> > > - if (INTEL_GEN(rq->engine->i915) >= 8)
> > > + if (GRAPHICS_VER(rq->engine->i915) >= 8)
> > > cmd++;
> > >
> > > *cs++ = cmd;
> > > @@ -193,7 +193,7 @@ int live_rc6_ctx_wa(void *arg)
> > > int err = 0;
> > >
> > > /* A read of CTX_INFO upsets rc6. Poke the bear! */
> > > - if (INTEL_GEN(gt->i915) < 8)
> > > + if (GRAPHICS_VER(gt->i915) < 8)
> > > return 0;
> > >
> > > engines = randomised_engines(gt, &prng, &count);
> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
> > > index c12e74171b63..041954408d0f 100644
> > > --- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
> > > @@ -41,10 +41,10 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
> > > return ERR_CAST(cs);
> > > }
> > >
> > > - if (INTEL_GEN(engine->i915) >= 6) {
> > > + if (GRAPHICS_VER(engine->i915) >= 6) {
> > > *cs++ = MI_STORE_DWORD_IMM_GEN4;
> > > *cs++ = 0;
> > > - } else if (INTEL_GEN(engine->i915) >= 4) {
> > > + } else if (GRAPHICS_VER(engine->i915) >= 4) {
> > > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> > > *cs++ = 0;
> > > } else {
> > > @@ -266,7 +266,7 @@ static int live_ctx_switch_wa(void *arg)
> > > if (!intel_engine_can_store_dword(engine))
> > > continue;
> > >
> > > - if (IS_GEN_RANGE(gt->i915, 4, 5))
> > > + if (IS_GRAPHICS_VER(gt->i915, 4, 5))
> > > continue; /* MI_STORE_DWORD is privileged! */
> > >
> > > saved_wa = fetch_and_zero(&engine->wa_ctx.vma);
> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
> > > index 3ca1bd5793c3..7ee2513e15f9 100644
> > > --- a/drivers/gpu/drm/i915/gt/selftest_rps.c
> > > +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
> > > @@ -204,7 +204,7 @@ static void show_pstate_limits(struct intel_rps *rps)
> > > i915_mmio_reg_offset(BXT_RP_STATE_CAP),
> > > intel_uncore_read(rps_to_uncore(rps),
> > > BXT_RP_STATE_CAP));
> > > - } else if (IS_GEN(i915, 9)) {
> > > + } else if (GRAPHICS_VER(i915) == 9) {
> > > pr_info("P_STATE_LIMITS[%x]: 0x%08x\n",
> > > i915_mmio_reg_offset(GEN9_RP_STATE_LIMITS),
> > > intel_uncore_read(rps_to_uncore(rps),
> > > @@ -222,7 +222,7 @@ int live_rps_clock_interval(void *arg)
> > > struct igt_spinner spin;
> > > int err = 0;
> > >
> > > - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
> > > + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
> > > return 0;
> > >
> > > if (igt_spinner_init(&spin, gt))
> > > @@ -506,7 +506,7 @@ static void show_pcu_config(struct intel_rps *rps)
> > >
> > > min_gpu_freq = rps->min_freq;
> > > max_gpu_freq = rps->max_freq;
> > > - if (INTEL_GEN(i915) >= 9) {
> > > + if (GRAPHICS_VER(i915) >= 9) {
> > > /* Convert GT frequency to 50 HZ units */
> > > min_gpu_freq /= GEN9_FREQ_SCALER;
> > > max_gpu_freq /= GEN9_FREQ_SCALER;
> > > @@ -614,7 +614,7 @@ int live_rps_frequency_cs(void *arg)
> > > if (!intel_rps_is_enabled(rps))
> > > return 0;
> > >
> > > - if (INTEL_GEN(gt->i915) < 8) /* for CS simplicity */
> > > + if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
> > > return 0;
> > >
> > > if (CPU_LATENCY >= 0)
> > > @@ -755,7 +755,7 @@ int live_rps_frequency_srm(void *arg)
> > > if (!intel_rps_is_enabled(rps))
> > > return 0;
> > >
> > > - if (INTEL_GEN(gt->i915) < 8) /* for CS simplicity */
> > > + if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
> > > return 0;
> > >
> > > if (CPU_LATENCY >= 0)
> > > @@ -1031,7 +1031,7 @@ int live_rps_interrupt(void *arg)
> > > * First, let's check whether or not we are receiving interrupts.
> > > */
> > >
> > > - if (!intel_rps_has_interrupts(rps) || INTEL_GEN(gt->i915) < 6)
> > > + if (!intel_rps_has_interrupts(rps) || GRAPHICS_VER(gt->i915) < 6)
> > > return 0;
> > >
> > > intel_gt_pm_get(gt);
> > > @@ -1136,7 +1136,7 @@ int live_rps_power(void *arg)
> > > * that theory.
> > > */
> > >
> > > - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
> > > + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
> > > return 0;
> > >
> > > if (!librapl_supported(gt->i915))
> > > @@ -1240,7 +1240,7 @@ int live_rps_dynamic(void *arg)
> > > * moving parts into dynamic reclocking based on load.
> > > */
> > >
> > > - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
> > > + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
> > > return 0;
> > >
> > > if (igt_spinner_init(&spin, gt))
> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> > > index 9adbd9d147be..64da0c91dec1 100644
> > > --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
> > > +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> > > @@ -457,12 +457,12 @@ static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
> > > if (IS_ERR(cs))
> > > return PTR_ERR(cs);
> > >
> > > - if (INTEL_GEN(rq->engine->i915) >= 8) {
> > > + if (GRAPHICS_VER(rq->engine->i915) >= 8) {
> > > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> > > *cs++ = addr;
> > > *cs++ = 0;
> > > *cs++ = value;
> > > - } else if (INTEL_GEN(rq->engine->i915) >= 4) {
> > > + } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
> > > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> > > *cs++ = 0;
> > > *cs++ = addr;
> > > @@ -992,7 +992,7 @@ static int live_hwsp_read(void *arg)
> > > * even across multiple wraps.
> > > */
> > >
> > > - if (INTEL_GEN(gt->i915) < 8) /* CS convenience [SRM/LRM] */
> > > + if (GRAPHICS_VER(gt->i915) < 8) /* CS convenience [SRM/LRM] */
> > > return 0;
> > >
> > > tl = intel_timeline_create(gt);
> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> > > index 64937ec3f2dc..c30754daf4b1 100644
> > > --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> > > @@ -145,7 +145,7 @@ read_nonprivs(struct intel_context *ce)
> > > goto err_req;
> > >
> > > srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
> > > - if (INTEL_GEN(engine->i915) >= 8)
> > > + if (GRAPHICS_VER(engine->i915) >= 8)
> > > srm++;
> > >
> > > cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
> > > @@ -546,7 +546,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
> > >
> > > srm = MI_STORE_REGISTER_MEM;
> > > lrm = MI_LOAD_REGISTER_MEM;
> > > - if (INTEL_GEN(engine->i915) >= 8)
> > > + if (GRAPHICS_VER(engine->i915) >= 8)
> > > lrm++, srm++;
> > >
> > > pr_debug("%s: Writing garbage to %x\n",
> > > @@ -749,7 +749,7 @@ static int live_dirty_whitelist(void *arg)
> > >
> > > /* Can the user write to the whitelisted registers? */
> > >
> > > - if (INTEL_GEN(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */
> > > + if (GRAPHICS_VER(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */
> > > return 0;
> > >
> > > for_each_engine(engine, gt, id) {
> > > @@ -829,7 +829,7 @@ static int read_whitelisted_registers(struct intel_context *ce,
> > > goto err_req;
> > >
> > > srm = MI_STORE_REGISTER_MEM;
> > > - if (INTEL_GEN(engine->i915) >= 8)
> > > + if (GRAPHICS_VER(engine->i915) >= 8)
> > > srm++;
> > >
> > > cs = intel_ring_begin(rq, 4 * engine->whitelist.count);
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > index adae04c47aab..84f806911370 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > @@ -60,7 +60,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
> > > enum forcewake_domains fw_domains = 0;
> > > unsigned int i;
> > >
> > > - if (INTEL_GEN(gt->i915) >= 11) {
> > > + if (GRAPHICS_VER(gt->i915) >= 11) {
> > > guc->send_regs.base =
> > > i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
> > > guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
> > > @@ -176,7 +176,7 @@ void intel_guc_init_early(struct intel_guc *guc)
> > >
> > > mutex_init(&guc->send_mutex);
> > > spin_lock_init(&guc->irq_lock);
> > > - if (INTEL_GEN(i915) >= 11) {
> > > + if (GRAPHICS_VER(i915) >= 11) {
> > > guc->notify_reg = GEN11_GUC_HOST_INTERRUPT;
> > > guc->interrupts.reset = gen11_reset_guc_interrupts;
> > > guc->interrupts.enable = gen11_enable_guc_interrupts;
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > > index 17526717368c..b32fafba2a90 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > > @@ -162,7 +162,7 @@ static void __guc_ads_init(struct intel_guc *guc)
> > > blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK] =
> > > gt->info.vdbox_sfc_access;
> > >
> > > - if (INTEL_GEN(i915) >= 12 && !IS_DGFX(i915)) {
> > > + if (GRAPHICS_VER(i915) >= 12 && !IS_DGFX(i915)) {
> > > u32 distdbreg = intel_uncore_read(gt->uncore,
> > > GEN12_DIST_DBS_POPULATED);
> > > blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI] =
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> > > index 2270d6b3b272..76fe766ad1bc 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> > > @@ -30,7 +30,7 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
> > > else
> > > intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> > >
> > > - if (IS_GEN(uncore->i915, 9)) {
> > > + if (GRAPHICS_VER(uncore->i915) == 9) {
> > > /* DOP Clock Gating Enable for GuC clocks */
> > > intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
> > > 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > index 335719f17490..541f6da1ec47 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > @@ -438,7 +438,7 @@ static void guc_interrupts_capture(struct intel_gt *gt)
> > > u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
> > > u32 dmask = irqs << 16 | irqs;
> > >
> > > - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
> > > + GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
> > >
> > > /* Don't handle the ctx switch interrupt in GuC submission mode */
> > > intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask, 0);
> > > @@ -451,7 +451,7 @@ static void guc_interrupts_release(struct intel_gt *gt)
> > > u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
> > > u32 dmask = irqs << 16 | irqs;
> > >
> > > - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
> > > + GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
> > >
> > > /* Handle ctx switch interrupts again */
> > > intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0, dmask);
> > > @@ -648,7 +648,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
> > > engine->emit_flush = gen8_emit_flush_xcs;
> > > engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
> > > engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
> > > - if (INTEL_GEN(engine->i915) >= 12) {
> > > + if (GRAPHICS_VER(engine->i915) >= 12) {
> > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;
> > > engine->emit_flush = gen12_emit_flush_xcs;
> > > }
> > > @@ -670,7 +670,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
> > >
> > > static void rcs_submission_override(struct intel_engine_cs *engine)
> > > {
> > > - switch (INTEL_GEN(engine->i915)) {
> > > + switch (GRAPHICS_VER(engine->i915)) {
> > > case 12:
> > > engine->emit_flush = gen12_emit_flush_rcs;
> > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
> > > @@ -700,7 +700,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
> > > * The setup relies on several assumptions (e.g. irqs always enabled)
> > > * that are only valid on gen11+
> > > */
> > > - GEM_BUG_ON(INTEL_GEN(i915) < 11);
> > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 11);
> > >
> > > tasklet_setup(&engine->execlists.tasklet, guc_submission_tasklet);
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> > > index 56d2144dc6a0..fc5387b410a2 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> > > @@ -43,7 +43,7 @@ void intel_huc_init_early(struct intel_huc *huc)
> > >
> > > intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC);
> > >
> > > - if (INTEL_GEN(i915) >= 11) {
> > > + if (GRAPHICS_VER(i915) >= 11) {
> > > huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
> > > huc->status.mask = HUC_LOAD_SUCCESSFUL;
> > > huc->status.value = HUC_LOAD_SUCCESSFUL;
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> > > index 6abb8f2dc33d..6c2bf4b6bc10 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> > > @@ -23,7 +23,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
> > > return;
> > >
> > > /* Don't enable GuC/HuC on pre-Gen12 */
> > > - if (INTEL_GEN(i915) < 12) {
> > > + if (GRAPHICS_VER(i915) < 12) {
> > > i915->params.enable_guc = 0;
> > > return;
> > > }
> > > @@ -467,7 +467,7 @@ static int __uc_init_hw(struct intel_uc *uc)
> > >
> > > /* WaEnableuKernelHeaderValidFix:skl */
> > > /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
> > > - if (IS_GEN(i915, 9))
> > > + if (GRAPHICS_VER(i915) == 9)
> > > attempts = 3;
> > > else
> > > attempts = 1;
> > > --
> > > 2.31.1
> > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > VTT-OSGC Platform Enablement
> > Intel Corporation
> > (916) 356-2795
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
2021-06-01 17:30 ` Matt Roper
@ 2021-06-01 19:13 ` Lucas De Marchi
2021-06-01 20:39 ` Matt Roper
0 siblings, 1 reply; 20+ messages in thread
From: Lucas De Marchi @ 2021-06-01 19:13 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Tue, Jun 01, 2021 at 10:30:55AM -0700, Matt Roper wrote:
>On Tue, Jun 01, 2021 at 10:15:14AM -0700, Lucas De Marchi wrote:
>> On Tue, Jun 01, 2021 at 09:58:34AM -0700, Matt Roper wrote:
>> > On Thu, May 27, 2021 at 11:16:54AM -0700, Lucas De Marchi wrote:
>> > > This was done by the following semantic patch:
>> >
>> > Is the commit message here out-of-date? The cocci doesn't appear to
>> > match the diff anymore. IS_GRAPHICS_VER() is the range macro now and
>> > IS_GEN is being replaced with a direct "==" comparison.
>>
>> not necessarily, it's included in "and friends...". Maybe rewording to
>> something like "replace gen-based macros with new ver-based ones" would
>> make it clearer?
>
>I mean that running the coccinelle rules below through spatch won't
>generate the code diff here; it would generate a completely different
>patch (that I don't think would build properly either).
oh, ok. I fixed the issues in the .cocci and forgot to update the commit
message. Thanks.
Lucas De Marchi
>
>
>Matt
>
>>
>> Lucas De Marchi
>>
>> >
>> >
>> > Matt
>> >
>> > >
>> > > @@ expression dev_priv, E; @@
>> > > - INTEL_GEN(dev_priv) == E
>> > > + IS_GRAPHICS_VER(dev_priv, E)
>> > >
>> > > @@ expression dev_priv; @@
>> > > - INTEL_GEN(dev_priv)
>> > > + GRAPHICS_VER(dev_priv)
>> > >
>> > > @@ expression dev_priv; expression E; @@
>> > > - IS_GEN(dev_priv, E)
>> > > + IS_GRAPHICS_VER(dev_priv, E)
>> > >
>> > > @@
>> > > expression dev_priv;
>> > > expression from, until;
>> > > @@
>> > > - IS_GEN_RANGE(dev_priv, from, until)
>> > > + IS_GRAPHICS_RANGE(dev_priv, from, until)
>> > >
>> > > @def@
>> > > expression E;
>> > > identifier id =~ "^gen$";
>> > > @@
>> > > - id = GRAPHICS_VER(E)
>> > > + ver = GRAPHICS_VER(E)
>> > >
>> > > @@
>> > > identifier def.id;
>> > > @@
>> > > - id
>> > > + ver
>> > >
>> > > It also takes care of renaming the variable we assign to GRAPHICS_VER()
>> > > so to use "ver" rather than "gen".
>> > >
>> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > ---
>> > > drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 38 +++++------
>> > > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
>> > > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
>> > > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 +-
>> > > drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
>> > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 54 +++++++--------
>> > > .../drm/i915/gt/intel_execlists_submission.c | 18 ++---
>> > > drivers/gpu/drm/i915/gt/intel_ggtt.c | 18 ++---
>> > > drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 34 +++++-----
>> > > drivers/gpu/drm/i915/gt/intel_gt.c | 27 ++++----
>> > > .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 12 ++--
>> > > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 6 +-
>> > > drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 10 +--
>> > > drivers/gpu/drm/i915/gt/intel_gtt.c | 14 ++--
>> > > drivers/gpu/drm/i915/gt/intel_llc.c | 6 +-
>> > > drivers/gpu/drm/i915/gt/intel_lrc.c | 46 ++++++-------
>> > > drivers/gpu/drm/i915/gt/intel_mocs.c | 8 +--
>> > > drivers/gpu/drm/i915/gt/intel_ppgtt.c | 6 +-
>> > > drivers/gpu/drm/i915/gt/intel_rc6.c | 16 ++---
>> > > drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
>> > > drivers/gpu/drm/i915/gt/intel_reset.c | 12 ++--
>> > > .../gpu/drm/i915/gt/intel_ring_submission.c | 64 +++++++++---------
>> > > drivers/gpu/drm/i915/gt/intel_rps.c | 60 ++++++++---------
>> > > drivers/gpu/drm/i915/gt/intel_sseu.c | 14 ++--
>> > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +++++++++----------
>> > > drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 6 +-
>> > > drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 +-
>> > > drivers/gpu/drm/i915/gt/selftest_execlists.c | 4 +-
>> > > drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +--
>> > > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 +--
>> > > drivers/gpu/drm/i915/gt/selftest_llc.c | 4 +-
>> > > drivers/gpu/drm/i915/gt/selftest_lrc.c | 8 +--
>> > > drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
>> > > drivers/gpu/drm/i915/gt/selftest_rc6.c | 4 +-
>> > > .../drm/i915/gt/selftest_ring_submission.c | 6 +-
>> > > drivers/gpu/drm/i915/gt/selftest_rps.c | 16 ++---
>> > > drivers/gpu/drm/i915/gt/selftest_timeline.c | 6 +-
>> > > .../gpu/drm/i915/gt/selftest_workarounds.c | 8 +--
>> > > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +-
>> > > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
>> > > drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
>> > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +--
>> > > drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
>> > > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
>> > > 44 files changed, 323 insertions(+), 322 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
>> > > index d4f4452ce5ed..0389bceebd06 100644
>> > > --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
>> > > +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
>> > > @@ -85,14 +85,14 @@ static int gen6_drpc(struct seq_file *m)
>> > > gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
>> > >
>> > > rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
>> > > - if (INTEL_GEN(i915) >= 9) {
>> > > + if (GRAPHICS_VER(i915) >= 9) {
>> > > gen9_powergate_enable =
>> > > intel_uncore_read(uncore, GEN9_PG_ENABLE);
>> > > gen9_powergate_status =
>> > > intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
>> > > }
>> > >
>> > > - if (INTEL_GEN(i915) <= 7)
>> > > + if (GRAPHICS_VER(i915) <= 7)
>> > > sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
>> > > &rc6vids, NULL);
>> > >
>> > > @@ -100,7 +100,7 @@ static int gen6_drpc(struct seq_file *m)
>> > > yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
>> > > seq_printf(m, "RC6 Enabled: %s\n",
>> > > yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
>> > > - if (INTEL_GEN(i915) >= 9) {
>> > > + if (GRAPHICS_VER(i915) >= 9) {
>> > > seq_printf(m, "Render Well Gating Enabled: %s\n",
>> > > yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
>> > > seq_printf(m, "Media Well Gating Enabled: %s\n",
>> > > @@ -134,7 +134,7 @@ static int gen6_drpc(struct seq_file *m)
>> > >
>> > > seq_printf(m, "Core Power Down: %s\n",
>> > > yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
>> > > - if (INTEL_GEN(i915) >= 9) {
>> > > + if (GRAPHICS_VER(i915) >= 9) {
>> > > seq_printf(m, "Render Power Well: %s\n",
>> > > (gen9_powergate_status &
>> > > GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
>> > > @@ -150,7 +150,7 @@ static int gen6_drpc(struct seq_file *m)
>> > > print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
>> > > print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
>> > >
>> > > - if (INTEL_GEN(i915) <= 7) {
>> > > + if (GRAPHICS_VER(i915) <= 7) {
>> > > seq_printf(m, "RC6 voltage: %dmV\n",
>> > > GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
>> > > seq_printf(m, "RC6+ voltage: %dmV\n",
>> > > @@ -250,7 +250,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>> > >
>> > > wakeref = intel_runtime_pm_get(uncore->rpm);
>> > >
>> > > - if (IS_GEN(i915, 5)) {
>> > > + if (GRAPHICS_VER(i915) == 5) {
>> > > u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
>> > > u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
>> > >
>> > > @@ -296,7 +296,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>> > >
>> > > seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
>> > > intel_gpu_freq(rps, rps->efficient_freq));
>> > > - } else if (INTEL_GEN(i915) >= 6) {
>> > > + } else if (GRAPHICS_VER(i915) >= 6) {
>> > > u32 rp_state_limits;
>> > > u32 gt_perf_status;
>> > > u32 rp_state_cap;
>> > > @@ -321,7 +321,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>> > > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>> > >
>> > > reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
>> > > - if (INTEL_GEN(i915) >= 9) {
>> > > + if (GRAPHICS_VER(i915) >= 9) {
>> > > reqf >>= 23;
>> > > } else {
>> > > reqf &= ~GEN6_TURBO_DISABLE;
>> > > @@ -354,7 +354,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>> > >
>> > > intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>> > >
>> > > - if (INTEL_GEN(i915) >= 11) {
>> > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
>> > > pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
>> > > /*
>> > > @@ -363,7 +363,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>> > > */
>> > > pm_isr = 0;
>> > > pm_iir = 0;
>> > > - } else if (INTEL_GEN(i915) >= 8) {
>> > > + } else if (GRAPHICS_VER(i915) >= 8) {
>> > > pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
>> > > pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
>> > > pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
>> > > @@ -386,14 +386,14 @@ static int frequency_show(struct seq_file *m, void *unused)
>> > >
>> > > seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
>> > > pm_ier, pm_imr, pm_mask);
>> > > - if (INTEL_GEN(i915) <= 10)
>> > > + if (GRAPHICS_VER(i915) <= 10)
>> > > seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
>> > > pm_isr, pm_iir);
>> > > seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
>> > > rps->pm_intrmsk_mbz);
>> > > seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
>> > > seq_printf(m, "Render p-state ratio: %d\n",
>> > > - (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
>> > > + (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
>> > > seq_printf(m, "Render p-state VID: %d\n",
>> > > gt_perf_status & 0xff);
>> > > seq_printf(m, "Render p-state limit: %d\n",
>> > > @@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void *unused)
>> > > max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
>> > > rp_state_cap >> 16) & 0xff;
>> > > max_freq *= (IS_GEN9_BC(i915) ||
>> > > - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> > > + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> > > seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
>> > > intel_gpu_freq(rps, max_freq));
>> > >
>> > > max_freq = (rp_state_cap & 0xff00) >> 8;
>> > > max_freq *= (IS_GEN9_BC(i915) ||
>> > > - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> > > + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> > > seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
>> > > intel_gpu_freq(rps, max_freq));
>> > >
>> > > max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
>> > > rp_state_cap >> 0) & 0xff;
>> > > max_freq *= (IS_GEN9_BC(i915) ||
>> > > - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> > > + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> > > seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
>> > > intel_gpu_freq(rps, max_freq));
>> > > seq_printf(m, "Max overclocked frequency: %dMHz\n",
>> > > @@ -488,7 +488,7 @@ static int llc_show(struct seq_file *m, void *data)
>> > > {
>> > > struct intel_gt *gt = m->private;
>> > > struct drm_i915_private *i915 = gt->i915;
>> > > - const bool edram = INTEL_GEN(i915) > 8;
>> > > + const bool edram = GRAPHICS_VER(i915) > 8;
>> > > struct intel_rps *rps = >->rps;
>> > > unsigned int max_gpu_freq, min_gpu_freq;
>> > > intel_wakeref_t wakeref;
>> > > @@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data)
>> > >
>> > > min_gpu_freq = rps->min_freq;
>> > > max_gpu_freq = rps->max_freq;
>> > > - if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
>> > > + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
>> > > /* Convert GT frequency to 50 HZ units */
>> > > min_gpu_freq /= GEN9_FREQ_SCALER;
>> > > max_gpu_freq /= GEN9_FREQ_SCALER;
>> > > @@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data)
>> > > intel_gpu_freq(rps,
>> > > (gpu_freq *
>> > > (IS_GEN9_BC(i915) ||
>> > > - INTEL_GEN(i915) >= 10 ?
>> > > + GRAPHICS_VER(i915) >= 10 ?
>> > > GEN9_FREQ_SCALER : 1))),
>> > > ((ia_freq >> 0) & 0xff) * 100,
>> > > ((ia_freq >> 8) & 0xff) * 100);
>> > > @@ -580,7 +580,7 @@ static int rps_boost_show(struct seq_file *m, void *data)
>> > >
>> > > seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
>> > >
>> > > - if (INTEL_GEN(i915) >= 6 && intel_rps_is_active(rps)) {
>> > > + if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) {
>> > > struct intel_uncore *uncore = gt->uncore;
>> > > u32 rpup, rpupei;
>> > > u32 rpdown, rpdownei;
>> > > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> > > index 9646200d2792..61383830505e 100644
>> > > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> > > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> > > @@ -74,7 +74,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
>> > > cmd = MI_FLUSH;
>> > > if (mode & EMIT_INVALIDATE) {
>> > > cmd |= MI_EXE_FLUSH;
>> > > - if (IS_G4X(rq->engine->i915) || IS_GEN(rq->engine->i915, 5))
>> > > + if (IS_G4X(rq->engine->i915) || GRAPHICS_VER(rq->engine->i915) == 5)
>> > > cmd |= MI_INVALIDATE_ISP;
>> > > }
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> > > index 732c2ed1d933..94e0a5669f90 100644
>> > > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> > > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> > > @@ -38,7 +38,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
>> > > * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
>> > > * pipe control.
>> > > */
>> > > - if (IS_GEN(rq->engine->i915, 9))
>> > > + if (GRAPHICS_VER(rq->engine->i915) == 9)
>> > > vf_flush_wa = true;
>> > >
>> > > /* WaForGAMHang:kbl */
>> > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> > > index e3a8924d2286..21c8b7350b7a 100644
>> > > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> > > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> > > @@ -709,7 +709,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
>> > > *
>> > > * Gen12 has inherited the same read-only fault issue from gen11.
>> > > */
>> > > - ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12);
>> > > + ppgtt->vm.has_read_only = !IS_GRAPHICS_VER(gt->i915, 11, 12);
>> > >
>> > > if (HAS_LMEM(gt->i915))
>> > > ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
>> > > index 8dfd8f656aaa..e86d8255feec 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
>> > > @@ -76,7 +76,7 @@ intel_context_reconfigure_sseu(struct intel_context *ce,
>> > > {
>> > > int ret;
>> > >
>> > > - GEM_BUG_ON(INTEL_GEN(ce->engine->i915) < 8);
>> > > + GEM_BUG_ON(GRAPHICS_VER(ce->engine->i915) < 8);
>> > >
>> > > ret = intel_context_lock_pinned(ce);
>> > > if (ret)
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> > > index 3f9a811eb02b..54baf17b81b6 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> > > @@ -240,10 +240,10 @@ void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
>> > > * Though they added more rings on g4x/ilk, they did not add
>> > > * per-engine HWSTAM until gen6.
>> > > */
>> > > - if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS)
>> > > + if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)
>> > > return;
>> > >
>> > > - if (INTEL_GEN(engine->i915) >= 3)
>> > > + if (GRAPHICS_VER(engine->i915) >= 3)
>> > > ENGINE_WRITE(engine, RING_HWSTAM, mask);
>> > > else
>> > > ENGINE_WRITE16(engine, RING_HWSTAM, mask);
>> > > @@ -315,7 +315,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
>> > > CONFIG_DRM_I915_TIMESLICE_DURATION;
>> > >
>> > > /* Override to uninterruptible for OpenCL workloads. */
>> > > - if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS)
>> > > + if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
>> > > engine->props.preempt_timeout_ms = 0;
>> > >
>> > > engine->defaults = engine->props; /* never to change again */
>> > > @@ -352,8 +352,8 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
>> > > * HEVC support is present on first engine instance
>> > > * before Gen11 and on all instances afterwards.
>> > > */
>> > > - if (INTEL_GEN(i915) >= 11 ||
>> > > - (INTEL_GEN(i915) >= 9 && engine->instance == 0))
>> > > + if (GRAPHICS_VER(i915) >= 11 ||
>> > > + (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
>> > > engine->uabi_capabilities |=
>> > > I915_VIDEO_CLASS_CAPABILITY_HEVC;
>> > >
>> > > @@ -361,14 +361,14 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
>> > > * SFC block is present only on even logical engine
>> > > * instances.
>> > > */
>> > > - if ((INTEL_GEN(i915) >= 11 &&
>> > > + if ((GRAPHICS_VER(i915) >= 11 &&
>> > > (engine->gt->info.vdbox_sfc_access &
>> > > BIT(engine->instance))) ||
>> > > - (INTEL_GEN(i915) >= 9 && engine->instance == 0))
>> > > + (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
>> > > engine->uabi_capabilities |=
>> > > I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
>> > > } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
>> > > - if (INTEL_GEN(i915) >= 9)
>> > > + if (GRAPHICS_VER(i915) >= 9)
>> > > engine->uabi_capabilities |=
>> > > I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
>> > > }
>> > > @@ -466,7 +466,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>> > >
>> > > info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
>> > >
>> > > - if (INTEL_GEN(i915) < 11)
>> > > + if (GRAPHICS_VER(i915) < 11)
>> > > return info->engine_mask;
>> > >
>> > > media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
>> > > @@ -492,7 +492,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>> > > * hooked up to an SFC (Scaler & Format Converter) unit.
>> > > * In TGL each VDBOX has access to an SFC.
>> > > */
>> > > - if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
>> > > + if (GRAPHICS_VER(i915) >= 12 || logical_vdbox++ % 2 == 0)
>> > > gt->info.vdbox_sfc_access |= BIT(i);
>> > > }
>> > > drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
>> > > @@ -729,7 +729,7 @@ static int engine_setup_common(struct intel_engine_cs *engine)
>> > > intel_engine_init_whitelist(engine);
>> > > intel_engine_init_ctx_wa(engine);
>> > >
>> > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
>> > >
>> > > return 0;
>> > > @@ -997,9 +997,9 @@ u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
>> > >
>> > > u64 acthd;
>> > >
>> > > - if (INTEL_GEN(i915) >= 8)
>> > > + if (GRAPHICS_VER(i915) >= 8)
>> > > acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
>> > > - else if (INTEL_GEN(i915) >= 4)
>> > > + else if (GRAPHICS_VER(i915) >= 4)
>> > > acthd = ENGINE_READ(engine, RING_ACTHD);
>> > > else
>> > > acthd = ENGINE_READ(engine, ACTHD);
>> > > @@ -1011,7 +1011,7 @@ u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
>> > > {
>> > > u64 bbaddr;
>> > >
>> > > - if (INTEL_GEN(engine->i915) >= 8)
>> > > + if (GRAPHICS_VER(engine->i915) >= 8)
>> > > bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
>> > > else
>> > > bbaddr = ENGINE_READ(engine, RING_BBADDR);
>> > > @@ -1058,7 +1058,7 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
>> > > {
>> > > int err = 0;
>> > >
>> > > - if (INTEL_GEN(engine->i915) < 3)
>> > > + if (GRAPHICS_VER(engine->i915) < 3)
>> > > return -ENODEV;
>> > >
>> > > ENGINE_TRACE(engine, "\n");
>> > > @@ -1108,7 +1108,7 @@ read_subslice_reg(const struct intel_engine_cs *engine,
>> > > u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
>> > > enum forcewake_domains fw_domains;
>> > >
>> > > - if (INTEL_GEN(i915) >= 11) {
>> > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
>> > > mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
>> > > } else {
>> > > @@ -1157,7 +1157,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
>> > >
>> > > memset(instdone, 0, sizeof(*instdone));
>> > >
>> > > - switch (INTEL_GEN(i915)) {
>> > > + switch (GRAPHICS_VER(i915)) {
>> > > default:
>> > > instdone->instdone =
>> > > intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
>> > > @@ -1167,7 +1167,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
>> > >
>> > > instdone->slice_common =
>> > > intel_uncore_read(uncore, GEN7_SC_INSTDONE);
>> > > - if (INTEL_GEN(i915) >= 12) {
>> > > + if (GRAPHICS_VER(i915) >= 12) {
>> > > instdone->slice_common_extra[0] =
>> > > intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
>> > > instdone->slice_common_extra[1] =
>> > > @@ -1230,7 +1230,7 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
>> > > idle = false;
>> > >
>> > > /* No bit for gen2, so assume the CS parser is idle */
>> > > - if (INTEL_GEN(engine->i915) > 2 &&
>> > > + if (GRAPHICS_VER(engine->i915) > 2 &&
>> > > !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
>> > > idle = false;
>> > >
>> > > @@ -1327,7 +1327,7 @@ void intel_engines_reset_default_submission(struct intel_gt *gt)
>> > >
>> > > bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
>> > > {
>> > > - switch (INTEL_GEN(engine->i915)) {
>> > > + switch (GRAPHICS_VER(engine->i915)) {
>> > > case 2:
>> > > return false; /* uses physical not virtual addresses */
>> > > case 3:
>> > > @@ -1432,7 +1432,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
>> > > struct intel_engine_execlists * const execlists = &engine->execlists;
>> > > u64 addr;
>> > >
>> > > - if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
>> > > + if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7))
>> > > drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
>> > > if (HAS_EXECLISTS(dev_priv)) {
>> > > drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
>> > > @@ -1449,13 +1449,13 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
>> > > drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
>> > > ENGINE_READ(engine, RING_CTL),
>> > > ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
>> > > - if (INTEL_GEN(engine->i915) > 2) {
>> > > + if (GRAPHICS_VER(engine->i915) > 2) {
>> > > drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
>> > > ENGINE_READ(engine, RING_MI_MODE),
>> > > ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
>> > > }
>> > >
>> > > - if (INTEL_GEN(dev_priv) >= 6) {
>> > > + if (GRAPHICS_VER(dev_priv) >= 6) {
>> > > drm_printf(m, "\tRING_IMR: 0x%08x\n",
>> > > ENGINE_READ(engine, RING_IMR));
>> > > drm_printf(m, "\tRING_ESR: 0x%08x\n",
>> > > @@ -1472,15 +1472,15 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
>> > > addr = intel_engine_get_last_batch_head(engine);
>> > > drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
>> > > upper_32_bits(addr), lower_32_bits(addr));
>> > > - if (INTEL_GEN(dev_priv) >= 8)
>> > > + if (GRAPHICS_VER(dev_priv) >= 8)
>> > > addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
>> > > - else if (INTEL_GEN(dev_priv) >= 4)
>> > > + else if (GRAPHICS_VER(dev_priv) >= 4)
>> > > addr = ENGINE_READ(engine, RING_DMA_FADD);
>> > > else
>> > > addr = ENGINE_READ(engine, DMA_FADD_I8XX);
>> > > drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
>> > > upper_32_bits(addr), lower_32_bits(addr));
>> > > - if (INTEL_GEN(dev_priv) >= 4) {
>> > > + if (GRAPHICS_VER(dev_priv) >= 4) {
>> > > drm_printf(m, "\tIPEIR: 0x%08x\n",
>> > > ENGINE_READ(engine, RING_IPEIR));
>> > > drm_printf(m, "\tIPEHR: 0x%08x\n",
>> > > @@ -1559,7 +1559,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
>> > > }
>> > > rcu_read_unlock();
>> > > execlists_active_unlock_bh(execlists);
>> > > - } else if (INTEL_GEN(dev_priv) > 6) {
>> > > + } else if (GRAPHICS_VER(dev_priv) > 6) {
>> > > drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
>> > > ENGINE_READ(engine, RING_PP_DIR_BASE));
>> > > drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> > > index 8db200422950..fc77592d88a9 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> > > @@ -1847,7 +1847,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
>> > > ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n",
>> > > head, upper_32_bits(csb), lower_32_bits(csb));
>> > >
>> > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > promote = gen12_csb_parse(csb);
>> > > else
>> > > promote = gen8_csb_parse(csb);
>> > > @@ -2772,7 +2772,7 @@ static void enable_execlists(struct intel_engine_cs *engine)
>> > >
>> > > intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
>> > >
>> > > - if (INTEL_GEN(engine->i915) >= 11)
>> > > + if (GRAPHICS_VER(engine->i915) >= 11)
>> > > mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
>> > > else
>> > > mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
>> > > @@ -3103,7 +3103,7 @@ static void execlists_park(struct intel_engine_cs *engine)
>> > >
>> > > static bool can_preempt(struct intel_engine_cs *engine)
>> > > {
>> > > - if (INTEL_GEN(engine->i915) > 8)
>> > > + if (GRAPHICS_VER(engine->i915) > 8)
>> > > return true;
>> > >
>> > > /* GPGPU on bdw requires extra w/a; not implemented */
>> > > @@ -3156,13 +3156,13 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
>> > > engine->emit_flush = gen8_emit_flush_xcs;
>> > > engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
>> > > engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
>> > > - if (INTEL_GEN(engine->i915) >= 12) {
>> > > + if (GRAPHICS_VER(engine->i915) >= 12) {
>> > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;
>> > > engine->emit_flush = gen12_emit_flush_xcs;
>> > > }
>> > > engine->set_default_submission = execlists_set_default_submission;
>> > >
>> > > - if (INTEL_GEN(engine->i915) < 11) {
>> > > + if (GRAPHICS_VER(engine->i915) < 11) {
>> > > engine->irq_enable = gen8_logical_ring_enable_irq;
>> > > engine->irq_disable = gen8_logical_ring_disable_irq;
>> > > } else {
>> > > @@ -3195,7 +3195,7 @@ static void logical_ring_default_irqs(struct intel_engine_cs *engine)
>> > > {
>> > > unsigned int shift = 0;
>> > >
>> > > - if (INTEL_GEN(engine->i915) < 11) {
>> > > + if (GRAPHICS_VER(engine->i915) < 11) {
>> > > const u8 irq_shifts[] = {
>> > > [RCS0] = GEN8_RCS_IRQ_SHIFT,
>> > > [BCS0] = GEN8_BCS_IRQ_SHIFT,
>> > > @@ -3215,7 +3215,7 @@ static void logical_ring_default_irqs(struct intel_engine_cs *engine)
>> > >
>> > > static void rcs_submission_override(struct intel_engine_cs *engine)
>> > > {
>> > > - switch (INTEL_GEN(engine->i915)) {
>> > > + switch (GRAPHICS_VER(engine->i915)) {
>> > > case 12:
>> > > engine->emit_flush = gen12_emit_flush_rcs;
>> > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
>> > > @@ -3266,13 +3266,13 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
>> > > execlists->csb_write =
>> > > &engine->status_page.addr[intel_hws_csb_write_index(i915)];
>> > >
>> > > - if (INTEL_GEN(i915) < 11)
>> > > + if (GRAPHICS_VER(i915) < 11)
>> > > execlists->csb_size = GEN8_CSB_ENTRIES;
>> > > else
>> > > execlists->csb_size = GEN11_CSB_ENTRIES;
>> > >
>> > > engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);
>> > > - if (INTEL_GEN(engine->i915) >= 11) {
>> > > + if (GRAPHICS_VER(engine->i915) >= 11) {
>> > > execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
>> > > execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
>> > > }
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> > > index 35069ca5d7de..19bd8856ce84 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> > > @@ -107,10 +107,10 @@ static bool needs_idle_maps(struct drm_i915_private *i915)
>> > > if (!intel_vtd_active())
>> > > return false;
>> > >
>> > > - if (IS_GEN(i915, 5) && IS_MOBILE(i915))
>> > > + if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
>> > > return true;
>> > >
>> > > - if (IS_GEN(i915, 12))
>> > > + if (GRAPHICS_VER(i915) == 12)
>> > > return true; /* XXX DMAR fault reason 7 */
>> > >
>> > > return false;
>> > > @@ -176,7 +176,7 @@ static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
>> > >
>> > > gen8_ggtt_invalidate(ggtt);
>> > >
>> > > - if (INTEL_GEN(i915) >= 12)
>> > > + if (GRAPHICS_VER(i915) >= 12)
>> > > intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
>> > > GEN12_GUC_TLB_INV_CR_INVALIDATE);
>> > > else
>> > > @@ -820,7 +820,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
>> > > * resort to an uncached mapping. The WC issue is easily caught by the
>> > > * readback check when writing GTT PTE entries.
>> > > */
>> > > - if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
>> > > + if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 10)
>> > > ggtt->gsm = ioremap(phys_addr, size);
>> > > else
>> > > ggtt->gsm = ioremap_wc(phys_addr, size);
>> > > @@ -1065,7 +1065,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
>> > > ggtt->vm.pte_encode = hsw_pte_encode;
>> > > else if (IS_VALLEYVIEW(i915))
>> > > ggtt->vm.pte_encode = byt_pte_encode;
>> > > - else if (INTEL_GEN(i915) >= 7)
>> > > + else if (GRAPHICS_VER(i915) >= 7)
>> > > ggtt->vm.pte_encode = ivb_pte_encode;
>> > > else
>> > > ggtt->vm.pte_encode = snb_pte_encode;
>> > > @@ -1137,9 +1137,9 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
>> > > ggtt->vm.dma = i915->drm.dev;
>> > > dma_resv_init(&ggtt->vm.resv);
>> > >
>> > > - if (INTEL_GEN(i915) <= 5)
>> > > + if (GRAPHICS_VER(i915) <= 5)
>> > > ret = i915_gmch_probe(ggtt);
>> > > - else if (INTEL_GEN(i915) < 8)
>> > > + else if (GRAPHICS_VER(i915) < 8)
>> > > ret = gen6_gmch_probe(ggtt);
>> > > else
>> > > ret = gen8_gmch_probe(ggtt);
>> > > @@ -1196,7 +1196,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
>> > >
>> > > int i915_ggtt_enable_hw(struct drm_i915_private *i915)
>> > > {
>> > > - if (INTEL_GEN(i915) < 6 && !intel_enable_gtt())
>> > > + if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
>> > > return -EIO;
>> > >
>> > > return 0;
>> > > @@ -1261,7 +1261,7 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt)
>> > > if (flush)
>> > > wbinvd_on_all_cpus();
>> > >
>> > > - if (INTEL_GEN(ggtt->vm.i915) >= 8)
>> > > + if (GRAPHICS_VER(ggtt->vm.i915) >= 8)
>> > > setup_private_pat(ggtt->vm.gt->uncore);
>> > >
>> > > intel_ggtt_restore_fences(ggtt);
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
>> > > index 7bf84cd21543..cac7f3f44642 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
>> > > @@ -56,7 +56,7 @@ static void i965_write_fence_reg(struct i915_fence_reg *fence)
>> > > int fence_pitch_shift;
>> > > u64 val;
>> > >
>> > > - if (INTEL_GEN(fence_to_i915(fence)) >= 6) {
>> > > + if (GRAPHICS_VER(fence_to_i915(fence)) >= 6) {
>> > > fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
>> > > fence_reg_hi = FENCE_REG_GEN6_HI(fence->id);
>> > > fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
>> > > @@ -173,9 +173,9 @@ static void fence_write(struct i915_fence_reg *fence)
>> > > * and explicitly managed for internal users.
>> > > */
>> > >
>> > > - if (IS_GEN(i915, 2))
>> > > + if (GRAPHICS_VER(i915) == 2)
>> > > i830_write_fence_reg(fence);
>> > > - else if (IS_GEN(i915, 3))
>> > > + else if (GRAPHICS_VER(i915) == 3)
>> > > i915_write_fence_reg(fence);
>> > > else
>> > > i965_write_fence_reg(fence);
>> > > @@ -188,7 +188,7 @@ static void fence_write(struct i915_fence_reg *fence)
>> > >
>> > > static bool gpu_uses_fence_registers(struct i915_fence_reg *fence)
>> > > {
>> > > - return INTEL_GEN(fence_to_i915(fence)) < 4;
>> > > + return GRAPHICS_VER(fence_to_i915(fence)) < 4;
>> > > }
>> > >
>> > > static int fence_update(struct i915_fence_reg *fence,
>> > > @@ -569,7 +569,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
>> > > u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
>> > > u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>> > >
>> > > - if (INTEL_GEN(i915) >= 8 || IS_VALLEYVIEW(i915)) {
>> > > + if (GRAPHICS_VER(i915) >= 8 || IS_VALLEYVIEW(i915)) {
>> > > /*
>> > > * On BDW+, swizzling is not used. We leave the CPU memory
>> > > * controller in charge of optimizing memory accesses without
>> > > @@ -579,7 +579,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
>> > > */
>> > > swizzle_x = I915_BIT_6_SWIZZLE_NONE;
>> > > swizzle_y = I915_BIT_6_SWIZZLE_NONE;
>> > > - } else if (INTEL_GEN(i915) >= 6) {
>> > > + } else if (GRAPHICS_VER(i915) >= 6) {
>> > > if (i915->preserve_bios_swizzle) {
>> > > if (intel_uncore_read(uncore, DISP_ARB_CTL) &
>> > > DISP_TILE_SURFACE_SWIZZLING) {
>> > > @@ -611,14 +611,14 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
>> > > swizzle_y = I915_BIT_6_SWIZZLE_NONE;
>> > > }
>> > > }
>> > > - } else if (IS_GEN(i915, 5)) {
>> > > + } else if (GRAPHICS_VER(i915) == 5) {
>> > > /*
>> > > * On Ironlake whatever DRAM config, GPU always do
>> > > * same swizzling setup.
>> > > */
>> > > swizzle_x = I915_BIT_6_SWIZZLE_9_10;
>> > > swizzle_y = I915_BIT_6_SWIZZLE_9;
>> > > - } else if (IS_GEN(i915, 2)) {
>> > > + } else if (GRAPHICS_VER(i915) == 2) {
>> > > /*
>> > > * As far as we know, the 865 doesn't have these bit 6
>> > > * swizzling issues.
>> > > @@ -697,7 +697,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
>> > > }
>> > >
>> > > /* check for L-shaped memory aka modified enhanced addressing */
>> > > - if (IS_GEN(i915, 4) &&
>> > > + if (GRAPHICS_VER(i915) == 4 &&
>> > > !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
>> > > swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
>> > > swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>> > > @@ -844,10 +844,10 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
>> > >
>> > > if (!i915_ggtt_has_aperture(ggtt))
>> > > num_fences = 0;
>> > > - else if (INTEL_GEN(i915) >= 7 &&
>> > > + else if (GRAPHICS_VER(i915) >= 7 &&
>> > > !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
>> > > num_fences = 32;
>> > > - else if (INTEL_GEN(i915) >= 4 ||
>> > > + else if (GRAPHICS_VER(i915) >= 4 ||
>> > > IS_I945G(i915) || IS_I945GM(i915) ||
>> > > IS_G33(i915) || IS_PINEVIEW(i915))
>> > > num_fences = 16;
>> > > @@ -895,29 +895,29 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
>> > > struct drm_i915_private *i915 = gt->i915;
>> > > struct intel_uncore *uncore = gt->uncore;
>> > >
>> > > - if (INTEL_GEN(i915) < 5 ||
>> > > + if (GRAPHICS_VER(i915) < 5 ||
>> > > i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
>> > > return;
>> > >
>> > > intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
>> > >
>> > > - if (IS_GEN(i915, 5))
>> > > + if (GRAPHICS_VER(i915) == 5)
>> > > return;
>> > >
>> > > intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL);
>> > >
>> > > - if (IS_GEN(i915, 6))
>> > > + if (GRAPHICS_VER(i915) == 6)
>> > > intel_uncore_write(uncore,
>> > > ARB_MODE,
>> > > _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
>> > > - else if (IS_GEN(i915, 7))
>> > > + else if (GRAPHICS_VER(i915) == 7)
>> > > intel_uncore_write(uncore,
>> > > ARB_MODE,
>> > > _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
>> > > - else if (IS_GEN(i915, 8))
>> > > + else if (GRAPHICS_VER(i915) == 8)
>> > > intel_uncore_write(uncore,
>> > > GAMTARBMODE,
>> > > _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
>> > > else
>> > > - MISSING_CASE(INTEL_GEN(i915));
>> > > + MISSING_CASE(GRAPHICS_VER(i915));
>> > > }
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>> > > index 8d77dcbad059..7f24301cef18 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> > > @@ -115,10 +115,10 @@ static void init_unused_rings(struct intel_gt *gt)
>> > > init_unused_ring(gt, SRB1_BASE);
>> > > init_unused_ring(gt, SRB2_BASE);
>> > > init_unused_ring(gt, SRB3_BASE);
>> > > - } else if (IS_GEN(i915, 2)) {
>> > > + } else if (GRAPHICS_VER(i915) == 2) {
>> > > init_unused_ring(gt, SRB0_BASE);
>> > > init_unused_ring(gt, SRB1_BASE);
>> > > - } else if (IS_GEN(i915, 3)) {
>> > > + } else if (GRAPHICS_VER(i915) == 3) {
>> > > init_unused_ring(gt, PRB1_BASE);
>> > > init_unused_ring(gt, PRB2_BASE);
>> > > }
>> > > @@ -135,7 +135,7 @@ int intel_gt_init_hw(struct intel_gt *gt)
>> > > /* Double layer security blanket, see i915_gem_init() */
>> > > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>> > >
>> > > - if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
>> > > + if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
>> > > intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
>> > >
>> > > if (IS_HASWELL(i915))
>> > > @@ -208,10 +208,10 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
>> > > struct intel_uncore *uncore = gt->uncore;
>> > > u32 eir;
>> > >
>> > > - if (!IS_GEN(i915, 2))
>> > > + if (GRAPHICS_VER(i915) != 2)
>> > > clear_register(uncore, PGTBL_ER);
>> > >
>> > > - if (INTEL_GEN(i915) < 4)
>> > > + if (GRAPHICS_VER(i915) < 4)
>> > > clear_register(uncore, IPEIR(RENDER_RING_BASE));
>> > > else
>> > > clear_register(uncore, IPEIR_I965);
>> > > @@ -229,13 +229,13 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
>> > > I915_MASTER_ERROR_INTERRUPT);
>> > > }
>> > >
>> > > - if (INTEL_GEN(i915) >= 12) {
>> > > + if (GRAPHICS_VER(i915) >= 12) {
>> > > rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
>> > > intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
>> > > - } else if (INTEL_GEN(i915) >= 8) {
>> > > + } else if (GRAPHICS_VER(i915) >= 8) {
>> > > rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
>> > > intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
>> > > - } else if (INTEL_GEN(i915) >= 6) {
>> > > + } else if (GRAPHICS_VER(i915) >= 6) {
>> > > struct intel_engine_cs *engine;
>> > > enum intel_engine_id id;
>> > >
>> > > @@ -273,7 +273,7 @@ static void gen8_check_faults(struct intel_gt *gt)
>> > > i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
>> > > u32 fault;
>> > >
>> > > - if (INTEL_GEN(gt->i915) >= 12) {
>> > > + if (GRAPHICS_VER(gt->i915) >= 12) {
>> > > fault_reg = GEN12_RING_FAULT_REG;
>> > > fault_data0_reg = GEN12_FAULT_TLB_DATA0;
>> > > fault_data1_reg = GEN12_FAULT_TLB_DATA1;
>> > > @@ -313,9 +313,9 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
>> > > struct drm_i915_private *i915 = gt->i915;
>> > >
>> > > /* From GEN8 onwards we only have one 'All Engine Fault Register' */
>> > > - if (INTEL_GEN(i915) >= 8)
>> > > + if (GRAPHICS_VER(i915) >= 8)
>> > > gen8_check_faults(gt);
>> > > - else if (INTEL_GEN(i915) >= 6)
>> > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > gen6_check_faults(gt);
>> > > else
>> > > return;
>> > > @@ -367,7 +367,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
>> > > void intel_gt_chipset_flush(struct intel_gt *gt)
>> > > {
>> > > wmb();
>> > > - if (INTEL_GEN(gt->i915) < 6)
>> > > + if (GRAPHICS_VER(gt->i915) < 6)
>> > > intel_gtt_chipset_flush();
>> > > }
>> > >
>> > > @@ -591,7 +591,8 @@ int intel_gt_init(struct intel_gt *gt)
>> > > */
>> > > intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
>> > >
>> > > - err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K);
>> > > + err = intel_gt_init_scratch(gt,
>> > > + GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
>> > > if (err)
>> > > goto out_fw;
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
>> > > index 582fcaee11aa..9f0e729d2d15 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
>> > > @@ -76,7 +76,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> > > u32 f19_2_mhz = 19200000;
>> > > u32 f24_mhz = 24000000;
>> > >
>> > > - if (INTEL_GEN(uncore->i915) <= 4) {
>> > > + if (GRAPHICS_VER(uncore->i915) <= 4) {
>> > > /*
>> > > * PRMs say:
>> > > *
>> > > @@ -85,7 +85,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> > > * (“CLKCFG”) MCHBAR register)
>> > > */
>> > > return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
>> > > - } else if (INTEL_GEN(uncore->i915) <= 8) {
>> > > + } else if (GRAPHICS_VER(uncore->i915) <= 8) {
>> > > /*
>> > > * PRMs say:
>> > > *
>> > > @@ -94,7 +94,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> > > * rolling over every 1.5 hours).
>> > > */
>> > > return f12_5_mhz;
>> > > - } else if (INTEL_GEN(uncore->i915) <= 9) {
>> > > + } else if (GRAPHICS_VER(uncore->i915) <= 9) {
>> > > u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
>> > > u32 freq = 0;
>> > >
>> > > @@ -113,7 +113,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> > > }
>> > >
>> > > return freq;
>> > > - } else if (INTEL_GEN(uncore->i915) <= 12) {
>> > > + } else if (GRAPHICS_VER(uncore->i915) <= 12) {
>> > > u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
>> > > u32 freq = 0;
>> > >
>> > > @@ -128,7 +128,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> > > } else {
>> > > u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
>> > >
>> > > - if (INTEL_GEN(uncore->i915) <= 10)
>> > > + if (GRAPHICS_VER(uncore->i915) <= 10)
>> > > freq = gen10_get_crystal_clock_freq(uncore, c0);
>> > > else
>> > > freq = gen11_get_crystal_clock_freq(uncore, c0);
>> > > @@ -211,7 +211,7 @@ u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns)
>> > > * frozen machine.
>> > > */
>> > > val = div_u64_roundup(intel_gt_ns_to_clock_interval(gt, ns), 16);
>> > > - if (IS_GEN(gt->i915, 6))
>> > > + if (GRAPHICS_VER(gt->i915) == 6)
>> > > val = div_u64_roundup(val, 25) * 25;
>> > >
>> > > return val;
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> > > index d29126c458ba..1ec63cceabf6 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> > > @@ -395,7 +395,7 @@ void gen5_gt_irq_reset(struct intel_gt *gt)
>> > > struct intel_uncore *uncore = gt->uncore;
>> > >
>> > > GEN3_IRQ_RESET(uncore, GT);
>> > > - if (INTEL_GEN(gt->i915) >= 6)
>> > > + if (GRAPHICS_VER(gt->i915) >= 6)
>> > > GEN3_IRQ_RESET(uncore, GEN6_PM);
>> > > }
>> > >
>> > > @@ -413,14 +413,14 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt)
>> > > }
>> > >
>> > > gt_irqs |= GT_RENDER_USER_INTERRUPT;
>> > > - if (IS_GEN(gt->i915, 5))
>> > > + if (GRAPHICS_VER(gt->i915) == 5)
>> > > gt_irqs |= ILK_BSD_USER_INTERRUPT;
>> > > else
>> > > gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
>> > >
>> > > GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs);
>> > >
>> > > - if (INTEL_GEN(gt->i915) >= 6) {
>> > > + if (GRAPHICS_VER(gt->i915) >= 6) {
>> > > /*
>> > > * RPS interrupts will get enabled/disabled on demand when RPS
>> > > * itself is enabled/disabled.
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
>> > > index 811a11ed181c..fe51f894b073 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
>> > > @@ -16,10 +16,10 @@ static void write_pm_imr(struct intel_gt *gt)
>> > > u32 mask = gt->pm_imr;
>> > > i915_reg_t reg;
>> > >
>> > > - if (INTEL_GEN(i915) >= 11) {
>> > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
>> > > mask <<= 16; /* pm is in upper half */
>> > > - } else if (INTEL_GEN(i915) >= 8) {
>> > > + } else if (GRAPHICS_VER(i915) >= 8) {
>> > > reg = GEN8_GT_IMR(2);
>> > > } else {
>> > > reg = GEN6_PMIMR;
>> > > @@ -61,7 +61,7 @@ void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask)
>> > > void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)
>> > > {
>> > > struct intel_uncore *uncore = gt->uncore;
>> > > - i915_reg_t reg = INTEL_GEN(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
>> > > + i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
>> > >
>> > > lockdep_assert_held(>->irq_lock);
>> > >
>> > > @@ -77,10 +77,10 @@ static void write_pm_ier(struct intel_gt *gt)
>> > > u32 mask = gt->pm_ier;
>> > > i915_reg_t reg;
>> > >
>> > > - if (INTEL_GEN(i915) >= 11) {
>> > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
>> > > mask <<= 16; /* pm is in upper half */
>> > > - } else if (INTEL_GEN(i915) >= 8) {
>> > > + } else if (GRAPHICS_VER(i915) >= 8) {
>> > > reg = GEN8_GT_IER(2);
>> > > } else {
>> > > reg = GEN6_PMIER;
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
>> > > index 9b98f9d9faa3..b9c9993573ec 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
>> > > @@ -327,7 +327,7 @@ void gtt_write_workarounds(struct intel_gt *gt)
>> > > intel_uncore_write(uncore,
>> > > GEN8_L3_LRA_1_GPGPU,
>> > > GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
>> > > - else if (INTEL_GEN(i915) >= 9 && INTEL_GEN(i915) <= 11)
>> > > + else if (GRAPHICS_VER(i915) >= 9 && GRAPHICS_VER(i915) <= 11)
>> > > intel_uncore_write(uncore,
>> > > GEN8_L3_LRA_1_GPGPU,
>> > > GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>> > > @@ -344,13 +344,13 @@ void gtt_write_workarounds(struct intel_gt *gt)
>> > > * driver.
>> > > */
>> > > if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
>> > > - INTEL_GEN(i915) <= 10)
>> > > + GRAPHICS_VER(i915) <= 10)
>> > > intel_uncore_rmw(uncore,
>> > > GEN8_GAMW_ECO_DEV_RW_IA,
>> > > 0,
>> > > GAMW_ECO_ENABLE_64K_IPS_FIELD);
>> > >
>> > > - if (IS_GEN_RANGE(i915, 8, 11)) {
>> > > + if (IS_GRAPHICS_VER(i915, 8, 11)) {
>> > > bool can_use_gtt_cache = true;
>> > >
>> > > /*
>> > > @@ -432,7 +432,7 @@ static void bdw_setup_private_ppat(struct intel_uncore *uncore)
>> > > GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
>> > >
>> > > /* for scanout with eLLC */
>> > > - if (INTEL_GEN(i915) >= 9)
>> > > + if (GRAPHICS_VER(i915) >= 9)
>> > > pat |= GEN8_PPAT(2, GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE);
>> > > else
>> > > pat |= GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
>> > > @@ -481,11 +481,11 @@ void setup_private_pat(struct intel_uncore *uncore)
>> > > {
>> > > struct drm_i915_private *i915 = uncore->i915;
>> > >
>> > > - GEM_BUG_ON(INTEL_GEN(i915) < 8);
>> > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
>> > >
>> > > - if (INTEL_GEN(i915) >= 12)
>> > > + if (GRAPHICS_VER(i915) >= 12)
>> > > tgl_setup_private_ppat(uncore);
>> > > - else if (INTEL_GEN(i915) >= 10)
>> > > + else if (GRAPHICS_VER(i915) >= 10)
>> > > cnl_setup_private_ppat(uncore);
>> > > else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))
>> > > chv_setup_private_ppat(uncore);
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
>> > > index 075d741644ae..eb1a15deed22 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_llc.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_llc.c
>> > > @@ -64,7 +64,7 @@ static bool get_ia_constants(struct intel_llc *llc,
>> > >
>> > > consts->min_gpu_freq = rps->min_freq;
>> > > consts->max_gpu_freq = rps->max_freq;
>> > > - if (INTEL_GEN(i915) >= 9) {
>> > > + if (GRAPHICS_VER(i915) >= 9) {
>> > > /* Convert GT frequency to 50 HZ units */
>> > > consts->min_gpu_freq /= GEN9_FREQ_SCALER;
>> > > consts->max_gpu_freq /= GEN9_FREQ_SCALER;
>> > > @@ -83,13 +83,13 @@ static void calc_ia_freq(struct intel_llc *llc,
>> > > const int diff = consts->max_gpu_freq - gpu_freq;
>> > > unsigned int ia_freq = 0, ring_freq = 0;
>> > >
>> > > - if (INTEL_GEN(i915) >= 9) {
>> > > + if (GRAPHICS_VER(i915) >= 9) {
>> > > /*
>> > > * ring_freq = 2 * GT. ring_freq is in 100MHz units
>> > > * No floor required for ring frequency on SKL.
>> > > */
>> > > ring_freq = gpu_freq;
>> > > - } else if (INTEL_GEN(i915) >= 8) {
>> > > + } else if (GRAPHICS_VER(i915) >= 8) {
>> > > /* max(2 * GT, DDR). NB: GT is 50MHz units */
>> > > ring_freq = max(consts->min_ring_freq, gpu_freq);
>> > > } else if (IS_HASWELL(i915)) {
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > > index aafe2a4df496..a27bac0a4bfb 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > > @@ -47,7 +47,7 @@ static void set_offsets(u32 *regs,
>> > > *regs = MI_LOAD_REGISTER_IMM(count);
>> > > if (flags & POSTED)
>> > > *regs |= MI_LRI_FORCE_POSTED;
>> > > - if (INTEL_GEN(engine->i915) >= 11)
>> > > + if (GRAPHICS_VER(engine->i915) >= 11)
>> > > *regs |= MI_LRI_LRM_CS_MMIO;
>> > > regs++;
>> > >
>> > > @@ -70,7 +70,7 @@ static void set_offsets(u32 *regs,
>> > > if (close) {
>> > > /* Close the batch; used mainly by live_lrc_layout() */
>> > > *regs = MI_BATCH_BUFFER_END;
>> > > - if (INTEL_GEN(engine->i915) >= 10)
>> > > + if (GRAPHICS_VER(engine->i915) >= 10)
>> > > *regs |= BIT(0);
>> > > }
>> > > }
>> > > @@ -498,22 +498,22 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
>> > > * addressing to automatic fixup the register state between the
>> > > * physical engines for virtual engine.
>> > > */
>> > > - GEM_BUG_ON(INTEL_GEN(engine->i915) >= 12 &&
>> > > + GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
>> > > !intel_engine_has_relative_mmio(engine));
>> > >
>> > > if (engine->class == RENDER_CLASS) {
>> > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > return gen12_rcs_offsets;
>> > > - else if (INTEL_GEN(engine->i915) >= 11)
>> > > + else if (GRAPHICS_VER(engine->i915) >= 11)
>> > > return gen11_rcs_offsets;
>> > > - else if (INTEL_GEN(engine->i915) >= 9)
>> > > + else if (GRAPHICS_VER(engine->i915) >= 9)
>> > > return gen9_rcs_offsets;
>> > > else
>> > > return gen8_rcs_offsets;
>> > > } else {
>> > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > return gen12_xcs_offsets;
>> > > - else if (INTEL_GEN(engine->i915) >= 9)
>> > > + else if (GRAPHICS_VER(engine->i915) >= 9)
>> > > return gen9_xcs_offsets;
>> > > else
>> > > return gen8_xcs_offsets;
>> > > @@ -522,9 +522,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
>> > >
>> > > static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
>> > > {
>> > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > return 0x60;
>> > > - else if (INTEL_GEN(engine->i915) >= 9)
>> > > + else if (GRAPHICS_VER(engine->i915) >= 9)
>> > > return 0x54;
>> > > else if (engine->class == RENDER_CLASS)
>> > > return 0x58;
>> > > @@ -534,9 +534,9 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
>> > >
>> > > static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
>> > > {
>> > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > return 0x74;
>> > > - else if (INTEL_GEN(engine->i915) >= 9)
>> > > + else if (GRAPHICS_VER(engine->i915) >= 9)
>> > > return 0x68;
>> > > else if (engine->class == RENDER_CLASS)
>> > > return 0xd8;
>> > > @@ -546,9 +546,9 @@ static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
>> > >
>> > > static int lrc_ring_wa_bb_per_ctx(const struct intel_engine_cs *engine)
>> > > {
>> > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > return 0x12;
>> > > - else if (INTEL_GEN(engine->i915) >= 9 || engine->class == RENDER_CLASS)
>> > > + else if (GRAPHICS_VER(engine->i915) >= 9 || engine->class == RENDER_CLASS)
>> > > return 0x18;
>> > > else
>> > > return -1;
>> > > @@ -581,9 +581,9 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
>> > > if (engine->class != RENDER_CLASS)
>> > > return -1;
>> > >
>> > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > return 0xb6;
>> > > - else if (INTEL_GEN(engine->i915) >= 11)
>> > > + else if (GRAPHICS_VER(engine->i915) >= 11)
>> > > return 0xaa;
>> > > else
>> > > return -1;
>> > > @@ -592,9 +592,9 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
>> > > static u32
>> > > lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
>> > > {
>> > > - switch (INTEL_GEN(engine->i915)) {
>> > > + switch (GRAPHICS_VER(engine->i915)) {
>> > > default:
>> > > - MISSING_CASE(INTEL_GEN(engine->i915));
>> > > + MISSING_CASE(GRAPHICS_VER(engine->i915));
>> > > fallthrough;
>> > > case 12:
>> > > return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
>> > > @@ -637,7 +637,7 @@ static void init_common_regs(u32 * const regs,
>> > > ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
>> > > if (inhibit)
>> > > ctl |= CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT;
>> > > - if (INTEL_GEN(engine->i915) < 11)
>> > > + if (GRAPHICS_VER(engine->i915) < 11)
>> > > ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
>> > > CTX_CTRL_RS_CTX_ENABLE);
>> > > regs[CTX_CONTEXT_CONTROL] = ctl;
>> > > @@ -805,7 +805,7 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
>> > > if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
>> > > context_size += I915_GTT_PAGE_SIZE; /* for redzone */
>> > >
>> > > - if (INTEL_GEN(engine->i915) == 12) {
>> > > + if (GRAPHICS_VER(engine->i915) == 12) {
>> > > ce->wa_bb_page = context_size / PAGE_SIZE;
>> > > context_size += PAGE_SIZE;
>> > > }
>> > > @@ -1114,7 +1114,7 @@ static u32 lrc_descriptor(const struct intel_context *ce)
>> > > desc <<= GEN8_CTX_ADDRESSING_MODE_SHIFT;
>> > >
>> > > desc |= GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
>> > > - if (IS_GEN(ce->vm->i915, 8))
>> > > + if (GRAPHICS_VER(ce->vm->i915) == 8)
>> > > desc |= GEN8_CTX_L3LLC_COHERENT;
>> > >
>> > > return i915_ggtt_offset(ce->state) | desc;
>> > > @@ -1469,7 +1469,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
>> > > if (engine->class != RENDER_CLASS)
>> > > return;
>> > >
>> > > - switch (INTEL_GEN(engine->i915)) {
>> > > + switch (GRAPHICS_VER(engine->i915)) {
>> > > case 12:
>> > > case 11:
>> > > return;
>> > > @@ -1486,7 +1486,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
>> > > wa_bb_fn[1] = NULL;
>> > > break;
>> > > default:
>> > > - MISSING_CASE(INTEL_GEN(engine->i915));
>> > > + MISSING_CASE(GRAPHICS_VER(engine->i915));
>> > > return;
>> > > }
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
>> > > index b14138fd505c..17848807f111 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
>> > > @@ -344,11 +344,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>> > > table->size = ARRAY_SIZE(dg1_mocs_table);
>> > > table->table = dg1_mocs_table;
>> > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>> > > - } else if (INTEL_GEN(i915) >= 12) {
>> > > + } else if (GRAPHICS_VER(i915) >= 12) {
>> > > table->size = ARRAY_SIZE(tgl_mocs_table);
>> > > table->table = tgl_mocs_table;
>> > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>> > > - } else if (IS_GEN(i915, 11)) {
>> > > + } else if (GRAPHICS_VER(i915) == 11) {
>> > > table->size = ARRAY_SIZE(icl_mocs_table);
>> > > table->table = icl_mocs_table;
>> > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>> > > @@ -361,7 +361,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>> > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>> > > table->table = broxton_mocs_table;
>> > > } else {
>> > > - drm_WARN_ONCE(&i915->drm, INTEL_GEN(i915) >= 9,
>> > > + drm_WARN_ONCE(&i915->drm, GRAPHICS_VER(i915) >= 9,
>> > > "Platform that should have a MOCS table does not.\n");
>> > > return 0;
>> > > }
>> > > @@ -370,7 +370,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>> > > return 0;
>> > >
>> > > /* WaDisableSkipCaching:skl,bxt,kbl,glk */
>> > > - if (IS_GEN(i915, 9)) {
>> > > + if (GRAPHICS_VER(i915) == 9) {
>> > > int i;
>> > >
>> > > for (i = 0; i < table->size; i++)
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>> > > index 4e3d80c2295c..3891c078906e 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>> > > @@ -146,9 +146,9 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
>> > >
>> > > gtt_write_workarounds(gt);
>> > >
>> > > - if (IS_GEN(i915, 6))
>> > > + if (GRAPHICS_VER(i915) == 6)
>> > > gen6_ppgtt_enable(gt);
>> > > - else if (IS_GEN(i915, 7))
>> > > + else if (GRAPHICS_VER(i915) == 7)
>> > > gen7_ppgtt_enable(gt);
>> > >
>> > > return 0;
>> > > @@ -157,7 +157,7 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
>> > > static struct i915_ppgtt *
>> > > __ppgtt_create(struct intel_gt *gt)
>> > > {
>> > > - if (INTEL_GEN(gt->i915) < 8)
>> > > + if (GRAPHICS_VER(gt->i915) < 8)
>> > > return gen6_ppgtt_create(gt);
>> > > else
>> > > return gen8_ppgtt_create(gt);
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
>> > > index 3b7e62debe7e..259d7eb4e165 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>> > > @@ -109,7 +109,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
>> > > GEN9_MEDIA_PG_ENABLE |
>> > > GEN11_MEDIA_SAMPLER_PG_ENABLE;
>> > >
>> > > - if (INTEL_GEN(gt->i915) >= 12) {
>> > > + if (GRAPHICS_VER(gt->i915) >= 12) {
>> > > for (i = 0; i < I915_MAX_VCS; i++)
>> > > if (HAS_ENGINE(gt, _VCS(i)))
>> > > pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
>> > > @@ -126,7 +126,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
>> > > enum intel_engine_id id;
>> > >
>> > > /* 2b: Program RC6 thresholds.*/
>> > > - if (INTEL_GEN(rc6_to_i915(rc6)) >= 10) {
>> > > + if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 10) {
>> > > set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
>> > > set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
>> > > } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
>> > > @@ -249,9 +249,9 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
>> > > rc6vids = 0;
>> > > ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
>> > > &rc6vids, NULL);
>> > > - if (IS_GEN(i915, 6) && ret) {
>> > > + if (GRAPHICS_VER(i915) == 6 && ret) {
>> > > drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
>> > > - } else if (IS_GEN(i915, 6) &&
>> > > + } else if (GRAPHICS_VER(i915) == 6 &&
>> > > (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
>> > > drm_dbg(&i915->drm,
>> > > "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
>> > > @@ -515,7 +515,7 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
>> > > struct intel_uncore *uncore = rc6_to_uncore(rc6);
>> > >
>> > > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>> > > - if (INTEL_GEN(i915) >= 9)
>> > > + if (GRAPHICS_VER(i915) >= 9)
>> > > set(uncore, GEN9_PG_ENABLE, 0);
>> > > set(uncore, GEN6_RC_CONTROL, 0);
>> > > set(uncore, GEN6_RC_STATE, 0);
>> > > @@ -575,13 +575,13 @@ void intel_rc6_enable(struct intel_rc6 *rc6)
>> > > chv_rc6_enable(rc6);
>> > > else if (IS_VALLEYVIEW(i915))
>> > > vlv_rc6_enable(rc6);
>> > > - else if (INTEL_GEN(i915) >= 11)
>> > > + else if (GRAPHICS_VER(i915) >= 11)
>> > > gen11_rc6_enable(rc6);
>> > > - else if (INTEL_GEN(i915) >= 9)
>> > > + else if (GRAPHICS_VER(i915) >= 9)
>> > > gen9_rc6_enable(rc6);
>> > > else if (IS_BROADWELL(i915))
>> > > gen8_rc6_enable(rc6);
>> > > - else if (INTEL_GEN(i915) >= 6)
>> > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > gen6_rc6_enable(rc6);
>> > >
>> > > rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE;
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
>> > > index b03e197b1d99..b575cd6e0b7a 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
>> > > @@ -15,7 +15,7 @@ render_state_get_rodata(const struct intel_engine_cs *engine)
>> > > if (engine->class != RENDER_CLASS)
>> > > return NULL;
>> > >
>> > > - switch (INTEL_GEN(engine->i915)) {
>> > > + switch (GRAPHICS_VER(engine->i915)) {
>> > > case 6:
>> > > return &gen6_null_state;
>> > > case 7:
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
>> > > index d5094be6d90f..27315d7f8935 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>> > > @@ -565,7 +565,7 @@ static int gen8_reset_engines(struct intel_gt *gt,
>> > > */
>> > > }
>> > >
>> > > - if (INTEL_GEN(gt->i915) >= 11)
>> > > + if (GRAPHICS_VER(gt->i915) >= 11)
>> > > ret = gen11_reset_engines(gt, engine_mask, retry);
>> > > else
>> > > ret = gen6_reset_engines(gt, engine_mask, retry);
>> > > @@ -594,17 +594,17 @@ static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
>> > >
>> > > if (is_mock_gt(gt))
>> > > return mock_reset;
>> > > - else if (INTEL_GEN(i915) >= 8)
>> > > + else if (GRAPHICS_VER(i915) >= 8)
>> > > return gen8_reset_engines;
>> > > - else if (INTEL_GEN(i915) >= 6)
>> > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > return gen6_reset_engines;
>> > > - else if (INTEL_GEN(i915) >= 5)
>> > > + else if (GRAPHICS_VER(i915) >= 5)
>> > > return ilk_do_reset;
>> > > else if (IS_G4X(i915))
>> > > return g4x_do_reset;
>> > > else if (IS_G33(i915) || IS_PINEVIEW(i915))
>> > > return g33_do_reset;
>> > > - else if (INTEL_GEN(i915) >= 3)
>> > > + else if (GRAPHICS_VER(i915) >= 3)
>> > > return i915_do_reset;
>> > > else
>> > > return NULL;
>> > > @@ -656,7 +656,7 @@ bool intel_has_reset_engine(const struct intel_gt *gt)
>> > > int intel_reset_guc(struct intel_gt *gt)
>> > > {
>> > > u32 guc_domain =
>> > > - INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
>> > > + GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
>> > > int ret;
>> > >
>> > > GEM_BUG_ON(!HAS_GT_UC(gt->i915));
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> > > index 2b6dffcc2262..0c423f096e2b 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> > > @@ -29,7 +29,7 @@ static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
>> > > * lost interrupts following a reset.
>> > > */
>> > > if (engine->class == RENDER_CLASS) {
>> > > - if (INTEL_GEN(engine->i915) >= 6)
>> > > + if (GRAPHICS_VER(engine->i915) >= 6)
>> > > mask &= ~BIT(0);
>> > > else
>> > > mask &= ~I915_USER_INTERRUPT;
>> > > @@ -43,7 +43,7 @@ static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
>> > > u32 addr;
>> > >
>> > > addr = lower_32_bits(phys);
>> > > - if (INTEL_GEN(engine->i915) >= 4)
>> > > + if (GRAPHICS_VER(engine->i915) >= 4)
>> > > addr |= (phys >> 28) & 0xf0;
>> > >
>> > > intel_uncore_write(engine->uncore, HWS_PGA, addr);
>> > > @@ -71,7 +71,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
>> > > * The ring status page addresses are no longer next to the rest of
>> > > * the ring registers as of gen7.
>> > > */
>> > > - if (IS_GEN(engine->i915, 7)) {
>> > > + if (GRAPHICS_VER(engine->i915) == 7) {
>> > > switch (engine->id) {
>> > > /*
>> > > * No more rings exist on Gen7. Default case is only to shut up
>> > > @@ -93,7 +93,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
>> > > hwsp = VEBOX_HWS_PGA_GEN7;
>> > > break;
>> > > }
>> > > - } else if (IS_GEN(engine->i915, 6)) {
>> > > + } else if (GRAPHICS_VER(engine->i915) == 6) {
>> > > hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
>> > > } else {
>> > > hwsp = RING_HWS_PGA(engine->mmio_base);
>> > > @@ -105,7 +105,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
>> > >
>> > > static void flush_cs_tlb(struct intel_engine_cs *engine)
>> > > {
>> > > - if (!IS_GEN_RANGE(engine->i915, 6, 7))
>> > > + if (!IS_GRAPHICS_VER(engine->i915, 6, 7))
>> > > return;
>> > >
>> > > /* ring should be idle before issuing a sync flush*/
>> > > @@ -153,7 +153,7 @@ static void set_pp_dir(struct intel_engine_cs *engine)
>> > > ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
>> > > ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm));
>> > >
>> > > - if (INTEL_GEN(engine->i915) >= 7) {
>> > > + if (GRAPHICS_VER(engine->i915) >= 7) {
>> > > ENGINE_WRITE_FW(engine,
>> > > RING_MODE_GEN7,
>> > > _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
>> > > @@ -229,7 +229,7 @@ static int xcs_resume(struct intel_engine_cs *engine)
>> > > 5000, 0, NULL))
>> > > goto err;
>> > >
>> > > - if (INTEL_GEN(engine->i915) > 2)
>> > > + if (GRAPHICS_VER(engine->i915) > 2)
>> > > ENGINE_WRITE_FW(engine,
>> > > RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
>> > >
>> > > @@ -646,9 +646,9 @@ static int mi_set_context(struct i915_request *rq,
>> > > u32 *cs;
>> > >
>> > > len = 4;
>> > > - if (IS_GEN(i915, 7))
>> > > + if (GRAPHICS_VER(i915) == 7)
>> > > len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
>> > > - else if (IS_GEN(i915, 5))
>> > > + else if (GRAPHICS_VER(i915) == 5)
>> > > len += 2;
>> > > if (flags & MI_FORCE_RESTORE) {
>> > > GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
>> > > @@ -662,7 +662,7 @@ static int mi_set_context(struct i915_request *rq,
>> > > return PTR_ERR(cs);
>> > >
>> > > /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
>> > > - if (IS_GEN(i915, 7)) {
>> > > + if (GRAPHICS_VER(i915) == 7) {
>> > > *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
>> > > if (num_engines) {
>> > > struct intel_engine_cs *signaller;
>> > > @@ -678,7 +678,7 @@ static int mi_set_context(struct i915_request *rq,
>> > > GEN6_PSMI_SLEEP_MSG_DISABLE);
>> > > }
>> > > }
>> > > - } else if (IS_GEN(i915, 5)) {
>> > > + } else if (GRAPHICS_VER(i915) == 5) {
>> > > /*
>> > > * This w/a is only listed for pre-production ilk a/b steppings,
>> > > * but is also mentioned for programming the powerctx. To be
>> > > @@ -716,7 +716,7 @@ static int mi_set_context(struct i915_request *rq,
>> > > */
>> > > *cs++ = MI_NOOP;
>> > >
>> > > - if (IS_GEN(i915, 7)) {
>> > > + if (GRAPHICS_VER(i915) == 7) {
>> > > if (num_engines) {
>> > > struct intel_engine_cs *signaller;
>> > > i915_reg_t last_reg = {}; /* keep gcc quiet */
>> > > @@ -740,7 +740,7 @@ static int mi_set_context(struct i915_request *rq,
>> > > *cs++ = MI_NOOP;
>> > > }
>> > > *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
>> > > - } else if (IS_GEN(i915, 5)) {
>> > > + } else if (GRAPHICS_VER(i915) == 5) {
>> > > *cs++ = MI_SUSPEND_FLUSH;
>> > > }
>> > >
>> > > @@ -1001,7 +1001,7 @@ static void ring_release(struct intel_engine_cs *engine)
>> > > {
>> > > struct drm_i915_private *dev_priv = engine->i915;
>> > >
>> > > - drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) > 2 &&
>> > > + drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) > 2 &&
>> > > (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
>> > >
>> > > intel_engine_cleanup_common(engine);
>> > > @@ -1029,13 +1029,13 @@ static void setup_irq(struct intel_engine_cs *engine)
>> > >
>> > > intel_engine_set_irq_handler(engine, irq_handler);
>> > >
>> > > - if (INTEL_GEN(i915) >= 6) {
>> > > + if (GRAPHICS_VER(i915) >= 6) {
>> > > engine->irq_enable = gen6_irq_enable;
>> > > engine->irq_disable = gen6_irq_disable;
>> > > - } else if (INTEL_GEN(i915) >= 5) {
>> > > + } else if (GRAPHICS_VER(i915) >= 5) {
>> > > engine->irq_enable = gen5_irq_enable;
>> > > engine->irq_disable = gen5_irq_disable;
>> > > - } else if (INTEL_GEN(i915) >= 3) {
>> > > + } else if (GRAPHICS_VER(i915) >= 3) {
>> > > engine->irq_enable = gen3_irq_enable;
>> > > engine->irq_disable = gen3_irq_disable;
>> > > } else {
>> > > @@ -1049,7 +1049,7 @@ static void setup_common(struct intel_engine_cs *engine)
>> > > struct drm_i915_private *i915 = engine->i915;
>> > >
>> > > /* gen8+ are only supported with execlists */
>> > > - GEM_BUG_ON(INTEL_GEN(i915) >= 8);
>> > > + GEM_BUG_ON(GRAPHICS_VER(i915) >= 8);
>> > >
>> > > setup_irq(engine);
>> > >
>> > > @@ -1070,14 +1070,14 @@ static void setup_common(struct intel_engine_cs *engine)
>> > > * engine->emit_init_breadcrumb().
>> > > */
>> > > engine->emit_fini_breadcrumb = gen3_emit_breadcrumb;
>> > > - if (IS_GEN(i915, 5))
>> > > + if (GRAPHICS_VER(i915) == 5)
>> > > engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
>> > >
>> > > engine->set_default_submission = i9xx_set_default_submission;
>> > >
>> > > - if (INTEL_GEN(i915) >= 6)
>> > > + if (GRAPHICS_VER(i915) >= 6)
>> > > engine->emit_bb_start = gen6_emit_bb_start;
>> > > - else if (INTEL_GEN(i915) >= 4)
>> > > + else if (GRAPHICS_VER(i915) >= 4)
>> > > engine->emit_bb_start = gen4_emit_bb_start;
>> > > else if (IS_I830(i915) || IS_I845G(i915))
>> > > engine->emit_bb_start = i830_emit_bb_start;
>> > > @@ -1094,16 +1094,16 @@ static void setup_rcs(struct intel_engine_cs *engine)
>> > >
>> > > engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
>> > >
>> > > - if (INTEL_GEN(i915) >= 7) {
>> > > + if (GRAPHICS_VER(i915) >= 7) {
>> > > engine->emit_flush = gen7_emit_flush_rcs;
>> > > engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs;
>> > > - } else if (IS_GEN(i915, 6)) {
>> > > + } else if (GRAPHICS_VER(i915) == 6) {
>> > > engine->emit_flush = gen6_emit_flush_rcs;
>> > > engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs;
>> > > - } else if (IS_GEN(i915, 5)) {
>> > > + } else if (GRAPHICS_VER(i915) == 5) {
>> > > engine->emit_flush = gen4_emit_flush_rcs;
>> > > } else {
>> > > - if (INTEL_GEN(i915) < 4)
>> > > + if (GRAPHICS_VER(i915) < 4)
>> > > engine->emit_flush = gen2_emit_flush;
>> > > else
>> > > engine->emit_flush = gen4_emit_flush_rcs;
>> > > @@ -1118,20 +1118,20 @@ static void setup_vcs(struct intel_engine_cs *engine)
>> > > {
>> > > struct drm_i915_private *i915 = engine->i915;
>> > >
>> > > - if (INTEL_GEN(i915) >= 6) {
>> > > + if (GRAPHICS_VER(i915) >= 6) {
>> > > /* gen6 bsd needs a special wa for tail updates */
>> > > - if (IS_GEN(i915, 6))
>> > > + if (GRAPHICS_VER(i915) == 6)
>> > > engine->set_default_submission = gen6_bsd_set_default_submission;
>> > > engine->emit_flush = gen6_emit_flush_vcs;
>> > > engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
>> > >
>> > > - if (IS_GEN(i915, 6))
>> > > + if (GRAPHICS_VER(i915) == 6)
>> > > engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
>> > > else
>> > > engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
>> > > } else {
>> > > engine->emit_flush = gen4_emit_flush_vcs;
>> > > - if (IS_GEN(i915, 5))
>> > > + if (GRAPHICS_VER(i915) == 5)
>> > > engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
>> > > else
>> > > engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
>> > > @@ -1145,7 +1145,7 @@ static void setup_bcs(struct intel_engine_cs *engine)
>> > > engine->emit_flush = gen6_emit_flush_xcs;
>> > > engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
>> > >
>> > > - if (IS_GEN(i915, 6))
>> > > + if (GRAPHICS_VER(i915) == 6)
>> > > engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
>> > > else
>> > > engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
>> > > @@ -1155,7 +1155,7 @@ static void setup_vecs(struct intel_engine_cs *engine)
>> > > {
>> > > struct drm_i915_private *i915 = engine->i915;
>> > >
>> > > - GEM_BUG_ON(INTEL_GEN(i915) < 7);
>> > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 7);
>> > >
>> > > engine->emit_flush = gen6_emit_flush_xcs;
>> > > engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
>> > > @@ -1203,7 +1203,7 @@ static struct i915_vma *gen7_ctx_vma(struct intel_engine_cs *engine)
>> > > struct i915_vma *vma;
>> > > int size, err;
>> > >
>> > > - if (!IS_GEN(engine->i915, 7) || engine->class != RENDER_CLASS)
>> > > + if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS)
>> > > return 0;
>> > >
>> > > err = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */);
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
>> > > index 97cab1b99871..06e9a8ed4e03 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_rps.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
>> > > @@ -196,7 +196,7 @@ static void rps_reset_interrupts(struct intel_rps *rps)
>> > > struct intel_gt *gt = rps_to_gt(rps);
>> > >
>> > > spin_lock_irq(>->irq_lock);
>> > > - if (INTEL_GEN(gt->i915) >= 11)
>> > > + if (GRAPHICS_VER(gt->i915) >= 11)
>> > > gen11_rps_reset_interrupts(rps);
>> > > else
>> > > gen6_rps_reset_interrupts(rps);
>> > > @@ -630,7 +630,7 @@ static u32 rps_limits(struct intel_rps *rps, u8 val)
>> > > * frequency, if the down threshold expires in that window we will not
>> > > * receive a down interrupt.
>> > > */
>> > > - if (INTEL_GEN(rps_to_i915(rps)) >= 9) {
>> > > + if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) {
>> > > limits = rps->max_freq_softlimit << 23;
>> > > if (val <= rps->min_freq_softlimit)
>> > > limits |= rps->min_freq_softlimit << 14;
>> > > @@ -697,7 +697,7 @@ static void rps_set_power(struct intel_rps *rps, int new_power)
>> > > intel_gt_ns_to_pm_interval(gt, ei_down * threshold_down * 10));
>> > >
>> > > set(uncore, GEN6_RP_CONTROL,
>> > > - (INTEL_GEN(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
>> > > + (GRAPHICS_VER(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
>> > > GEN6_RP_MEDIA_HW_NORMAL_MODE |
>> > > GEN6_RP_MEDIA_IS_GFX |
>> > > GEN6_RP_ENABLE |
>> > > @@ -771,7 +771,7 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val)
>> > > struct drm_i915_private *i915 = rps_to_i915(rps);
>> > > u32 swreq;
>> > >
>> > > - if (INTEL_GEN(i915) >= 9)
>> > > + if (GRAPHICS_VER(i915) >= 9)
>> > > swreq = GEN9_FREQUENCY(val);
>> > > else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
>> > > swreq = HSW_FREQUENCY(val);
>> > > @@ -812,14 +812,14 @@ static int rps_set(struct intel_rps *rps, u8 val, bool update)
>> > >
>> > > if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
>> > > err = vlv_rps_set(rps, val);
>> > > - else if (INTEL_GEN(i915) >= 6)
>> > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > err = gen6_rps_set(rps, val);
>> > > else
>> > > err = gen5_rps_set(rps, val);
>> > > if (err)
>> > > return err;
>> > >
>> > > - if (update && INTEL_GEN(i915) >= 6)
>> > > + if (update && GRAPHICS_VER(i915) >= 6)
>> > > gen6_rps_set_thresholds(rps, val);
>> > > rps->last_freq = val;
>> > >
>> > > @@ -853,7 +853,7 @@ void intel_rps_unpark(struct intel_rps *rps)
>> > > if (intel_rps_uses_timer(rps))
>> > > rps_start_timer(rps);
>> > >
>> > > - if (IS_GEN(rps_to_i915(rps), 5))
>> > > + if (GRAPHICS_VER(rps_to_i915(rps)) == 5)
>> > > gen5_rps_update(rps);
>> > > }
>> > >
>> > > @@ -999,7 +999,7 @@ static void gen6_rps_init(struct intel_rps *rps)
>> > >
>> > > rps->efficient_freq = rps->rp1_freq;
>> > > if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
>> > > - IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
>> > > + IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
>> > > u32 ddcc_status = 0;
>> > >
>> > > if (sandybridge_pcode_read(i915,
>> > > @@ -1012,7 +1012,7 @@ static void gen6_rps_init(struct intel_rps *rps)
>> > > rps->max_freq);
>> > > }
>> > >
>> > > - if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
>> > > + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
>> > > /* Store the frequency values in 16.66 MHZ units, which is
>> > > * the natural hardware unit for SKL
>> > > */
>> > > @@ -1048,7 +1048,7 @@ static bool gen9_rps_enable(struct intel_rps *rps)
>> > > struct intel_uncore *uncore = gt->uncore;
>> > >
>> > > /* Program defaults and thresholds for RPS */
>> > > - if (IS_GEN(gt->i915, 9))
>> > > + if (GRAPHICS_VER(gt->i915) == 9)
>> > > intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ,
>> > > GEN9_FREQUENCY(rps->rp1_freq));
>> > >
>> > > @@ -1365,16 +1365,16 @@ void intel_rps_enable(struct intel_rps *rps)
>> > > enabled = chv_rps_enable(rps);
>> > > else if (IS_VALLEYVIEW(i915))
>> > > enabled = vlv_rps_enable(rps);
>> > > - else if (INTEL_GEN(i915) >= 9)
>> > > + else if (GRAPHICS_VER(i915) >= 9)
>> > > enabled = gen9_rps_enable(rps);
>> > > - else if (INTEL_GEN(i915) >= 8)
>> > > + else if (GRAPHICS_VER(i915) >= 8)
>> > > enabled = gen8_rps_enable(rps);
>> > > - else if (INTEL_GEN(i915) >= 6)
>> > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > enabled = gen6_rps_enable(rps);
>> > > else if (IS_IRONLAKE_M(i915))
>> > > enabled = gen5_rps_enable(rps);
>> > > else
>> > > - MISSING_CASE(INTEL_GEN(i915));
>> > > + MISSING_CASE(GRAPHICS_VER(i915));
>> > > intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>> > > if (!enabled)
>> > > return;
>> > > @@ -1393,7 +1393,7 @@ void intel_rps_enable(struct intel_rps *rps)
>> > >
>> > > if (has_busy_stats(rps))
>> > > intel_rps_set_timer(rps);
>> > > - else if (INTEL_GEN(i915) >= 6)
>> > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > intel_rps_set_interrupts(rps);
>> > > else
>> > > /* Ironlake currently uses intel_ips.ko */ {}
>> > > @@ -1414,7 +1414,7 @@ void intel_rps_disable(struct intel_rps *rps)
>> > > intel_rps_clear_interrupts(rps);
>> > > intel_rps_clear_timer(rps);
>> > >
>> > > - if (INTEL_GEN(i915) >= 6)
>> > > + if (GRAPHICS_VER(i915) >= 6)
>> > > gen6_rps_disable(rps);
>> > > else if (IS_IRONLAKE_M(i915))
>> > > gen5_rps_disable(rps);
>> > > @@ -1453,14 +1453,14 @@ int intel_gpu_freq(struct intel_rps *rps, int val)
>> > > {
>> > > struct drm_i915_private *i915 = rps_to_i915(rps);
>> > >
>> > > - if (INTEL_GEN(i915) >= 9)
>> > > + if (GRAPHICS_VER(i915) >= 9)
>> > > return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
>> > > GEN9_FREQ_SCALER);
>> > > else if (IS_CHERRYVIEW(i915))
>> > > return chv_gpu_freq(rps, val);
>> > > else if (IS_VALLEYVIEW(i915))
>> > > return byt_gpu_freq(rps, val);
>> > > - else if (INTEL_GEN(i915) >= 6)
>> > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > return val * GT_FREQUENCY_MULTIPLIER;
>> > > else
>> > > return val;
>> > > @@ -1470,14 +1470,14 @@ int intel_freq_opcode(struct intel_rps *rps, int val)
>> > > {
>> > > struct drm_i915_private *i915 = rps_to_i915(rps);
>> > >
>> > > - if (INTEL_GEN(i915) >= 9)
>> > > + if (GRAPHICS_VER(i915) >= 9)
>> > > return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
>> > > GT_FREQUENCY_MULTIPLIER);
>> > > else if (IS_CHERRYVIEW(i915))
>> > > return chv_freq_opcode(rps, val);
>> > > else if (IS_VALLEYVIEW(i915))
>> > > return byt_freq_opcode(rps, val);
>> > > - else if (INTEL_GEN(i915) >= 6)
>> > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
>> > > else
>> > > return val;
>> > > @@ -1770,7 +1770,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
>> > > spin_unlock(>->irq_lock);
>> > > }
>> > >
>> > > - if (INTEL_GEN(gt->i915) >= 8)
>> > > + if (GRAPHICS_VER(gt->i915) >= 8)
>> > > return;
>> > >
>> > > if (pm_iir & PM_VEBOX_USER_INTERRUPT)
>> > > @@ -1833,7 +1833,7 @@ void intel_rps_init(struct intel_rps *rps)
>> > > chv_rps_init(rps);
>> > > else if (IS_VALLEYVIEW(i915))
>> > > vlv_rps_init(rps);
>> > > - else if (INTEL_GEN(i915) >= 6)
>> > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > gen6_rps_init(rps);
>> > > else if (IS_IRONLAKE_M(i915))
>> > > gen5_rps_init(rps);
>> > > @@ -1843,7 +1843,7 @@ void intel_rps_init(struct intel_rps *rps)
>> > > rps->min_freq_softlimit = rps->min_freq;
>> > >
>> > > /* After setting max-softlimit, find the overclock max freq */
>> > > - if (IS_GEN(i915, 6) || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
>> > > + if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
>> > > u32 params = 0;
>> > >
>> > > sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS,
>> > > @@ -1872,16 +1872,16 @@ void intel_rps_init(struct intel_rps *rps)
>> > > *
>> > > * TODO: verify if this can be reproduced on VLV,CHV.
>> > > */
>> > > - if (INTEL_GEN(i915) <= 7)
>> > > + if (GRAPHICS_VER(i915) <= 7)
>> > > rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
>> > >
>> > > - if (INTEL_GEN(i915) >= 8 && INTEL_GEN(i915) < 11)
>> > > + if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) < 11)
>> > > rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
>> > > }
>> > >
>> > > void intel_rps_sanitize(struct intel_rps *rps)
>> > > {
>> > > - if (INTEL_GEN(rps_to_i915(rps)) >= 6)
>> > > + if (GRAPHICS_VER(rps_to_i915(rps)) >= 6)
>> > > rps_disable_interrupts(rps);
>> > > }
>> > >
>> > > @@ -1892,11 +1892,11 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
>> > >
>> > > if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
>> > > cagf = (rpstat >> 8) & 0xff;
>> > > - else if (INTEL_GEN(i915) >= 9)
>> > > + else if (GRAPHICS_VER(i915) >= 9)
>> > > cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
>> > > else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
>> > > cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
>> > > - else if (INTEL_GEN(i915) >= 6)
>> > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
>> > > else
>> > > cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >>
>> > > @@ -1915,7 +1915,7 @@ static u32 read_cagf(struct intel_rps *rps)
>> > > vlv_punit_get(i915);
>> > > freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
>> > > vlv_punit_put(i915);
>> > > - } else if (INTEL_GEN(i915) >= 6) {
>> > > + } else if (GRAPHICS_VER(i915) >= 6) {
>> > > freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
>> > > } else {
>> > > freq = intel_uncore_read(uncore, MEMSTAT_ILK);
>> > > @@ -1968,7 +1968,7 @@ void intel_rps_driver_register(struct intel_rps *rps)
>> > > * We only register the i915 ips part with intel-ips once everything is
>> > > * set up, to avoid intel-ips sneaking in and reading bogus values.
>> > > */
>> > > - if (IS_GEN(gt->i915, 5)) {
>> > > + if (GRAPHICS_VER(gt->i915) == 5) {
>> > > GEM_BUG_ON(ips_mchdev);
>> > > rcu_assign_pointer(ips_mchdev, gt->i915);
>> > > ips_ping_for_i915_load();
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
>> > > index 0d9f74aec8fe..367fd44b81c8 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
>> > > @@ -590,13 +590,13 @@ void intel_sseu_info_init(struct intel_gt *gt)
>> > > cherryview_sseu_info_init(gt);
>> > > else if (IS_BROADWELL(i915))
>> > > bdw_sseu_info_init(gt);
>> > > - else if (IS_GEN(i915, 9))
>> > > + else if (GRAPHICS_VER(i915) == 9)
>> > > gen9_sseu_info_init(gt);
>> > > - else if (IS_GEN(i915, 10))
>> > > + else if (GRAPHICS_VER(i915) == 10)
>> > > gen10_sseu_info_init(gt);
>> > > - else if (IS_GEN(i915, 11))
>> > > + else if (GRAPHICS_VER(i915) == 11)
>> > > gen11_sseu_info_init(gt);
>> > > - else if (INTEL_GEN(i915) >= 12)
>> > > + else if (GRAPHICS_VER(i915) >= 12)
>> > > gen12_sseu_info_init(gt);
>> > > }
>> > >
>> > > @@ -613,7 +613,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
>> > > * No explicit RPCS request is needed to ensure full
>> > > * slice/subslice/EU enablement prior to Gen9.
>> > > */
>> > > - if (INTEL_GEN(i915) < 9)
>> > > + if (GRAPHICS_VER(i915) < 9)
>> > > return 0;
>> > >
>> > > /*
>> > > @@ -651,7 +651,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
>> > > * subslices are enabled, or a count between one and four on the first
>> > > * slice.
>> > > */
>> > > - if (IS_GEN(i915, 11) &&
>> > > + if (GRAPHICS_VER(i915) == 11 &&
>> > > slices == 1 &&
>> > > subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
>> > > GEM_BUG_ON(subslices & 1);
>> > > @@ -669,7 +669,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
>> > > if (sseu->has_slice_pg) {
>> > > u32 mask, val = slices;
>> > >
>> > > - if (INTEL_GEN(i915) >= 11) {
>> > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > mask = GEN11_RPCS_S_CNT_MASK;
>> > > val <<= GEN11_RPCS_S_CNT_SHIFT;
>> > > } else {
>> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > > index 62cb9ee5bfc3..b62d1e31a645 100644
>> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > > @@ -699,9 +699,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>> > >
>> > > if (IS_DG1(i915))
>> > > dg1_ctx_workarounds_init(engine, wal);
>> > > - else if (IS_GEN(i915, 12))
>> > > + else if (GRAPHICS_VER(i915) == 12)
>> > > gen12_ctx_workarounds_init(engine, wal);
>> > > - else if (IS_GEN(i915, 11))
>> > > + else if (GRAPHICS_VER(i915) == 11)
>> > > icl_ctx_workarounds_init(engine, wal);
>> > > else if (IS_CANNONLAKE(i915))
>> > > cnl_ctx_workarounds_init(engine, wal);
>> > > @@ -719,14 +719,14 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>> > > chv_ctx_workarounds_init(engine, wal);
>> > > else if (IS_BROADWELL(i915))
>> > > bdw_ctx_workarounds_init(engine, wal);
>> > > - else if (IS_GEN(i915, 7))
>> > > + else if (GRAPHICS_VER(i915) == 7)
>> > > gen7_ctx_workarounds_init(engine, wal);
>> > > - else if (IS_GEN(i915, 6))
>> > > + else if (GRAPHICS_VER(i915) == 6)
>> > > gen6_ctx_workarounds_init(engine, wal);
>> > > - else if (INTEL_GEN(i915) < 8)
>> > > + else if (GRAPHICS_VER(i915) < 8)
>> > > ;
>> > > else
>> > > - MISSING_CASE(INTEL_GEN(i915));
>> > > + MISSING_CASE(GRAPHICS_VER(i915));
>> > >
>> > > wa_init_finish(wal);
>> > > }
>> > > @@ -950,7 +950,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> > > unsigned int slice, subslice;
>> > > u32 l3_en, mcr, mcr_mask;
>> > >
>> > > - GEM_BUG_ON(INTEL_GEN(i915) < 10);
>> > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 10);
>> > >
>> > > /*
>> > > * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
>> > > @@ -980,7 +980,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> > > * of every MMIO read.
>> > > */
>> > >
>> > > - if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
>> > > + if (GRAPHICS_VER(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
>> > > u32 l3_fuse =
>> > > intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
>> > > GEN10_L3BANK_MASK;
>> > > @@ -1002,7 +1002,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> > > }
>> > > subslice--;
>> > >
>> > > - if (INTEL_GEN(i915) >= 11) {
>> > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
>> > > mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
>> > > } else {
>> > > @@ -1171,9 +1171,9 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> > > dg1_gt_workarounds_init(i915, wal);
>> > > else if (IS_TIGERLAKE(i915))
>> > > tgl_gt_workarounds_init(i915, wal);
>> > > - else if (IS_GEN(i915, 12))
>> > > + else if (GRAPHICS_VER(i915) == 12)
>> > > gen12_gt_workarounds_init(i915, wal);
>> > > - else if (IS_GEN(i915, 11))
>> > > + else if (GRAPHICS_VER(i915) == 11)
>> > > icl_gt_workarounds_init(i915, wal);
>> > > else if (IS_CANNONLAKE(i915))
>> > > cnl_gt_workarounds_init(i915, wal);
>> > > @@ -1193,18 +1193,18 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> > > vlv_gt_workarounds_init(i915, wal);
>> > > else if (IS_IVYBRIDGE(i915))
>> > > ivb_gt_workarounds_init(i915, wal);
>> > > - else if (IS_GEN(i915, 6))
>> > > + else if (GRAPHICS_VER(i915) == 6)
>> > > snb_gt_workarounds_init(i915, wal);
>> > > - else if (IS_GEN(i915, 5))
>> > > + else if (GRAPHICS_VER(i915) == 5)
>> > > ilk_gt_workarounds_init(i915, wal);
>> > > else if (IS_G4X(i915))
>> > > g4x_gt_workarounds_init(i915, wal);
>> > > - else if (IS_GEN(i915, 4))
>> > > + else if (GRAPHICS_VER(i915) == 4)
>> > > gen4_gt_workarounds_init(i915, wal);
>> > > - else if (INTEL_GEN(i915) <= 8)
>> > > + else if (GRAPHICS_VER(i915) <= 8)
>> > > ;
>> > > else
>> > > - MISSING_CASE(INTEL_GEN(i915));
>> > > + MISSING_CASE(GRAPHICS_VER(i915));
>> > > }
>> > >
>> > > void intel_gt_init_workarounds(struct drm_i915_private *i915)
>> > > @@ -1558,9 +1558,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>> > >
>> > > if (IS_DG1(i915))
>> > > dg1_whitelist_build(engine);
>> > > - else if (IS_GEN(i915, 12))
>> > > + else if (GRAPHICS_VER(i915) == 12)
>> > > tgl_whitelist_build(engine);
>> > > - else if (IS_GEN(i915, 11))
>> > > + else if (GRAPHICS_VER(i915) == 11)
>> > > icl_whitelist_build(engine);
>> > > else if (IS_CANNONLAKE(i915))
>> > > cnl_whitelist_build(engine);
>> > > @@ -1576,10 +1576,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>> > > bxt_whitelist_build(engine);
>> > > else if (IS_SKYLAKE(i915))
>> > > skl_whitelist_build(engine);
>> > > - else if (INTEL_GEN(i915) <= 8)
>> > > + else if (GRAPHICS_VER(i915) <= 8)
>> > > ;
>> > > else
>> > > - MISSING_CASE(INTEL_GEN(i915));
>> > > + MISSING_CASE(GRAPHICS_VER(i915));
>> > >
>> > > wa_init_finish(w);
>> > > }
>> > > @@ -1695,7 +1695,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > ENABLE_SMALLPL);
>> > > }
>> > >
>> > > - if (IS_GEN(i915, 11)) {
>> > > + if (GRAPHICS_VER(i915) == 11) {
>> > > /* This is not an Wa. Enable for better image quality */
>> > > wa_masked_en(wal,
>> > > _3D_CHICKEN3,
>> > > @@ -1793,7 +1793,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > FF_DOP_CLOCK_GATE_DISABLE);
>> > > }
>> > >
>> > > - if (IS_GEN_RANGE(i915, 9, 12)) {
>> > > + if (IS_GRAPHICS_VER(i915, 9, 12)) {
>> > > /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
>> > > wa_masked_en(wal,
>> > > GEN7_FF_SLICE_CS_CHICKEN1,
>> > > @@ -1817,7 +1817,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
>> > > }
>> > >
>> > > - if (IS_GEN(i915, 9)) {
>> > > + if (GRAPHICS_VER(i915) == 9) {
>> > > /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
>> > > wa_masked_en(wal,
>> > > GEN9_CSFE_CHICKEN1_RCS,
>> > > @@ -1921,7 +1921,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
>> > > }
>> > >
>> > > - if (IS_GEN(i915, 7)) {
>> > > + if (GRAPHICS_VER(i915) == 7) {
>> > > /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
>> > > wa_masked_en(wal,
>> > > GFX_MODE_GEN7,
>> > > @@ -1953,7 +1953,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > GEN6_WIZ_HASHING_16x4);
>> > > }
>> > >
>> > > - if (IS_GEN_RANGE(i915, 6, 7))
>> > > + if (IS_GRAPHICS_VER(i915, 6, 7))
>> > > /*
>> > > * We need to disable the AsyncFlip performance optimisations in
>> > > * order to use MI_WAIT_FOR_EVENT within the CS. It should
>> > > @@ -1965,7 +1965,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > MI_MODE,
>> > > ASYNC_FLIP_PERF_DISABLE);
>> > >
>> > > - if (IS_GEN(i915, 6)) {
>> > > + if (GRAPHICS_VER(i915) == 6) {
>> > > /*
>> > > * Required for the hardware to program scanline values for
>> > > * waiting
>> > > @@ -2019,14 +2019,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > CM0_STC_EVICT_DISABLE_LRA_SNB);
>> > > }
>> > >
>> > > - if (IS_GEN_RANGE(i915, 4, 6))
>> > > + if (IS_GRAPHICS_VER(i915, 4, 6))
>> > > /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
>> > > wa_add(wal, MI_MODE,
>> > > 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
>> > > /* XXX bit doesn't stick on Broadwater */
>> > > IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
>> > >
>> > > - if (IS_GEN(i915, 4))
>> > > + if (GRAPHICS_VER(i915) == 4)
>> > > /*
>> > > * Disable CONSTANT_BUFFER before it is loaded from the context
>> > > * image. For as it is loaded, it is executed and the stored
>> > > @@ -2058,7 +2058,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > static void
>> > > engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > {
>> > > - if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4))
>> > > + if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4))
>> > > return;
>> > >
>> > > if (engine->class == RENDER_CLASS)
>> > > @@ -2071,7 +2071,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
>> > > {
>> > > struct i915_wa_list *wal = &engine->wa_list;
>> > >
>> > > - if (INTEL_GEN(engine->i915) < 4)
>> > > + if (GRAPHICS_VER(engine->i915) < 4)
>> > > return;
>> > >
>> > > wa_init_start(wal, "engine", engine->name);
>> > > @@ -2112,9 +2112,9 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
>> > > const struct mcr_range *mcr_ranges;
>> > > int i;
>> > >
>> > > - if (INTEL_GEN(i915) >= 12)
>> > > + if (GRAPHICS_VER(i915) >= 12)
>> > > mcr_ranges = mcr_ranges_gen12;
>> > > - else if (INTEL_GEN(i915) >= 8)
>> > > + else if (GRAPHICS_VER(i915) >= 8)
>> > > mcr_ranges = mcr_ranges_gen8;
>> > > else
>> > > return false;
>> > > @@ -2143,7 +2143,7 @@ wa_list_srm(struct i915_request *rq,
>> > > u32 srm, *cs;
>> > >
>> > > srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
>> > > - if (INTEL_GEN(i915) >= 8)
>> > > + if (GRAPHICS_VER(i915) >= 8)
>> > > srm++;
>> > >
>> > > for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
>> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>> > > index 3453eb77c498..64abf5feabfa 100644
>> > > --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>> > > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>> > > @@ -52,7 +52,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
>> > > return PTR_ERR(cs);
>> > >
>> > > cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
>> > > - if (INTEL_GEN(rq->engine->i915) >= 8)
>> > > + if (GRAPHICS_VER(rq->engine->i915) >= 8)
>> > > cmd++;
>> > > *cs++ = cmd;
>> > > *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
>> > > @@ -125,7 +125,7 @@ static int perf_mi_bb_start(void *arg)
>> > > enum intel_engine_id id;
>> > > int err = 0;
>> > >
>> > > - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
>> > > + if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
>> > > return 0;
>> > >
>> > > perf_begin(gt);
>> > > @@ -249,7 +249,7 @@ static int perf_mi_noop(void *arg)
>> > > enum intel_engine_id id;
>> > > int err = 0;
>> > >
>> > > - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
>> > > + if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
>> > > return 0;
>> > >
>> > > perf_begin(gt);
>> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
>> > > index 2c898622bdfb..72cca3f0da21 100644
>> > > --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
>> > > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
>> > > @@ -198,7 +198,7 @@ static int live_engine_timestamps(void *arg)
>> > > * the same CS clock.
>> > > */
>> > >
>> > > - if (INTEL_GEN(gt->i915) < 8)
>> > > + if (GRAPHICS_VER(gt->i915) < 8)
>> > > return 0;
>> > >
>> > > for_each_engine(engine, gt, id) {
>> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
>> > > index 1f93591a8c69..ea2203af0764 100644
>> > > --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
>> > > +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
>> > > @@ -3269,7 +3269,7 @@ static int live_preempt_user(void *arg)
>> > > if (!intel_engine_has_preemption(engine))
>> > > continue;
>> > >
>> > > - if (IS_GEN(gt->i915, 8) && engine->class != RENDER_CLASS)
>> > > + if (GRAPHICS_VER(gt->i915) == 8 && engine->class != RENDER_CLASS)
>> > > continue; /* we need per-context GPR */
>> > >
>> > > if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {
>> > > @@ -4293,7 +4293,7 @@ static int live_virtual_preserved(void *arg)
>> > > return 0;
>> > >
>> > > /* As we use CS_GPR we cannot run before they existed on all engines. */
>> > > - if (INTEL_GEN(gt->i915) < 9)
>> > > + if (GRAPHICS_VER(gt->i915) < 9)
>> > > return 0;
>> > >
>> > > for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
>> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
>> > > index c0845bf72dd3..b9441217ca3d 100644
>> > > --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
>> > > +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
>> > > @@ -74,10 +74,10 @@ static int live_gt_clocks(void *arg)
>> > > return 0;
>> > > }
>> > >
>> > > - if (INTEL_GEN(gt->i915) < 4) /* Any CS_TIMESTAMP? */
>> > > + if (GRAPHICS_VER(gt->i915) < 4) /* Any CS_TIMESTAMP? */
>> > > return 0;
>> > >
>> > > - if (IS_GEN(gt->i915, 5))
>> > > + if (GRAPHICS_VER(gt->i915) == 5)
>> > > /*
>> > > * XXX CS_TIMESTAMP low dword is dysfunctional?
>> > > *
>> > > @@ -86,7 +86,7 @@ static int live_gt_clocks(void *arg)
>> > > */
>> > > return 0;
>> > >
>> > > - if (IS_GEN(gt->i915, 4))
>> > > + if (GRAPHICS_VER(gt->i915) == 4)
>> > > /*
>> > > * XXX CS_TIMESTAMP appears gibberish
>> > > *
>> > > @@ -105,7 +105,7 @@ static int live_gt_clocks(void *arg)
>> > > u64 time;
>> > > u64 dt;
>> > >
>> > > - if (INTEL_GEN(engine->i915) < 7 && engine->id != RCS0)
>> > > + if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0)
>> > > continue;
>> > >
>> > > measure_clocks(engine, &cycles, &dt);
>> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
>> > > index 5b63d4df8c93..853246fad05f 100644
>> > > --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
>> > > +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
>> > > @@ -180,7 +180,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>> > > goto cancel_rq;
>> > >
>> > > batch = h->batch;
>> > > - if (INTEL_GEN(gt->i915) >= 8) {
>> > > + if (GRAPHICS_VER(gt->i915) >= 8) {
>> > > *batch++ = MI_STORE_DWORD_IMM_GEN4;
>> > > *batch++ = lower_32_bits(hws_address(hws, rq));
>> > > *batch++ = upper_32_bits(hws_address(hws, rq));
>> > > @@ -194,7 +194,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>> > > *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
>> > > *batch++ = lower_32_bits(vma->node.start);
>> > > *batch++ = upper_32_bits(vma->node.start);
>> > > - } else if (INTEL_GEN(gt->i915) >= 6) {
>> > > + } else if (GRAPHICS_VER(gt->i915) >= 6) {
>> > > *batch++ = MI_STORE_DWORD_IMM_GEN4;
>> > > *batch++ = 0;
>> > > *batch++ = lower_32_bits(hws_address(hws, rq));
>> > > @@ -207,7 +207,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>> > > *batch++ = MI_NOOP;
>> > > *batch++ = MI_BATCH_BUFFER_START | 1 << 8;
>> > > *batch++ = lower_32_bits(vma->node.start);
>> > > - } else if (INTEL_GEN(gt->i915) >= 4) {
>> > > + } else if (GRAPHICS_VER(gt->i915) >= 4) {
>> > > *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> > > *batch++ = 0;
>> > > *batch++ = lower_32_bits(hws_address(hws, rq));
>> > > @@ -243,7 +243,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>> > > }
>> > >
>> > > flags = 0;
>> > > - if (INTEL_GEN(gt->i915) <= 5)
>> > > + if (GRAPHICS_VER(gt->i915) <= 5)
>> > > flags |= I915_DISPATCH_SECURE;
>> > >
>> > > err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
>> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
>> > > index 94006f117bbd..459b775f163a 100644
>> > > --- a/drivers/gpu/drm/i915/gt/selftest_llc.c
>> > > +++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
>> > > @@ -44,7 +44,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
>> > > if (found != ia_freq) {
>> > > pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected CPU freq, found %d, expected %d\n",
>> > > gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
>> > > - intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
>> > > + intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
>> > > found, ia_freq);
>> > > err = -EINVAL;
>> > > break;
>> > > @@ -54,7 +54,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
>> > > if (found != ring_freq) {
>> > > pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected ring freq, found %d, expected %d\n",
>> > > gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
>> > > - intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
>> > > + intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
>> > > found, ring_freq);
>> > > err = -EINVAL;
>> > > break;
>> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> > > index d8f6623524e8..3119016d9910 100644
>> > > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> > > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> > > @@ -584,7 +584,7 @@ static int __live_lrc_gpr(struct intel_engine_cs *engine,
>> > > int err;
>> > > int n;
>> > >
>> > > - if (INTEL_GEN(engine->i915) < 9 && engine->class != RENDER_CLASS)
>> > > + if (GRAPHICS_VER(engine->i915) < 9 && engine->class != RENDER_CLASS)
>> > > return 0; /* GPR only on rcs0 for gen8 */
>> > >
>> > > err = gpr_make_dirty(engine->kernel_context);
>> > > @@ -1389,10 +1389,10 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
>> > >
>> > > static bool skip_isolation(const struct intel_engine_cs *engine)
>> > > {
>> > > - if (engine->class == COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) == 9)
>> > > + if (engine->class == COPY_ENGINE_CLASS && GRAPHICS_VER(engine->i915) == 9)
>> > > return true;
>> > >
>> > > - if (engine->class == RENDER_CLASS && INTEL_GEN(engine->i915) == 11)
>> > > + if (engine->class == RENDER_CLASS && GRAPHICS_VER(engine->i915) == 11)
>> > > return true;
>> > >
>> > > return false;
>> > > @@ -1551,7 +1551,7 @@ static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)
>> > > /* We use the already reserved extra page in context state */
>> > > if (!a->wa_bb_page) {
>> > > GEM_BUG_ON(b->wa_bb_page);
>> > > - GEM_BUG_ON(INTEL_GEN(engine->i915) == 12);
>> > > + GEM_BUG_ON(GRAPHICS_VER(engine->i915) == 12);
>> > > goto unpin_b;
>> > > }
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
>> > > index e55a887d11e2..b9bb0e6e97f7 100644
>> > > --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
>> > > +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
>> > > @@ -183,7 +183,7 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
>> > > * which only controls CPU initiated MMIO. Routing does not
>> > > * work for CS access so we cannot verify them on this path.
>> > > */
>> > > - return INTEL_GEN(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
>> > > + return GRAPHICS_VER(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
>> > > }
>> > >
>> > > static int check_l3cc_table(struct intel_engine_cs *engine,
>> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
>> > > index 710f825f6e5a..8c70b7e12074 100644
>> > > --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
>> > > +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
>> > > @@ -140,7 +140,7 @@ static const u32 *__live_rc6_ctx(struct intel_context *ce)
>> > > }
>> > >
>> > > cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
>> > > - if (INTEL_GEN(rq->engine->i915) >= 8)
>> > > + if (GRAPHICS_VER(rq->engine->i915) >= 8)
>> > > cmd++;
>> > >
>> > > *cs++ = cmd;
>> > > @@ -193,7 +193,7 @@ int live_rc6_ctx_wa(void *arg)
>> > > int err = 0;
>> > >
>> > > /* A read of CTX_INFO upsets rc6. Poke the bear! */
>> > > - if (INTEL_GEN(gt->i915) < 8)
>> > > + if (GRAPHICS_VER(gt->i915) < 8)
>> > > return 0;
>> > >
>> > > engines = randomised_engines(gt, &prng, &count);
>> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
>> > > index c12e74171b63..041954408d0f 100644
>> > > --- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
>> > > +++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
>> > > @@ -41,10 +41,10 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
>> > > return ERR_CAST(cs);
>> > > }
>> > >
>> > > - if (INTEL_GEN(engine->i915) >= 6) {
>> > > + if (GRAPHICS_VER(engine->i915) >= 6) {
>> > > *cs++ = MI_STORE_DWORD_IMM_GEN4;
>> > > *cs++ = 0;
>> > > - } else if (INTEL_GEN(engine->i915) >= 4) {
>> > > + } else if (GRAPHICS_VER(engine->i915) >= 4) {
>> > > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> > > *cs++ = 0;
>> > > } else {
>> > > @@ -266,7 +266,7 @@ static int live_ctx_switch_wa(void *arg)
>> > > if (!intel_engine_can_store_dword(engine))
>> > > continue;
>> > >
>> > > - if (IS_GEN_RANGE(gt->i915, 4, 5))
>> > > + if (IS_GRAPHICS_VER(gt->i915, 4, 5))
>> > > continue; /* MI_STORE_DWORD is privileged! */
>> > >
>> > > saved_wa = fetch_and_zero(&engine->wa_ctx.vma);
>> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
>> > > index 3ca1bd5793c3..7ee2513e15f9 100644
>> > > --- a/drivers/gpu/drm/i915/gt/selftest_rps.c
>> > > +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
>> > > @@ -204,7 +204,7 @@ static void show_pstate_limits(struct intel_rps *rps)
>> > > i915_mmio_reg_offset(BXT_RP_STATE_CAP),
>> > > intel_uncore_read(rps_to_uncore(rps),
>> > > BXT_RP_STATE_CAP));
>> > > - } else if (IS_GEN(i915, 9)) {
>> > > + } else if (GRAPHICS_VER(i915) == 9) {
>> > > pr_info("P_STATE_LIMITS[%x]: 0x%08x\n",
>> > > i915_mmio_reg_offset(GEN9_RP_STATE_LIMITS),
>> > > intel_uncore_read(rps_to_uncore(rps),
>> > > @@ -222,7 +222,7 @@ int live_rps_clock_interval(void *arg)
>> > > struct igt_spinner spin;
>> > > int err = 0;
>> > >
>> > > - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
>> > > + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
>> > > return 0;
>> > >
>> > > if (igt_spinner_init(&spin, gt))
>> > > @@ -506,7 +506,7 @@ static void show_pcu_config(struct intel_rps *rps)
>> > >
>> > > min_gpu_freq = rps->min_freq;
>> > > max_gpu_freq = rps->max_freq;
>> > > - if (INTEL_GEN(i915) >= 9) {
>> > > + if (GRAPHICS_VER(i915) >= 9) {
>> > > /* Convert GT frequency to 50 HZ units */
>> > > min_gpu_freq /= GEN9_FREQ_SCALER;
>> > > max_gpu_freq /= GEN9_FREQ_SCALER;
>> > > @@ -614,7 +614,7 @@ int live_rps_frequency_cs(void *arg)
>> > > if (!intel_rps_is_enabled(rps))
>> > > return 0;
>> > >
>> > > - if (INTEL_GEN(gt->i915) < 8) /* for CS simplicity */
>> > > + if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
>> > > return 0;
>> > >
>> > > if (CPU_LATENCY >= 0)
>> > > @@ -755,7 +755,7 @@ int live_rps_frequency_srm(void *arg)
>> > > if (!intel_rps_is_enabled(rps))
>> > > return 0;
>> > >
>> > > - if (INTEL_GEN(gt->i915) < 8) /* for CS simplicity */
>> > > + if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
>> > > return 0;
>> > >
>> > > if (CPU_LATENCY >= 0)
>> > > @@ -1031,7 +1031,7 @@ int live_rps_interrupt(void *arg)
>> > > * First, let's check whether or not we are receiving interrupts.
>> > > */
>> > >
>> > > - if (!intel_rps_has_interrupts(rps) || INTEL_GEN(gt->i915) < 6)
>> > > + if (!intel_rps_has_interrupts(rps) || GRAPHICS_VER(gt->i915) < 6)
>> > > return 0;
>> > >
>> > > intel_gt_pm_get(gt);
>> > > @@ -1136,7 +1136,7 @@ int live_rps_power(void *arg)
>> > > * that theory.
>> > > */
>> > >
>> > > - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
>> > > + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
>> > > return 0;
>> > >
>> > > if (!librapl_supported(gt->i915))
>> > > @@ -1240,7 +1240,7 @@ int live_rps_dynamic(void *arg)
>> > > * moving parts into dynamic reclocking based on load.
>> > > */
>> > >
>> > > - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
>> > > + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
>> > > return 0;
>> > >
>> > > if (igt_spinner_init(&spin, gt))
>> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> > > index 9adbd9d147be..64da0c91dec1 100644
>> > > --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> > > +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> > > @@ -457,12 +457,12 @@ static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
>> > > if (IS_ERR(cs))
>> > > return PTR_ERR(cs);
>> > >
>> > > - if (INTEL_GEN(rq->engine->i915) >= 8) {
>> > > + if (GRAPHICS_VER(rq->engine->i915) >= 8) {
>> > > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> > > *cs++ = addr;
>> > > *cs++ = 0;
>> > > *cs++ = value;
>> > > - } else if (INTEL_GEN(rq->engine->i915) >= 4) {
>> > > + } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
>> > > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> > > *cs++ = 0;
>> > > *cs++ = addr;
>> > > @@ -992,7 +992,7 @@ static int live_hwsp_read(void *arg)
>> > > * even across multiple wraps.
>> > > */
>> > >
>> > > - if (INTEL_GEN(gt->i915) < 8) /* CS convenience [SRM/LRM] */
>> > > + if (GRAPHICS_VER(gt->i915) < 8) /* CS convenience [SRM/LRM] */
>> > > return 0;
>> > >
>> > > tl = intel_timeline_create(gt);
>> > > diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
>> > > index 64937ec3f2dc..c30754daf4b1 100644
>> > > --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
>> > > +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
>> > > @@ -145,7 +145,7 @@ read_nonprivs(struct intel_context *ce)
>> > > goto err_req;
>> > >
>> > > srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
>> > > - if (INTEL_GEN(engine->i915) >= 8)
>> > > + if (GRAPHICS_VER(engine->i915) >= 8)
>> > > srm++;
>> > >
>> > > cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
>> > > @@ -546,7 +546,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
>> > >
>> > > srm = MI_STORE_REGISTER_MEM;
>> > > lrm = MI_LOAD_REGISTER_MEM;
>> > > - if (INTEL_GEN(engine->i915) >= 8)
>> > > + if (GRAPHICS_VER(engine->i915) >= 8)
>> > > lrm++, srm++;
>> > >
>> > > pr_debug("%s: Writing garbage to %x\n",
>> > > @@ -749,7 +749,7 @@ static int live_dirty_whitelist(void *arg)
>> > >
>> > > /* Can the user write to the whitelisted registers? */
>> > >
>> > > - if (INTEL_GEN(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */
>> > > + if (GRAPHICS_VER(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */
>> > > return 0;
>> > >
>> > > for_each_engine(engine, gt, id) {
>> > > @@ -829,7 +829,7 @@ static int read_whitelisted_registers(struct intel_context *ce,
>> > > goto err_req;
>> > >
>> > > srm = MI_STORE_REGISTER_MEM;
>> > > - if (INTEL_GEN(engine->i915) >= 8)
>> > > + if (GRAPHICS_VER(engine->i915) >= 8)
>> > > srm++;
>> > >
>> > > cs = intel_ring_begin(rq, 4 * engine->whitelist.count);
>> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> > > index adae04c47aab..84f806911370 100644
>> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> > > @@ -60,7 +60,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
>> > > enum forcewake_domains fw_domains = 0;
>> > > unsigned int i;
>> > >
>> > > - if (INTEL_GEN(gt->i915) >= 11) {
>> > > + if (GRAPHICS_VER(gt->i915) >= 11) {
>> > > guc->send_regs.base =
>> > > i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
>> > > guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
>> > > @@ -176,7 +176,7 @@ void intel_guc_init_early(struct intel_guc *guc)
>> > >
>> > > mutex_init(&guc->send_mutex);
>> > > spin_lock_init(&guc->irq_lock);
>> > > - if (INTEL_GEN(i915) >= 11) {
>> > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > guc->notify_reg = GEN11_GUC_HOST_INTERRUPT;
>> > > guc->interrupts.reset = gen11_reset_guc_interrupts;
>> > > guc->interrupts.enable = gen11_enable_guc_interrupts;
>> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> > > index 17526717368c..b32fafba2a90 100644
>> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> > > @@ -162,7 +162,7 @@ static void __guc_ads_init(struct intel_guc *guc)
>> > > blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK] =
>> > > gt->info.vdbox_sfc_access;
>> > >
>> > > - if (INTEL_GEN(i915) >= 12 && !IS_DGFX(i915)) {
>> > > + if (GRAPHICS_VER(i915) >= 12 && !IS_DGFX(i915)) {
>> > > u32 distdbreg = intel_uncore_read(gt->uncore,
>> > > GEN12_DIST_DBS_POPULATED);
>> > > blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI] =
>> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> > > index 2270d6b3b272..76fe766ad1bc 100644
>> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> > > @@ -30,7 +30,7 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
>> > > else
>> > > intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
>> > >
>> > > - if (IS_GEN(uncore->i915, 9)) {
>> > > + if (GRAPHICS_VER(uncore->i915) == 9) {
>> > > /* DOP Clock Gating Enable for GuC clocks */
>> > > intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
>> > > 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
>> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> > > index 335719f17490..541f6da1ec47 100644
>> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> > > @@ -438,7 +438,7 @@ static void guc_interrupts_capture(struct intel_gt *gt)
>> > > u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
>> > > u32 dmask = irqs << 16 | irqs;
>> > >
>> > > - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
>> > > + GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
>> > >
>> > > /* Don't handle the ctx switch interrupt in GuC submission mode */
>> > > intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask, 0);
>> > > @@ -451,7 +451,7 @@ static void guc_interrupts_release(struct intel_gt *gt)
>> > > u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
>> > > u32 dmask = irqs << 16 | irqs;
>> > >
>> > > - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
>> > > + GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
>> > >
>> > > /* Handle ctx switch interrupts again */
>> > > intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0, dmask);
>> > > @@ -648,7 +648,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>> > > engine->emit_flush = gen8_emit_flush_xcs;
>> > > engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
>> > > engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
>> > > - if (INTEL_GEN(engine->i915) >= 12) {
>> > > + if (GRAPHICS_VER(engine->i915) >= 12) {
>> > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;
>> > > engine->emit_flush = gen12_emit_flush_xcs;
>> > > }
>> > > @@ -670,7 +670,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>> > >
>> > > static void rcs_submission_override(struct intel_engine_cs *engine)
>> > > {
>> > > - switch (INTEL_GEN(engine->i915)) {
>> > > + switch (GRAPHICS_VER(engine->i915)) {
>> > > case 12:
>> > > engine->emit_flush = gen12_emit_flush_rcs;
>> > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
>> > > @@ -700,7 +700,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
>> > > * The setup relies on several assumptions (e.g. irqs always enabled)
>> > > * that are only valid on gen11+
>> > > */
>> > > - GEM_BUG_ON(INTEL_GEN(i915) < 11);
>> > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 11);
>> > >
>> > > tasklet_setup(&engine->execlists.tasklet, guc_submission_tasklet);
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>> > > index 56d2144dc6a0..fc5387b410a2 100644
>> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>> > > @@ -43,7 +43,7 @@ void intel_huc_init_early(struct intel_huc *huc)
>> > >
>> > > intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC);
>> > >
>> > > - if (INTEL_GEN(i915) >= 11) {
>> > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
>> > > huc->status.mask = HUC_LOAD_SUCCESSFUL;
>> > > huc->status.value = HUC_LOAD_SUCCESSFUL;
>> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> > > index 6abb8f2dc33d..6c2bf4b6bc10 100644
>> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> > > @@ -23,7 +23,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
>> > > return;
>> > >
>> > > /* Don't enable GuC/HuC on pre-Gen12 */
>> > > - if (INTEL_GEN(i915) < 12) {
>> > > + if (GRAPHICS_VER(i915) < 12) {
>> > > i915->params.enable_guc = 0;
>> > > return;
>> > > }
>> > > @@ -467,7 +467,7 @@ static int __uc_init_hw(struct intel_uc *uc)
>> > >
>> > > /* WaEnableuKernelHeaderValidFix:skl */
>> > > /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
>> > > - if (IS_GEN(i915, 9))
>> > > + if (GRAPHICS_VER(i915) == 9)
>> > > attempts = 3;
>> > > else
>> > > attempts = 1;
>> > > --
>> > > 2.31.1
>> > >
>> >
>> > --
>> > Matt Roper
>> > Graphics Software Engineer
>> > VTT-OSGC Platform Enablement
>> > Intel Corporation
>> > (916) 356-2795
>
>--
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
2021-06-01 19:13 ` Lucas De Marchi
@ 2021-06-01 20:39 ` Matt Roper
2021-06-01 20:53 ` Lucas De Marchi
2021-06-02 6:34 ` Lucas De Marchi
0 siblings, 2 replies; 20+ messages in thread
From: Matt Roper @ 2021-06-01 20:39 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, Jun 01, 2021 at 12:13:17PM -0700, Lucas De Marchi wrote:
> On Tue, Jun 01, 2021 at 10:30:55AM -0700, Matt Roper wrote:
> > On Tue, Jun 01, 2021 at 10:15:14AM -0700, Lucas De Marchi wrote:
> > > On Tue, Jun 01, 2021 at 09:58:34AM -0700, Matt Roper wrote:
> > > > On Thu, May 27, 2021 at 11:16:54AM -0700, Lucas De Marchi wrote:
> > > > > This was done by the following semantic patch:
> > > >
> > > > Is the commit message here out-of-date? The cocci doesn't appear to
> > > > match the diff anymore. IS_GRAPHICS_VER() is the range macro now and
> > > > IS_GEN is being replaced with a direct "==" comparison.
> > >
> > > not necessarily, it's included in "and friends...". Maybe rewording to
> > > something like "replace gen-based macros with new ver-based ones" would
> > > make it clearer?
> >
> > I mean that running the coccinelle rules below through spatch won't
> > generate the code diff here; it would generate a completely different
> > patch (that I don't think would build properly either).
>
> oh, ok. I fixed the issues in the .cocci and forgot to update the commit
> message. Thanks.
>
> Lucas De Marchi
Aside from the commit messages needing updated Coccinelle rules, the
code deltas look correct to me.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
The one remaining thing not covered by this series is the
IS_GEN9_{BC,LP}, but that can be addressed as a follow-up if that's
easier. I'm guessing that, as we saw in the display code, it might be
easier to handle those manually since sometimes the conditions can be
simplified to just a simple version 9 test or combined into a version
10+ test depending on what conditions are already present on the other
branches of the if/else trees.
Matt
>
> >
> >
> > Matt
> >
> > >
> > > Lucas De Marchi
> > >
> > > >
> > > >
> > > > Matt
> > > >
> > > > >
> > > > > @@ expression dev_priv, E; @@
> > > > > - INTEL_GEN(dev_priv) == E
> > > > > + IS_GRAPHICS_VER(dev_priv, E)
> > > > >
> > > > > @@ expression dev_priv; @@
> > > > > - INTEL_GEN(dev_priv)
> > > > > + GRAPHICS_VER(dev_priv)
> > > > >
> > > > > @@ expression dev_priv; expression E; @@
> > > > > - IS_GEN(dev_priv, E)
> > > > > + IS_GRAPHICS_VER(dev_priv, E)
> > > > >
> > > > > @@
> > > > > expression dev_priv;
> > > > > expression from, until;
> > > > > @@
> > > > > - IS_GEN_RANGE(dev_priv, from, until)
> > > > > + IS_GRAPHICS_RANGE(dev_priv, from, until)
> > > > >
> > > > > @def@
> > > > > expression E;
> > > > > identifier id =~ "^gen$";
> > > > > @@
> > > > > - id = GRAPHICS_VER(E)
> > > > > + ver = GRAPHICS_VER(E)
> > > > >
> > > > > @@
> > > > > identifier def.id;
> > > > > @@
> > > > > - id
> > > > > + ver
> > > > >
> > > > > It also takes care of renaming the variable we assign to GRAPHICS_VER()
> > > > > so to use "ver" rather than "gen".
> > > > >
> > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 38 +++++------
> > > > > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
> > > > > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
> > > > > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 +-
> > > > > drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
> > > > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 54 +++++++--------
> > > > > .../drm/i915/gt/intel_execlists_submission.c | 18 ++---
> > > > > drivers/gpu/drm/i915/gt/intel_ggtt.c | 18 ++---
> > > > > drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 34 +++++-----
> > > > > drivers/gpu/drm/i915/gt/intel_gt.c | 27 ++++----
> > > > > .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 12 ++--
> > > > > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 6 +-
> > > > > drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 10 +--
> > > > > drivers/gpu/drm/i915/gt/intel_gtt.c | 14 ++--
> > > > > drivers/gpu/drm/i915/gt/intel_llc.c | 6 +-
> > > > > drivers/gpu/drm/i915/gt/intel_lrc.c | 46 ++++++-------
> > > > > drivers/gpu/drm/i915/gt/intel_mocs.c | 8 +--
> > > > > drivers/gpu/drm/i915/gt/intel_ppgtt.c | 6 +-
> > > > > drivers/gpu/drm/i915/gt/intel_rc6.c | 16 ++---
> > > > > drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
> > > > > drivers/gpu/drm/i915/gt/intel_reset.c | 12 ++--
> > > > > .../gpu/drm/i915/gt/intel_ring_submission.c | 64 +++++++++---------
> > > > > drivers/gpu/drm/i915/gt/intel_rps.c | 60 ++++++++---------
> > > > > drivers/gpu/drm/i915/gt/intel_sseu.c | 14 ++--
> > > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +++++++++----------
> > > > > drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 6 +-
> > > > > drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 +-
> > > > > drivers/gpu/drm/i915/gt/selftest_execlists.c | 4 +-
> > > > > drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +--
> > > > > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 +--
> > > > > drivers/gpu/drm/i915/gt/selftest_llc.c | 4 +-
> > > > > drivers/gpu/drm/i915/gt/selftest_lrc.c | 8 +--
> > > > > drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
> > > > > drivers/gpu/drm/i915/gt/selftest_rc6.c | 4 +-
> > > > > .../drm/i915/gt/selftest_ring_submission.c | 6 +-
> > > > > drivers/gpu/drm/i915/gt/selftest_rps.c | 16 ++---
> > > > > drivers/gpu/drm/i915/gt/selftest_timeline.c | 6 +-
> > > > > .../gpu/drm/i915/gt/selftest_workarounds.c | 8 +--
> > > > > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +-
> > > > > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
> > > > > drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
> > > > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +--
> > > > > drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
> > > > > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
> > > > > 44 files changed, 323 insertions(+), 322 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> > > > > index d4f4452ce5ed..0389bceebd06 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
> > > > > @@ -85,14 +85,14 @@ static int gen6_drpc(struct seq_file *m)
> > > > > gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
> > > > >
> > > > > rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
> > > > > - if (INTEL_GEN(i915) >= 9) {
> > > > > + if (GRAPHICS_VER(i915) >= 9) {
> > > > > gen9_powergate_enable =
> > > > > intel_uncore_read(uncore, GEN9_PG_ENABLE);
> > > > > gen9_powergate_status =
> > > > > intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
> > > > > }
> > > > >
> > > > > - if (INTEL_GEN(i915) <= 7)
> > > > > + if (GRAPHICS_VER(i915) <= 7)
> > > > > sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
> > > > > &rc6vids, NULL);
> > > > >
> > > > > @@ -100,7 +100,7 @@ static int gen6_drpc(struct seq_file *m)
> > > > > yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
> > > > > seq_printf(m, "RC6 Enabled: %s\n",
> > > > > yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
> > > > > - if (INTEL_GEN(i915) >= 9) {
> > > > > + if (GRAPHICS_VER(i915) >= 9) {
> > > > > seq_printf(m, "Render Well Gating Enabled: %s\n",
> > > > > yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
> > > > > seq_printf(m, "Media Well Gating Enabled: %s\n",
> > > > > @@ -134,7 +134,7 @@ static int gen6_drpc(struct seq_file *m)
> > > > >
> > > > > seq_printf(m, "Core Power Down: %s\n",
> > > > > yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
> > > > > - if (INTEL_GEN(i915) >= 9) {
> > > > > + if (GRAPHICS_VER(i915) >= 9) {
> > > > > seq_printf(m, "Render Power Well: %s\n",
> > > > > (gen9_powergate_status &
> > > > > GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
> > > > > @@ -150,7 +150,7 @@ static int gen6_drpc(struct seq_file *m)
> > > > > print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
> > > > > print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
> > > > >
> > > > > - if (INTEL_GEN(i915) <= 7) {
> > > > > + if (GRAPHICS_VER(i915) <= 7) {
> > > > > seq_printf(m, "RC6 voltage: %dmV\n",
> > > > > GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
> > > > > seq_printf(m, "RC6+ voltage: %dmV\n",
> > > > > @@ -250,7 +250,7 @@ static int frequency_show(struct seq_file *m, void *unused)
> > > > >
> > > > > wakeref = intel_runtime_pm_get(uncore->rpm);
> > > > >
> > > > > - if (IS_GEN(i915, 5)) {
> > > > > + if (GRAPHICS_VER(i915) == 5) {
> > > > > u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
> > > > > u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
> > > > >
> > > > > @@ -296,7 +296,7 @@ static int frequency_show(struct seq_file *m, void *unused)
> > > > >
> > > > > seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
> > > > > intel_gpu_freq(rps, rps->efficient_freq));
> > > > > - } else if (INTEL_GEN(i915) >= 6) {
> > > > > + } else if (GRAPHICS_VER(i915) >= 6) {
> > > > > u32 rp_state_limits;
> > > > > u32 gt_perf_status;
> > > > > u32 rp_state_cap;
> > > > > @@ -321,7 +321,7 @@ static int frequency_show(struct seq_file *m, void *unused)
> > > > > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> > > > >
> > > > > reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
> > > > > - if (INTEL_GEN(i915) >= 9) {
> > > > > + if (GRAPHICS_VER(i915) >= 9) {
> > > > > reqf >>= 23;
> > > > > } else {
> > > > > reqf &= ~GEN6_TURBO_DISABLE;
> > > > > @@ -354,7 +354,7 @@ static int frequency_show(struct seq_file *m, void *unused)
> > > > >
> > > > > intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 11) {
> > > > > + if (GRAPHICS_VER(i915) >= 11) {
> > > > > pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
> > > > > pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
> > > > > /*
> > > > > @@ -363,7 +363,7 @@ static int frequency_show(struct seq_file *m, void *unused)
> > > > > */
> > > > > pm_isr = 0;
> > > > > pm_iir = 0;
> > > > > - } else if (INTEL_GEN(i915) >= 8) {
> > > > > + } else if (GRAPHICS_VER(i915) >= 8) {
> > > > > pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
> > > > > pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
> > > > > pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
> > > > > @@ -386,14 +386,14 @@ static int frequency_show(struct seq_file *m, void *unused)
> > > > >
> > > > > seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
> > > > > pm_ier, pm_imr, pm_mask);
> > > > > - if (INTEL_GEN(i915) <= 10)
> > > > > + if (GRAPHICS_VER(i915) <= 10)
> > > > > seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
> > > > > pm_isr, pm_iir);
> > > > > seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
> > > > > rps->pm_intrmsk_mbz);
> > > > > seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> > > > > seq_printf(m, "Render p-state ratio: %d\n",
> > > > > - (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> > > > > + (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> > > > > seq_printf(m, "Render p-state VID: %d\n",
> > > > > gt_perf_status & 0xff);
> > > > > seq_printf(m, "Render p-state limit: %d\n",
> > > > > @@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void *unused)
> > > > > max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
> > > > > rp_state_cap >> 16) & 0xff;
> > > > > max_freq *= (IS_GEN9_BC(i915) ||
> > > > > - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> > > > > + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> > > > > seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
> > > > > intel_gpu_freq(rps, max_freq));
> > > > >
> > > > > max_freq = (rp_state_cap & 0xff00) >> 8;
> > > > > max_freq *= (IS_GEN9_BC(i915) ||
> > > > > - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> > > > > + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> > > > > seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
> > > > > intel_gpu_freq(rps, max_freq));
> > > > >
> > > > > max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
> > > > > rp_state_cap >> 0) & 0xff;
> > > > > max_freq *= (IS_GEN9_BC(i915) ||
> > > > > - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> > > > > + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
> > > > > seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
> > > > > intel_gpu_freq(rps, max_freq));
> > > > > seq_printf(m, "Max overclocked frequency: %dMHz\n",
> > > > > @@ -488,7 +488,7 @@ static int llc_show(struct seq_file *m, void *data)
> > > > > {
> > > > > struct intel_gt *gt = m->private;
> > > > > struct drm_i915_private *i915 = gt->i915;
> > > > > - const bool edram = INTEL_GEN(i915) > 8;
> > > > > + const bool edram = GRAPHICS_VER(i915) > 8;
> > > > > struct intel_rps *rps = >->rps;
> > > > > unsigned int max_gpu_freq, min_gpu_freq;
> > > > > intel_wakeref_t wakeref;
> > > > > @@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data)
> > > > >
> > > > > min_gpu_freq = rps->min_freq;
> > > > > max_gpu_freq = rps->max_freq;
> > > > > - if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
> > > > > + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
> > > > > /* Convert GT frequency to 50 HZ units */
> > > > > min_gpu_freq /= GEN9_FREQ_SCALER;
> > > > > max_gpu_freq /= GEN9_FREQ_SCALER;
> > > > > @@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data)
> > > > > intel_gpu_freq(rps,
> > > > > (gpu_freq *
> > > > > (IS_GEN9_BC(i915) ||
> > > > > - INTEL_GEN(i915) >= 10 ?
> > > > > + GRAPHICS_VER(i915) >= 10 ?
> > > > > GEN9_FREQ_SCALER : 1))),
> > > > > ((ia_freq >> 0) & 0xff) * 100,
> > > > > ((ia_freq >> 8) & 0xff) * 100);
> > > > > @@ -580,7 +580,7 @@ static int rps_boost_show(struct seq_file *m, void *data)
> > > > >
> > > > > seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 6 && intel_rps_is_active(rps)) {
> > > > > + if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) {
> > > > > struct intel_uncore *uncore = gt->uncore;
> > > > > u32 rpup, rpupei;
> > > > > u32 rpdown, rpdownei;
> > > > > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> > > > > index 9646200d2792..61383830505e 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> > > > > @@ -74,7 +74,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
> > > > > cmd = MI_FLUSH;
> > > > > if (mode & EMIT_INVALIDATE) {
> > > > > cmd |= MI_EXE_FLUSH;
> > > > > - if (IS_G4X(rq->engine->i915) || IS_GEN(rq->engine->i915, 5))
> > > > > + if (IS_G4X(rq->engine->i915) || GRAPHICS_VER(rq->engine->i915) == 5)
> > > > > cmd |= MI_INVALIDATE_ISP;
> > > > > }
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > > > index 732c2ed1d933..94e0a5669f90 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > > > @@ -38,7 +38,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
> > > > > * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
> > > > > * pipe control.
> > > > > */
> > > > > - if (IS_GEN(rq->engine->i915, 9))
> > > > > + if (GRAPHICS_VER(rq->engine->i915) == 9)
> > > > > vf_flush_wa = true;
> > > > >
> > > > > /* WaForGAMHang:kbl */
> > > > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > > > > index e3a8924d2286..21c8b7350b7a 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> > > > > @@ -709,7 +709,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> > > > > *
> > > > > * Gen12 has inherited the same read-only fault issue from gen11.
> > > > > */
> > > > > - ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12);
> > > > > + ppgtt->vm.has_read_only = !IS_GRAPHICS_VER(gt->i915, 11, 12);
> > > > >
> > > > > if (HAS_LMEM(gt->i915))
> > > > > ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
> > > > > index 8dfd8f656aaa..e86d8255feec 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
> > > > > @@ -76,7 +76,7 @@ intel_context_reconfigure_sseu(struct intel_context *ce,
> > > > > {
> > > > > int ret;
> > > > >
> > > > > - GEM_BUG_ON(INTEL_GEN(ce->engine->i915) < 8);
> > > > > + GEM_BUG_ON(GRAPHICS_VER(ce->engine->i915) < 8);
> > > > >
> > > > > ret = intel_context_lock_pinned(ce);
> > > > > if (ret)
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > > > index 3f9a811eb02b..54baf17b81b6 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> > > > > @@ -240,10 +240,10 @@ void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
> > > > > * Though they added more rings on g4x/ilk, they did not add
> > > > > * per-engine HWSTAM until gen6.
> > > > > */
> > > > > - if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS)
> > > > > + if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)
> > > > > return;
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) >= 3)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 3)
> > > > > ENGINE_WRITE(engine, RING_HWSTAM, mask);
> > > > > else
> > > > > ENGINE_WRITE16(engine, RING_HWSTAM, mask);
> > > > > @@ -315,7 +315,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
> > > > > CONFIG_DRM_I915_TIMESLICE_DURATION;
> > > > >
> > > > > /* Override to uninterruptible for OpenCL workloads. */
> > > > > - if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS)
> > > > > + if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
> > > > > engine->props.preempt_timeout_ms = 0;
> > > > >
> > > > > engine->defaults = engine->props; /* never to change again */
> > > > > @@ -352,8 +352,8 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
> > > > > * HEVC support is present on first engine instance
> > > > > * before Gen11 and on all instances afterwards.
> > > > > */
> > > > > - if (INTEL_GEN(i915) >= 11 ||
> > > > > - (INTEL_GEN(i915) >= 9 && engine->instance == 0))
> > > > > + if (GRAPHICS_VER(i915) >= 11 ||
> > > > > + (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
> > > > > engine->uabi_capabilities |=
> > > > > I915_VIDEO_CLASS_CAPABILITY_HEVC;
> > > > >
> > > > > @@ -361,14 +361,14 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
> > > > > * SFC block is present only on even logical engine
> > > > > * instances.
> > > > > */
> > > > > - if ((INTEL_GEN(i915) >= 11 &&
> > > > > + if ((GRAPHICS_VER(i915) >= 11 &&
> > > > > (engine->gt->info.vdbox_sfc_access &
> > > > > BIT(engine->instance))) ||
> > > > > - (INTEL_GEN(i915) >= 9 && engine->instance == 0))
> > > > > + (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
> > > > > engine->uabi_capabilities |=
> > > > > I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
> > > > > } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
> > > > > - if (INTEL_GEN(i915) >= 9)
> > > > > + if (GRAPHICS_VER(i915) >= 9)
> > > > > engine->uabi_capabilities |=
> > > > > I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
> > > > > }
> > > > > @@ -466,7 +466,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> > > > >
> > > > > info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
> > > > >
> > > > > - if (INTEL_GEN(i915) < 11)
> > > > > + if (GRAPHICS_VER(i915) < 11)
> > > > > return info->engine_mask;
> > > > >
> > > > > media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
> > > > > @@ -492,7 +492,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
> > > > > * hooked up to an SFC (Scaler & Format Converter) unit.
> > > > > * In TGL each VDBOX has access to an SFC.
> > > > > */
> > > > > - if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
> > > > > + if (GRAPHICS_VER(i915) >= 12 || logical_vdbox++ % 2 == 0)
> > > > > gt->info.vdbox_sfc_access |= BIT(i);
> > > > > }
> > > > > drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
> > > > > @@ -729,7 +729,7 @@ static int engine_setup_common(struct intel_engine_cs *engine)
> > > > > intel_engine_init_whitelist(engine);
> > > > > intel_engine_init_ctx_wa(engine);
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) >= 12)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > > > engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
> > > > >
> > > > > return 0;
> > > > > @@ -997,9 +997,9 @@ u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
> > > > >
> > > > > u64 acthd;
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 8)
> > > > > + if (GRAPHICS_VER(i915) >= 8)
> > > > > acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
> > > > > - else if (INTEL_GEN(i915) >= 4)
> > > > > + else if (GRAPHICS_VER(i915) >= 4)
> > > > > acthd = ENGINE_READ(engine, RING_ACTHD);
> > > > > else
> > > > > acthd = ENGINE_READ(engine, ACTHD);
> > > > > @@ -1011,7 +1011,7 @@ u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
> > > > > {
> > > > > u64 bbaddr;
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) >= 8)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 8)
> > > > > bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
> > > > > else
> > > > > bbaddr = ENGINE_READ(engine, RING_BBADDR);
> > > > > @@ -1058,7 +1058,7 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
> > > > > {
> > > > > int err = 0;
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) < 3)
> > > > > + if (GRAPHICS_VER(engine->i915) < 3)
> > > > > return -ENODEV;
> > > > >
> > > > > ENGINE_TRACE(engine, "\n");
> > > > > @@ -1108,7 +1108,7 @@ read_subslice_reg(const struct intel_engine_cs *engine,
> > > > > u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
> > > > > enum forcewake_domains fw_domains;
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 11) {
> > > > > + if (GRAPHICS_VER(i915) >= 11) {
> > > > > mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
> > > > > mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
> > > > > } else {
> > > > > @@ -1157,7 +1157,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
> > > > >
> > > > > memset(instdone, 0, sizeof(*instdone));
> > > > >
> > > > > - switch (INTEL_GEN(i915)) {
> > > > > + switch (GRAPHICS_VER(i915)) {
> > > > > default:
> > > > > instdone->instdone =
> > > > > intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
> > > > > @@ -1167,7 +1167,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
> > > > >
> > > > > instdone->slice_common =
> > > > > intel_uncore_read(uncore, GEN7_SC_INSTDONE);
> > > > > - if (INTEL_GEN(i915) >= 12) {
> > > > > + if (GRAPHICS_VER(i915) >= 12) {
> > > > > instdone->slice_common_extra[0] =
> > > > > intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
> > > > > instdone->slice_common_extra[1] =
> > > > > @@ -1230,7 +1230,7 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
> > > > > idle = false;
> > > > >
> > > > > /* No bit for gen2, so assume the CS parser is idle */
> > > > > - if (INTEL_GEN(engine->i915) > 2 &&
> > > > > + if (GRAPHICS_VER(engine->i915) > 2 &&
> > > > > !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
> > > > > idle = false;
> > > > >
> > > > > @@ -1327,7 +1327,7 @@ void intel_engines_reset_default_submission(struct intel_gt *gt)
> > > > >
> > > > > bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
> > > > > {
> > > > > - switch (INTEL_GEN(engine->i915)) {
> > > > > + switch (GRAPHICS_VER(engine->i915)) {
> > > > > case 2:
> > > > > return false; /* uses physical not virtual addresses */
> > > > > case 3:
> > > > > @@ -1432,7 +1432,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
> > > > > struct intel_engine_execlists * const execlists = &engine->execlists;
> > > > > u64 addr;
> > > > >
> > > > > - if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
> > > > > + if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7))
> > > > > drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
> > > > > if (HAS_EXECLISTS(dev_priv)) {
> > > > > drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
> > > > > @@ -1449,13 +1449,13 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
> > > > > drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
> > > > > ENGINE_READ(engine, RING_CTL),
> > > > > ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
> > > > > - if (INTEL_GEN(engine->i915) > 2) {
> > > > > + if (GRAPHICS_VER(engine->i915) > 2) {
> > > > > drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
> > > > > ENGINE_READ(engine, RING_MI_MODE),
> > > > > ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
> > > > > }
> > > > >
> > > > > - if (INTEL_GEN(dev_priv) >= 6) {
> > > > > + if (GRAPHICS_VER(dev_priv) >= 6) {
> > > > > drm_printf(m, "\tRING_IMR: 0x%08x\n",
> > > > > ENGINE_READ(engine, RING_IMR));
> > > > > drm_printf(m, "\tRING_ESR: 0x%08x\n",
> > > > > @@ -1472,15 +1472,15 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
> > > > > addr = intel_engine_get_last_batch_head(engine);
> > > > > drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
> > > > > upper_32_bits(addr), lower_32_bits(addr));
> > > > > - if (INTEL_GEN(dev_priv) >= 8)
> > > > > + if (GRAPHICS_VER(dev_priv) >= 8)
> > > > > addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
> > > > > - else if (INTEL_GEN(dev_priv) >= 4)
> > > > > + else if (GRAPHICS_VER(dev_priv) >= 4)
> > > > > addr = ENGINE_READ(engine, RING_DMA_FADD);
> > > > > else
> > > > > addr = ENGINE_READ(engine, DMA_FADD_I8XX);
> > > > > drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
> > > > > upper_32_bits(addr), lower_32_bits(addr));
> > > > > - if (INTEL_GEN(dev_priv) >= 4) {
> > > > > + if (GRAPHICS_VER(dev_priv) >= 4) {
> > > > > drm_printf(m, "\tIPEIR: 0x%08x\n",
> > > > > ENGINE_READ(engine, RING_IPEIR));
> > > > > drm_printf(m, "\tIPEHR: 0x%08x\n",
> > > > > @@ -1559,7 +1559,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
> > > > > }
> > > > > rcu_read_unlock();
> > > > > execlists_active_unlock_bh(execlists);
> > > > > - } else if (INTEL_GEN(dev_priv) > 6) {
> > > > > + } else if (GRAPHICS_VER(dev_priv) > 6) {
> > > > > drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
> > > > > ENGINE_READ(engine, RING_PP_DIR_BASE));
> > > > > drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > > > index 8db200422950..fc77592d88a9 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> > > > > @@ -1847,7 +1847,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
> > > > > ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n",
> > > > > head, upper_32_bits(csb), lower_32_bits(csb));
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) >= 12)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > > > promote = gen12_csb_parse(csb);
> > > > > else
> > > > > promote = gen8_csb_parse(csb);
> > > > > @@ -2772,7 +2772,7 @@ static void enable_execlists(struct intel_engine_cs *engine)
> > > > >
> > > > > intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) >= 11)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 11)
> > > > > mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
> > > > > else
> > > > > mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
> > > > > @@ -3103,7 +3103,7 @@ static void execlists_park(struct intel_engine_cs *engine)
> > > > >
> > > > > static bool can_preempt(struct intel_engine_cs *engine)
> > > > > {
> > > > > - if (INTEL_GEN(engine->i915) > 8)
> > > > > + if (GRAPHICS_VER(engine->i915) > 8)
> > > > > return true;
> > > > >
> > > > > /* GPGPU on bdw requires extra w/a; not implemented */
> > > > > @@ -3156,13 +3156,13 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> > > > > engine->emit_flush = gen8_emit_flush_xcs;
> > > > > engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
> > > > > engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
> > > > > - if (INTEL_GEN(engine->i915) >= 12) {
> > > > > + if (GRAPHICS_VER(engine->i915) >= 12) {
> > > > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;
> > > > > engine->emit_flush = gen12_emit_flush_xcs;
> > > > > }
> > > > > engine->set_default_submission = execlists_set_default_submission;
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) < 11) {
> > > > > + if (GRAPHICS_VER(engine->i915) < 11) {
> > > > > engine->irq_enable = gen8_logical_ring_enable_irq;
> > > > > engine->irq_disable = gen8_logical_ring_disable_irq;
> > > > > } else {
> > > > > @@ -3195,7 +3195,7 @@ static void logical_ring_default_irqs(struct intel_engine_cs *engine)
> > > > > {
> > > > > unsigned int shift = 0;
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) < 11) {
> > > > > + if (GRAPHICS_VER(engine->i915) < 11) {
> > > > > const u8 irq_shifts[] = {
> > > > > [RCS0] = GEN8_RCS_IRQ_SHIFT,
> > > > > [BCS0] = GEN8_BCS_IRQ_SHIFT,
> > > > > @@ -3215,7 +3215,7 @@ static void logical_ring_default_irqs(struct intel_engine_cs *engine)
> > > > >
> > > > > static void rcs_submission_override(struct intel_engine_cs *engine)
> > > > > {
> > > > > - switch (INTEL_GEN(engine->i915)) {
> > > > > + switch (GRAPHICS_VER(engine->i915)) {
> > > > > case 12:
> > > > > engine->emit_flush = gen12_emit_flush_rcs;
> > > > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
> > > > > @@ -3266,13 +3266,13 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
> > > > > execlists->csb_write =
> > > > > &engine->status_page.addr[intel_hws_csb_write_index(i915)];
> > > > >
> > > > > - if (INTEL_GEN(i915) < 11)
> > > > > + if (GRAPHICS_VER(i915) < 11)
> > > > > execlists->csb_size = GEN8_CSB_ENTRIES;
> > > > > else
> > > > > execlists->csb_size = GEN11_CSB_ENTRIES;
> > > > >
> > > > > engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);
> > > > > - if (INTEL_GEN(engine->i915) >= 11) {
> > > > > + if (GRAPHICS_VER(engine->i915) >= 11) {
> > > > > execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
> > > > > execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
> > > > > }
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > > > index 35069ca5d7de..19bd8856ce84 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > > > @@ -107,10 +107,10 @@ static bool needs_idle_maps(struct drm_i915_private *i915)
> > > > > if (!intel_vtd_active())
> > > > > return false;
> > > > >
> > > > > - if (IS_GEN(i915, 5) && IS_MOBILE(i915))
> > > > > + if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
> > > > > return true;
> > > > >
> > > > > - if (IS_GEN(i915, 12))
> > > > > + if (GRAPHICS_VER(i915) == 12)
> > > > > return true; /* XXX DMAR fault reason 7 */
> > > > >
> > > > > return false;
> > > > > @@ -176,7 +176,7 @@ static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
> > > > >
> > > > > gen8_ggtt_invalidate(ggtt);
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 12)
> > > > > + if (GRAPHICS_VER(i915) >= 12)
> > > > > intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
> > > > > GEN12_GUC_TLB_INV_CR_INVALIDATE);
> > > > > else
> > > > > @@ -820,7 +820,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
> > > > > * resort to an uncached mapping. The WC issue is easily caught by the
> > > > > * readback check when writing GTT PTE entries.
> > > > > */
> > > > > - if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
> > > > > + if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 10)
> > > > > ggtt->gsm = ioremap(phys_addr, size);
> > > > > else
> > > > > ggtt->gsm = ioremap_wc(phys_addr, size);
> > > > > @@ -1065,7 +1065,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
> > > > > ggtt->vm.pte_encode = hsw_pte_encode;
> > > > > else if (IS_VALLEYVIEW(i915))
> > > > > ggtt->vm.pte_encode = byt_pte_encode;
> > > > > - else if (INTEL_GEN(i915) >= 7)
> > > > > + else if (GRAPHICS_VER(i915) >= 7)
> > > > > ggtt->vm.pte_encode = ivb_pte_encode;
> > > > > else
> > > > > ggtt->vm.pte_encode = snb_pte_encode;
> > > > > @@ -1137,9 +1137,9 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
> > > > > ggtt->vm.dma = i915->drm.dev;
> > > > > dma_resv_init(&ggtt->vm.resv);
> > > > >
> > > > > - if (INTEL_GEN(i915) <= 5)
> > > > > + if (GRAPHICS_VER(i915) <= 5)
> > > > > ret = i915_gmch_probe(ggtt);
> > > > > - else if (INTEL_GEN(i915) < 8)
> > > > > + else if (GRAPHICS_VER(i915) < 8)
> > > > > ret = gen6_gmch_probe(ggtt);
> > > > > else
> > > > > ret = gen8_gmch_probe(ggtt);
> > > > > @@ -1196,7 +1196,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
> > > > >
> > > > > int i915_ggtt_enable_hw(struct drm_i915_private *i915)
> > > > > {
> > > > > - if (INTEL_GEN(i915) < 6 && !intel_enable_gtt())
> > > > > + if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
> > > > > return -EIO;
> > > > >
> > > > > return 0;
> > > > > @@ -1261,7 +1261,7 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt)
> > > > > if (flush)
> > > > > wbinvd_on_all_cpus();
> > > > >
> > > > > - if (INTEL_GEN(ggtt->vm.i915) >= 8)
> > > > > + if (GRAPHICS_VER(ggtt->vm.i915) >= 8)
> > > > > setup_private_pat(ggtt->vm.gt->uncore);
> > > > >
> > > > > intel_ggtt_restore_fences(ggtt);
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > > > > index 7bf84cd21543..cac7f3f44642 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > > > > @@ -56,7 +56,7 @@ static void i965_write_fence_reg(struct i915_fence_reg *fence)
> > > > > int fence_pitch_shift;
> > > > > u64 val;
> > > > >
> > > > > - if (INTEL_GEN(fence_to_i915(fence)) >= 6) {
> > > > > + if (GRAPHICS_VER(fence_to_i915(fence)) >= 6) {
> > > > > fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
> > > > > fence_reg_hi = FENCE_REG_GEN6_HI(fence->id);
> > > > > fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
> > > > > @@ -173,9 +173,9 @@ static void fence_write(struct i915_fence_reg *fence)
> > > > > * and explicitly managed for internal users.
> > > > > */
> > > > >
> > > > > - if (IS_GEN(i915, 2))
> > > > > + if (GRAPHICS_VER(i915) == 2)
> > > > > i830_write_fence_reg(fence);
> > > > > - else if (IS_GEN(i915, 3))
> > > > > + else if (GRAPHICS_VER(i915) == 3)
> > > > > i915_write_fence_reg(fence);
> > > > > else
> > > > > i965_write_fence_reg(fence);
> > > > > @@ -188,7 +188,7 @@ static void fence_write(struct i915_fence_reg *fence)
> > > > >
> > > > > static bool gpu_uses_fence_registers(struct i915_fence_reg *fence)
> > > > > {
> > > > > - return INTEL_GEN(fence_to_i915(fence)) < 4;
> > > > > + return GRAPHICS_VER(fence_to_i915(fence)) < 4;
> > > > > }
> > > > >
> > > > > static int fence_update(struct i915_fence_reg *fence,
> > > > > @@ -569,7 +569,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> > > > > u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> > > > > u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 8 || IS_VALLEYVIEW(i915)) {
> > > > > + if (GRAPHICS_VER(i915) >= 8 || IS_VALLEYVIEW(i915)) {
> > > > > /*
> > > > > * On BDW+, swizzling is not used. We leave the CPU memory
> > > > > * controller in charge of optimizing memory accesses without
> > > > > @@ -579,7 +579,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> > > > > */
> > > > > swizzle_x = I915_BIT_6_SWIZZLE_NONE;
> > > > > swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> > > > > - } else if (INTEL_GEN(i915) >= 6) {
> > > > > + } else if (GRAPHICS_VER(i915) >= 6) {
> > > > > if (i915->preserve_bios_swizzle) {
> > > > > if (intel_uncore_read(uncore, DISP_ARB_CTL) &
> > > > > DISP_TILE_SURFACE_SWIZZLING) {
> > > > > @@ -611,14 +611,14 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> > > > > swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> > > > > }
> > > > > }
> > > > > - } else if (IS_GEN(i915, 5)) {
> > > > > + } else if (GRAPHICS_VER(i915) == 5) {
> > > > > /*
> > > > > * On Ironlake whatever DRAM config, GPU always do
> > > > > * same swizzling setup.
> > > > > */
> > > > > swizzle_x = I915_BIT_6_SWIZZLE_9_10;
> > > > > swizzle_y = I915_BIT_6_SWIZZLE_9;
> > > > > - } else if (IS_GEN(i915, 2)) {
> > > > > + } else if (GRAPHICS_VER(i915) == 2) {
> > > > > /*
> > > > > * As far as we know, the 865 doesn't have these bit 6
> > > > > * swizzling issues.
> > > > > @@ -697,7 +697,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
> > > > > }
> > > > >
> > > > > /* check for L-shaped memory aka modified enhanced addressing */
> > > > > - if (IS_GEN(i915, 4) &&
> > > > > + if (GRAPHICS_VER(i915) == 4 &&
> > > > > !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
> > > > > swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> > > > > swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> > > > > @@ -844,10 +844,10 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
> > > > >
> > > > > if (!i915_ggtt_has_aperture(ggtt))
> > > > > num_fences = 0;
> > > > > - else if (INTEL_GEN(i915) >= 7 &&
> > > > > + else if (GRAPHICS_VER(i915) >= 7 &&
> > > > > !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
> > > > > num_fences = 32;
> > > > > - else if (INTEL_GEN(i915) >= 4 ||
> > > > > + else if (GRAPHICS_VER(i915) >= 4 ||
> > > > > IS_I945G(i915) || IS_I945GM(i915) ||
> > > > > IS_G33(i915) || IS_PINEVIEW(i915))
> > > > > num_fences = 16;
> > > > > @@ -895,29 +895,29 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
> > > > > struct drm_i915_private *i915 = gt->i915;
> > > > > struct intel_uncore *uncore = gt->uncore;
> > > > >
> > > > > - if (INTEL_GEN(i915) < 5 ||
> > > > > + if (GRAPHICS_VER(i915) < 5 ||
> > > > > i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
> > > > > return;
> > > > >
> > > > > intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
> > > > >
> > > > > - if (IS_GEN(i915, 5))
> > > > > + if (GRAPHICS_VER(i915) == 5)
> > > > > return;
> > > > >
> > > > > intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL);
> > > > >
> > > > > - if (IS_GEN(i915, 6))
> > > > > + if (GRAPHICS_VER(i915) == 6)
> > > > > intel_uncore_write(uncore,
> > > > > ARB_MODE,
> > > > > _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
> > > > > - else if (IS_GEN(i915, 7))
> > > > > + else if (GRAPHICS_VER(i915) == 7)
> > > > > intel_uncore_write(uncore,
> > > > > ARB_MODE,
> > > > > _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
> > > > > - else if (IS_GEN(i915, 8))
> > > > > + else if (GRAPHICS_VER(i915) == 8)
> > > > > intel_uncore_write(uncore,
> > > > > GAMTARBMODE,
> > > > > _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
> > > > > else
> > > > > - MISSING_CASE(INTEL_GEN(i915));
> > > > > + MISSING_CASE(GRAPHICS_VER(i915));
> > > > > }
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > > index 8d77dcbad059..7f24301cef18 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > > @@ -115,10 +115,10 @@ static void init_unused_rings(struct intel_gt *gt)
> > > > > init_unused_ring(gt, SRB1_BASE);
> > > > > init_unused_ring(gt, SRB2_BASE);
> > > > > init_unused_ring(gt, SRB3_BASE);
> > > > > - } else if (IS_GEN(i915, 2)) {
> > > > > + } else if (GRAPHICS_VER(i915) == 2) {
> > > > > init_unused_ring(gt, SRB0_BASE);
> > > > > init_unused_ring(gt, SRB1_BASE);
> > > > > - } else if (IS_GEN(i915, 3)) {
> > > > > + } else if (GRAPHICS_VER(i915) == 3) {
> > > > > init_unused_ring(gt, PRB1_BASE);
> > > > > init_unused_ring(gt, PRB2_BASE);
> > > > > }
> > > > > @@ -135,7 +135,7 @@ int intel_gt_init_hw(struct intel_gt *gt)
> > > > > /* Double layer security blanket, see i915_gem_init() */
> > > > > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> > > > >
> > > > > - if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
> > > > > + if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
> > > > > intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
> > > > >
> > > > > if (IS_HASWELL(i915))
> > > > > @@ -208,10 +208,10 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
> > > > > struct intel_uncore *uncore = gt->uncore;
> > > > > u32 eir;
> > > > >
> > > > > - if (!IS_GEN(i915, 2))
> > > > > + if (GRAPHICS_VER(i915) != 2)
> > > > > clear_register(uncore, PGTBL_ER);
> > > > >
> > > > > - if (INTEL_GEN(i915) < 4)
> > > > > + if (GRAPHICS_VER(i915) < 4)
> > > > > clear_register(uncore, IPEIR(RENDER_RING_BASE));
> > > > > else
> > > > > clear_register(uncore, IPEIR_I965);
> > > > > @@ -229,13 +229,13 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
> > > > > I915_MASTER_ERROR_INTERRUPT);
> > > > > }
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 12) {
> > > > > + if (GRAPHICS_VER(i915) >= 12) {
> > > > > rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
> > > > > intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
> > > > > - } else if (INTEL_GEN(i915) >= 8) {
> > > > > + } else if (GRAPHICS_VER(i915) >= 8) {
> > > > > rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
> > > > > intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
> > > > > - } else if (INTEL_GEN(i915) >= 6) {
> > > > > + } else if (GRAPHICS_VER(i915) >= 6) {
> > > > > struct intel_engine_cs *engine;
> > > > > enum intel_engine_id id;
> > > > >
> > > > > @@ -273,7 +273,7 @@ static void gen8_check_faults(struct intel_gt *gt)
> > > > > i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
> > > > > u32 fault;
> > > > >
> > > > > - if (INTEL_GEN(gt->i915) >= 12) {
> > > > > + if (GRAPHICS_VER(gt->i915) >= 12) {
> > > > > fault_reg = GEN12_RING_FAULT_REG;
> > > > > fault_data0_reg = GEN12_FAULT_TLB_DATA0;
> > > > > fault_data1_reg = GEN12_FAULT_TLB_DATA1;
> > > > > @@ -313,9 +313,9 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
> > > > > struct drm_i915_private *i915 = gt->i915;
> > > > >
> > > > > /* From GEN8 onwards we only have one 'All Engine Fault Register' */
> > > > > - if (INTEL_GEN(i915) >= 8)
> > > > > + if (GRAPHICS_VER(i915) >= 8)
> > > > > gen8_check_faults(gt);
> > > > > - else if (INTEL_GEN(i915) >= 6)
> > > > > + else if (GRAPHICS_VER(i915) >= 6)
> > > > > gen6_check_faults(gt);
> > > > > else
> > > > > return;
> > > > > @@ -367,7 +367,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
> > > > > void intel_gt_chipset_flush(struct intel_gt *gt)
> > > > > {
> > > > > wmb();
> > > > > - if (INTEL_GEN(gt->i915) < 6)
> > > > > + if (GRAPHICS_VER(gt->i915) < 6)
> > > > > intel_gtt_chipset_flush();
> > > > > }
> > > > >
> > > > > @@ -591,7 +591,8 @@ int intel_gt_init(struct intel_gt *gt)
> > > > > */
> > > > > intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
> > > > >
> > > > > - err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K);
> > > > > + err = intel_gt_init_scratch(gt,
> > > > > + GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
> > > > > if (err)
> > > > > goto out_fw;
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> > > > > index 582fcaee11aa..9f0e729d2d15 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
> > > > > @@ -76,7 +76,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> > > > > u32 f19_2_mhz = 19200000;
> > > > > u32 f24_mhz = 24000000;
> > > > >
> > > > > - if (INTEL_GEN(uncore->i915) <= 4) {
> > > > > + if (GRAPHICS_VER(uncore->i915) <= 4) {
> > > > > /*
> > > > > * PRMs say:
> > > > > *
> > > > > @@ -85,7 +85,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> > > > > * (“CLKCFG”) MCHBAR register)
> > > > > */
> > > > > return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
> > > > > - } else if (INTEL_GEN(uncore->i915) <= 8) {
> > > > > + } else if (GRAPHICS_VER(uncore->i915) <= 8) {
> > > > > /*
> > > > > * PRMs say:
> > > > > *
> > > > > @@ -94,7 +94,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> > > > > * rolling over every 1.5 hours).
> > > > > */
> > > > > return f12_5_mhz;
> > > > > - } else if (INTEL_GEN(uncore->i915) <= 9) {
> > > > > + } else if (GRAPHICS_VER(uncore->i915) <= 9) {
> > > > > u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> > > > > u32 freq = 0;
> > > > >
> > > > > @@ -113,7 +113,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> > > > > }
> > > > >
> > > > > return freq;
> > > > > - } else if (INTEL_GEN(uncore->i915) <= 12) {
> > > > > + } else if (GRAPHICS_VER(uncore->i915) <= 12) {
> > > > > u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
> > > > > u32 freq = 0;
> > > > >
> > > > > @@ -128,7 +128,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
> > > > > } else {
> > > > > u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
> > > > >
> > > > > - if (INTEL_GEN(uncore->i915) <= 10)
> > > > > + if (GRAPHICS_VER(uncore->i915) <= 10)
> > > > > freq = gen10_get_crystal_clock_freq(uncore, c0);
> > > > > else
> > > > > freq = gen11_get_crystal_clock_freq(uncore, c0);
> > > > > @@ -211,7 +211,7 @@ u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns)
> > > > > * frozen machine.
> > > > > */
> > > > > val = div_u64_roundup(intel_gt_ns_to_clock_interval(gt, ns), 16);
> > > > > - if (IS_GEN(gt->i915, 6))
> > > > > + if (GRAPHICS_VER(gt->i915) == 6)
> > > > > val = div_u64_roundup(val, 25) * 25;
> > > > >
> > > > > return val;
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> > > > > index d29126c458ba..1ec63cceabf6 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> > > > > @@ -395,7 +395,7 @@ void gen5_gt_irq_reset(struct intel_gt *gt)
> > > > > struct intel_uncore *uncore = gt->uncore;
> > > > >
> > > > > GEN3_IRQ_RESET(uncore, GT);
> > > > > - if (INTEL_GEN(gt->i915) >= 6)
> > > > > + if (GRAPHICS_VER(gt->i915) >= 6)
> > > > > GEN3_IRQ_RESET(uncore, GEN6_PM);
> > > > > }
> > > > >
> > > > > @@ -413,14 +413,14 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt)
> > > > > }
> > > > >
> > > > > gt_irqs |= GT_RENDER_USER_INTERRUPT;
> > > > > - if (IS_GEN(gt->i915, 5))
> > > > > + if (GRAPHICS_VER(gt->i915) == 5)
> > > > > gt_irqs |= ILK_BSD_USER_INTERRUPT;
> > > > > else
> > > > > gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
> > > > >
> > > > > GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs);
> > > > >
> > > > > - if (INTEL_GEN(gt->i915) >= 6) {
> > > > > + if (GRAPHICS_VER(gt->i915) >= 6) {
> > > > > /*
> > > > > * RPS interrupts will get enabled/disabled on demand when RPS
> > > > > * itself is enabled/disabled.
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
> > > > > index 811a11ed181c..fe51f894b073 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
> > > > > @@ -16,10 +16,10 @@ static void write_pm_imr(struct intel_gt *gt)
> > > > > u32 mask = gt->pm_imr;
> > > > > i915_reg_t reg;
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 11) {
> > > > > + if (GRAPHICS_VER(i915) >= 11) {
> > > > > reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
> > > > > mask <<= 16; /* pm is in upper half */
> > > > > - } else if (INTEL_GEN(i915) >= 8) {
> > > > > + } else if (GRAPHICS_VER(i915) >= 8) {
> > > > > reg = GEN8_GT_IMR(2);
> > > > > } else {
> > > > > reg = GEN6_PMIMR;
> > > > > @@ -61,7 +61,7 @@ void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask)
> > > > > void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)
> > > > > {
> > > > > struct intel_uncore *uncore = gt->uncore;
> > > > > - i915_reg_t reg = INTEL_GEN(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
> > > > > + i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
> > > > >
> > > > > lockdep_assert_held(>->irq_lock);
> > > > >
> > > > > @@ -77,10 +77,10 @@ static void write_pm_ier(struct intel_gt *gt)
> > > > > u32 mask = gt->pm_ier;
> > > > > i915_reg_t reg;
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 11) {
> > > > > + if (GRAPHICS_VER(i915) >= 11) {
> > > > > reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
> > > > > mask <<= 16; /* pm is in upper half */
> > > > > - } else if (INTEL_GEN(i915) >= 8) {
> > > > > + } else if (GRAPHICS_VER(i915) >= 8) {
> > > > > reg = GEN8_GT_IER(2);
> > > > > } else {
> > > > > reg = GEN6_PMIER;
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > > > index 9b98f9d9faa3..b9c9993573ec 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > > > @@ -327,7 +327,7 @@ void gtt_write_workarounds(struct intel_gt *gt)
> > > > > intel_uncore_write(uncore,
> > > > > GEN8_L3_LRA_1_GPGPU,
> > > > > GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> > > > > - else if (INTEL_GEN(i915) >= 9 && INTEL_GEN(i915) <= 11)
> > > > > + else if (GRAPHICS_VER(i915) >= 9 && GRAPHICS_VER(i915) <= 11)
> > > > > intel_uncore_write(uncore,
> > > > > GEN8_L3_LRA_1_GPGPU,
> > > > > GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> > > > > @@ -344,13 +344,13 @@ void gtt_write_workarounds(struct intel_gt *gt)
> > > > > * driver.
> > > > > */
> > > > > if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
> > > > > - INTEL_GEN(i915) <= 10)
> > > > > + GRAPHICS_VER(i915) <= 10)
> > > > > intel_uncore_rmw(uncore,
> > > > > GEN8_GAMW_ECO_DEV_RW_IA,
> > > > > 0,
> > > > > GAMW_ECO_ENABLE_64K_IPS_FIELD);
> > > > >
> > > > > - if (IS_GEN_RANGE(i915, 8, 11)) {
> > > > > + if (IS_GRAPHICS_VER(i915, 8, 11)) {
> > > > > bool can_use_gtt_cache = true;
> > > > >
> > > > > /*
> > > > > @@ -432,7 +432,7 @@ static void bdw_setup_private_ppat(struct intel_uncore *uncore)
> > > > > GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
> > > > >
> > > > > /* for scanout with eLLC */
> > > > > - if (INTEL_GEN(i915) >= 9)
> > > > > + if (GRAPHICS_VER(i915) >= 9)
> > > > > pat |= GEN8_PPAT(2, GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE);
> > > > > else
> > > > > pat |= GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
> > > > > @@ -481,11 +481,11 @@ void setup_private_pat(struct intel_uncore *uncore)
> > > > > {
> > > > > struct drm_i915_private *i915 = uncore->i915;
> > > > >
> > > > > - GEM_BUG_ON(INTEL_GEN(i915) < 8);
> > > > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 12)
> > > > > + if (GRAPHICS_VER(i915) >= 12)
> > > > > tgl_setup_private_ppat(uncore);
> > > > > - else if (INTEL_GEN(i915) >= 10)
> > > > > + else if (GRAPHICS_VER(i915) >= 10)
> > > > > cnl_setup_private_ppat(uncore);
> > > > > else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))
> > > > > chv_setup_private_ppat(uncore);
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
> > > > > index 075d741644ae..eb1a15deed22 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_llc.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_llc.c
> > > > > @@ -64,7 +64,7 @@ static bool get_ia_constants(struct intel_llc *llc,
> > > > >
> > > > > consts->min_gpu_freq = rps->min_freq;
> > > > > consts->max_gpu_freq = rps->max_freq;
> > > > > - if (INTEL_GEN(i915) >= 9) {
> > > > > + if (GRAPHICS_VER(i915) >= 9) {
> > > > > /* Convert GT frequency to 50 HZ units */
> > > > > consts->min_gpu_freq /= GEN9_FREQ_SCALER;
> > > > > consts->max_gpu_freq /= GEN9_FREQ_SCALER;
> > > > > @@ -83,13 +83,13 @@ static void calc_ia_freq(struct intel_llc *llc,
> > > > > const int diff = consts->max_gpu_freq - gpu_freq;
> > > > > unsigned int ia_freq = 0, ring_freq = 0;
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 9) {
> > > > > + if (GRAPHICS_VER(i915) >= 9) {
> > > > > /*
> > > > > * ring_freq = 2 * GT. ring_freq is in 100MHz units
> > > > > * No floor required for ring frequency on SKL.
> > > > > */
> > > > > ring_freq = gpu_freq;
> > > > > - } else if (INTEL_GEN(i915) >= 8) {
> > > > > + } else if (GRAPHICS_VER(i915) >= 8) {
> > > > > /* max(2 * GT, DDR). NB: GT is 50MHz units */
> > > > > ring_freq = max(consts->min_ring_freq, gpu_freq);
> > > > > } else if (IS_HASWELL(i915)) {
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > > > index aafe2a4df496..a27bac0a4bfb 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > > > @@ -47,7 +47,7 @@ static void set_offsets(u32 *regs,
> > > > > *regs = MI_LOAD_REGISTER_IMM(count);
> > > > > if (flags & POSTED)
> > > > > *regs |= MI_LRI_FORCE_POSTED;
> > > > > - if (INTEL_GEN(engine->i915) >= 11)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 11)
> > > > > *regs |= MI_LRI_LRM_CS_MMIO;
> > > > > regs++;
> > > > >
> > > > > @@ -70,7 +70,7 @@ static void set_offsets(u32 *regs,
> > > > > if (close) {
> > > > > /* Close the batch; used mainly by live_lrc_layout() */
> > > > > *regs = MI_BATCH_BUFFER_END;
> > > > > - if (INTEL_GEN(engine->i915) >= 10)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 10)
> > > > > *regs |= BIT(0);
> > > > > }
> > > > > }
> > > > > @@ -498,22 +498,22 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> > > > > * addressing to automatic fixup the register state between the
> > > > > * physical engines for virtual engine.
> > > > > */
> > > > > - GEM_BUG_ON(INTEL_GEN(engine->i915) >= 12 &&
> > > > > + GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
> > > > > !intel_engine_has_relative_mmio(engine));
> > > > >
> > > > > if (engine->class == RENDER_CLASS) {
> > > > > - if (INTEL_GEN(engine->i915) >= 12)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > > > return gen12_rcs_offsets;
> > > > > - else if (INTEL_GEN(engine->i915) >= 11)
> > > > > + else if (GRAPHICS_VER(engine->i915) >= 11)
> > > > > return gen11_rcs_offsets;
> > > > > - else if (INTEL_GEN(engine->i915) >= 9)
> > > > > + else if (GRAPHICS_VER(engine->i915) >= 9)
> > > > > return gen9_rcs_offsets;
> > > > > else
> > > > > return gen8_rcs_offsets;
> > > > > } else {
> > > > > - if (INTEL_GEN(engine->i915) >= 12)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > > > return gen12_xcs_offsets;
> > > > > - else if (INTEL_GEN(engine->i915) >= 9)
> > > > > + else if (GRAPHICS_VER(engine->i915) >= 9)
> > > > > return gen9_xcs_offsets;
> > > > > else
> > > > > return gen8_xcs_offsets;
> > > > > @@ -522,9 +522,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
> > > > >
> > > > > static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
> > > > > {
> > > > > - if (INTEL_GEN(engine->i915) >= 12)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > > > return 0x60;
> > > > > - else if (INTEL_GEN(engine->i915) >= 9)
> > > > > + else if (GRAPHICS_VER(engine->i915) >= 9)
> > > > > return 0x54;
> > > > > else if (engine->class == RENDER_CLASS)
> > > > > return 0x58;
> > > > > @@ -534,9 +534,9 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
> > > > >
> > > > > static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
> > > > > {
> > > > > - if (INTEL_GEN(engine->i915) >= 12)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > > > return 0x74;
> > > > > - else if (INTEL_GEN(engine->i915) >= 9)
> > > > > + else if (GRAPHICS_VER(engine->i915) >= 9)
> > > > > return 0x68;
> > > > > else if (engine->class == RENDER_CLASS)
> > > > > return 0xd8;
> > > > > @@ -546,9 +546,9 @@ static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
> > > > >
> > > > > static int lrc_ring_wa_bb_per_ctx(const struct intel_engine_cs *engine)
> > > > > {
> > > > > - if (INTEL_GEN(engine->i915) >= 12)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > > > return 0x12;
> > > > > - else if (INTEL_GEN(engine->i915) >= 9 || engine->class == RENDER_CLASS)
> > > > > + else if (GRAPHICS_VER(engine->i915) >= 9 || engine->class == RENDER_CLASS)
> > > > > return 0x18;
> > > > > else
> > > > > return -1;
> > > > > @@ -581,9 +581,9 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
> > > > > if (engine->class != RENDER_CLASS)
> > > > > return -1;
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) >= 12)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
> > > > > return 0xb6;
> > > > > - else if (INTEL_GEN(engine->i915) >= 11)
> > > > > + else if (GRAPHICS_VER(engine->i915) >= 11)
> > > > > return 0xaa;
> > > > > else
> > > > > return -1;
> > > > > @@ -592,9 +592,9 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
> > > > > static u32
> > > > > lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
> > > > > {
> > > > > - switch (INTEL_GEN(engine->i915)) {
> > > > > + switch (GRAPHICS_VER(engine->i915)) {
> > > > > default:
> > > > > - MISSING_CASE(INTEL_GEN(engine->i915));
> > > > > + MISSING_CASE(GRAPHICS_VER(engine->i915));
> > > > > fallthrough;
> > > > > case 12:
> > > > > return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
> > > > > @@ -637,7 +637,7 @@ static void init_common_regs(u32 * const regs,
> > > > > ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
> > > > > if (inhibit)
> > > > > ctl |= CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT;
> > > > > - if (INTEL_GEN(engine->i915) < 11)
> > > > > + if (GRAPHICS_VER(engine->i915) < 11)
> > > > > ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
> > > > > CTX_CTRL_RS_CTX_ENABLE);
> > > > > regs[CTX_CONTEXT_CONTROL] = ctl;
> > > > > @@ -805,7 +805,7 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
> > > > > if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> > > > > context_size += I915_GTT_PAGE_SIZE; /* for redzone */
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) == 12) {
> > > > > + if (GRAPHICS_VER(engine->i915) == 12) {
> > > > > ce->wa_bb_page = context_size / PAGE_SIZE;
> > > > > context_size += PAGE_SIZE;
> > > > > }
> > > > > @@ -1114,7 +1114,7 @@ static u32 lrc_descriptor(const struct intel_context *ce)
> > > > > desc <<= GEN8_CTX_ADDRESSING_MODE_SHIFT;
> > > > >
> > > > > desc |= GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
> > > > > - if (IS_GEN(ce->vm->i915, 8))
> > > > > + if (GRAPHICS_VER(ce->vm->i915) == 8)
> > > > > desc |= GEN8_CTX_L3LLC_COHERENT;
> > > > >
> > > > > return i915_ggtt_offset(ce->state) | desc;
> > > > > @@ -1469,7 +1469,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
> > > > > if (engine->class != RENDER_CLASS)
> > > > > return;
> > > > >
> > > > > - switch (INTEL_GEN(engine->i915)) {
> > > > > + switch (GRAPHICS_VER(engine->i915)) {
> > > > > case 12:
> > > > > case 11:
> > > > > return;
> > > > > @@ -1486,7 +1486,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
> > > > > wa_bb_fn[1] = NULL;
> > > > > break;
> > > > > default:
> > > > > - MISSING_CASE(INTEL_GEN(engine->i915));
> > > > > + MISSING_CASE(GRAPHICS_VER(engine->i915));
> > > > > return;
> > > > > }
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > > > > index b14138fd505c..17848807f111 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > > > > @@ -344,11 +344,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> > > > > table->size = ARRAY_SIZE(dg1_mocs_table);
> > > > > table->table = dg1_mocs_table;
> > > > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> > > > > - } else if (INTEL_GEN(i915) >= 12) {
> > > > > + } else if (GRAPHICS_VER(i915) >= 12) {
> > > > > table->size = ARRAY_SIZE(tgl_mocs_table);
> > > > > table->table = tgl_mocs_table;
> > > > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> > > > > - } else if (IS_GEN(i915, 11)) {
> > > > > + } else if (GRAPHICS_VER(i915) == 11) {
> > > > > table->size = ARRAY_SIZE(icl_mocs_table);
> > > > > table->table = icl_mocs_table;
> > > > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> > > > > @@ -361,7 +361,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> > > > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> > > > > table->table = broxton_mocs_table;
> > > > > } else {
> > > > > - drm_WARN_ONCE(&i915->drm, INTEL_GEN(i915) >= 9,
> > > > > + drm_WARN_ONCE(&i915->drm, GRAPHICS_VER(i915) >= 9,
> > > > > "Platform that should have a MOCS table does not.\n");
> > > > > return 0;
> > > > > }
> > > > > @@ -370,7 +370,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> > > > > return 0;
> > > > >
> > > > > /* WaDisableSkipCaching:skl,bxt,kbl,glk */
> > > > > - if (IS_GEN(i915, 9)) {
> > > > > + if (GRAPHICS_VER(i915) == 9) {
> > > > > int i;
> > > > >
> > > > > for (i = 0; i < table->size; i++)
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> > > > > index 4e3d80c2295c..3891c078906e 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> > > > > @@ -146,9 +146,9 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
> > > > >
> > > > > gtt_write_workarounds(gt);
> > > > >
> > > > > - if (IS_GEN(i915, 6))
> > > > > + if (GRAPHICS_VER(i915) == 6)
> > > > > gen6_ppgtt_enable(gt);
> > > > > - else if (IS_GEN(i915, 7))
> > > > > + else if (GRAPHICS_VER(i915) == 7)
> > > > > gen7_ppgtt_enable(gt);
> > > > >
> > > > > return 0;
> > > > > @@ -157,7 +157,7 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
> > > > > static struct i915_ppgtt *
> > > > > __ppgtt_create(struct intel_gt *gt)
> > > > > {
> > > > > - if (INTEL_GEN(gt->i915) < 8)
> > > > > + if (GRAPHICS_VER(gt->i915) < 8)
> > > > > return gen6_ppgtt_create(gt);
> > > > > else
> > > > > return gen8_ppgtt_create(gt);
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> > > > > index 3b7e62debe7e..259d7eb4e165 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> > > > > @@ -109,7 +109,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
> > > > > GEN9_MEDIA_PG_ENABLE |
> > > > > GEN11_MEDIA_SAMPLER_PG_ENABLE;
> > > > >
> > > > > - if (INTEL_GEN(gt->i915) >= 12) {
> > > > > + if (GRAPHICS_VER(gt->i915) >= 12) {
> > > > > for (i = 0; i < I915_MAX_VCS; i++)
> > > > > if (HAS_ENGINE(gt, _VCS(i)))
> > > > > pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
> > > > > @@ -126,7 +126,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
> > > > > enum intel_engine_id id;
> > > > >
> > > > > /* 2b: Program RC6 thresholds.*/
> > > > > - if (INTEL_GEN(rc6_to_i915(rc6)) >= 10) {
> > > > > + if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 10) {
> > > > > set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> > > > > set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
> > > > > } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
> > > > > @@ -249,9 +249,9 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
> > > > > rc6vids = 0;
> > > > > ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
> > > > > &rc6vids, NULL);
> > > > > - if (IS_GEN(i915, 6) && ret) {
> > > > > + if (GRAPHICS_VER(i915) == 6 && ret) {
> > > > > drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
> > > > > - } else if (IS_GEN(i915, 6) &&
> > > > > + } else if (GRAPHICS_VER(i915) == 6 &&
> > > > > (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
> > > > > drm_dbg(&i915->drm,
> > > > > "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
> > > > > @@ -515,7 +515,7 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
> > > > > struct intel_uncore *uncore = rc6_to_uncore(rc6);
> > > > >
> > > > > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> > > > > - if (INTEL_GEN(i915) >= 9)
> > > > > + if (GRAPHICS_VER(i915) >= 9)
> > > > > set(uncore, GEN9_PG_ENABLE, 0);
> > > > > set(uncore, GEN6_RC_CONTROL, 0);
> > > > > set(uncore, GEN6_RC_STATE, 0);
> > > > > @@ -575,13 +575,13 @@ void intel_rc6_enable(struct intel_rc6 *rc6)
> > > > > chv_rc6_enable(rc6);
> > > > > else if (IS_VALLEYVIEW(i915))
> > > > > vlv_rc6_enable(rc6);
> > > > > - else if (INTEL_GEN(i915) >= 11)
> > > > > + else if (GRAPHICS_VER(i915) >= 11)
> > > > > gen11_rc6_enable(rc6);
> > > > > - else if (INTEL_GEN(i915) >= 9)
> > > > > + else if (GRAPHICS_VER(i915) >= 9)
> > > > > gen9_rc6_enable(rc6);
> > > > > else if (IS_BROADWELL(i915))
> > > > > gen8_rc6_enable(rc6);
> > > > > - else if (INTEL_GEN(i915) >= 6)
> > > > > + else if (GRAPHICS_VER(i915) >= 6)
> > > > > gen6_rc6_enable(rc6);
> > > > >
> > > > > rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE;
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
> > > > > index b03e197b1d99..b575cd6e0b7a 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
> > > > > @@ -15,7 +15,7 @@ render_state_get_rodata(const struct intel_engine_cs *engine)
> > > > > if (engine->class != RENDER_CLASS)
> > > > > return NULL;
> > > > >
> > > > > - switch (INTEL_GEN(engine->i915)) {
> > > > > + switch (GRAPHICS_VER(engine->i915)) {
> > > > > case 6:
> > > > > return &gen6_null_state;
> > > > > case 7:
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> > > > > index d5094be6d90f..27315d7f8935 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > > > > @@ -565,7 +565,7 @@ static int gen8_reset_engines(struct intel_gt *gt,
> > > > > */
> > > > > }
> > > > >
> > > > > - if (INTEL_GEN(gt->i915) >= 11)
> > > > > + if (GRAPHICS_VER(gt->i915) >= 11)
> > > > > ret = gen11_reset_engines(gt, engine_mask, retry);
> > > > > else
> > > > > ret = gen6_reset_engines(gt, engine_mask, retry);
> > > > > @@ -594,17 +594,17 @@ static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
> > > > >
> > > > > if (is_mock_gt(gt))
> > > > > return mock_reset;
> > > > > - else if (INTEL_GEN(i915) >= 8)
> > > > > + else if (GRAPHICS_VER(i915) >= 8)
> > > > > return gen8_reset_engines;
> > > > > - else if (INTEL_GEN(i915) >= 6)
> > > > > + else if (GRAPHICS_VER(i915) >= 6)
> > > > > return gen6_reset_engines;
> > > > > - else if (INTEL_GEN(i915) >= 5)
> > > > > + else if (GRAPHICS_VER(i915) >= 5)
> > > > > return ilk_do_reset;
> > > > > else if (IS_G4X(i915))
> > > > > return g4x_do_reset;
> > > > > else if (IS_G33(i915) || IS_PINEVIEW(i915))
> > > > > return g33_do_reset;
> > > > > - else if (INTEL_GEN(i915) >= 3)
> > > > > + else if (GRAPHICS_VER(i915) >= 3)
> > > > > return i915_do_reset;
> > > > > else
> > > > > return NULL;
> > > > > @@ -656,7 +656,7 @@ bool intel_has_reset_engine(const struct intel_gt *gt)
> > > > > int intel_reset_guc(struct intel_gt *gt)
> > > > > {
> > > > > u32 guc_domain =
> > > > > - INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
> > > > > + GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
> > > > > int ret;
> > > > >
> > > > > GEM_BUG_ON(!HAS_GT_UC(gt->i915));
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > > > > index 2b6dffcc2262..0c423f096e2b 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> > > > > @@ -29,7 +29,7 @@ static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
> > > > > * lost interrupts following a reset.
> > > > > */
> > > > > if (engine->class == RENDER_CLASS) {
> > > > > - if (INTEL_GEN(engine->i915) >= 6)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 6)
> > > > > mask &= ~BIT(0);
> > > > > else
> > > > > mask &= ~I915_USER_INTERRUPT;
> > > > > @@ -43,7 +43,7 @@ static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
> > > > > u32 addr;
> > > > >
> > > > > addr = lower_32_bits(phys);
> > > > > - if (INTEL_GEN(engine->i915) >= 4)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 4)
> > > > > addr |= (phys >> 28) & 0xf0;
> > > > >
> > > > > intel_uncore_write(engine->uncore, HWS_PGA, addr);
> > > > > @@ -71,7 +71,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
> > > > > * The ring status page addresses are no longer next to the rest of
> > > > > * the ring registers as of gen7.
> > > > > */
> > > > > - if (IS_GEN(engine->i915, 7)) {
> > > > > + if (GRAPHICS_VER(engine->i915) == 7) {
> > > > > switch (engine->id) {
> > > > > /*
> > > > > * No more rings exist on Gen7. Default case is only to shut up
> > > > > @@ -93,7 +93,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
> > > > > hwsp = VEBOX_HWS_PGA_GEN7;
> > > > > break;
> > > > > }
> > > > > - } else if (IS_GEN(engine->i915, 6)) {
> > > > > + } else if (GRAPHICS_VER(engine->i915) == 6) {
> > > > > hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
> > > > > } else {
> > > > > hwsp = RING_HWS_PGA(engine->mmio_base);
> > > > > @@ -105,7 +105,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
> > > > >
> > > > > static void flush_cs_tlb(struct intel_engine_cs *engine)
> > > > > {
> > > > > - if (!IS_GEN_RANGE(engine->i915, 6, 7))
> > > > > + if (!IS_GRAPHICS_VER(engine->i915, 6, 7))
> > > > > return;
> > > > >
> > > > > /* ring should be idle before issuing a sync flush*/
> > > > > @@ -153,7 +153,7 @@ static void set_pp_dir(struct intel_engine_cs *engine)
> > > > > ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
> > > > > ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm));
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) >= 7) {
> > > > > + if (GRAPHICS_VER(engine->i915) >= 7) {
> > > > > ENGINE_WRITE_FW(engine,
> > > > > RING_MODE_GEN7,
> > > > > _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> > > > > @@ -229,7 +229,7 @@ static int xcs_resume(struct intel_engine_cs *engine)
> > > > > 5000, 0, NULL))
> > > > > goto err;
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) > 2)
> > > > > + if (GRAPHICS_VER(engine->i915) > 2)
> > > > > ENGINE_WRITE_FW(engine,
> > > > > RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
> > > > >
> > > > > @@ -646,9 +646,9 @@ static int mi_set_context(struct i915_request *rq,
> > > > > u32 *cs;
> > > > >
> > > > > len = 4;
> > > > > - if (IS_GEN(i915, 7))
> > > > > + if (GRAPHICS_VER(i915) == 7)
> > > > > len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
> > > > > - else if (IS_GEN(i915, 5))
> > > > > + else if (GRAPHICS_VER(i915) == 5)
> > > > > len += 2;
> > > > > if (flags & MI_FORCE_RESTORE) {
> > > > > GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
> > > > > @@ -662,7 +662,7 @@ static int mi_set_context(struct i915_request *rq,
> > > > > return PTR_ERR(cs);
> > > > >
> > > > > /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
> > > > > - if (IS_GEN(i915, 7)) {
> > > > > + if (GRAPHICS_VER(i915) == 7) {
> > > > > *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> > > > > if (num_engines) {
> > > > > struct intel_engine_cs *signaller;
> > > > > @@ -678,7 +678,7 @@ static int mi_set_context(struct i915_request *rq,
> > > > > GEN6_PSMI_SLEEP_MSG_DISABLE);
> > > > > }
> > > > > }
> > > > > - } else if (IS_GEN(i915, 5)) {
> > > > > + } else if (GRAPHICS_VER(i915) == 5) {
> > > > > /*
> > > > > * This w/a is only listed for pre-production ilk a/b steppings,
> > > > > * but is also mentioned for programming the powerctx. To be
> > > > > @@ -716,7 +716,7 @@ static int mi_set_context(struct i915_request *rq,
> > > > > */
> > > > > *cs++ = MI_NOOP;
> > > > >
> > > > > - if (IS_GEN(i915, 7)) {
> > > > > + if (GRAPHICS_VER(i915) == 7) {
> > > > > if (num_engines) {
> > > > > struct intel_engine_cs *signaller;
> > > > > i915_reg_t last_reg = {}; /* keep gcc quiet */
> > > > > @@ -740,7 +740,7 @@ static int mi_set_context(struct i915_request *rq,
> > > > > *cs++ = MI_NOOP;
> > > > > }
> > > > > *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
> > > > > - } else if (IS_GEN(i915, 5)) {
> > > > > + } else if (GRAPHICS_VER(i915) == 5) {
> > > > > *cs++ = MI_SUSPEND_FLUSH;
> > > > > }
> > > > >
> > > > > @@ -1001,7 +1001,7 @@ static void ring_release(struct intel_engine_cs *engine)
> > > > > {
> > > > > struct drm_i915_private *dev_priv = engine->i915;
> > > > >
> > > > > - drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) > 2 &&
> > > > > + drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) > 2 &&
> > > > > (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
> > > > >
> > > > > intel_engine_cleanup_common(engine);
> > > > > @@ -1029,13 +1029,13 @@ static void setup_irq(struct intel_engine_cs *engine)
> > > > >
> > > > > intel_engine_set_irq_handler(engine, irq_handler);
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 6) {
> > > > > + if (GRAPHICS_VER(i915) >= 6) {
> > > > > engine->irq_enable = gen6_irq_enable;
> > > > > engine->irq_disable = gen6_irq_disable;
> > > > > - } else if (INTEL_GEN(i915) >= 5) {
> > > > > + } else if (GRAPHICS_VER(i915) >= 5) {
> > > > > engine->irq_enable = gen5_irq_enable;
> > > > > engine->irq_disable = gen5_irq_disable;
> > > > > - } else if (INTEL_GEN(i915) >= 3) {
> > > > > + } else if (GRAPHICS_VER(i915) >= 3) {
> > > > > engine->irq_enable = gen3_irq_enable;
> > > > > engine->irq_disable = gen3_irq_disable;
> > > > > } else {
> > > > > @@ -1049,7 +1049,7 @@ static void setup_common(struct intel_engine_cs *engine)
> > > > > struct drm_i915_private *i915 = engine->i915;
> > > > >
> > > > > /* gen8+ are only supported with execlists */
> > > > > - GEM_BUG_ON(INTEL_GEN(i915) >= 8);
> > > > > + GEM_BUG_ON(GRAPHICS_VER(i915) >= 8);
> > > > >
> > > > > setup_irq(engine);
> > > > >
> > > > > @@ -1070,14 +1070,14 @@ static void setup_common(struct intel_engine_cs *engine)
> > > > > * engine->emit_init_breadcrumb().
> > > > > */
> > > > > engine->emit_fini_breadcrumb = gen3_emit_breadcrumb;
> > > > > - if (IS_GEN(i915, 5))
> > > > > + if (GRAPHICS_VER(i915) == 5)
> > > > > engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
> > > > >
> > > > > engine->set_default_submission = i9xx_set_default_submission;
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 6)
> > > > > + if (GRAPHICS_VER(i915) >= 6)
> > > > > engine->emit_bb_start = gen6_emit_bb_start;
> > > > > - else if (INTEL_GEN(i915) >= 4)
> > > > > + else if (GRAPHICS_VER(i915) >= 4)
> > > > > engine->emit_bb_start = gen4_emit_bb_start;
> > > > > else if (IS_I830(i915) || IS_I845G(i915))
> > > > > engine->emit_bb_start = i830_emit_bb_start;
> > > > > @@ -1094,16 +1094,16 @@ static void setup_rcs(struct intel_engine_cs *engine)
> > > > >
> > > > > engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 7) {
> > > > > + if (GRAPHICS_VER(i915) >= 7) {
> > > > > engine->emit_flush = gen7_emit_flush_rcs;
> > > > > engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs;
> > > > > - } else if (IS_GEN(i915, 6)) {
> > > > > + } else if (GRAPHICS_VER(i915) == 6) {
> > > > > engine->emit_flush = gen6_emit_flush_rcs;
> > > > > engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs;
> > > > > - } else if (IS_GEN(i915, 5)) {
> > > > > + } else if (GRAPHICS_VER(i915) == 5) {
> > > > > engine->emit_flush = gen4_emit_flush_rcs;
> > > > > } else {
> > > > > - if (INTEL_GEN(i915) < 4)
> > > > > + if (GRAPHICS_VER(i915) < 4)
> > > > > engine->emit_flush = gen2_emit_flush;
> > > > > else
> > > > > engine->emit_flush = gen4_emit_flush_rcs;
> > > > > @@ -1118,20 +1118,20 @@ static void setup_vcs(struct intel_engine_cs *engine)
> > > > > {
> > > > > struct drm_i915_private *i915 = engine->i915;
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 6) {
> > > > > + if (GRAPHICS_VER(i915) >= 6) {
> > > > > /* gen6 bsd needs a special wa for tail updates */
> > > > > - if (IS_GEN(i915, 6))
> > > > > + if (GRAPHICS_VER(i915) == 6)
> > > > > engine->set_default_submission = gen6_bsd_set_default_submission;
> > > > > engine->emit_flush = gen6_emit_flush_vcs;
> > > > > engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
> > > > >
> > > > > - if (IS_GEN(i915, 6))
> > > > > + if (GRAPHICS_VER(i915) == 6)
> > > > > engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
> > > > > else
> > > > > engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
> > > > > } else {
> > > > > engine->emit_flush = gen4_emit_flush_vcs;
> > > > > - if (IS_GEN(i915, 5))
> > > > > + if (GRAPHICS_VER(i915) == 5)
> > > > > engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
> > > > > else
> > > > > engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
> > > > > @@ -1145,7 +1145,7 @@ static void setup_bcs(struct intel_engine_cs *engine)
> > > > > engine->emit_flush = gen6_emit_flush_xcs;
> > > > > engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
> > > > >
> > > > > - if (IS_GEN(i915, 6))
> > > > > + if (GRAPHICS_VER(i915) == 6)
> > > > > engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
> > > > > else
> > > > > engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
> > > > > @@ -1155,7 +1155,7 @@ static void setup_vecs(struct intel_engine_cs *engine)
> > > > > {
> > > > > struct drm_i915_private *i915 = engine->i915;
> > > > >
> > > > > - GEM_BUG_ON(INTEL_GEN(i915) < 7);
> > > > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 7);
> > > > >
> > > > > engine->emit_flush = gen6_emit_flush_xcs;
> > > > > engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
> > > > > @@ -1203,7 +1203,7 @@ static struct i915_vma *gen7_ctx_vma(struct intel_engine_cs *engine)
> > > > > struct i915_vma *vma;
> > > > > int size, err;
> > > > >
> > > > > - if (!IS_GEN(engine->i915, 7) || engine->class != RENDER_CLASS)
> > > > > + if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS)
> > > > > return 0;
> > > > >
> > > > > err = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */);
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> > > > > index 97cab1b99871..06e9a8ed4e03 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> > > > > @@ -196,7 +196,7 @@ static void rps_reset_interrupts(struct intel_rps *rps)
> > > > > struct intel_gt *gt = rps_to_gt(rps);
> > > > >
> > > > > spin_lock_irq(>->irq_lock);
> > > > > - if (INTEL_GEN(gt->i915) >= 11)
> > > > > + if (GRAPHICS_VER(gt->i915) >= 11)
> > > > > gen11_rps_reset_interrupts(rps);
> > > > > else
> > > > > gen6_rps_reset_interrupts(rps);
> > > > > @@ -630,7 +630,7 @@ static u32 rps_limits(struct intel_rps *rps, u8 val)
> > > > > * frequency, if the down threshold expires in that window we will not
> > > > > * receive a down interrupt.
> > > > > */
> > > > > - if (INTEL_GEN(rps_to_i915(rps)) >= 9) {
> > > > > + if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) {
> > > > > limits = rps->max_freq_softlimit << 23;
> > > > > if (val <= rps->min_freq_softlimit)
> > > > > limits |= rps->min_freq_softlimit << 14;
> > > > > @@ -697,7 +697,7 @@ static void rps_set_power(struct intel_rps *rps, int new_power)
> > > > > intel_gt_ns_to_pm_interval(gt, ei_down * threshold_down * 10));
> > > > >
> > > > > set(uncore, GEN6_RP_CONTROL,
> > > > > - (INTEL_GEN(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
> > > > > + (GRAPHICS_VER(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
> > > > > GEN6_RP_MEDIA_HW_NORMAL_MODE |
> > > > > GEN6_RP_MEDIA_IS_GFX |
> > > > > GEN6_RP_ENABLE |
> > > > > @@ -771,7 +771,7 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val)
> > > > > struct drm_i915_private *i915 = rps_to_i915(rps);
> > > > > u32 swreq;
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 9)
> > > > > + if (GRAPHICS_VER(i915) >= 9)
> > > > > swreq = GEN9_FREQUENCY(val);
> > > > > else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> > > > > swreq = HSW_FREQUENCY(val);
> > > > > @@ -812,14 +812,14 @@ static int rps_set(struct intel_rps *rps, u8 val, bool update)
> > > > >
> > > > > if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > > > > err = vlv_rps_set(rps, val);
> > > > > - else if (INTEL_GEN(i915) >= 6)
> > > > > + else if (GRAPHICS_VER(i915) >= 6)
> > > > > err = gen6_rps_set(rps, val);
> > > > > else
> > > > > err = gen5_rps_set(rps, val);
> > > > > if (err)
> > > > > return err;
> > > > >
> > > > > - if (update && INTEL_GEN(i915) >= 6)
> > > > > + if (update && GRAPHICS_VER(i915) >= 6)
> > > > > gen6_rps_set_thresholds(rps, val);
> > > > > rps->last_freq = val;
> > > > >
> > > > > @@ -853,7 +853,7 @@ void intel_rps_unpark(struct intel_rps *rps)
> > > > > if (intel_rps_uses_timer(rps))
> > > > > rps_start_timer(rps);
> > > > >
> > > > > - if (IS_GEN(rps_to_i915(rps), 5))
> > > > > + if (GRAPHICS_VER(rps_to_i915(rps)) == 5)
> > > > > gen5_rps_update(rps);
> > > > > }
> > > > >
> > > > > @@ -999,7 +999,7 @@ static void gen6_rps_init(struct intel_rps *rps)
> > > > >
> > > > > rps->efficient_freq = rps->rp1_freq;
> > > > > if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
> > > > > - IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
> > > > > + IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
> > > > > u32 ddcc_status = 0;
> > > > >
> > > > > if (sandybridge_pcode_read(i915,
> > > > > @@ -1012,7 +1012,7 @@ static void gen6_rps_init(struct intel_rps *rps)
> > > > > rps->max_freq);
> > > > > }
> > > > >
> > > > > - if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
> > > > > + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
> > > > > /* Store the frequency values in 16.66 MHZ units, which is
> > > > > * the natural hardware unit for SKL
> > > > > */
> > > > > @@ -1048,7 +1048,7 @@ static bool gen9_rps_enable(struct intel_rps *rps)
> > > > > struct intel_uncore *uncore = gt->uncore;
> > > > >
> > > > > /* Program defaults and thresholds for RPS */
> > > > > - if (IS_GEN(gt->i915, 9))
> > > > > + if (GRAPHICS_VER(gt->i915) == 9)
> > > > > intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ,
> > > > > GEN9_FREQUENCY(rps->rp1_freq));
> > > > >
> > > > > @@ -1365,16 +1365,16 @@ void intel_rps_enable(struct intel_rps *rps)
> > > > > enabled = chv_rps_enable(rps);
> > > > > else if (IS_VALLEYVIEW(i915))
> > > > > enabled = vlv_rps_enable(rps);
> > > > > - else if (INTEL_GEN(i915) >= 9)
> > > > > + else if (GRAPHICS_VER(i915) >= 9)
> > > > > enabled = gen9_rps_enable(rps);
> > > > > - else if (INTEL_GEN(i915) >= 8)
> > > > > + else if (GRAPHICS_VER(i915) >= 8)
> > > > > enabled = gen8_rps_enable(rps);
> > > > > - else if (INTEL_GEN(i915) >= 6)
> > > > > + else if (GRAPHICS_VER(i915) >= 6)
> > > > > enabled = gen6_rps_enable(rps);
> > > > > else if (IS_IRONLAKE_M(i915))
> > > > > enabled = gen5_rps_enable(rps);
> > > > > else
> > > > > - MISSING_CASE(INTEL_GEN(i915));
> > > > > + MISSING_CASE(GRAPHICS_VER(i915));
> > > > > intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> > > > > if (!enabled)
> > > > > return;
> > > > > @@ -1393,7 +1393,7 @@ void intel_rps_enable(struct intel_rps *rps)
> > > > >
> > > > > if (has_busy_stats(rps))
> > > > > intel_rps_set_timer(rps);
> > > > > - else if (INTEL_GEN(i915) >= 6)
> > > > > + else if (GRAPHICS_VER(i915) >= 6)
> > > > > intel_rps_set_interrupts(rps);
> > > > > else
> > > > > /* Ironlake currently uses intel_ips.ko */ {}
> > > > > @@ -1414,7 +1414,7 @@ void intel_rps_disable(struct intel_rps *rps)
> > > > > intel_rps_clear_interrupts(rps);
> > > > > intel_rps_clear_timer(rps);
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 6)
> > > > > + if (GRAPHICS_VER(i915) >= 6)
> > > > > gen6_rps_disable(rps);
> > > > > else if (IS_IRONLAKE_M(i915))
> > > > > gen5_rps_disable(rps);
> > > > > @@ -1453,14 +1453,14 @@ int intel_gpu_freq(struct intel_rps *rps, int val)
> > > > > {
> > > > > struct drm_i915_private *i915 = rps_to_i915(rps);
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 9)
> > > > > + if (GRAPHICS_VER(i915) >= 9)
> > > > > return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
> > > > > GEN9_FREQ_SCALER);
> > > > > else if (IS_CHERRYVIEW(i915))
> > > > > return chv_gpu_freq(rps, val);
> > > > > else if (IS_VALLEYVIEW(i915))
> > > > > return byt_gpu_freq(rps, val);
> > > > > - else if (INTEL_GEN(i915) >= 6)
> > > > > + else if (GRAPHICS_VER(i915) >= 6)
> > > > > return val * GT_FREQUENCY_MULTIPLIER;
> > > > > else
> > > > > return val;
> > > > > @@ -1470,14 +1470,14 @@ int intel_freq_opcode(struct intel_rps *rps, int val)
> > > > > {
> > > > > struct drm_i915_private *i915 = rps_to_i915(rps);
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 9)
> > > > > + if (GRAPHICS_VER(i915) >= 9)
> > > > > return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
> > > > > GT_FREQUENCY_MULTIPLIER);
> > > > > else if (IS_CHERRYVIEW(i915))
> > > > > return chv_freq_opcode(rps, val);
> > > > > else if (IS_VALLEYVIEW(i915))
> > > > > return byt_freq_opcode(rps, val);
> > > > > - else if (INTEL_GEN(i915) >= 6)
> > > > > + else if (GRAPHICS_VER(i915) >= 6)
> > > > > return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
> > > > > else
> > > > > return val;
> > > > > @@ -1770,7 +1770,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
> > > > > spin_unlock(>->irq_lock);
> > > > > }
> > > > >
> > > > > - if (INTEL_GEN(gt->i915) >= 8)
> > > > > + if (GRAPHICS_VER(gt->i915) >= 8)
> > > > > return;
> > > > >
> > > > > if (pm_iir & PM_VEBOX_USER_INTERRUPT)
> > > > > @@ -1833,7 +1833,7 @@ void intel_rps_init(struct intel_rps *rps)
> > > > > chv_rps_init(rps);
> > > > > else if (IS_VALLEYVIEW(i915))
> > > > > vlv_rps_init(rps);
> > > > > - else if (INTEL_GEN(i915) >= 6)
> > > > > + else if (GRAPHICS_VER(i915) >= 6)
> > > > > gen6_rps_init(rps);
> > > > > else if (IS_IRONLAKE_M(i915))
> > > > > gen5_rps_init(rps);
> > > > > @@ -1843,7 +1843,7 @@ void intel_rps_init(struct intel_rps *rps)
> > > > > rps->min_freq_softlimit = rps->min_freq;
> > > > >
> > > > > /* After setting max-softlimit, find the overclock max freq */
> > > > > - if (IS_GEN(i915, 6) || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
> > > > > + if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
> > > > > u32 params = 0;
> > > > >
> > > > > sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS,
> > > > > @@ -1872,16 +1872,16 @@ void intel_rps_init(struct intel_rps *rps)
> > > > > *
> > > > > * TODO: verify if this can be reproduced on VLV,CHV.
> > > > > */
> > > > > - if (INTEL_GEN(i915) <= 7)
> > > > > + if (GRAPHICS_VER(i915) <= 7)
> > > > > rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 8 && INTEL_GEN(i915) < 11)
> > > > > + if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) < 11)
> > > > > rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
> > > > > }
> > > > >
> > > > > void intel_rps_sanitize(struct intel_rps *rps)
> > > > > {
> > > > > - if (INTEL_GEN(rps_to_i915(rps)) >= 6)
> > > > > + if (GRAPHICS_VER(rps_to_i915(rps)) >= 6)
> > > > > rps_disable_interrupts(rps);
> > > > > }
> > > > >
> > > > > @@ -1892,11 +1892,11 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
> > > > >
> > > > > if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> > > > > cagf = (rpstat >> 8) & 0xff;
> > > > > - else if (INTEL_GEN(i915) >= 9)
> > > > > + else if (GRAPHICS_VER(i915) >= 9)
> > > > > cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> > > > > else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> > > > > cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
> > > > > - else if (INTEL_GEN(i915) >= 6)
> > > > > + else if (GRAPHICS_VER(i915) >= 6)
> > > > > cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
> > > > > else
> > > > > cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >>
> > > > > @@ -1915,7 +1915,7 @@ static u32 read_cagf(struct intel_rps *rps)
> > > > > vlv_punit_get(i915);
> > > > > freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
> > > > > vlv_punit_put(i915);
> > > > > - } else if (INTEL_GEN(i915) >= 6) {
> > > > > + } else if (GRAPHICS_VER(i915) >= 6) {
> > > > > freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
> > > > > } else {
> > > > > freq = intel_uncore_read(uncore, MEMSTAT_ILK);
> > > > > @@ -1968,7 +1968,7 @@ void intel_rps_driver_register(struct intel_rps *rps)
> > > > > * We only register the i915 ips part with intel-ips once everything is
> > > > > * set up, to avoid intel-ips sneaking in and reading bogus values.
> > > > > */
> > > > > - if (IS_GEN(gt->i915, 5)) {
> > > > > + if (GRAPHICS_VER(gt->i915) == 5) {
> > > > > GEM_BUG_ON(ips_mchdev);
> > > > > rcu_assign_pointer(ips_mchdev, gt->i915);
> > > > > ips_ping_for_i915_load();
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > > > > index 0d9f74aec8fe..367fd44b81c8 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > > > > @@ -590,13 +590,13 @@ void intel_sseu_info_init(struct intel_gt *gt)
> > > > > cherryview_sseu_info_init(gt);
> > > > > else if (IS_BROADWELL(i915))
> > > > > bdw_sseu_info_init(gt);
> > > > > - else if (IS_GEN(i915, 9))
> > > > > + else if (GRAPHICS_VER(i915) == 9)
> > > > > gen9_sseu_info_init(gt);
> > > > > - else if (IS_GEN(i915, 10))
> > > > > + else if (GRAPHICS_VER(i915) == 10)
> > > > > gen10_sseu_info_init(gt);
> > > > > - else if (IS_GEN(i915, 11))
> > > > > + else if (GRAPHICS_VER(i915) == 11)
> > > > > gen11_sseu_info_init(gt);
> > > > > - else if (INTEL_GEN(i915) >= 12)
> > > > > + else if (GRAPHICS_VER(i915) >= 12)
> > > > > gen12_sseu_info_init(gt);
> > > > > }
> > > > >
> > > > > @@ -613,7 +613,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> > > > > * No explicit RPCS request is needed to ensure full
> > > > > * slice/subslice/EU enablement prior to Gen9.
> > > > > */
> > > > > - if (INTEL_GEN(i915) < 9)
> > > > > + if (GRAPHICS_VER(i915) < 9)
> > > > > return 0;
> > > > >
> > > > > /*
> > > > > @@ -651,7 +651,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> > > > > * subslices are enabled, or a count between one and four on the first
> > > > > * slice.
> > > > > */
> > > > > - if (IS_GEN(i915, 11) &&
> > > > > + if (GRAPHICS_VER(i915) == 11 &&
> > > > > slices == 1 &&
> > > > > subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
> > > > > GEM_BUG_ON(subslices & 1);
> > > > > @@ -669,7 +669,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
> > > > > if (sseu->has_slice_pg) {
> > > > > u32 mask, val = slices;
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 11) {
> > > > > + if (GRAPHICS_VER(i915) >= 11) {
> > > > > mask = GEN11_RPCS_S_CNT_MASK;
> > > > > val <<= GEN11_RPCS_S_CNT_SHIFT;
> > > > > } else {
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > > index 62cb9ee5bfc3..b62d1e31a645 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > > @@ -699,9 +699,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> > > > >
> > > > > if (IS_DG1(i915))
> > > > > dg1_ctx_workarounds_init(engine, wal);
> > > > > - else if (IS_GEN(i915, 12))
> > > > > + else if (GRAPHICS_VER(i915) == 12)
> > > > > gen12_ctx_workarounds_init(engine, wal);
> > > > > - else if (IS_GEN(i915, 11))
> > > > > + else if (GRAPHICS_VER(i915) == 11)
> > > > > icl_ctx_workarounds_init(engine, wal);
> > > > > else if (IS_CANNONLAKE(i915))
> > > > > cnl_ctx_workarounds_init(engine, wal);
> > > > > @@ -719,14 +719,14 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> > > > > chv_ctx_workarounds_init(engine, wal);
> > > > > else if (IS_BROADWELL(i915))
> > > > > bdw_ctx_workarounds_init(engine, wal);
> > > > > - else if (IS_GEN(i915, 7))
> > > > > + else if (GRAPHICS_VER(i915) == 7)
> > > > > gen7_ctx_workarounds_init(engine, wal);
> > > > > - else if (IS_GEN(i915, 6))
> > > > > + else if (GRAPHICS_VER(i915) == 6)
> > > > > gen6_ctx_workarounds_init(engine, wal);
> > > > > - else if (INTEL_GEN(i915) < 8)
> > > > > + else if (GRAPHICS_VER(i915) < 8)
> > > > > ;
> > > > > else
> > > > > - MISSING_CASE(INTEL_GEN(i915));
> > > > > + MISSING_CASE(GRAPHICS_VER(i915));
> > > > >
> > > > > wa_init_finish(wal);
> > > > > }
> > > > > @@ -950,7 +950,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > > > > unsigned int slice, subslice;
> > > > > u32 l3_en, mcr, mcr_mask;
> > > > >
> > > > > - GEM_BUG_ON(INTEL_GEN(i915) < 10);
> > > > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 10);
> > > > >
> > > > > /*
> > > > > * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
> > > > > @@ -980,7 +980,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > > > > * of every MMIO read.
> > > > > */
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
> > > > > + if (GRAPHICS_VER(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
> > > > > u32 l3_fuse =
> > > > > intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
> > > > > GEN10_L3BANK_MASK;
> > > > > @@ -1002,7 +1002,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > > > > }
> > > > > subslice--;
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 11) {
> > > > > + if (GRAPHICS_VER(i915) >= 11) {
> > > > > mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
> > > > > mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
> > > > > } else {
> > > > > @@ -1171,9 +1171,9 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > > > > dg1_gt_workarounds_init(i915, wal);
> > > > > else if (IS_TIGERLAKE(i915))
> > > > > tgl_gt_workarounds_init(i915, wal);
> > > > > - else if (IS_GEN(i915, 12))
> > > > > + else if (GRAPHICS_VER(i915) == 12)
> > > > > gen12_gt_workarounds_init(i915, wal);
> > > > > - else if (IS_GEN(i915, 11))
> > > > > + else if (GRAPHICS_VER(i915) == 11)
> > > > > icl_gt_workarounds_init(i915, wal);
> > > > > else if (IS_CANNONLAKE(i915))
> > > > > cnl_gt_workarounds_init(i915, wal);
> > > > > @@ -1193,18 +1193,18 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> > > > > vlv_gt_workarounds_init(i915, wal);
> > > > > else if (IS_IVYBRIDGE(i915))
> > > > > ivb_gt_workarounds_init(i915, wal);
> > > > > - else if (IS_GEN(i915, 6))
> > > > > + else if (GRAPHICS_VER(i915) == 6)
> > > > > snb_gt_workarounds_init(i915, wal);
> > > > > - else if (IS_GEN(i915, 5))
> > > > > + else if (GRAPHICS_VER(i915) == 5)
> > > > > ilk_gt_workarounds_init(i915, wal);
> > > > > else if (IS_G4X(i915))
> > > > > g4x_gt_workarounds_init(i915, wal);
> > > > > - else if (IS_GEN(i915, 4))
> > > > > + else if (GRAPHICS_VER(i915) == 4)
> > > > > gen4_gt_workarounds_init(i915, wal);
> > > > > - else if (INTEL_GEN(i915) <= 8)
> > > > > + else if (GRAPHICS_VER(i915) <= 8)
> > > > > ;
> > > > > else
> > > > > - MISSING_CASE(INTEL_GEN(i915));
> > > > > + MISSING_CASE(GRAPHICS_VER(i915));
> > > > > }
> > > > >
> > > > > void intel_gt_init_workarounds(struct drm_i915_private *i915)
> > > > > @@ -1558,9 +1558,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> > > > >
> > > > > if (IS_DG1(i915))
> > > > > dg1_whitelist_build(engine);
> > > > > - else if (IS_GEN(i915, 12))
> > > > > + else if (GRAPHICS_VER(i915) == 12)
> > > > > tgl_whitelist_build(engine);
> > > > > - else if (IS_GEN(i915, 11))
> > > > > + else if (GRAPHICS_VER(i915) == 11)
> > > > > icl_whitelist_build(engine);
> > > > > else if (IS_CANNONLAKE(i915))
> > > > > cnl_whitelist_build(engine);
> > > > > @@ -1576,10 +1576,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> > > > > bxt_whitelist_build(engine);
> > > > > else if (IS_SKYLAKE(i915))
> > > > > skl_whitelist_build(engine);
> > > > > - else if (INTEL_GEN(i915) <= 8)
> > > > > + else if (GRAPHICS_VER(i915) <= 8)
> > > > > ;
> > > > > else
> > > > > - MISSING_CASE(INTEL_GEN(i915));
> > > > > + MISSING_CASE(GRAPHICS_VER(i915));
> > > > >
> > > > > wa_init_finish(w);
> > > > > }
> > > > > @@ -1695,7 +1695,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > > > ENABLE_SMALLPL);
> > > > > }
> > > > >
> > > > > - if (IS_GEN(i915, 11)) {
> > > > > + if (GRAPHICS_VER(i915) == 11) {
> > > > > /* This is not an Wa. Enable for better image quality */
> > > > > wa_masked_en(wal,
> > > > > _3D_CHICKEN3,
> > > > > @@ -1793,7 +1793,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > > > FF_DOP_CLOCK_GATE_DISABLE);
> > > > > }
> > > > >
> > > > > - if (IS_GEN_RANGE(i915, 9, 12)) {
> > > > > + if (IS_GRAPHICS_VER(i915, 9, 12)) {
> > > > > /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
> > > > > wa_masked_en(wal,
> > > > > GEN7_FF_SLICE_CS_CHICKEN1,
> > > > > @@ -1817,7 +1817,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > > > GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
> > > > > }
> > > > >
> > > > > - if (IS_GEN(i915, 9)) {
> > > > > + if (GRAPHICS_VER(i915) == 9) {
> > > > > /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
> > > > > wa_masked_en(wal,
> > > > > GEN9_CSFE_CHICKEN1_RCS,
> > > > > @@ -1921,7 +1921,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > > > GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
> > > > > }
> > > > >
> > > > > - if (IS_GEN(i915, 7)) {
> > > > > + if (GRAPHICS_VER(i915) == 7) {
> > > > > /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
> > > > > wa_masked_en(wal,
> > > > > GFX_MODE_GEN7,
> > > > > @@ -1953,7 +1953,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > > > GEN6_WIZ_HASHING_16x4);
> > > > > }
> > > > >
> > > > > - if (IS_GEN_RANGE(i915, 6, 7))
> > > > > + if (IS_GRAPHICS_VER(i915, 6, 7))
> > > > > /*
> > > > > * We need to disable the AsyncFlip performance optimisations in
> > > > > * order to use MI_WAIT_FOR_EVENT within the CS. It should
> > > > > @@ -1965,7 +1965,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > > > MI_MODE,
> > > > > ASYNC_FLIP_PERF_DISABLE);
> > > > >
> > > > > - if (IS_GEN(i915, 6)) {
> > > > > + if (GRAPHICS_VER(i915) == 6) {
> > > > > /*
> > > > > * Required for the hardware to program scanline values for
> > > > > * waiting
> > > > > @@ -2019,14 +2019,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > > > CM0_STC_EVICT_DISABLE_LRA_SNB);
> > > > > }
> > > > >
> > > > > - if (IS_GEN_RANGE(i915, 4, 6))
> > > > > + if (IS_GRAPHICS_VER(i915, 4, 6))
> > > > > /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
> > > > > wa_add(wal, MI_MODE,
> > > > > 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
> > > > > /* XXX bit doesn't stick on Broadwater */
> > > > > IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
> > > > >
> > > > > - if (IS_GEN(i915, 4))
> > > > > + if (GRAPHICS_VER(i915) == 4)
> > > > > /*
> > > > > * Disable CONSTANT_BUFFER before it is loaded from the context
> > > > > * image. For as it is loaded, it is executed and the stored
> > > > > @@ -2058,7 +2058,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > > > static void
> > > > > engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > > > {
> > > > > - if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4))
> > > > > + if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4))
> > > > > return;
> > > > >
> > > > > if (engine->class == RENDER_CLASS)
> > > > > @@ -2071,7 +2071,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
> > > > > {
> > > > > struct i915_wa_list *wal = &engine->wa_list;
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) < 4)
> > > > > + if (GRAPHICS_VER(engine->i915) < 4)
> > > > > return;
> > > > >
> > > > > wa_init_start(wal, "engine", engine->name);
> > > > > @@ -2112,9 +2112,9 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
> > > > > const struct mcr_range *mcr_ranges;
> > > > > int i;
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 12)
> > > > > + if (GRAPHICS_VER(i915) >= 12)
> > > > > mcr_ranges = mcr_ranges_gen12;
> > > > > - else if (INTEL_GEN(i915) >= 8)
> > > > > + else if (GRAPHICS_VER(i915) >= 8)
> > > > > mcr_ranges = mcr_ranges_gen8;
> > > > > else
> > > > > return false;
> > > > > @@ -2143,7 +2143,7 @@ wa_list_srm(struct i915_request *rq,
> > > > > u32 srm, *cs;
> > > > >
> > > > > srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
> > > > > - if (INTEL_GEN(i915) >= 8)
> > > > > + if (GRAPHICS_VER(i915) >= 8)
> > > > > srm++;
> > > > >
> > > > > for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> > > > > index 3453eb77c498..64abf5feabfa 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> > > > > @@ -52,7 +52,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
> > > > > return PTR_ERR(cs);
> > > > >
> > > > > cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
> > > > > - if (INTEL_GEN(rq->engine->i915) >= 8)
> > > > > + if (GRAPHICS_VER(rq->engine->i915) >= 8)
> > > > > cmd++;
> > > > > *cs++ = cmd;
> > > > > *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
> > > > > @@ -125,7 +125,7 @@ static int perf_mi_bb_start(void *arg)
> > > > > enum intel_engine_id id;
> > > > > int err = 0;
> > > > >
> > > > > - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
> > > > > + if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
> > > > > return 0;
> > > > >
> > > > > perf_begin(gt);
> > > > > @@ -249,7 +249,7 @@ static int perf_mi_noop(void *arg)
> > > > > enum intel_engine_id id;
> > > > > int err = 0;
> > > > >
> > > > > - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
> > > > > + if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
> > > > > return 0;
> > > > >
> > > > > perf_begin(gt);
> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> > > > > index 2c898622bdfb..72cca3f0da21 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
> > > > > @@ -198,7 +198,7 @@ static int live_engine_timestamps(void *arg)
> > > > > * the same CS clock.
> > > > > */
> > > > >
> > > > > - if (INTEL_GEN(gt->i915) < 8)
> > > > > + if (GRAPHICS_VER(gt->i915) < 8)
> > > > > return 0;
> > > > >
> > > > > for_each_engine(engine, gt, id) {
> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> > > > > index 1f93591a8c69..ea2203af0764 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
> > > > > @@ -3269,7 +3269,7 @@ static int live_preempt_user(void *arg)
> > > > > if (!intel_engine_has_preemption(engine))
> > > > > continue;
> > > > >
> > > > > - if (IS_GEN(gt->i915, 8) && engine->class != RENDER_CLASS)
> > > > > + if (GRAPHICS_VER(gt->i915) == 8 && engine->class != RENDER_CLASS)
> > > > > continue; /* we need per-context GPR */
> > > > >
> > > > > if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {
> > > > > @@ -4293,7 +4293,7 @@ static int live_virtual_preserved(void *arg)
> > > > > return 0;
> > > > >
> > > > > /* As we use CS_GPR we cannot run before they existed on all engines. */
> > > > > - if (INTEL_GEN(gt->i915) < 9)
> > > > > + if (GRAPHICS_VER(gt->i915) < 9)
> > > > > return 0;
> > > > >
> > > > > for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> > > > > index c0845bf72dd3..b9441217ca3d 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> > > > > @@ -74,10 +74,10 @@ static int live_gt_clocks(void *arg)
> > > > > return 0;
> > > > > }
> > > > >
> > > > > - if (INTEL_GEN(gt->i915) < 4) /* Any CS_TIMESTAMP? */
> > > > > + if (GRAPHICS_VER(gt->i915) < 4) /* Any CS_TIMESTAMP? */
> > > > > return 0;
> > > > >
> > > > > - if (IS_GEN(gt->i915, 5))
> > > > > + if (GRAPHICS_VER(gt->i915) == 5)
> > > > > /*
> > > > > * XXX CS_TIMESTAMP low dword is dysfunctional?
> > > > > *
> > > > > @@ -86,7 +86,7 @@ static int live_gt_clocks(void *arg)
> > > > > */
> > > > > return 0;
> > > > >
> > > > > - if (IS_GEN(gt->i915, 4))
> > > > > + if (GRAPHICS_VER(gt->i915) == 4)
> > > > > /*
> > > > > * XXX CS_TIMESTAMP appears gibberish
> > > > > *
> > > > > @@ -105,7 +105,7 @@ static int live_gt_clocks(void *arg)
> > > > > u64 time;
> > > > > u64 dt;
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) < 7 && engine->id != RCS0)
> > > > > + if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0)
> > > > > continue;
> > > > >
> > > > > measure_clocks(engine, &cycles, &dt);
> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> > > > > index 5b63d4df8c93..853246fad05f 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> > > > > @@ -180,7 +180,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> > > > > goto cancel_rq;
> > > > >
> > > > > batch = h->batch;
> > > > > - if (INTEL_GEN(gt->i915) >= 8) {
> > > > > + if (GRAPHICS_VER(gt->i915) >= 8) {
> > > > > *batch++ = MI_STORE_DWORD_IMM_GEN4;
> > > > > *batch++ = lower_32_bits(hws_address(hws, rq));
> > > > > *batch++ = upper_32_bits(hws_address(hws, rq));
> > > > > @@ -194,7 +194,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> > > > > *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
> > > > > *batch++ = lower_32_bits(vma->node.start);
> > > > > *batch++ = upper_32_bits(vma->node.start);
> > > > > - } else if (INTEL_GEN(gt->i915) >= 6) {
> > > > > + } else if (GRAPHICS_VER(gt->i915) >= 6) {
> > > > > *batch++ = MI_STORE_DWORD_IMM_GEN4;
> > > > > *batch++ = 0;
> > > > > *batch++ = lower_32_bits(hws_address(hws, rq));
> > > > > @@ -207,7 +207,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> > > > > *batch++ = MI_NOOP;
> > > > > *batch++ = MI_BATCH_BUFFER_START | 1 << 8;
> > > > > *batch++ = lower_32_bits(vma->node.start);
> > > > > - } else if (INTEL_GEN(gt->i915) >= 4) {
> > > > > + } else if (GRAPHICS_VER(gt->i915) >= 4) {
> > > > > *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> > > > > *batch++ = 0;
> > > > > *batch++ = lower_32_bits(hws_address(hws, rq));
> > > > > @@ -243,7 +243,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> > > > > }
> > > > >
> > > > > flags = 0;
> > > > > - if (INTEL_GEN(gt->i915) <= 5)
> > > > > + if (GRAPHICS_VER(gt->i915) <= 5)
> > > > > flags |= I915_DISPATCH_SECURE;
> > > > >
> > > > > err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
> > > > > index 94006f117bbd..459b775f163a 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_llc.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
> > > > > @@ -44,7 +44,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
> > > > > if (found != ia_freq) {
> > > > > pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected CPU freq, found %d, expected %d\n",
> > > > > gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
> > > > > - intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
> > > > > + intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
> > > > > found, ia_freq);
> > > > > err = -EINVAL;
> > > > > break;
> > > > > @@ -54,7 +54,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
> > > > > if (found != ring_freq) {
> > > > > pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected ring freq, found %d, expected %d\n",
> > > > > gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
> > > > > - intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
> > > > > + intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
> > > > > found, ring_freq);
> > > > > err = -EINVAL;
> > > > > break;
> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > > > > index d8f6623524e8..3119016d9910 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> > > > > @@ -584,7 +584,7 @@ static int __live_lrc_gpr(struct intel_engine_cs *engine,
> > > > > int err;
> > > > > int n;
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) < 9 && engine->class != RENDER_CLASS)
> > > > > + if (GRAPHICS_VER(engine->i915) < 9 && engine->class != RENDER_CLASS)
> > > > > return 0; /* GPR only on rcs0 for gen8 */
> > > > >
> > > > > err = gpr_make_dirty(engine->kernel_context);
> > > > > @@ -1389,10 +1389,10 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
> > > > >
> > > > > static bool skip_isolation(const struct intel_engine_cs *engine)
> > > > > {
> > > > > - if (engine->class == COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) == 9)
> > > > > + if (engine->class == COPY_ENGINE_CLASS && GRAPHICS_VER(engine->i915) == 9)
> > > > > return true;
> > > > >
> > > > > - if (engine->class == RENDER_CLASS && INTEL_GEN(engine->i915) == 11)
> > > > > + if (engine->class == RENDER_CLASS && GRAPHICS_VER(engine->i915) == 11)
> > > > > return true;
> > > > >
> > > > > return false;
> > > > > @@ -1551,7 +1551,7 @@ static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)
> > > > > /* We use the already reserved extra page in context state */
> > > > > if (!a->wa_bb_page) {
> > > > > GEM_BUG_ON(b->wa_bb_page);
> > > > > - GEM_BUG_ON(INTEL_GEN(engine->i915) == 12);
> > > > > + GEM_BUG_ON(GRAPHICS_VER(engine->i915) == 12);
> > > > > goto unpin_b;
> > > > > }
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> > > > > index e55a887d11e2..b9bb0e6e97f7 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> > > > > @@ -183,7 +183,7 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
> > > > > * which only controls CPU initiated MMIO. Routing does not
> > > > > * work for CS access so we cannot verify them on this path.
> > > > > */
> > > > > - return INTEL_GEN(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
> > > > > + return GRAPHICS_VER(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
> > > > > }
> > > > >
> > > > > static int check_l3cc_table(struct intel_engine_cs *engine,
> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> > > > > index 710f825f6e5a..8c70b7e12074 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> > > > > @@ -140,7 +140,7 @@ static const u32 *__live_rc6_ctx(struct intel_context *ce)
> > > > > }
> > > > >
> > > > > cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
> > > > > - if (INTEL_GEN(rq->engine->i915) >= 8)
> > > > > + if (GRAPHICS_VER(rq->engine->i915) >= 8)
> > > > > cmd++;
> > > > >
> > > > > *cs++ = cmd;
> > > > > @@ -193,7 +193,7 @@ int live_rc6_ctx_wa(void *arg)
> > > > > int err = 0;
> > > > >
> > > > > /* A read of CTX_INFO upsets rc6. Poke the bear! */
> > > > > - if (INTEL_GEN(gt->i915) < 8)
> > > > > + if (GRAPHICS_VER(gt->i915) < 8)
> > > > > return 0;
> > > > >
> > > > > engines = randomised_engines(gt, &prng, &count);
> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
> > > > > index c12e74171b63..041954408d0f 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
> > > > > @@ -41,10 +41,10 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
> > > > > return ERR_CAST(cs);
> > > > > }
> > > > >
> > > > > - if (INTEL_GEN(engine->i915) >= 6) {
> > > > > + if (GRAPHICS_VER(engine->i915) >= 6) {
> > > > > *cs++ = MI_STORE_DWORD_IMM_GEN4;
> > > > > *cs++ = 0;
> > > > > - } else if (INTEL_GEN(engine->i915) >= 4) {
> > > > > + } else if (GRAPHICS_VER(engine->i915) >= 4) {
> > > > > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> > > > > *cs++ = 0;
> > > > > } else {
> > > > > @@ -266,7 +266,7 @@ static int live_ctx_switch_wa(void *arg)
> > > > > if (!intel_engine_can_store_dword(engine))
> > > > > continue;
> > > > >
> > > > > - if (IS_GEN_RANGE(gt->i915, 4, 5))
> > > > > + if (IS_GRAPHICS_VER(gt->i915, 4, 5))
> > > > > continue; /* MI_STORE_DWORD is privileged! */
> > > > >
> > > > > saved_wa = fetch_and_zero(&engine->wa_ctx.vma);
> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
> > > > > index 3ca1bd5793c3..7ee2513e15f9 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_rps.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
> > > > > @@ -204,7 +204,7 @@ static void show_pstate_limits(struct intel_rps *rps)
> > > > > i915_mmio_reg_offset(BXT_RP_STATE_CAP),
> > > > > intel_uncore_read(rps_to_uncore(rps),
> > > > > BXT_RP_STATE_CAP));
> > > > > - } else if (IS_GEN(i915, 9)) {
> > > > > + } else if (GRAPHICS_VER(i915) == 9) {
> > > > > pr_info("P_STATE_LIMITS[%x]: 0x%08x\n",
> > > > > i915_mmio_reg_offset(GEN9_RP_STATE_LIMITS),
> > > > > intel_uncore_read(rps_to_uncore(rps),
> > > > > @@ -222,7 +222,7 @@ int live_rps_clock_interval(void *arg)
> > > > > struct igt_spinner spin;
> > > > > int err = 0;
> > > > >
> > > > > - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
> > > > > + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
> > > > > return 0;
> > > > >
> > > > > if (igt_spinner_init(&spin, gt))
> > > > > @@ -506,7 +506,7 @@ static void show_pcu_config(struct intel_rps *rps)
> > > > >
> > > > > min_gpu_freq = rps->min_freq;
> > > > > max_gpu_freq = rps->max_freq;
> > > > > - if (INTEL_GEN(i915) >= 9) {
> > > > > + if (GRAPHICS_VER(i915) >= 9) {
> > > > > /* Convert GT frequency to 50 HZ units */
> > > > > min_gpu_freq /= GEN9_FREQ_SCALER;
> > > > > max_gpu_freq /= GEN9_FREQ_SCALER;
> > > > > @@ -614,7 +614,7 @@ int live_rps_frequency_cs(void *arg)
> > > > > if (!intel_rps_is_enabled(rps))
> > > > > return 0;
> > > > >
> > > > > - if (INTEL_GEN(gt->i915) < 8) /* for CS simplicity */
> > > > > + if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
> > > > > return 0;
> > > > >
> > > > > if (CPU_LATENCY >= 0)
> > > > > @@ -755,7 +755,7 @@ int live_rps_frequency_srm(void *arg)
> > > > > if (!intel_rps_is_enabled(rps))
> > > > > return 0;
> > > > >
> > > > > - if (INTEL_GEN(gt->i915) < 8) /* for CS simplicity */
> > > > > + if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
> > > > > return 0;
> > > > >
> > > > > if (CPU_LATENCY >= 0)
> > > > > @@ -1031,7 +1031,7 @@ int live_rps_interrupt(void *arg)
> > > > > * First, let's check whether or not we are receiving interrupts.
> > > > > */
> > > > >
> > > > > - if (!intel_rps_has_interrupts(rps) || INTEL_GEN(gt->i915) < 6)
> > > > > + if (!intel_rps_has_interrupts(rps) || GRAPHICS_VER(gt->i915) < 6)
> > > > > return 0;
> > > > >
> > > > > intel_gt_pm_get(gt);
> > > > > @@ -1136,7 +1136,7 @@ int live_rps_power(void *arg)
> > > > > * that theory.
> > > > > */
> > > > >
> > > > > - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
> > > > > + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
> > > > > return 0;
> > > > >
> > > > > if (!librapl_supported(gt->i915))
> > > > > @@ -1240,7 +1240,7 @@ int live_rps_dynamic(void *arg)
> > > > > * moving parts into dynamic reclocking based on load.
> > > > > */
> > > > >
> > > > > - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
> > > > > + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
> > > > > return 0;
> > > > >
> > > > > if (igt_spinner_init(&spin, gt))
> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> > > > > index 9adbd9d147be..64da0c91dec1 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> > > > > @@ -457,12 +457,12 @@ static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
> > > > > if (IS_ERR(cs))
> > > > > return PTR_ERR(cs);
> > > > >
> > > > > - if (INTEL_GEN(rq->engine->i915) >= 8) {
> > > > > + if (GRAPHICS_VER(rq->engine->i915) >= 8) {
> > > > > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> > > > > *cs++ = addr;
> > > > > *cs++ = 0;
> > > > > *cs++ = value;
> > > > > - } else if (INTEL_GEN(rq->engine->i915) >= 4) {
> > > > > + } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
> > > > > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> > > > > *cs++ = 0;
> > > > > *cs++ = addr;
> > > > > @@ -992,7 +992,7 @@ static int live_hwsp_read(void *arg)
> > > > > * even across multiple wraps.
> > > > > */
> > > > >
> > > > > - if (INTEL_GEN(gt->i915) < 8) /* CS convenience [SRM/LRM] */
> > > > > + if (GRAPHICS_VER(gt->i915) < 8) /* CS convenience [SRM/LRM] */
> > > > > return 0;
> > > > >
> > > > > tl = intel_timeline_create(gt);
> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> > > > > index 64937ec3f2dc..c30754daf4b1 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> > > > > @@ -145,7 +145,7 @@ read_nonprivs(struct intel_context *ce)
> > > > > goto err_req;
> > > > >
> > > > > srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
> > > > > - if (INTEL_GEN(engine->i915) >= 8)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 8)
> > > > > srm++;
> > > > >
> > > > > cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
> > > > > @@ -546,7 +546,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
> > > > >
> > > > > srm = MI_STORE_REGISTER_MEM;
> > > > > lrm = MI_LOAD_REGISTER_MEM;
> > > > > - if (INTEL_GEN(engine->i915) >= 8)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 8)
> > > > > lrm++, srm++;
> > > > >
> > > > > pr_debug("%s: Writing garbage to %x\n",
> > > > > @@ -749,7 +749,7 @@ static int live_dirty_whitelist(void *arg)
> > > > >
> > > > > /* Can the user write to the whitelisted registers? */
> > > > >
> > > > > - if (INTEL_GEN(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */
> > > > > + if (GRAPHICS_VER(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */
> > > > > return 0;
> > > > >
> > > > > for_each_engine(engine, gt, id) {
> > > > > @@ -829,7 +829,7 @@ static int read_whitelisted_registers(struct intel_context *ce,
> > > > > goto err_req;
> > > > >
> > > > > srm = MI_STORE_REGISTER_MEM;
> > > > > - if (INTEL_GEN(engine->i915) >= 8)
> > > > > + if (GRAPHICS_VER(engine->i915) >= 8)
> > > > > srm++;
> > > > >
> > > > > cs = intel_ring_begin(rq, 4 * engine->whitelist.count);
> > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > > > index adae04c47aab..84f806911370 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > > > @@ -60,7 +60,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
> > > > > enum forcewake_domains fw_domains = 0;
> > > > > unsigned int i;
> > > > >
> > > > > - if (INTEL_GEN(gt->i915) >= 11) {
> > > > > + if (GRAPHICS_VER(gt->i915) >= 11) {
> > > > > guc->send_regs.base =
> > > > > i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
> > > > > guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
> > > > > @@ -176,7 +176,7 @@ void intel_guc_init_early(struct intel_guc *guc)
> > > > >
> > > > > mutex_init(&guc->send_mutex);
> > > > > spin_lock_init(&guc->irq_lock);
> > > > > - if (INTEL_GEN(i915) >= 11) {
> > > > > + if (GRAPHICS_VER(i915) >= 11) {
> > > > > guc->notify_reg = GEN11_GUC_HOST_INTERRUPT;
> > > > > guc->interrupts.reset = gen11_reset_guc_interrupts;
> > > > > guc->interrupts.enable = gen11_enable_guc_interrupts;
> > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > > > > index 17526717368c..b32fafba2a90 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > > > > @@ -162,7 +162,7 @@ static void __guc_ads_init(struct intel_guc *guc)
> > > > > blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK] =
> > > > > gt->info.vdbox_sfc_access;
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 12 && !IS_DGFX(i915)) {
> > > > > + if (GRAPHICS_VER(i915) >= 12 && !IS_DGFX(i915)) {
> > > > > u32 distdbreg = intel_uncore_read(gt->uncore,
> > > > > GEN12_DIST_DBS_POPULATED);
> > > > > blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI] =
> > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> > > > > index 2270d6b3b272..76fe766ad1bc 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> > > > > @@ -30,7 +30,7 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
> > > > > else
> > > > > intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> > > > >
> > > > > - if (IS_GEN(uncore->i915, 9)) {
> > > > > + if (GRAPHICS_VER(uncore->i915) == 9) {
> > > > > /* DOP Clock Gating Enable for GuC clocks */
> > > > > intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
> > > > > 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
> > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > > > index 335719f17490..541f6da1ec47 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > > > @@ -438,7 +438,7 @@ static void guc_interrupts_capture(struct intel_gt *gt)
> > > > > u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
> > > > > u32 dmask = irqs << 16 | irqs;
> > > > >
> > > > > - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
> > > > > + GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
> > > > >
> > > > > /* Don't handle the ctx switch interrupt in GuC submission mode */
> > > > > intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask, 0);
> > > > > @@ -451,7 +451,7 @@ static void guc_interrupts_release(struct intel_gt *gt)
> > > > > u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
> > > > > u32 dmask = irqs << 16 | irqs;
> > > > >
> > > > > - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
> > > > > + GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
> > > > >
> > > > > /* Handle ctx switch interrupts again */
> > > > > intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0, dmask);
> > > > > @@ -648,7 +648,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
> > > > > engine->emit_flush = gen8_emit_flush_xcs;
> > > > > engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
> > > > > engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
> > > > > - if (INTEL_GEN(engine->i915) >= 12) {
> > > > > + if (GRAPHICS_VER(engine->i915) >= 12) {
> > > > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;
> > > > > engine->emit_flush = gen12_emit_flush_xcs;
> > > > > }
> > > > > @@ -670,7 +670,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
> > > > >
> > > > > static void rcs_submission_override(struct intel_engine_cs *engine)
> > > > > {
> > > > > - switch (INTEL_GEN(engine->i915)) {
> > > > > + switch (GRAPHICS_VER(engine->i915)) {
> > > > > case 12:
> > > > > engine->emit_flush = gen12_emit_flush_rcs;
> > > > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
> > > > > @@ -700,7 +700,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
> > > > > * The setup relies on several assumptions (e.g. irqs always enabled)
> > > > > * that are only valid on gen11+
> > > > > */
> > > > > - GEM_BUG_ON(INTEL_GEN(i915) < 11);
> > > > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 11);
> > > > >
> > > > > tasklet_setup(&engine->execlists.tasklet, guc_submission_tasklet);
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> > > > > index 56d2144dc6a0..fc5387b410a2 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> > > > > @@ -43,7 +43,7 @@ void intel_huc_init_early(struct intel_huc *huc)
> > > > >
> > > > > intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC);
> > > > >
> > > > > - if (INTEL_GEN(i915) >= 11) {
> > > > > + if (GRAPHICS_VER(i915) >= 11) {
> > > > > huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
> > > > > huc->status.mask = HUC_LOAD_SUCCESSFUL;
> > > > > huc->status.value = HUC_LOAD_SUCCESSFUL;
> > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> > > > > index 6abb8f2dc33d..6c2bf4b6bc10 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> > > > > @@ -23,7 +23,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
> > > > > return;
> > > > >
> > > > > /* Don't enable GuC/HuC on pre-Gen12 */
> > > > > - if (INTEL_GEN(i915) < 12) {
> > > > > + if (GRAPHICS_VER(i915) < 12) {
> > > > > i915->params.enable_guc = 0;
> > > > > return;
> > > > > }
> > > > > @@ -467,7 +467,7 @@ static int __uc_init_hw(struct intel_uc *uc)
> > > > >
> > > > > /* WaEnableuKernelHeaderValidFix:skl */
> > > > > /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
> > > > > - if (IS_GEN(i915, 9))
> > > > > + if (GRAPHICS_VER(i915) == 9)
> > > > > attempts = 3;
> > > > > else
> > > > > attempts = 1;
> > > > > --
> > > > > 2.31.1
> > > > >
> > > >
> > > > --
> > > > Matt Roper
> > > > Graphics Software Engineer
> > > > VTT-OSGC Platform Enablement
> > > > Intel Corporation
> > > > (916) 356-2795
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > VTT-OSGC Platform Enablement
> > Intel Corporation
> > (916) 356-2795
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
2021-06-01 20:39 ` Matt Roper
@ 2021-06-01 20:53 ` Lucas De Marchi
2021-06-02 6:34 ` Lucas De Marchi
1 sibling, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2021-06-01 20:53 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Tue, Jun 01, 2021 at 01:39:25PM -0700, Matt Roper wrote:
>On Tue, Jun 01, 2021 at 12:13:17PM -0700, Lucas De Marchi wrote:
>> On Tue, Jun 01, 2021 at 10:30:55AM -0700, Matt Roper wrote:
>> > On Tue, Jun 01, 2021 at 10:15:14AM -0700, Lucas De Marchi wrote:
>> > > On Tue, Jun 01, 2021 at 09:58:34AM -0700, Matt Roper wrote:
>> > > > On Thu, May 27, 2021 at 11:16:54AM -0700, Lucas De Marchi wrote:
>> > > > > This was done by the following semantic patch:
>> > > >
>> > > > Is the commit message here out-of-date? The cocci doesn't appear to
>> > > > match the diff anymore. IS_GRAPHICS_VER() is the range macro now and
>> > > > IS_GEN is being replaced with a direct "==" comparison.
>> > >
>> > > not necessarily, it's included in "and friends...". Maybe rewording to
>> > > something like "replace gen-based macros with new ver-based ones" would
>> > > make it clearer?
>> >
>> > I mean that running the coccinelle rules below through spatch won't
>> > generate the code diff here; it would generate a completely different
>> > patch (that I don't think would build properly either).
>>
>> oh, ok. I fixed the issues in the .cocci and forgot to update the commit
>> message. Thanks.
>>
>> Lucas De Marchi
>
>Aside from the commit messages needing updated Coccinelle rules, the
>code deltas look correct to me.
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
thanks,
>
>The one remaining thing not covered by this series is the
>IS_GEN9_{BC,LP}, but that can be addressed as a follow-up if that's
>easier. I'm guessing that, as we saw in the display code, it might be
>easier to handle those manually since sometimes the conditions can be
>simplified to just a simple version 9 test or combined into a version
>10+ test depending on what conditions are already present on the other
>branches of the if/else trees.
I thought a bit about those but couldn't find a good alternative to
those. Indeed doing it manually case by case would be better. Not sure
we want a replacement macro for GEN9_BC/GEN9_LP. Btw only recently I
came to know "BC" stands for "big core". I always found this confusing.
Lucas De Marchi
>
>
>Matt
>
>>
>> >
>> >
>> > Matt
>> >
>> > >
>> > > Lucas De Marchi
>> > >
>> > > >
>> > > >
>> > > > Matt
>> > > >
>> > > > >
>> > > > > @@ expression dev_priv, E; @@
>> > > > > - INTEL_GEN(dev_priv) == E
>> > > > > + IS_GRAPHICS_VER(dev_priv, E)
>> > > > >
>> > > > > @@ expression dev_priv; @@
>> > > > > - INTEL_GEN(dev_priv)
>> > > > > + GRAPHICS_VER(dev_priv)
>> > > > >
>> > > > > @@ expression dev_priv; expression E; @@
>> > > > > - IS_GEN(dev_priv, E)
>> > > > > + IS_GRAPHICS_VER(dev_priv, E)
>> > > > >
>> > > > > @@
>> > > > > expression dev_priv;
>> > > > > expression from, until;
>> > > > > @@
>> > > > > - IS_GEN_RANGE(dev_priv, from, until)
>> > > > > + IS_GRAPHICS_RANGE(dev_priv, from, until)
>> > > > >
>> > > > > @def@
>> > > > > expression E;
>> > > > > identifier id =~ "^gen$";
>> > > > > @@
>> > > > > - id = GRAPHICS_VER(E)
>> > > > > + ver = GRAPHICS_VER(E)
>> > > > >
>> > > > > @@
>> > > > > identifier def.id;
>> > > > > @@
>> > > > > - id
>> > > > > + ver
>> > > > >
>> > > > > It also takes care of renaming the variable we assign to GRAPHICS_VER()
>> > > > > so to use "ver" rather than "gen".
>> > > > >
>> > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> > > > > ---
>> > > > > drivers/gpu/drm/i915/gt/debugfs_gt_pm.c | 38 +++++------
>> > > > > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
>> > > > > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +-
>> > > > > drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 +-
>> > > > > drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 +-
>> > > > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 54 +++++++--------
>> > > > > .../drm/i915/gt/intel_execlists_submission.c | 18 ++---
>> > > > > drivers/gpu/drm/i915/gt/intel_ggtt.c | 18 ++---
>> > > > > drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 34 +++++-----
>> > > > > drivers/gpu/drm/i915/gt/intel_gt.c | 27 ++++----
>> > > > > .../gpu/drm/i915/gt/intel_gt_clock_utils.c | 12 ++--
>> > > > > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 6 +-
>> > > > > drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 10 +--
>> > > > > drivers/gpu/drm/i915/gt/intel_gtt.c | 14 ++--
>> > > > > drivers/gpu/drm/i915/gt/intel_llc.c | 6 +-
>> > > > > drivers/gpu/drm/i915/gt/intel_lrc.c | 46 ++++++-------
>> > > > > drivers/gpu/drm/i915/gt/intel_mocs.c | 8 +--
>> > > > > drivers/gpu/drm/i915/gt/intel_ppgtt.c | 6 +-
>> > > > > drivers/gpu/drm/i915/gt/intel_rc6.c | 16 ++---
>> > > > > drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
>> > > > > drivers/gpu/drm/i915/gt/intel_reset.c | 12 ++--
>> > > > > .../gpu/drm/i915/gt/intel_ring_submission.c | 64 +++++++++---------
>> > > > > drivers/gpu/drm/i915/gt/intel_rps.c | 60 ++++++++---------
>> > > > > drivers/gpu/drm/i915/gt/intel_sseu.c | 14 ++--
>> > > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +++++++++----------
>> > > > > drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 6 +-
>> > > > > drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 2 +-
>> > > > > drivers/gpu/drm/i915/gt/selftest_execlists.c | 4 +-
>> > > > > drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 8 +--
>> > > > > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 +--
>> > > > > drivers/gpu/drm/i915/gt/selftest_llc.c | 4 +-
>> > > > > drivers/gpu/drm/i915/gt/selftest_lrc.c | 8 +--
>> > > > > drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
>> > > > > drivers/gpu/drm/i915/gt/selftest_rc6.c | 4 +-
>> > > > > .../drm/i915/gt/selftest_ring_submission.c | 6 +-
>> > > > > drivers/gpu/drm/i915/gt/selftest_rps.c | 16 ++---
>> > > > > drivers/gpu/drm/i915/gt/selftest_timeline.c | 6 +-
>> > > > > .../gpu/drm/i915/gt/selftest_workarounds.c | 8 +--
>> > > > > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +-
>> > > > > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
>> > > > > drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
>> > > > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 10 +--
>> > > > > drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
>> > > > > drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
>> > > > > 44 files changed, 323 insertions(+), 322 deletions(-)
>> > > > >
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
>> > > > > index d4f4452ce5ed..0389bceebd06 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
>> > > > > @@ -85,14 +85,14 @@ static int gen6_drpc(struct seq_file *m)
>> > > > > gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
>> > > > >
>> > > > > rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
>> > > > > - if (INTEL_GEN(i915) >= 9) {
>> > > > > + if (GRAPHICS_VER(i915) >= 9) {
>> > > > > gen9_powergate_enable =
>> > > > > intel_uncore_read(uncore, GEN9_PG_ENABLE);
>> > > > > gen9_powergate_status =
>> > > > > intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS);
>> > > > > }
>> > > > >
>> > > > > - if (INTEL_GEN(i915) <= 7)
>> > > > > + if (GRAPHICS_VER(i915) <= 7)
>> > > > > sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
>> > > > > &rc6vids, NULL);
>> > > > >
>> > > > > @@ -100,7 +100,7 @@ static int gen6_drpc(struct seq_file *m)
>> > > > > yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
>> > > > > seq_printf(m, "RC6 Enabled: %s\n",
>> > > > > yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
>> > > > > - if (INTEL_GEN(i915) >= 9) {
>> > > > > + if (GRAPHICS_VER(i915) >= 9) {
>> > > > > seq_printf(m, "Render Well Gating Enabled: %s\n",
>> > > > > yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
>> > > > > seq_printf(m, "Media Well Gating Enabled: %s\n",
>> > > > > @@ -134,7 +134,7 @@ static int gen6_drpc(struct seq_file *m)
>> > > > >
>> > > > > seq_printf(m, "Core Power Down: %s\n",
>> > > > > yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
>> > > > > - if (INTEL_GEN(i915) >= 9) {
>> > > > > + if (GRAPHICS_VER(i915) >= 9) {
>> > > > > seq_printf(m, "Render Power Well: %s\n",
>> > > > > (gen9_powergate_status &
>> > > > > GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
>> > > > > @@ -150,7 +150,7 @@ static int gen6_drpc(struct seq_file *m)
>> > > > > print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
>> > > > > print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
>> > > > >
>> > > > > - if (INTEL_GEN(i915) <= 7) {
>> > > > > + if (GRAPHICS_VER(i915) <= 7) {
>> > > > > seq_printf(m, "RC6 voltage: %dmV\n",
>> > > > > GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
>> > > > > seq_printf(m, "RC6+ voltage: %dmV\n",
>> > > > > @@ -250,7 +250,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>> > > > >
>> > > > > wakeref = intel_runtime_pm_get(uncore->rpm);
>> > > > >
>> > > > > - if (IS_GEN(i915, 5)) {
>> > > > > + if (GRAPHICS_VER(i915) == 5) {
>> > > > > u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
>> > > > > u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
>> > > > >
>> > > > > @@ -296,7 +296,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>> > > > >
>> > > > > seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
>> > > > > intel_gpu_freq(rps, rps->efficient_freq));
>> > > > > - } else if (INTEL_GEN(i915) >= 6) {
>> > > > > + } else if (GRAPHICS_VER(i915) >= 6) {
>> > > > > u32 rp_state_limits;
>> > > > > u32 gt_perf_status;
>> > > > > u32 rp_state_cap;
>> > > > > @@ -321,7 +321,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>> > > > > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>> > > > >
>> > > > > reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
>> > > > > - if (INTEL_GEN(i915) >= 9) {
>> > > > > + if (GRAPHICS_VER(i915) >= 9) {
>> > > > > reqf >>= 23;
>> > > > > } else {
>> > > > > reqf &= ~GEN6_TURBO_DISABLE;
>> > > > > @@ -354,7 +354,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>> > > > >
>> > > > > intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 11) {
>> > > > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > > > pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
>> > > > > pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
>> > > > > /*
>> > > > > @@ -363,7 +363,7 @@ static int frequency_show(struct seq_file *m, void *unused)
>> > > > > */
>> > > > > pm_isr = 0;
>> > > > > pm_iir = 0;
>> > > > > - } else if (INTEL_GEN(i915) >= 8) {
>> > > > > + } else if (GRAPHICS_VER(i915) >= 8) {
>> > > > > pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
>> > > > > pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
>> > > > > pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
>> > > > > @@ -386,14 +386,14 @@ static int frequency_show(struct seq_file *m, void *unused)
>> > > > >
>> > > > > seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
>> > > > > pm_ier, pm_imr, pm_mask);
>> > > > > - if (INTEL_GEN(i915) <= 10)
>> > > > > + if (GRAPHICS_VER(i915) <= 10)
>> > > > > seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
>> > > > > pm_isr, pm_iir);
>> > > > > seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
>> > > > > rps->pm_intrmsk_mbz);
>> > > > > seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
>> > > > > seq_printf(m, "Render p-state ratio: %d\n",
>> > > > > - (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
>> > > > > + (gt_perf_status & (GRAPHICS_VER(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
>> > > > > seq_printf(m, "Render p-state VID: %d\n",
>> > > > > gt_perf_status & 0xff);
>> > > > > seq_printf(m, "Render p-state limit: %d\n",
>> > > > > @@ -437,20 +437,20 @@ static int frequency_show(struct seq_file *m, void *unused)
>> > > > > max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
>> > > > > rp_state_cap >> 16) & 0xff;
>> > > > > max_freq *= (IS_GEN9_BC(i915) ||
>> > > > > - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> > > > > + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> > > > > seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
>> > > > > intel_gpu_freq(rps, max_freq));
>> > > > >
>> > > > > max_freq = (rp_state_cap & 0xff00) >> 8;
>> > > > > max_freq *= (IS_GEN9_BC(i915) ||
>> > > > > - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> > > > > + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> > > > > seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
>> > > > > intel_gpu_freq(rps, max_freq));
>> > > > >
>> > > > > max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
>> > > > > rp_state_cap >> 0) & 0xff;
>> > > > > max_freq *= (IS_GEN9_BC(i915) ||
>> > > > > - INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> > > > > + GRAPHICS_VER(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
>> > > > > seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
>> > > > > intel_gpu_freq(rps, max_freq));
>> > > > > seq_printf(m, "Max overclocked frequency: %dMHz\n",
>> > > > > @@ -488,7 +488,7 @@ static int llc_show(struct seq_file *m, void *data)
>> > > > > {
>> > > > > struct intel_gt *gt = m->private;
>> > > > > struct drm_i915_private *i915 = gt->i915;
>> > > > > - const bool edram = INTEL_GEN(i915) > 8;
>> > > > > + const bool edram = GRAPHICS_VER(i915) > 8;
>> > > > > struct intel_rps *rps = >->rps;
>> > > > > unsigned int max_gpu_freq, min_gpu_freq;
>> > > > > intel_wakeref_t wakeref;
>> > > > > @@ -500,7 +500,7 @@ static int llc_show(struct seq_file *m, void *data)
>> > > > >
>> > > > > min_gpu_freq = rps->min_freq;
>> > > > > max_gpu_freq = rps->max_freq;
>> > > > > - if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
>> > > > > + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
>> > > > > /* Convert GT frequency to 50 HZ units */
>> > > > > min_gpu_freq /= GEN9_FREQ_SCALER;
>> > > > > max_gpu_freq /= GEN9_FREQ_SCALER;
>> > > > > @@ -518,7 +518,7 @@ static int llc_show(struct seq_file *m, void *data)
>> > > > > intel_gpu_freq(rps,
>> > > > > (gpu_freq *
>> > > > > (IS_GEN9_BC(i915) ||
>> > > > > - INTEL_GEN(i915) >= 10 ?
>> > > > > + GRAPHICS_VER(i915) >= 10 ?
>> > > > > GEN9_FREQ_SCALER : 1))),
>> > > > > ((ia_freq >> 0) & 0xff) * 100,
>> > > > > ((ia_freq >> 8) & 0xff) * 100);
>> > > > > @@ -580,7 +580,7 @@ static int rps_boost_show(struct seq_file *m, void *data)
>> > > > >
>> > > > > seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 6 && intel_rps_is_active(rps)) {
>> > > > > + if (GRAPHICS_VER(i915) >= 6 && intel_rps_is_active(rps)) {
>> > > > > struct intel_uncore *uncore = gt->uncore;
>> > > > > u32 rpup, rpupei;
>> > > > > u32 rpdown, rpdownei;
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> > > > > index 9646200d2792..61383830505e 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> > > > > @@ -74,7 +74,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
>> > > > > cmd = MI_FLUSH;
>> > > > > if (mode & EMIT_INVALIDATE) {
>> > > > > cmd |= MI_EXE_FLUSH;
>> > > > > - if (IS_G4X(rq->engine->i915) || IS_GEN(rq->engine->i915, 5))
>> > > > > + if (IS_G4X(rq->engine->i915) || GRAPHICS_VER(rq->engine->i915) == 5)
>> > > > > cmd |= MI_INVALIDATE_ISP;
>> > > > > }
>> > > > >
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> > > > > index 732c2ed1d933..94e0a5669f90 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> > > > > @@ -38,7 +38,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
>> > > > > * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
>> > > > > * pipe control.
>> > > > > */
>> > > > > - if (IS_GEN(rq->engine->i915, 9))
>> > > > > + if (GRAPHICS_VER(rq->engine->i915) == 9)
>> > > > > vf_flush_wa = true;
>> > > > >
>> > > > > /* WaForGAMHang:kbl */
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> > > > > index e3a8924d2286..21c8b7350b7a 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> > > > > @@ -709,7 +709,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
>> > > > > *
>> > > > > * Gen12 has inherited the same read-only fault issue from gen11.
>> > > > > */
>> > > > > - ppgtt->vm.has_read_only = !IS_GEN_RANGE(gt->i915, 11, 12);
>> > > > > + ppgtt->vm.has_read_only = !IS_GRAPHICS_VER(gt->i915, 11, 12);
>> > > > >
>> > > > > if (HAS_LMEM(gt->i915))
>> > > > > ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
>> > > > > index 8dfd8f656aaa..e86d8255feec 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c
>> > > > > @@ -76,7 +76,7 @@ intel_context_reconfigure_sseu(struct intel_context *ce,
>> > > > > {
>> > > > > int ret;
>> > > > >
>> > > > > - GEM_BUG_ON(INTEL_GEN(ce->engine->i915) < 8);
>> > > > > + GEM_BUG_ON(GRAPHICS_VER(ce->engine->i915) < 8);
>> > > > >
>> > > > > ret = intel_context_lock_pinned(ce);
>> > > > > if (ret)
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> > > > > index 3f9a811eb02b..54baf17b81b6 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>> > > > > @@ -240,10 +240,10 @@ void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
>> > > > > * Though they added more rings on g4x/ilk, they did not add
>> > > > > * per-engine HWSTAM until gen6.
>> > > > > */
>> > > > > - if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS)
>> > > > > + if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)
>> > > > > return;
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) >= 3)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 3)
>> > > > > ENGINE_WRITE(engine, RING_HWSTAM, mask);
>> > > > > else
>> > > > > ENGINE_WRITE16(engine, RING_HWSTAM, mask);
>> > > > > @@ -315,7 +315,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
>> > > > > CONFIG_DRM_I915_TIMESLICE_DURATION;
>> > > > >
>> > > > > /* Override to uninterruptible for OpenCL workloads. */
>> > > > > - if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS)
>> > > > > + if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
>> > > > > engine->props.preempt_timeout_ms = 0;
>> > > > >
>> > > > > engine->defaults = engine->props; /* never to change again */
>> > > > > @@ -352,8 +352,8 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
>> > > > > * HEVC support is present on first engine instance
>> > > > > * before Gen11 and on all instances afterwards.
>> > > > > */
>> > > > > - if (INTEL_GEN(i915) >= 11 ||
>> > > > > - (INTEL_GEN(i915) >= 9 && engine->instance == 0))
>> > > > > + if (GRAPHICS_VER(i915) >= 11 ||
>> > > > > + (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
>> > > > > engine->uabi_capabilities |=
>> > > > > I915_VIDEO_CLASS_CAPABILITY_HEVC;
>> > > > >
>> > > > > @@ -361,14 +361,14 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
>> > > > > * SFC block is present only on even logical engine
>> > > > > * instances.
>> > > > > */
>> > > > > - if ((INTEL_GEN(i915) >= 11 &&
>> > > > > + if ((GRAPHICS_VER(i915) >= 11 &&
>> > > > > (engine->gt->info.vdbox_sfc_access &
>> > > > > BIT(engine->instance))) ||
>> > > > > - (INTEL_GEN(i915) >= 9 && engine->instance == 0))
>> > > > > + (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
>> > > > > engine->uabi_capabilities |=
>> > > > > I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
>> > > > > } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
>> > > > > - if (INTEL_GEN(i915) >= 9)
>> > > > > + if (GRAPHICS_VER(i915) >= 9)
>> > > > > engine->uabi_capabilities |=
>> > > > > I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
>> > > > > }
>> > > > > @@ -466,7 +466,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>> > > > >
>> > > > > info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) < 11)
>> > > > > + if (GRAPHICS_VER(i915) < 11)
>> > > > > return info->engine_mask;
>> > > > >
>> > > > > media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
>> > > > > @@ -492,7 +492,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>> > > > > * hooked up to an SFC (Scaler & Format Converter) unit.
>> > > > > * In TGL each VDBOX has access to an SFC.
>> > > > > */
>> > > > > - if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
>> > > > > + if (GRAPHICS_VER(i915) >= 12 || logical_vdbox++ % 2 == 0)
>> > > > > gt->info.vdbox_sfc_access |= BIT(i);
>> > > > > }
>> > > > > drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
>> > > > > @@ -729,7 +729,7 @@ static int engine_setup_common(struct intel_engine_cs *engine)
>> > > > > intel_engine_init_whitelist(engine);
>> > > > > intel_engine_init_ctx_wa(engine);
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > > > engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
>> > > > >
>> > > > > return 0;
>> > > > > @@ -997,9 +997,9 @@ u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
>> > > > >
>> > > > > u64 acthd;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 8)
>> > > > > + if (GRAPHICS_VER(i915) >= 8)
>> > > > > acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
>> > > > > - else if (INTEL_GEN(i915) >= 4)
>> > > > > + else if (GRAPHICS_VER(i915) >= 4)
>> > > > > acthd = ENGINE_READ(engine, RING_ACTHD);
>> > > > > else
>> > > > > acthd = ENGINE_READ(engine, ACTHD);
>> > > > > @@ -1011,7 +1011,7 @@ u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
>> > > > > {
>> > > > > u64 bbaddr;
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) >= 8)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 8)
>> > > > > bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
>> > > > > else
>> > > > > bbaddr = ENGINE_READ(engine, RING_BBADDR);
>> > > > > @@ -1058,7 +1058,7 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine)
>> > > > > {
>> > > > > int err = 0;
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) < 3)
>> > > > > + if (GRAPHICS_VER(engine->i915) < 3)
>> > > > > return -ENODEV;
>> > > > >
>> > > > > ENGINE_TRACE(engine, "\n");
>> > > > > @@ -1108,7 +1108,7 @@ read_subslice_reg(const struct intel_engine_cs *engine,
>> > > > > u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
>> > > > > enum forcewake_domains fw_domains;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 11) {
>> > > > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > > > mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
>> > > > > mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
>> > > > > } else {
>> > > > > @@ -1157,7 +1157,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
>> > > > >
>> > > > > memset(instdone, 0, sizeof(*instdone));
>> > > > >
>> > > > > - switch (INTEL_GEN(i915)) {
>> > > > > + switch (GRAPHICS_VER(i915)) {
>> > > > > default:
>> > > > > instdone->instdone =
>> > > > > intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
>> > > > > @@ -1167,7 +1167,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
>> > > > >
>> > > > > instdone->slice_common =
>> > > > > intel_uncore_read(uncore, GEN7_SC_INSTDONE);
>> > > > > - if (INTEL_GEN(i915) >= 12) {
>> > > > > + if (GRAPHICS_VER(i915) >= 12) {
>> > > > > instdone->slice_common_extra[0] =
>> > > > > intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
>> > > > > instdone->slice_common_extra[1] =
>> > > > > @@ -1230,7 +1230,7 @@ static bool ring_is_idle(struct intel_engine_cs *engine)
>> > > > > idle = false;
>> > > > >
>> > > > > /* No bit for gen2, so assume the CS parser is idle */
>> > > > > - if (INTEL_GEN(engine->i915) > 2 &&
>> > > > > + if (GRAPHICS_VER(engine->i915) > 2 &&
>> > > > > !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
>> > > > > idle = false;
>> > > > >
>> > > > > @@ -1327,7 +1327,7 @@ void intel_engines_reset_default_submission(struct intel_gt *gt)
>> > > > >
>> > > > > bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
>> > > > > {
>> > > > > - switch (INTEL_GEN(engine->i915)) {
>> > > > > + switch (GRAPHICS_VER(engine->i915)) {
>> > > > > case 2:
>> > > > > return false; /* uses physical not virtual addresses */
>> > > > > case 3:
>> > > > > @@ -1432,7 +1432,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
>> > > > > struct intel_engine_execlists * const execlists = &engine->execlists;
>> > > > > u64 addr;
>> > > > >
>> > > > > - if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
>> > > > > + if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7))
>> > > > > drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
>> > > > > if (HAS_EXECLISTS(dev_priv)) {
>> > > > > drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
>> > > > > @@ -1449,13 +1449,13 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
>> > > > > drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
>> > > > > ENGINE_READ(engine, RING_CTL),
>> > > > > ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
>> > > > > - if (INTEL_GEN(engine->i915) > 2) {
>> > > > > + if (GRAPHICS_VER(engine->i915) > 2) {
>> > > > > drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
>> > > > > ENGINE_READ(engine, RING_MI_MODE),
>> > > > > ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
>> > > > > }
>> > > > >
>> > > > > - if (INTEL_GEN(dev_priv) >= 6) {
>> > > > > + if (GRAPHICS_VER(dev_priv) >= 6) {
>> > > > > drm_printf(m, "\tRING_IMR: 0x%08x\n",
>> > > > > ENGINE_READ(engine, RING_IMR));
>> > > > > drm_printf(m, "\tRING_ESR: 0x%08x\n",
>> > > > > @@ -1472,15 +1472,15 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
>> > > > > addr = intel_engine_get_last_batch_head(engine);
>> > > > > drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
>> > > > > upper_32_bits(addr), lower_32_bits(addr));
>> > > > > - if (INTEL_GEN(dev_priv) >= 8)
>> > > > > + if (GRAPHICS_VER(dev_priv) >= 8)
>> > > > > addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
>> > > > > - else if (INTEL_GEN(dev_priv) >= 4)
>> > > > > + else if (GRAPHICS_VER(dev_priv) >= 4)
>> > > > > addr = ENGINE_READ(engine, RING_DMA_FADD);
>> > > > > else
>> > > > > addr = ENGINE_READ(engine, DMA_FADD_I8XX);
>> > > > > drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
>> > > > > upper_32_bits(addr), lower_32_bits(addr));
>> > > > > - if (INTEL_GEN(dev_priv) >= 4) {
>> > > > > + if (GRAPHICS_VER(dev_priv) >= 4) {
>> > > > > drm_printf(m, "\tIPEIR: 0x%08x\n",
>> > > > > ENGINE_READ(engine, RING_IPEIR));
>> > > > > drm_printf(m, "\tIPEHR: 0x%08x\n",
>> > > > > @@ -1559,7 +1559,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
>> > > > > }
>> > > > > rcu_read_unlock();
>> > > > > execlists_active_unlock_bh(execlists);
>> > > > > - } else if (INTEL_GEN(dev_priv) > 6) {
>> > > > > + } else if (GRAPHICS_VER(dev_priv) > 6) {
>> > > > > drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
>> > > > > ENGINE_READ(engine, RING_PP_DIR_BASE));
>> > > > > drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> > > > > index 8db200422950..fc77592d88a9 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> > > > > @@ -1847,7 +1847,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
>> > > > > ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n",
>> > > > > head, upper_32_bits(csb), lower_32_bits(csb));
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > > > promote = gen12_csb_parse(csb);
>> > > > > else
>> > > > > promote = gen8_csb_parse(csb);
>> > > > > @@ -2772,7 +2772,7 @@ static void enable_execlists(struct intel_engine_cs *engine)
>> > > > >
>> > > > > intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) >= 11)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 11)
>> > > > > mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
>> > > > > else
>> > > > > mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
>> > > > > @@ -3103,7 +3103,7 @@ static void execlists_park(struct intel_engine_cs *engine)
>> > > > >
>> > > > > static bool can_preempt(struct intel_engine_cs *engine)
>> > > > > {
>> > > > > - if (INTEL_GEN(engine->i915) > 8)
>> > > > > + if (GRAPHICS_VER(engine->i915) > 8)
>> > > > > return true;
>> > > > >
>> > > > > /* GPGPU on bdw requires extra w/a; not implemented */
>> > > > > @@ -3156,13 +3156,13 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
>> > > > > engine->emit_flush = gen8_emit_flush_xcs;
>> > > > > engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
>> > > > > engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
>> > > > > - if (INTEL_GEN(engine->i915) >= 12) {
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 12) {
>> > > > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;
>> > > > > engine->emit_flush = gen12_emit_flush_xcs;
>> > > > > }
>> > > > > engine->set_default_submission = execlists_set_default_submission;
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) < 11) {
>> > > > > + if (GRAPHICS_VER(engine->i915) < 11) {
>> > > > > engine->irq_enable = gen8_logical_ring_enable_irq;
>> > > > > engine->irq_disable = gen8_logical_ring_disable_irq;
>> > > > > } else {
>> > > > > @@ -3195,7 +3195,7 @@ static void logical_ring_default_irqs(struct intel_engine_cs *engine)
>> > > > > {
>> > > > > unsigned int shift = 0;
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) < 11) {
>> > > > > + if (GRAPHICS_VER(engine->i915) < 11) {
>> > > > > const u8 irq_shifts[] = {
>> > > > > [RCS0] = GEN8_RCS_IRQ_SHIFT,
>> > > > > [BCS0] = GEN8_BCS_IRQ_SHIFT,
>> > > > > @@ -3215,7 +3215,7 @@ static void logical_ring_default_irqs(struct intel_engine_cs *engine)
>> > > > >
>> > > > > static void rcs_submission_override(struct intel_engine_cs *engine)
>> > > > > {
>> > > > > - switch (INTEL_GEN(engine->i915)) {
>> > > > > + switch (GRAPHICS_VER(engine->i915)) {
>> > > > > case 12:
>> > > > > engine->emit_flush = gen12_emit_flush_rcs;
>> > > > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
>> > > > > @@ -3266,13 +3266,13 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
>> > > > > execlists->csb_write =
>> > > > > &engine->status_page.addr[intel_hws_csb_write_index(i915)];
>> > > > >
>> > > > > - if (INTEL_GEN(i915) < 11)
>> > > > > + if (GRAPHICS_VER(i915) < 11)
>> > > > > execlists->csb_size = GEN8_CSB_ENTRIES;
>> > > > > else
>> > > > > execlists->csb_size = GEN11_CSB_ENTRIES;
>> > > > >
>> > > > > engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);
>> > > > > - if (INTEL_GEN(engine->i915) >= 11) {
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 11) {
>> > > > > execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
>> > > > > execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);
>> > > > > }
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> > > > > index 35069ca5d7de..19bd8856ce84 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> > > > > @@ -107,10 +107,10 @@ static bool needs_idle_maps(struct drm_i915_private *i915)
>> > > > > if (!intel_vtd_active())
>> > > > > return false;
>> > > > >
>> > > > > - if (IS_GEN(i915, 5) && IS_MOBILE(i915))
>> > > > > + if (GRAPHICS_VER(i915) == 5 && IS_MOBILE(i915))
>> > > > > return true;
>> > > > >
>> > > > > - if (IS_GEN(i915, 12))
>> > > > > + if (GRAPHICS_VER(i915) == 12)
>> > > > > return true; /* XXX DMAR fault reason 7 */
>> > > > >
>> > > > > return false;
>> > > > > @@ -176,7 +176,7 @@ static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
>> > > > >
>> > > > > gen8_ggtt_invalidate(ggtt);
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 12)
>> > > > > + if (GRAPHICS_VER(i915) >= 12)
>> > > > > intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
>> > > > > GEN12_GUC_TLB_INV_CR_INVALIDATE);
>> > > > > else
>> > > > > @@ -820,7 +820,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
>> > > > > * resort to an uncached mapping. The WC issue is easily caught by the
>> > > > > * readback check when writing GTT PTE entries.
>> > > > > */
>> > > > > - if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
>> > > > > + if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 10)
>> > > > > ggtt->gsm = ioremap(phys_addr, size);
>> > > > > else
>> > > > > ggtt->gsm = ioremap_wc(phys_addr, size);
>> > > > > @@ -1065,7 +1065,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
>> > > > > ggtt->vm.pte_encode = hsw_pte_encode;
>> > > > > else if (IS_VALLEYVIEW(i915))
>> > > > > ggtt->vm.pte_encode = byt_pte_encode;
>> > > > > - else if (INTEL_GEN(i915) >= 7)
>> > > > > + else if (GRAPHICS_VER(i915) >= 7)
>> > > > > ggtt->vm.pte_encode = ivb_pte_encode;
>> > > > > else
>> > > > > ggtt->vm.pte_encode = snb_pte_encode;
>> > > > > @@ -1137,9 +1137,9 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
>> > > > > ggtt->vm.dma = i915->drm.dev;
>> > > > > dma_resv_init(&ggtt->vm.resv);
>> > > > >
>> > > > > - if (INTEL_GEN(i915) <= 5)
>> > > > > + if (GRAPHICS_VER(i915) <= 5)
>> > > > > ret = i915_gmch_probe(ggtt);
>> > > > > - else if (INTEL_GEN(i915) < 8)
>> > > > > + else if (GRAPHICS_VER(i915) < 8)
>> > > > > ret = gen6_gmch_probe(ggtt);
>> > > > > else
>> > > > > ret = gen8_gmch_probe(ggtt);
>> > > > > @@ -1196,7 +1196,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *i915)
>> > > > >
>> > > > > int i915_ggtt_enable_hw(struct drm_i915_private *i915)
>> > > > > {
>> > > > > - if (INTEL_GEN(i915) < 6 && !intel_enable_gtt())
>> > > > > + if (GRAPHICS_VER(i915) < 6 && !intel_enable_gtt())
>> > > > > return -EIO;
>> > > > >
>> > > > > return 0;
>> > > > > @@ -1261,7 +1261,7 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt)
>> > > > > if (flush)
>> > > > > wbinvd_on_all_cpus();
>> > > > >
>> > > > > - if (INTEL_GEN(ggtt->vm.i915) >= 8)
>> > > > > + if (GRAPHICS_VER(ggtt->vm.i915) >= 8)
>> > > > > setup_private_pat(ggtt->vm.gt->uncore);
>> > > > >
>> > > > > intel_ggtt_restore_fences(ggtt);
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
>> > > > > index 7bf84cd21543..cac7f3f44642 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
>> > > > > @@ -56,7 +56,7 @@ static void i965_write_fence_reg(struct i915_fence_reg *fence)
>> > > > > int fence_pitch_shift;
>> > > > > u64 val;
>> > > > >
>> > > > > - if (INTEL_GEN(fence_to_i915(fence)) >= 6) {
>> > > > > + if (GRAPHICS_VER(fence_to_i915(fence)) >= 6) {
>> > > > > fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
>> > > > > fence_reg_hi = FENCE_REG_GEN6_HI(fence->id);
>> > > > > fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
>> > > > > @@ -173,9 +173,9 @@ static void fence_write(struct i915_fence_reg *fence)
>> > > > > * and explicitly managed for internal users.
>> > > > > */
>> > > > >
>> > > > > - if (IS_GEN(i915, 2))
>> > > > > + if (GRAPHICS_VER(i915) == 2)
>> > > > > i830_write_fence_reg(fence);
>> > > > > - else if (IS_GEN(i915, 3))
>> > > > > + else if (GRAPHICS_VER(i915) == 3)
>> > > > > i915_write_fence_reg(fence);
>> > > > > else
>> > > > > i965_write_fence_reg(fence);
>> > > > > @@ -188,7 +188,7 @@ static void fence_write(struct i915_fence_reg *fence)
>> > > > >
>> > > > > static bool gpu_uses_fence_registers(struct i915_fence_reg *fence)
>> > > > > {
>> > > > > - return INTEL_GEN(fence_to_i915(fence)) < 4;
>> > > > > + return GRAPHICS_VER(fence_to_i915(fence)) < 4;
>> > > > > }
>> > > > >
>> > > > > static int fence_update(struct i915_fence_reg *fence,
>> > > > > @@ -569,7 +569,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
>> > > > > u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
>> > > > > u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 8 || IS_VALLEYVIEW(i915)) {
>> > > > > + if (GRAPHICS_VER(i915) >= 8 || IS_VALLEYVIEW(i915)) {
>> > > > > /*
>> > > > > * On BDW+, swizzling is not used. We leave the CPU memory
>> > > > > * controller in charge of optimizing memory accesses without
>> > > > > @@ -579,7 +579,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
>> > > > > */
>> > > > > swizzle_x = I915_BIT_6_SWIZZLE_NONE;
>> > > > > swizzle_y = I915_BIT_6_SWIZZLE_NONE;
>> > > > > - } else if (INTEL_GEN(i915) >= 6) {
>> > > > > + } else if (GRAPHICS_VER(i915) >= 6) {
>> > > > > if (i915->preserve_bios_swizzle) {
>> > > > > if (intel_uncore_read(uncore, DISP_ARB_CTL) &
>> > > > > DISP_TILE_SURFACE_SWIZZLING) {
>> > > > > @@ -611,14 +611,14 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
>> > > > > swizzle_y = I915_BIT_6_SWIZZLE_NONE;
>> > > > > }
>> > > > > }
>> > > > > - } else if (IS_GEN(i915, 5)) {
>> > > > > + } else if (GRAPHICS_VER(i915) == 5) {
>> > > > > /*
>> > > > > * On Ironlake whatever DRAM config, GPU always do
>> > > > > * same swizzling setup.
>> > > > > */
>> > > > > swizzle_x = I915_BIT_6_SWIZZLE_9_10;
>> > > > > swizzle_y = I915_BIT_6_SWIZZLE_9;
>> > > > > - } else if (IS_GEN(i915, 2)) {
>> > > > > + } else if (GRAPHICS_VER(i915) == 2) {
>> > > > > /*
>> > > > > * As far as we know, the 865 doesn't have these bit 6
>> > > > > * swizzling issues.
>> > > > > @@ -697,7 +697,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
>> > > > > }
>> > > > >
>> > > > > /* check for L-shaped memory aka modified enhanced addressing */
>> > > > > - if (IS_GEN(i915, 4) &&
>> > > > > + if (GRAPHICS_VER(i915) == 4 &&
>> > > > > !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
>> > > > > swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
>> > > > > swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>> > > > > @@ -844,10 +844,10 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
>> > > > >
>> > > > > if (!i915_ggtt_has_aperture(ggtt))
>> > > > > num_fences = 0;
>> > > > > - else if (INTEL_GEN(i915) >= 7 &&
>> > > > > + else if (GRAPHICS_VER(i915) >= 7 &&
>> > > > > !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
>> > > > > num_fences = 32;
>> > > > > - else if (INTEL_GEN(i915) >= 4 ||
>> > > > > + else if (GRAPHICS_VER(i915) >= 4 ||
>> > > > > IS_I945G(i915) || IS_I945GM(i915) ||
>> > > > > IS_G33(i915) || IS_PINEVIEW(i915))
>> > > > > num_fences = 16;
>> > > > > @@ -895,29 +895,29 @@ void intel_gt_init_swizzling(struct intel_gt *gt)
>> > > > > struct drm_i915_private *i915 = gt->i915;
>> > > > > struct intel_uncore *uncore = gt->uncore;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) < 5 ||
>> > > > > + if (GRAPHICS_VER(i915) < 5 ||
>> > > > > i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
>> > > > > return;
>> > > > >
>> > > > > intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
>> > > > >
>> > > > > - if (IS_GEN(i915, 5))
>> > > > > + if (GRAPHICS_VER(i915) == 5)
>> > > > > return;
>> > > > >
>> > > > > intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL);
>> > > > >
>> > > > > - if (IS_GEN(i915, 6))
>> > > > > + if (GRAPHICS_VER(i915) == 6)
>> > > > > intel_uncore_write(uncore,
>> > > > > ARB_MODE,
>> > > > > _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
>> > > > > - else if (IS_GEN(i915, 7))
>> > > > > + else if (GRAPHICS_VER(i915) == 7)
>> > > > > intel_uncore_write(uncore,
>> > > > > ARB_MODE,
>> > > > > _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
>> > > > > - else if (IS_GEN(i915, 8))
>> > > > > + else if (GRAPHICS_VER(i915) == 8)
>> > > > > intel_uncore_write(uncore,
>> > > > > GAMTARBMODE,
>> > > > > _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
>> > > > > else
>> > > > > - MISSING_CASE(INTEL_GEN(i915));
>> > > > > + MISSING_CASE(GRAPHICS_VER(i915));
>> > > > > }
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>> > > > > index 8d77dcbad059..7f24301cef18 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> > > > > @@ -115,10 +115,10 @@ static void init_unused_rings(struct intel_gt *gt)
>> > > > > init_unused_ring(gt, SRB1_BASE);
>> > > > > init_unused_ring(gt, SRB2_BASE);
>> > > > > init_unused_ring(gt, SRB3_BASE);
>> > > > > - } else if (IS_GEN(i915, 2)) {
>> > > > > + } else if (GRAPHICS_VER(i915) == 2) {
>> > > > > init_unused_ring(gt, SRB0_BASE);
>> > > > > init_unused_ring(gt, SRB1_BASE);
>> > > > > - } else if (IS_GEN(i915, 3)) {
>> > > > > + } else if (GRAPHICS_VER(i915) == 3) {
>> > > > > init_unused_ring(gt, PRB1_BASE);
>> > > > > init_unused_ring(gt, PRB2_BASE);
>> > > > > }
>> > > > > @@ -135,7 +135,7 @@ int intel_gt_init_hw(struct intel_gt *gt)
>> > > > > /* Double layer security blanket, see i915_gem_init() */
>> > > > > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>> > > > >
>> > > > > - if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
>> > > > > + if (HAS_EDRAM(i915) && GRAPHICS_VER(i915) < 9)
>> > > > > intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
>> > > > >
>> > > > > if (IS_HASWELL(i915))
>> > > > > @@ -208,10 +208,10 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
>> > > > > struct intel_uncore *uncore = gt->uncore;
>> > > > > u32 eir;
>> > > > >
>> > > > > - if (!IS_GEN(i915, 2))
>> > > > > + if (GRAPHICS_VER(i915) != 2)
>> > > > > clear_register(uncore, PGTBL_ER);
>> > > > >
>> > > > > - if (INTEL_GEN(i915) < 4)
>> > > > > + if (GRAPHICS_VER(i915) < 4)
>> > > > > clear_register(uncore, IPEIR(RENDER_RING_BASE));
>> > > > > else
>> > > > > clear_register(uncore, IPEIR_I965);
>> > > > > @@ -229,13 +229,13 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
>> > > > > I915_MASTER_ERROR_INTERRUPT);
>> > > > > }
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 12) {
>> > > > > + if (GRAPHICS_VER(i915) >= 12) {
>> > > > > rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
>> > > > > intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
>> > > > > - } else if (INTEL_GEN(i915) >= 8) {
>> > > > > + } else if (GRAPHICS_VER(i915) >= 8) {
>> > > > > rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
>> > > > > intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
>> > > > > - } else if (INTEL_GEN(i915) >= 6) {
>> > > > > + } else if (GRAPHICS_VER(i915) >= 6) {
>> > > > > struct intel_engine_cs *engine;
>> > > > > enum intel_engine_id id;
>> > > > >
>> > > > > @@ -273,7 +273,7 @@ static void gen8_check_faults(struct intel_gt *gt)
>> > > > > i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
>> > > > > u32 fault;
>> > > > >
>> > > > > - if (INTEL_GEN(gt->i915) >= 12) {
>> > > > > + if (GRAPHICS_VER(gt->i915) >= 12) {
>> > > > > fault_reg = GEN12_RING_FAULT_REG;
>> > > > > fault_data0_reg = GEN12_FAULT_TLB_DATA0;
>> > > > > fault_data1_reg = GEN12_FAULT_TLB_DATA1;
>> > > > > @@ -313,9 +313,9 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
>> > > > > struct drm_i915_private *i915 = gt->i915;
>> > > > >
>> > > > > /* From GEN8 onwards we only have one 'All Engine Fault Register' */
>> > > > > - if (INTEL_GEN(i915) >= 8)
>> > > > > + if (GRAPHICS_VER(i915) >= 8)
>> > > > > gen8_check_faults(gt);
>> > > > > - else if (INTEL_GEN(i915) >= 6)
>> > > > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > > > gen6_check_faults(gt);
>> > > > > else
>> > > > > return;
>> > > > > @@ -367,7 +367,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
>> > > > > void intel_gt_chipset_flush(struct intel_gt *gt)
>> > > > > {
>> > > > > wmb();
>> > > > > - if (INTEL_GEN(gt->i915) < 6)
>> > > > > + if (GRAPHICS_VER(gt->i915) < 6)
>> > > > > intel_gtt_chipset_flush();
>> > > > > }
>> > > > >
>> > > > > @@ -591,7 +591,8 @@ int intel_gt_init(struct intel_gt *gt)
>> > > > > */
>> > > > > intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
>> > > > >
>> > > > > - err = intel_gt_init_scratch(gt, IS_GEN(gt->i915, 2) ? SZ_256K : SZ_4K);
>> > > > > + err = intel_gt_init_scratch(gt,
>> > > > > + GRAPHICS_VER(gt->i915) == 2 ? SZ_256K : SZ_4K);
>> > > > > if (err)
>> > > > > goto out_fw;
>> > > > >
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
>> > > > > index 582fcaee11aa..9f0e729d2d15 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
>> > > > > @@ -76,7 +76,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> > > > > u32 f19_2_mhz = 19200000;
>> > > > > u32 f24_mhz = 24000000;
>> > > > >
>> > > > > - if (INTEL_GEN(uncore->i915) <= 4) {
>> > > > > + if (GRAPHICS_VER(uncore->i915) <= 4) {
>> > > > > /*
>> > > > > * PRMs say:
>> > > > > *
>> > > > > @@ -85,7 +85,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> > > > > * (“CLKCFG”) MCHBAR register)
>> > > > > */
>> > > > > return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
>> > > > > - } else if (INTEL_GEN(uncore->i915) <= 8) {
>> > > > > + } else if (GRAPHICS_VER(uncore->i915) <= 8) {
>> > > > > /*
>> > > > > * PRMs say:
>> > > > > *
>> > > > > @@ -94,7 +94,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> > > > > * rolling over every 1.5 hours).
>> > > > > */
>> > > > > return f12_5_mhz;
>> > > > > - } else if (INTEL_GEN(uncore->i915) <= 9) {
>> > > > > + } else if (GRAPHICS_VER(uncore->i915) <= 9) {
>> > > > > u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
>> > > > > u32 freq = 0;
>> > > > >
>> > > > > @@ -113,7 +113,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> > > > > }
>> > > > >
>> > > > > return freq;
>> > > > > - } else if (INTEL_GEN(uncore->i915) <= 12) {
>> > > > > + } else if (GRAPHICS_VER(uncore->i915) <= 12) {
>> > > > > u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
>> > > > > u32 freq = 0;
>> > > > >
>> > > > > @@ -128,7 +128,7 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
>> > > > > } else {
>> > > > > u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
>> > > > >
>> > > > > - if (INTEL_GEN(uncore->i915) <= 10)
>> > > > > + if (GRAPHICS_VER(uncore->i915) <= 10)
>> > > > > freq = gen10_get_crystal_clock_freq(uncore, c0);
>> > > > > else
>> > > > > freq = gen11_get_crystal_clock_freq(uncore, c0);
>> > > > > @@ -211,7 +211,7 @@ u64 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u64 ns)
>> > > > > * frozen machine.
>> > > > > */
>> > > > > val = div_u64_roundup(intel_gt_ns_to_clock_interval(gt, ns), 16);
>> > > > > - if (IS_GEN(gt->i915, 6))
>> > > > > + if (GRAPHICS_VER(gt->i915) == 6)
>> > > > > val = div_u64_roundup(val, 25) * 25;
>> > > > >
>> > > > > return val;
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> > > > > index d29126c458ba..1ec63cceabf6 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> > > > > @@ -395,7 +395,7 @@ void gen5_gt_irq_reset(struct intel_gt *gt)
>> > > > > struct intel_uncore *uncore = gt->uncore;
>> > > > >
>> > > > > GEN3_IRQ_RESET(uncore, GT);
>> > > > > - if (INTEL_GEN(gt->i915) >= 6)
>> > > > > + if (GRAPHICS_VER(gt->i915) >= 6)
>> > > > > GEN3_IRQ_RESET(uncore, GEN6_PM);
>> > > > > }
>> > > > >
>> > > > > @@ -413,14 +413,14 @@ void gen5_gt_irq_postinstall(struct intel_gt *gt)
>> > > > > }
>> > > > >
>> > > > > gt_irqs |= GT_RENDER_USER_INTERRUPT;
>> > > > > - if (IS_GEN(gt->i915, 5))
>> > > > > + if (GRAPHICS_VER(gt->i915) == 5)
>> > > > > gt_irqs |= ILK_BSD_USER_INTERRUPT;
>> > > > > else
>> > > > > gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
>> > > > >
>> > > > > GEN3_IRQ_INIT(uncore, GT, gt->gt_imr, gt_irqs);
>> > > > >
>> > > > > - if (INTEL_GEN(gt->i915) >= 6) {
>> > > > > + if (GRAPHICS_VER(gt->i915) >= 6) {
>> > > > > /*
>> > > > > * RPS interrupts will get enabled/disabled on demand when RPS
>> > > > > * itself is enabled/disabled.
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
>> > > > > index 811a11ed181c..fe51f894b073 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c
>> > > > > @@ -16,10 +16,10 @@ static void write_pm_imr(struct intel_gt *gt)
>> > > > > u32 mask = gt->pm_imr;
>> > > > > i915_reg_t reg;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 11) {
>> > > > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > > > reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
>> > > > > mask <<= 16; /* pm is in upper half */
>> > > > > - } else if (INTEL_GEN(i915) >= 8) {
>> > > > > + } else if (GRAPHICS_VER(i915) >= 8) {
>> > > > > reg = GEN8_GT_IMR(2);
>> > > > > } else {
>> > > > > reg = GEN6_PMIMR;
>> > > > > @@ -61,7 +61,7 @@ void gen6_gt_pm_mask_irq(struct intel_gt *gt, u32 mask)
>> > > > > void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask)
>> > > > > {
>> > > > > struct intel_uncore *uncore = gt->uncore;
>> > > > > - i915_reg_t reg = INTEL_GEN(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
>> > > > > + i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
>> > > > >
>> > > > > lockdep_assert_held(>->irq_lock);
>> > > > >
>> > > > > @@ -77,10 +77,10 @@ static void write_pm_ier(struct intel_gt *gt)
>> > > > > u32 mask = gt->pm_ier;
>> > > > > i915_reg_t reg;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 11) {
>> > > > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > > > reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
>> > > > > mask <<= 16; /* pm is in upper half */
>> > > > > - } else if (INTEL_GEN(i915) >= 8) {
>> > > > > + } else if (GRAPHICS_VER(i915) >= 8) {
>> > > > > reg = GEN8_GT_IER(2);
>> > > > > } else {
>> > > > > reg = GEN6_PMIER;
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
>> > > > > index 9b98f9d9faa3..b9c9993573ec 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
>> > > > > @@ -327,7 +327,7 @@ void gtt_write_workarounds(struct intel_gt *gt)
>> > > > > intel_uncore_write(uncore,
>> > > > > GEN8_L3_LRA_1_GPGPU,
>> > > > > GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
>> > > > > - else if (INTEL_GEN(i915) >= 9 && INTEL_GEN(i915) <= 11)
>> > > > > + else if (GRAPHICS_VER(i915) >= 9 && GRAPHICS_VER(i915) <= 11)
>> > > > > intel_uncore_write(uncore,
>> > > > > GEN8_L3_LRA_1_GPGPU,
>> > > > > GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>> > > > > @@ -344,13 +344,13 @@ void gtt_write_workarounds(struct intel_gt *gt)
>> > > > > * driver.
>> > > > > */
>> > > > > if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
>> > > > > - INTEL_GEN(i915) <= 10)
>> > > > > + GRAPHICS_VER(i915) <= 10)
>> > > > > intel_uncore_rmw(uncore,
>> > > > > GEN8_GAMW_ECO_DEV_RW_IA,
>> > > > > 0,
>> > > > > GAMW_ECO_ENABLE_64K_IPS_FIELD);
>> > > > >
>> > > > > - if (IS_GEN_RANGE(i915, 8, 11)) {
>> > > > > + if (IS_GRAPHICS_VER(i915, 8, 11)) {
>> > > > > bool can_use_gtt_cache = true;
>> > > > >
>> > > > > /*
>> > > > > @@ -432,7 +432,7 @@ static void bdw_setup_private_ppat(struct intel_uncore *uncore)
>> > > > > GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
>> > > > >
>> > > > > /* for scanout with eLLC */
>> > > > > - if (INTEL_GEN(i915) >= 9)
>> > > > > + if (GRAPHICS_VER(i915) >= 9)
>> > > > > pat |= GEN8_PPAT(2, GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE);
>> > > > > else
>> > > > > pat |= GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
>> > > > > @@ -481,11 +481,11 @@ void setup_private_pat(struct intel_uncore *uncore)
>> > > > > {
>> > > > > struct drm_i915_private *i915 = uncore->i915;
>> > > > >
>> > > > > - GEM_BUG_ON(INTEL_GEN(i915) < 8);
>> > > > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 12)
>> > > > > + if (GRAPHICS_VER(i915) >= 12)
>> > > > > tgl_setup_private_ppat(uncore);
>> > > > > - else if (INTEL_GEN(i915) >= 10)
>> > > > > + else if (GRAPHICS_VER(i915) >= 10)
>> > > > > cnl_setup_private_ppat(uncore);
>> > > > > else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))
>> > > > > chv_setup_private_ppat(uncore);
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
>> > > > > index 075d741644ae..eb1a15deed22 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_llc.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_llc.c
>> > > > > @@ -64,7 +64,7 @@ static bool get_ia_constants(struct intel_llc *llc,
>> > > > >
>> > > > > consts->min_gpu_freq = rps->min_freq;
>> > > > > consts->max_gpu_freq = rps->max_freq;
>> > > > > - if (INTEL_GEN(i915) >= 9) {
>> > > > > + if (GRAPHICS_VER(i915) >= 9) {
>> > > > > /* Convert GT frequency to 50 HZ units */
>> > > > > consts->min_gpu_freq /= GEN9_FREQ_SCALER;
>> > > > > consts->max_gpu_freq /= GEN9_FREQ_SCALER;
>> > > > > @@ -83,13 +83,13 @@ static void calc_ia_freq(struct intel_llc *llc,
>> > > > > const int diff = consts->max_gpu_freq - gpu_freq;
>> > > > > unsigned int ia_freq = 0, ring_freq = 0;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 9) {
>> > > > > + if (GRAPHICS_VER(i915) >= 9) {
>> > > > > /*
>> > > > > * ring_freq = 2 * GT. ring_freq is in 100MHz units
>> > > > > * No floor required for ring frequency on SKL.
>> > > > > */
>> > > > > ring_freq = gpu_freq;
>> > > > > - } else if (INTEL_GEN(i915) >= 8) {
>> > > > > + } else if (GRAPHICS_VER(i915) >= 8) {
>> > > > > /* max(2 * GT, DDR). NB: GT is 50MHz units */
>> > > > > ring_freq = max(consts->min_ring_freq, gpu_freq);
>> > > > > } else if (IS_HASWELL(i915)) {
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > > > > index aafe2a4df496..a27bac0a4bfb 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > > > > @@ -47,7 +47,7 @@ static void set_offsets(u32 *regs,
>> > > > > *regs = MI_LOAD_REGISTER_IMM(count);
>> > > > > if (flags & POSTED)
>> > > > > *regs |= MI_LRI_FORCE_POSTED;
>> > > > > - if (INTEL_GEN(engine->i915) >= 11)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 11)
>> > > > > *regs |= MI_LRI_LRM_CS_MMIO;
>> > > > > regs++;
>> > > > >
>> > > > > @@ -70,7 +70,7 @@ static void set_offsets(u32 *regs,
>> > > > > if (close) {
>> > > > > /* Close the batch; used mainly by live_lrc_layout() */
>> > > > > *regs = MI_BATCH_BUFFER_END;
>> > > > > - if (INTEL_GEN(engine->i915) >= 10)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 10)
>> > > > > *regs |= BIT(0);
>> > > > > }
>> > > > > }
>> > > > > @@ -498,22 +498,22 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
>> > > > > * addressing to automatic fixup the register state between the
>> > > > > * physical engines for virtual engine.
>> > > > > */
>> > > > > - GEM_BUG_ON(INTEL_GEN(engine->i915) >= 12 &&
>> > > > > + GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
>> > > > > !intel_engine_has_relative_mmio(engine));
>> > > > >
>> > > > > if (engine->class == RENDER_CLASS) {
>> > > > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > > > return gen12_rcs_offsets;
>> > > > > - else if (INTEL_GEN(engine->i915) >= 11)
>> > > > > + else if (GRAPHICS_VER(engine->i915) >= 11)
>> > > > > return gen11_rcs_offsets;
>> > > > > - else if (INTEL_GEN(engine->i915) >= 9)
>> > > > > + else if (GRAPHICS_VER(engine->i915) >= 9)
>> > > > > return gen9_rcs_offsets;
>> > > > > else
>> > > > > return gen8_rcs_offsets;
>> > > > > } else {
>> > > > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > > > return gen12_xcs_offsets;
>> > > > > - else if (INTEL_GEN(engine->i915) >= 9)
>> > > > > + else if (GRAPHICS_VER(engine->i915) >= 9)
>> > > > > return gen9_xcs_offsets;
>> > > > > else
>> > > > > return gen8_xcs_offsets;
>> > > > > @@ -522,9 +522,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
>> > > > >
>> > > > > static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
>> > > > > {
>> > > > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > > > return 0x60;
>> > > > > - else if (INTEL_GEN(engine->i915) >= 9)
>> > > > > + else if (GRAPHICS_VER(engine->i915) >= 9)
>> > > > > return 0x54;
>> > > > > else if (engine->class == RENDER_CLASS)
>> > > > > return 0x58;
>> > > > > @@ -534,9 +534,9 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
>> > > > >
>> > > > > static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
>> > > > > {
>> > > > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > > > return 0x74;
>> > > > > - else if (INTEL_GEN(engine->i915) >= 9)
>> > > > > + else if (GRAPHICS_VER(engine->i915) >= 9)
>> > > > > return 0x68;
>> > > > > else if (engine->class == RENDER_CLASS)
>> > > > > return 0xd8;
>> > > > > @@ -546,9 +546,9 @@ static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
>> > > > >
>> > > > > static int lrc_ring_wa_bb_per_ctx(const struct intel_engine_cs *engine)
>> > > > > {
>> > > > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > > > return 0x12;
>> > > > > - else if (INTEL_GEN(engine->i915) >= 9 || engine->class == RENDER_CLASS)
>> > > > > + else if (GRAPHICS_VER(engine->i915) >= 9 || engine->class == RENDER_CLASS)
>> > > > > return 0x18;
>> > > > > else
>> > > > > return -1;
>> > > > > @@ -581,9 +581,9 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
>> > > > > if (engine->class != RENDER_CLASS)
>> > > > > return -1;
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) >= 12)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 12)
>> > > > > return 0xb6;
>> > > > > - else if (INTEL_GEN(engine->i915) >= 11)
>> > > > > + else if (GRAPHICS_VER(engine->i915) >= 11)
>> > > > > return 0xaa;
>> > > > > else
>> > > > > return -1;
>> > > > > @@ -592,9 +592,9 @@ static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
>> > > > > static u32
>> > > > > lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
>> > > > > {
>> > > > > - switch (INTEL_GEN(engine->i915)) {
>> > > > > + switch (GRAPHICS_VER(engine->i915)) {
>> > > > > default:
>> > > > > - MISSING_CASE(INTEL_GEN(engine->i915));
>> > > > > + MISSING_CASE(GRAPHICS_VER(engine->i915));
>> > > > > fallthrough;
>> > > > > case 12:
>> > > > > return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
>> > > > > @@ -637,7 +637,7 @@ static void init_common_regs(u32 * const regs,
>> > > > > ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
>> > > > > if (inhibit)
>> > > > > ctl |= CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT;
>> > > > > - if (INTEL_GEN(engine->i915) < 11)
>> > > > > + if (GRAPHICS_VER(engine->i915) < 11)
>> > > > > ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
>> > > > > CTX_CTRL_RS_CTX_ENABLE);
>> > > > > regs[CTX_CONTEXT_CONTROL] = ctl;
>> > > > > @@ -805,7 +805,7 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
>> > > > > if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
>> > > > > context_size += I915_GTT_PAGE_SIZE; /* for redzone */
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) == 12) {
>> > > > > + if (GRAPHICS_VER(engine->i915) == 12) {
>> > > > > ce->wa_bb_page = context_size / PAGE_SIZE;
>> > > > > context_size += PAGE_SIZE;
>> > > > > }
>> > > > > @@ -1114,7 +1114,7 @@ static u32 lrc_descriptor(const struct intel_context *ce)
>> > > > > desc <<= GEN8_CTX_ADDRESSING_MODE_SHIFT;
>> > > > >
>> > > > > desc |= GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
>> > > > > - if (IS_GEN(ce->vm->i915, 8))
>> > > > > + if (GRAPHICS_VER(ce->vm->i915) == 8)
>> > > > > desc |= GEN8_CTX_L3LLC_COHERENT;
>> > > > >
>> > > > > return i915_ggtt_offset(ce->state) | desc;
>> > > > > @@ -1469,7 +1469,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
>> > > > > if (engine->class != RENDER_CLASS)
>> > > > > return;
>> > > > >
>> > > > > - switch (INTEL_GEN(engine->i915)) {
>> > > > > + switch (GRAPHICS_VER(engine->i915)) {
>> > > > > case 12:
>> > > > > case 11:
>> > > > > return;
>> > > > > @@ -1486,7 +1486,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
>> > > > > wa_bb_fn[1] = NULL;
>> > > > > break;
>> > > > > default:
>> > > > > - MISSING_CASE(INTEL_GEN(engine->i915));
>> > > > > + MISSING_CASE(GRAPHICS_VER(engine->i915));
>> > > > > return;
>> > > > > }
>> > > > >
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
>> > > > > index b14138fd505c..17848807f111 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
>> > > > > @@ -344,11 +344,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>> > > > > table->size = ARRAY_SIZE(dg1_mocs_table);
>> > > > > table->table = dg1_mocs_table;
>> > > > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>> > > > > - } else if (INTEL_GEN(i915) >= 12) {
>> > > > > + } else if (GRAPHICS_VER(i915) >= 12) {
>> > > > > table->size = ARRAY_SIZE(tgl_mocs_table);
>> > > > > table->table = tgl_mocs_table;
>> > > > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>> > > > > - } else if (IS_GEN(i915, 11)) {
>> > > > > + } else if (GRAPHICS_VER(i915) == 11) {
>> > > > > table->size = ARRAY_SIZE(icl_mocs_table);
>> > > > > table->table = icl_mocs_table;
>> > > > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>> > > > > @@ -361,7 +361,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>> > > > > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>> > > > > table->table = broxton_mocs_table;
>> > > > > } else {
>> > > > > - drm_WARN_ONCE(&i915->drm, INTEL_GEN(i915) >= 9,
>> > > > > + drm_WARN_ONCE(&i915->drm, GRAPHICS_VER(i915) >= 9,
>> > > > > "Platform that should have a MOCS table does not.\n");
>> > > > > return 0;
>> > > > > }
>> > > > > @@ -370,7 +370,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>> > > > > return 0;
>> > > > >
>> > > > > /* WaDisableSkipCaching:skl,bxt,kbl,glk */
>> > > > > - if (IS_GEN(i915, 9)) {
>> > > > > + if (GRAPHICS_VER(i915) == 9) {
>> > > > > int i;
>> > > > >
>> > > > > for (i = 0; i < table->size; i++)
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>> > > > > index 4e3d80c2295c..3891c078906e 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
>> > > > > @@ -146,9 +146,9 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
>> > > > >
>> > > > > gtt_write_workarounds(gt);
>> > > > >
>> > > > > - if (IS_GEN(i915, 6))
>> > > > > + if (GRAPHICS_VER(i915) == 6)
>> > > > > gen6_ppgtt_enable(gt);
>> > > > > - else if (IS_GEN(i915, 7))
>> > > > > + else if (GRAPHICS_VER(i915) == 7)
>> > > > > gen7_ppgtt_enable(gt);
>> > > > >
>> > > > > return 0;
>> > > > > @@ -157,7 +157,7 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
>> > > > > static struct i915_ppgtt *
>> > > > > __ppgtt_create(struct intel_gt *gt)
>> > > > > {
>> > > > > - if (INTEL_GEN(gt->i915) < 8)
>> > > > > + if (GRAPHICS_VER(gt->i915) < 8)
>> > > > > return gen6_ppgtt_create(gt);
>> > > > > else
>> > > > > return gen8_ppgtt_create(gt);
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
>> > > > > index 3b7e62debe7e..259d7eb4e165 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>> > > > > @@ -109,7 +109,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
>> > > > > GEN9_MEDIA_PG_ENABLE |
>> > > > > GEN11_MEDIA_SAMPLER_PG_ENABLE;
>> > > > >
>> > > > > - if (INTEL_GEN(gt->i915) >= 12) {
>> > > > > + if (GRAPHICS_VER(gt->i915) >= 12) {
>> > > > > for (i = 0; i < I915_MAX_VCS; i++)
>> > > > > if (HAS_ENGINE(gt, _VCS(i)))
>> > > > > pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
>> > > > > @@ -126,7 +126,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
>> > > > > enum intel_engine_id id;
>> > > > >
>> > > > > /* 2b: Program RC6 thresholds.*/
>> > > > > - if (INTEL_GEN(rc6_to_i915(rc6)) >= 10) {
>> > > > > + if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 10) {
>> > > > > set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
>> > > > > set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
>> > > > > } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
>> > > > > @@ -249,9 +249,9 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
>> > > > > rc6vids = 0;
>> > > > > ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
>> > > > > &rc6vids, NULL);
>> > > > > - if (IS_GEN(i915, 6) && ret) {
>> > > > > + if (GRAPHICS_VER(i915) == 6 && ret) {
>> > > > > drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
>> > > > > - } else if (IS_GEN(i915, 6) &&
>> > > > > + } else if (GRAPHICS_VER(i915) == 6 &&
>> > > > > (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
>> > > > > drm_dbg(&i915->drm,
>> > > > > "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
>> > > > > @@ -515,7 +515,7 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
>> > > > > struct intel_uncore *uncore = rc6_to_uncore(rc6);
>> > > > >
>> > > > > intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>> > > > > - if (INTEL_GEN(i915) >= 9)
>> > > > > + if (GRAPHICS_VER(i915) >= 9)
>> > > > > set(uncore, GEN9_PG_ENABLE, 0);
>> > > > > set(uncore, GEN6_RC_CONTROL, 0);
>> > > > > set(uncore, GEN6_RC_STATE, 0);
>> > > > > @@ -575,13 +575,13 @@ void intel_rc6_enable(struct intel_rc6 *rc6)
>> > > > > chv_rc6_enable(rc6);
>> > > > > else if (IS_VALLEYVIEW(i915))
>> > > > > vlv_rc6_enable(rc6);
>> > > > > - else if (INTEL_GEN(i915) >= 11)
>> > > > > + else if (GRAPHICS_VER(i915) >= 11)
>> > > > > gen11_rc6_enable(rc6);
>> > > > > - else if (INTEL_GEN(i915) >= 9)
>> > > > > + else if (GRAPHICS_VER(i915) >= 9)
>> > > > > gen9_rc6_enable(rc6);
>> > > > > else if (IS_BROADWELL(i915))
>> > > > > gen8_rc6_enable(rc6);
>> > > > > - else if (INTEL_GEN(i915) >= 6)
>> > > > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > > > gen6_rc6_enable(rc6);
>> > > > >
>> > > > > rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE;
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
>> > > > > index b03e197b1d99..b575cd6e0b7a 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
>> > > > > @@ -15,7 +15,7 @@ render_state_get_rodata(const struct intel_engine_cs *engine)
>> > > > > if (engine->class != RENDER_CLASS)
>> > > > > return NULL;
>> > > > >
>> > > > > - switch (INTEL_GEN(engine->i915)) {
>> > > > > + switch (GRAPHICS_VER(engine->i915)) {
>> > > > > case 6:
>> > > > > return &gen6_null_state;
>> > > > > case 7:
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
>> > > > > index d5094be6d90f..27315d7f8935 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>> > > > > @@ -565,7 +565,7 @@ static int gen8_reset_engines(struct intel_gt *gt,
>> > > > > */
>> > > > > }
>> > > > >
>> > > > > - if (INTEL_GEN(gt->i915) >= 11)
>> > > > > + if (GRAPHICS_VER(gt->i915) >= 11)
>> > > > > ret = gen11_reset_engines(gt, engine_mask, retry);
>> > > > > else
>> > > > > ret = gen6_reset_engines(gt, engine_mask, retry);
>> > > > > @@ -594,17 +594,17 @@ static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
>> > > > >
>> > > > > if (is_mock_gt(gt))
>> > > > > return mock_reset;
>> > > > > - else if (INTEL_GEN(i915) >= 8)
>> > > > > + else if (GRAPHICS_VER(i915) >= 8)
>> > > > > return gen8_reset_engines;
>> > > > > - else if (INTEL_GEN(i915) >= 6)
>> > > > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > > > return gen6_reset_engines;
>> > > > > - else if (INTEL_GEN(i915) >= 5)
>> > > > > + else if (GRAPHICS_VER(i915) >= 5)
>> > > > > return ilk_do_reset;
>> > > > > else if (IS_G4X(i915))
>> > > > > return g4x_do_reset;
>> > > > > else if (IS_G33(i915) || IS_PINEVIEW(i915))
>> > > > > return g33_do_reset;
>> > > > > - else if (INTEL_GEN(i915) >= 3)
>> > > > > + else if (GRAPHICS_VER(i915) >= 3)
>> > > > > return i915_do_reset;
>> > > > > else
>> > > > > return NULL;
>> > > > > @@ -656,7 +656,7 @@ bool intel_has_reset_engine(const struct intel_gt *gt)
>> > > > > int intel_reset_guc(struct intel_gt *gt)
>> > > > > {
>> > > > > u32 guc_domain =
>> > > > > - INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
>> > > > > + GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
>> > > > > int ret;
>> > > > >
>> > > > > GEM_BUG_ON(!HAS_GT_UC(gt->i915));
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> > > > > index 2b6dffcc2262..0c423f096e2b 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> > > > > @@ -29,7 +29,7 @@ static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
>> > > > > * lost interrupts following a reset.
>> > > > > */
>> > > > > if (engine->class == RENDER_CLASS) {
>> > > > > - if (INTEL_GEN(engine->i915) >= 6)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 6)
>> > > > > mask &= ~BIT(0);
>> > > > > else
>> > > > > mask &= ~I915_USER_INTERRUPT;
>> > > > > @@ -43,7 +43,7 @@ static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
>> > > > > u32 addr;
>> > > > >
>> > > > > addr = lower_32_bits(phys);
>> > > > > - if (INTEL_GEN(engine->i915) >= 4)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 4)
>> > > > > addr |= (phys >> 28) & 0xf0;
>> > > > >
>> > > > > intel_uncore_write(engine->uncore, HWS_PGA, addr);
>> > > > > @@ -71,7 +71,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
>> > > > > * The ring status page addresses are no longer next to the rest of
>> > > > > * the ring registers as of gen7.
>> > > > > */
>> > > > > - if (IS_GEN(engine->i915, 7)) {
>> > > > > + if (GRAPHICS_VER(engine->i915) == 7) {
>> > > > > switch (engine->id) {
>> > > > > /*
>> > > > > * No more rings exist on Gen7. Default case is only to shut up
>> > > > > @@ -93,7 +93,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
>> > > > > hwsp = VEBOX_HWS_PGA_GEN7;
>> > > > > break;
>> > > > > }
>> > > > > - } else if (IS_GEN(engine->i915, 6)) {
>> > > > > + } else if (GRAPHICS_VER(engine->i915) == 6) {
>> > > > > hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
>> > > > > } else {
>> > > > > hwsp = RING_HWS_PGA(engine->mmio_base);
>> > > > > @@ -105,7 +105,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
>> > > > >
>> > > > > static void flush_cs_tlb(struct intel_engine_cs *engine)
>> > > > > {
>> > > > > - if (!IS_GEN_RANGE(engine->i915, 6, 7))
>> > > > > + if (!IS_GRAPHICS_VER(engine->i915, 6, 7))
>> > > > > return;
>> > > > >
>> > > > > /* ring should be idle before issuing a sync flush*/
>> > > > > @@ -153,7 +153,7 @@ static void set_pp_dir(struct intel_engine_cs *engine)
>> > > > > ENGINE_WRITE_FW(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
>> > > > > ENGINE_WRITE_FW(engine, RING_PP_DIR_BASE, pp_dir(vm));
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) >= 7) {
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 7) {
>> > > > > ENGINE_WRITE_FW(engine,
>> > > > > RING_MODE_GEN7,
>> > > > > _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
>> > > > > @@ -229,7 +229,7 @@ static int xcs_resume(struct intel_engine_cs *engine)
>> > > > > 5000, 0, NULL))
>> > > > > goto err;
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) > 2)
>> > > > > + if (GRAPHICS_VER(engine->i915) > 2)
>> > > > > ENGINE_WRITE_FW(engine,
>> > > > > RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
>> > > > >
>> > > > > @@ -646,9 +646,9 @@ static int mi_set_context(struct i915_request *rq,
>> > > > > u32 *cs;
>> > > > >
>> > > > > len = 4;
>> > > > > - if (IS_GEN(i915, 7))
>> > > > > + if (GRAPHICS_VER(i915) == 7)
>> > > > > len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
>> > > > > - else if (IS_GEN(i915, 5))
>> > > > > + else if (GRAPHICS_VER(i915) == 5)
>> > > > > len += 2;
>> > > > > if (flags & MI_FORCE_RESTORE) {
>> > > > > GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
>> > > > > @@ -662,7 +662,7 @@ static int mi_set_context(struct i915_request *rq,
>> > > > > return PTR_ERR(cs);
>> > > > >
>> > > > > /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
>> > > > > - if (IS_GEN(i915, 7)) {
>> > > > > + if (GRAPHICS_VER(i915) == 7) {
>> > > > > *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
>> > > > > if (num_engines) {
>> > > > > struct intel_engine_cs *signaller;
>> > > > > @@ -678,7 +678,7 @@ static int mi_set_context(struct i915_request *rq,
>> > > > > GEN6_PSMI_SLEEP_MSG_DISABLE);
>> > > > > }
>> > > > > }
>> > > > > - } else if (IS_GEN(i915, 5)) {
>> > > > > + } else if (GRAPHICS_VER(i915) == 5) {
>> > > > > /*
>> > > > > * This w/a is only listed for pre-production ilk a/b steppings,
>> > > > > * but is also mentioned for programming the powerctx. To be
>> > > > > @@ -716,7 +716,7 @@ static int mi_set_context(struct i915_request *rq,
>> > > > > */
>> > > > > *cs++ = MI_NOOP;
>> > > > >
>> > > > > - if (IS_GEN(i915, 7)) {
>> > > > > + if (GRAPHICS_VER(i915) == 7) {
>> > > > > if (num_engines) {
>> > > > > struct intel_engine_cs *signaller;
>> > > > > i915_reg_t last_reg = {}; /* keep gcc quiet */
>> > > > > @@ -740,7 +740,7 @@ static int mi_set_context(struct i915_request *rq,
>> > > > > *cs++ = MI_NOOP;
>> > > > > }
>> > > > > *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
>> > > > > - } else if (IS_GEN(i915, 5)) {
>> > > > > + } else if (GRAPHICS_VER(i915) == 5) {
>> > > > > *cs++ = MI_SUSPEND_FLUSH;
>> > > > > }
>> > > > >
>> > > > > @@ -1001,7 +1001,7 @@ static void ring_release(struct intel_engine_cs *engine)
>> > > > > {
>> > > > > struct drm_i915_private *dev_priv = engine->i915;
>> > > > >
>> > > > > - drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) > 2 &&
>> > > > > + drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) > 2 &&
>> > > > > (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
>> > > > >
>> > > > > intel_engine_cleanup_common(engine);
>> > > > > @@ -1029,13 +1029,13 @@ static void setup_irq(struct intel_engine_cs *engine)
>> > > > >
>> > > > > intel_engine_set_irq_handler(engine, irq_handler);
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 6) {
>> > > > > + if (GRAPHICS_VER(i915) >= 6) {
>> > > > > engine->irq_enable = gen6_irq_enable;
>> > > > > engine->irq_disable = gen6_irq_disable;
>> > > > > - } else if (INTEL_GEN(i915) >= 5) {
>> > > > > + } else if (GRAPHICS_VER(i915) >= 5) {
>> > > > > engine->irq_enable = gen5_irq_enable;
>> > > > > engine->irq_disable = gen5_irq_disable;
>> > > > > - } else if (INTEL_GEN(i915) >= 3) {
>> > > > > + } else if (GRAPHICS_VER(i915) >= 3) {
>> > > > > engine->irq_enable = gen3_irq_enable;
>> > > > > engine->irq_disable = gen3_irq_disable;
>> > > > > } else {
>> > > > > @@ -1049,7 +1049,7 @@ static void setup_common(struct intel_engine_cs *engine)
>> > > > > struct drm_i915_private *i915 = engine->i915;
>> > > > >
>> > > > > /* gen8+ are only supported with execlists */
>> > > > > - GEM_BUG_ON(INTEL_GEN(i915) >= 8);
>> > > > > + GEM_BUG_ON(GRAPHICS_VER(i915) >= 8);
>> > > > >
>> > > > > setup_irq(engine);
>> > > > >
>> > > > > @@ -1070,14 +1070,14 @@ static void setup_common(struct intel_engine_cs *engine)
>> > > > > * engine->emit_init_breadcrumb().
>> > > > > */
>> > > > > engine->emit_fini_breadcrumb = gen3_emit_breadcrumb;
>> > > > > - if (IS_GEN(i915, 5))
>> > > > > + if (GRAPHICS_VER(i915) == 5)
>> > > > > engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
>> > > > >
>> > > > > engine->set_default_submission = i9xx_set_default_submission;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 6)
>> > > > > + if (GRAPHICS_VER(i915) >= 6)
>> > > > > engine->emit_bb_start = gen6_emit_bb_start;
>> > > > > - else if (INTEL_GEN(i915) >= 4)
>> > > > > + else if (GRAPHICS_VER(i915) >= 4)
>> > > > > engine->emit_bb_start = gen4_emit_bb_start;
>> > > > > else if (IS_I830(i915) || IS_I845G(i915))
>> > > > > engine->emit_bb_start = i830_emit_bb_start;
>> > > > > @@ -1094,16 +1094,16 @@ static void setup_rcs(struct intel_engine_cs *engine)
>> > > > >
>> > > > > engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 7) {
>> > > > > + if (GRAPHICS_VER(i915) >= 7) {
>> > > > > engine->emit_flush = gen7_emit_flush_rcs;
>> > > > > engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs;
>> > > > > - } else if (IS_GEN(i915, 6)) {
>> > > > > + } else if (GRAPHICS_VER(i915) == 6) {
>> > > > > engine->emit_flush = gen6_emit_flush_rcs;
>> > > > > engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs;
>> > > > > - } else if (IS_GEN(i915, 5)) {
>> > > > > + } else if (GRAPHICS_VER(i915) == 5) {
>> > > > > engine->emit_flush = gen4_emit_flush_rcs;
>> > > > > } else {
>> > > > > - if (INTEL_GEN(i915) < 4)
>> > > > > + if (GRAPHICS_VER(i915) < 4)
>> > > > > engine->emit_flush = gen2_emit_flush;
>> > > > > else
>> > > > > engine->emit_flush = gen4_emit_flush_rcs;
>> > > > > @@ -1118,20 +1118,20 @@ static void setup_vcs(struct intel_engine_cs *engine)
>> > > > > {
>> > > > > struct drm_i915_private *i915 = engine->i915;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 6) {
>> > > > > + if (GRAPHICS_VER(i915) >= 6) {
>> > > > > /* gen6 bsd needs a special wa for tail updates */
>> > > > > - if (IS_GEN(i915, 6))
>> > > > > + if (GRAPHICS_VER(i915) == 6)
>> > > > > engine->set_default_submission = gen6_bsd_set_default_submission;
>> > > > > engine->emit_flush = gen6_emit_flush_vcs;
>> > > > > engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
>> > > > >
>> > > > > - if (IS_GEN(i915, 6))
>> > > > > + if (GRAPHICS_VER(i915) == 6)
>> > > > > engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
>> > > > > else
>> > > > > engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
>> > > > > } else {
>> > > > > engine->emit_flush = gen4_emit_flush_vcs;
>> > > > > - if (IS_GEN(i915, 5))
>> > > > > + if (GRAPHICS_VER(i915) == 5)
>> > > > > engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
>> > > > > else
>> > > > > engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
>> > > > > @@ -1145,7 +1145,7 @@ static void setup_bcs(struct intel_engine_cs *engine)
>> > > > > engine->emit_flush = gen6_emit_flush_xcs;
>> > > > > engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
>> > > > >
>> > > > > - if (IS_GEN(i915, 6))
>> > > > > + if (GRAPHICS_VER(i915) == 6)
>> > > > > engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
>> > > > > else
>> > > > > engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
>> > > > > @@ -1155,7 +1155,7 @@ static void setup_vecs(struct intel_engine_cs *engine)
>> > > > > {
>> > > > > struct drm_i915_private *i915 = engine->i915;
>> > > > >
>> > > > > - GEM_BUG_ON(INTEL_GEN(i915) < 7);
>> > > > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 7);
>> > > > >
>> > > > > engine->emit_flush = gen6_emit_flush_xcs;
>> > > > > engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
>> > > > > @@ -1203,7 +1203,7 @@ static struct i915_vma *gen7_ctx_vma(struct intel_engine_cs *engine)
>> > > > > struct i915_vma *vma;
>> > > > > int size, err;
>> > > > >
>> > > > > - if (!IS_GEN(engine->i915, 7) || engine->class != RENDER_CLASS)
>> > > > > + if (GRAPHICS_VER(engine->i915) != 7 || engine->class != RENDER_CLASS)
>> > > > > return 0;
>> > > > >
>> > > > > err = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */);
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
>> > > > > index 97cab1b99871..06e9a8ed4e03 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_rps.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
>> > > > > @@ -196,7 +196,7 @@ static void rps_reset_interrupts(struct intel_rps *rps)
>> > > > > struct intel_gt *gt = rps_to_gt(rps);
>> > > > >
>> > > > > spin_lock_irq(>->irq_lock);
>> > > > > - if (INTEL_GEN(gt->i915) >= 11)
>> > > > > + if (GRAPHICS_VER(gt->i915) >= 11)
>> > > > > gen11_rps_reset_interrupts(rps);
>> > > > > else
>> > > > > gen6_rps_reset_interrupts(rps);
>> > > > > @@ -630,7 +630,7 @@ static u32 rps_limits(struct intel_rps *rps, u8 val)
>> > > > > * frequency, if the down threshold expires in that window we will not
>> > > > > * receive a down interrupt.
>> > > > > */
>> > > > > - if (INTEL_GEN(rps_to_i915(rps)) >= 9) {
>> > > > > + if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) {
>> > > > > limits = rps->max_freq_softlimit << 23;
>> > > > > if (val <= rps->min_freq_softlimit)
>> > > > > limits |= rps->min_freq_softlimit << 14;
>> > > > > @@ -697,7 +697,7 @@ static void rps_set_power(struct intel_rps *rps, int new_power)
>> > > > > intel_gt_ns_to_pm_interval(gt, ei_down * threshold_down * 10));
>> > > > >
>> > > > > set(uncore, GEN6_RP_CONTROL,
>> > > > > - (INTEL_GEN(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
>> > > > > + (GRAPHICS_VER(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
>> > > > > GEN6_RP_MEDIA_HW_NORMAL_MODE |
>> > > > > GEN6_RP_MEDIA_IS_GFX |
>> > > > > GEN6_RP_ENABLE |
>> > > > > @@ -771,7 +771,7 @@ static int gen6_rps_set(struct intel_rps *rps, u8 val)
>> > > > > struct drm_i915_private *i915 = rps_to_i915(rps);
>> > > > > u32 swreq;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 9)
>> > > > > + if (GRAPHICS_VER(i915) >= 9)
>> > > > > swreq = GEN9_FREQUENCY(val);
>> > > > > else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
>> > > > > swreq = HSW_FREQUENCY(val);
>> > > > > @@ -812,14 +812,14 @@ static int rps_set(struct intel_rps *rps, u8 val, bool update)
>> > > > >
>> > > > > if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
>> > > > > err = vlv_rps_set(rps, val);
>> > > > > - else if (INTEL_GEN(i915) >= 6)
>> > > > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > > > err = gen6_rps_set(rps, val);
>> > > > > else
>> > > > > err = gen5_rps_set(rps, val);
>> > > > > if (err)
>> > > > > return err;
>> > > > >
>> > > > > - if (update && INTEL_GEN(i915) >= 6)
>> > > > > + if (update && GRAPHICS_VER(i915) >= 6)
>> > > > > gen6_rps_set_thresholds(rps, val);
>> > > > > rps->last_freq = val;
>> > > > >
>> > > > > @@ -853,7 +853,7 @@ void intel_rps_unpark(struct intel_rps *rps)
>> > > > > if (intel_rps_uses_timer(rps))
>> > > > > rps_start_timer(rps);
>> > > > >
>> > > > > - if (IS_GEN(rps_to_i915(rps), 5))
>> > > > > + if (GRAPHICS_VER(rps_to_i915(rps)) == 5)
>> > > > > gen5_rps_update(rps);
>> > > > > }
>> > > > >
>> > > > > @@ -999,7 +999,7 @@ static void gen6_rps_init(struct intel_rps *rps)
>> > > > >
>> > > > > rps->efficient_freq = rps->rp1_freq;
>> > > > > if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
>> > > > > - IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
>> > > > > + IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
>> > > > > u32 ddcc_status = 0;
>> > > > >
>> > > > > if (sandybridge_pcode_read(i915,
>> > > > > @@ -1012,7 +1012,7 @@ static void gen6_rps_init(struct intel_rps *rps)
>> > > > > rps->max_freq);
>> > > > > }
>> > > > >
>> > > > > - if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
>> > > > > + if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 10) {
>> > > > > /* Store the frequency values in 16.66 MHZ units, which is
>> > > > > * the natural hardware unit for SKL
>> > > > > */
>> > > > > @@ -1048,7 +1048,7 @@ static bool gen9_rps_enable(struct intel_rps *rps)
>> > > > > struct intel_uncore *uncore = gt->uncore;
>> > > > >
>> > > > > /* Program defaults and thresholds for RPS */
>> > > > > - if (IS_GEN(gt->i915, 9))
>> > > > > + if (GRAPHICS_VER(gt->i915) == 9)
>> > > > > intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ,
>> > > > > GEN9_FREQUENCY(rps->rp1_freq));
>> > > > >
>> > > > > @@ -1365,16 +1365,16 @@ void intel_rps_enable(struct intel_rps *rps)
>> > > > > enabled = chv_rps_enable(rps);
>> > > > > else if (IS_VALLEYVIEW(i915))
>> > > > > enabled = vlv_rps_enable(rps);
>> > > > > - else if (INTEL_GEN(i915) >= 9)
>> > > > > + else if (GRAPHICS_VER(i915) >= 9)
>> > > > > enabled = gen9_rps_enable(rps);
>> > > > > - else if (INTEL_GEN(i915) >= 8)
>> > > > > + else if (GRAPHICS_VER(i915) >= 8)
>> > > > > enabled = gen8_rps_enable(rps);
>> > > > > - else if (INTEL_GEN(i915) >= 6)
>> > > > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > > > enabled = gen6_rps_enable(rps);
>> > > > > else if (IS_IRONLAKE_M(i915))
>> > > > > enabled = gen5_rps_enable(rps);
>> > > > > else
>> > > > > - MISSING_CASE(INTEL_GEN(i915));
>> > > > > + MISSING_CASE(GRAPHICS_VER(i915));
>> > > > > intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>> > > > > if (!enabled)
>> > > > > return;
>> > > > > @@ -1393,7 +1393,7 @@ void intel_rps_enable(struct intel_rps *rps)
>> > > > >
>> > > > > if (has_busy_stats(rps))
>> > > > > intel_rps_set_timer(rps);
>> > > > > - else if (INTEL_GEN(i915) >= 6)
>> > > > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > > > intel_rps_set_interrupts(rps);
>> > > > > else
>> > > > > /* Ironlake currently uses intel_ips.ko */ {}
>> > > > > @@ -1414,7 +1414,7 @@ void intel_rps_disable(struct intel_rps *rps)
>> > > > > intel_rps_clear_interrupts(rps);
>> > > > > intel_rps_clear_timer(rps);
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 6)
>> > > > > + if (GRAPHICS_VER(i915) >= 6)
>> > > > > gen6_rps_disable(rps);
>> > > > > else if (IS_IRONLAKE_M(i915))
>> > > > > gen5_rps_disable(rps);
>> > > > > @@ -1453,14 +1453,14 @@ int intel_gpu_freq(struct intel_rps *rps, int val)
>> > > > > {
>> > > > > struct drm_i915_private *i915 = rps_to_i915(rps);
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 9)
>> > > > > + if (GRAPHICS_VER(i915) >= 9)
>> > > > > return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
>> > > > > GEN9_FREQ_SCALER);
>> > > > > else if (IS_CHERRYVIEW(i915))
>> > > > > return chv_gpu_freq(rps, val);
>> > > > > else if (IS_VALLEYVIEW(i915))
>> > > > > return byt_gpu_freq(rps, val);
>> > > > > - else if (INTEL_GEN(i915) >= 6)
>> > > > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > > > return val * GT_FREQUENCY_MULTIPLIER;
>> > > > > else
>> > > > > return val;
>> > > > > @@ -1470,14 +1470,14 @@ int intel_freq_opcode(struct intel_rps *rps, int val)
>> > > > > {
>> > > > > struct drm_i915_private *i915 = rps_to_i915(rps);
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 9)
>> > > > > + if (GRAPHICS_VER(i915) >= 9)
>> > > > > return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
>> > > > > GT_FREQUENCY_MULTIPLIER);
>> > > > > else if (IS_CHERRYVIEW(i915))
>> > > > > return chv_freq_opcode(rps, val);
>> > > > > else if (IS_VALLEYVIEW(i915))
>> > > > > return byt_freq_opcode(rps, val);
>> > > > > - else if (INTEL_GEN(i915) >= 6)
>> > > > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > > > return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
>> > > > > else
>> > > > > return val;
>> > > > > @@ -1770,7 +1770,7 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
>> > > > > spin_unlock(>->irq_lock);
>> > > > > }
>> > > > >
>> > > > > - if (INTEL_GEN(gt->i915) >= 8)
>> > > > > + if (GRAPHICS_VER(gt->i915) >= 8)
>> > > > > return;
>> > > > >
>> > > > > if (pm_iir & PM_VEBOX_USER_INTERRUPT)
>> > > > > @@ -1833,7 +1833,7 @@ void intel_rps_init(struct intel_rps *rps)
>> > > > > chv_rps_init(rps);
>> > > > > else if (IS_VALLEYVIEW(i915))
>> > > > > vlv_rps_init(rps);
>> > > > > - else if (INTEL_GEN(i915) >= 6)
>> > > > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > > > gen6_rps_init(rps);
>> > > > > else if (IS_IRONLAKE_M(i915))
>> > > > > gen5_rps_init(rps);
>> > > > > @@ -1843,7 +1843,7 @@ void intel_rps_init(struct intel_rps *rps)
>> > > > > rps->min_freq_softlimit = rps->min_freq;
>> > > > >
>> > > > > /* After setting max-softlimit, find the overclock max freq */
>> > > > > - if (IS_GEN(i915, 6) || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
>> > > > > + if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
>> > > > > u32 params = 0;
>> > > > >
>> > > > > sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS,
>> > > > > @@ -1872,16 +1872,16 @@ void intel_rps_init(struct intel_rps *rps)
>> > > > > *
>> > > > > * TODO: verify if this can be reproduced on VLV,CHV.
>> > > > > */
>> > > > > - if (INTEL_GEN(i915) <= 7)
>> > > > > + if (GRAPHICS_VER(i915) <= 7)
>> > > > > rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 8 && INTEL_GEN(i915) < 11)
>> > > > > + if (GRAPHICS_VER(i915) >= 8 && GRAPHICS_VER(i915) < 11)
>> > > > > rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
>> > > > > }
>> > > > >
>> > > > > void intel_rps_sanitize(struct intel_rps *rps)
>> > > > > {
>> > > > > - if (INTEL_GEN(rps_to_i915(rps)) >= 6)
>> > > > > + if (GRAPHICS_VER(rps_to_i915(rps)) >= 6)
>> > > > > rps_disable_interrupts(rps);
>> > > > > }
>> > > > >
>> > > > > @@ -1892,11 +1892,11 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
>> > > > >
>> > > > > if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
>> > > > > cagf = (rpstat >> 8) & 0xff;
>> > > > > - else if (INTEL_GEN(i915) >= 9)
>> > > > > + else if (GRAPHICS_VER(i915) >= 9)
>> > > > > cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
>> > > > > else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
>> > > > > cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
>> > > > > - else if (INTEL_GEN(i915) >= 6)
>> > > > > + else if (GRAPHICS_VER(i915) >= 6)
>> > > > > cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
>> > > > > else
>> > > > > cagf = gen5_invert_freq(rps, (rpstat & MEMSTAT_PSTATE_MASK) >>
>> > > > > @@ -1915,7 +1915,7 @@ static u32 read_cagf(struct intel_rps *rps)
>> > > > > vlv_punit_get(i915);
>> > > > > freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
>> > > > > vlv_punit_put(i915);
>> > > > > - } else if (INTEL_GEN(i915) >= 6) {
>> > > > > + } else if (GRAPHICS_VER(i915) >= 6) {
>> > > > > freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
>> > > > > } else {
>> > > > > freq = intel_uncore_read(uncore, MEMSTAT_ILK);
>> > > > > @@ -1968,7 +1968,7 @@ void intel_rps_driver_register(struct intel_rps *rps)
>> > > > > * We only register the i915 ips part with intel-ips once everything is
>> > > > > * set up, to avoid intel-ips sneaking in and reading bogus values.
>> > > > > */
>> > > > > - if (IS_GEN(gt->i915, 5)) {
>> > > > > + if (GRAPHICS_VER(gt->i915) == 5) {
>> > > > > GEM_BUG_ON(ips_mchdev);
>> > > > > rcu_assign_pointer(ips_mchdev, gt->i915);
>> > > > > ips_ping_for_i915_load();
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
>> > > > > index 0d9f74aec8fe..367fd44b81c8 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
>> > > > > @@ -590,13 +590,13 @@ void intel_sseu_info_init(struct intel_gt *gt)
>> > > > > cherryview_sseu_info_init(gt);
>> > > > > else if (IS_BROADWELL(i915))
>> > > > > bdw_sseu_info_init(gt);
>> > > > > - else if (IS_GEN(i915, 9))
>> > > > > + else if (GRAPHICS_VER(i915) == 9)
>> > > > > gen9_sseu_info_init(gt);
>> > > > > - else if (IS_GEN(i915, 10))
>> > > > > + else if (GRAPHICS_VER(i915) == 10)
>> > > > > gen10_sseu_info_init(gt);
>> > > > > - else if (IS_GEN(i915, 11))
>> > > > > + else if (GRAPHICS_VER(i915) == 11)
>> > > > > gen11_sseu_info_init(gt);
>> > > > > - else if (INTEL_GEN(i915) >= 12)
>> > > > > + else if (GRAPHICS_VER(i915) >= 12)
>> > > > > gen12_sseu_info_init(gt);
>> > > > > }
>> > > > >
>> > > > > @@ -613,7 +613,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
>> > > > > * No explicit RPCS request is needed to ensure full
>> > > > > * slice/subslice/EU enablement prior to Gen9.
>> > > > > */
>> > > > > - if (INTEL_GEN(i915) < 9)
>> > > > > + if (GRAPHICS_VER(i915) < 9)
>> > > > > return 0;
>> > > > >
>> > > > > /*
>> > > > > @@ -651,7 +651,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
>> > > > > * subslices are enabled, or a count between one and four on the first
>> > > > > * slice.
>> > > > > */
>> > > > > - if (IS_GEN(i915, 11) &&
>> > > > > + if (GRAPHICS_VER(i915) == 11 &&
>> > > > > slices == 1 &&
>> > > > > subslices > min_t(u8, 4, hweight8(sseu->subslice_mask[0]) / 2)) {
>> > > > > GEM_BUG_ON(subslices & 1);
>> > > > > @@ -669,7 +669,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt,
>> > > > > if (sseu->has_slice_pg) {
>> > > > > u32 mask, val = slices;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 11) {
>> > > > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > > > mask = GEN11_RPCS_S_CNT_MASK;
>> > > > > val <<= GEN11_RPCS_S_CNT_SHIFT;
>> > > > > } else {
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > > > > index 62cb9ee5bfc3..b62d1e31a645 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> > > > > @@ -699,9 +699,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>> > > > >
>> > > > > if (IS_DG1(i915))
>> > > > > dg1_ctx_workarounds_init(engine, wal);
>> > > > > - else if (IS_GEN(i915, 12))
>> > > > > + else if (GRAPHICS_VER(i915) == 12)
>> > > > > gen12_ctx_workarounds_init(engine, wal);
>> > > > > - else if (IS_GEN(i915, 11))
>> > > > > + else if (GRAPHICS_VER(i915) == 11)
>> > > > > icl_ctx_workarounds_init(engine, wal);
>> > > > > else if (IS_CANNONLAKE(i915))
>> > > > > cnl_ctx_workarounds_init(engine, wal);
>> > > > > @@ -719,14 +719,14 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>> > > > > chv_ctx_workarounds_init(engine, wal);
>> > > > > else if (IS_BROADWELL(i915))
>> > > > > bdw_ctx_workarounds_init(engine, wal);
>> > > > > - else if (IS_GEN(i915, 7))
>> > > > > + else if (GRAPHICS_VER(i915) == 7)
>> > > > > gen7_ctx_workarounds_init(engine, wal);
>> > > > > - else if (IS_GEN(i915, 6))
>> > > > > + else if (GRAPHICS_VER(i915) == 6)
>> > > > > gen6_ctx_workarounds_init(engine, wal);
>> > > > > - else if (INTEL_GEN(i915) < 8)
>> > > > > + else if (GRAPHICS_VER(i915) < 8)
>> > > > > ;
>> > > > > else
>> > > > > - MISSING_CASE(INTEL_GEN(i915));
>> > > > > + MISSING_CASE(GRAPHICS_VER(i915));
>> > > > >
>> > > > > wa_init_finish(wal);
>> > > > > }
>> > > > > @@ -950,7 +950,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> > > > > unsigned int slice, subslice;
>> > > > > u32 l3_en, mcr, mcr_mask;
>> > > > >
>> > > > > - GEM_BUG_ON(INTEL_GEN(i915) < 10);
>> > > > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 10);
>> > > > >
>> > > > > /*
>> > > > > * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
>> > > > > @@ -980,7 +980,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> > > > > * of every MMIO read.
>> > > > > */
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
>> > > > > + if (GRAPHICS_VER(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
>> > > > > u32 l3_fuse =
>> > > > > intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
>> > > > > GEN10_L3BANK_MASK;
>> > > > > @@ -1002,7 +1002,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> > > > > }
>> > > > > subslice--;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 11) {
>> > > > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > > > mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
>> > > > > mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
>> > > > > } else {
>> > > > > @@ -1171,9 +1171,9 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> > > > > dg1_gt_workarounds_init(i915, wal);
>> > > > > else if (IS_TIGERLAKE(i915))
>> > > > > tgl_gt_workarounds_init(i915, wal);
>> > > > > - else if (IS_GEN(i915, 12))
>> > > > > + else if (GRAPHICS_VER(i915) == 12)
>> > > > > gen12_gt_workarounds_init(i915, wal);
>> > > > > - else if (IS_GEN(i915, 11))
>> > > > > + else if (GRAPHICS_VER(i915) == 11)
>> > > > > icl_gt_workarounds_init(i915, wal);
>> > > > > else if (IS_CANNONLAKE(i915))
>> > > > > cnl_gt_workarounds_init(i915, wal);
>> > > > > @@ -1193,18 +1193,18 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> > > > > vlv_gt_workarounds_init(i915, wal);
>> > > > > else if (IS_IVYBRIDGE(i915))
>> > > > > ivb_gt_workarounds_init(i915, wal);
>> > > > > - else if (IS_GEN(i915, 6))
>> > > > > + else if (GRAPHICS_VER(i915) == 6)
>> > > > > snb_gt_workarounds_init(i915, wal);
>> > > > > - else if (IS_GEN(i915, 5))
>> > > > > + else if (GRAPHICS_VER(i915) == 5)
>> > > > > ilk_gt_workarounds_init(i915, wal);
>> > > > > else if (IS_G4X(i915))
>> > > > > g4x_gt_workarounds_init(i915, wal);
>> > > > > - else if (IS_GEN(i915, 4))
>> > > > > + else if (GRAPHICS_VER(i915) == 4)
>> > > > > gen4_gt_workarounds_init(i915, wal);
>> > > > > - else if (INTEL_GEN(i915) <= 8)
>> > > > > + else if (GRAPHICS_VER(i915) <= 8)
>> > > > > ;
>> > > > > else
>> > > > > - MISSING_CASE(INTEL_GEN(i915));
>> > > > > + MISSING_CASE(GRAPHICS_VER(i915));
>> > > > > }
>> > > > >
>> > > > > void intel_gt_init_workarounds(struct drm_i915_private *i915)
>> > > > > @@ -1558,9 +1558,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>> > > > >
>> > > > > if (IS_DG1(i915))
>> > > > > dg1_whitelist_build(engine);
>> > > > > - else if (IS_GEN(i915, 12))
>> > > > > + else if (GRAPHICS_VER(i915) == 12)
>> > > > > tgl_whitelist_build(engine);
>> > > > > - else if (IS_GEN(i915, 11))
>> > > > > + else if (GRAPHICS_VER(i915) == 11)
>> > > > > icl_whitelist_build(engine);
>> > > > > else if (IS_CANNONLAKE(i915))
>> > > > > cnl_whitelist_build(engine);
>> > > > > @@ -1576,10 +1576,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>> > > > > bxt_whitelist_build(engine);
>> > > > > else if (IS_SKYLAKE(i915))
>> > > > > skl_whitelist_build(engine);
>> > > > > - else if (INTEL_GEN(i915) <= 8)
>> > > > > + else if (GRAPHICS_VER(i915) <= 8)
>> > > > > ;
>> > > > > else
>> > > > > - MISSING_CASE(INTEL_GEN(i915));
>> > > > > + MISSING_CASE(GRAPHICS_VER(i915));
>> > > > >
>> > > > > wa_init_finish(w);
>> > > > > }
>> > > > > @@ -1695,7 +1695,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > > > ENABLE_SMALLPL);
>> > > > > }
>> > > > >
>> > > > > - if (IS_GEN(i915, 11)) {
>> > > > > + if (GRAPHICS_VER(i915) == 11) {
>> > > > > /* This is not an Wa. Enable for better image quality */
>> > > > > wa_masked_en(wal,
>> > > > > _3D_CHICKEN3,
>> > > > > @@ -1793,7 +1793,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > > > FF_DOP_CLOCK_GATE_DISABLE);
>> > > > > }
>> > > > >
>> > > > > - if (IS_GEN_RANGE(i915, 9, 12)) {
>> > > > > + if (IS_GRAPHICS_VER(i915, 9, 12)) {
>> > > > > /* FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
>> > > > > wa_masked_en(wal,
>> > > > > GEN7_FF_SLICE_CS_CHICKEN1,
>> > > > > @@ -1817,7 +1817,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > > > GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
>> > > > > }
>> > > > >
>> > > > > - if (IS_GEN(i915, 9)) {
>> > > > > + if (GRAPHICS_VER(i915) == 9) {
>> > > > > /* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
>> > > > > wa_masked_en(wal,
>> > > > > GEN9_CSFE_CHICKEN1_RCS,
>> > > > > @@ -1921,7 +1921,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > > > GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
>> > > > > }
>> > > > >
>> > > > > - if (IS_GEN(i915, 7)) {
>> > > > > + if (GRAPHICS_VER(i915) == 7) {
>> > > > > /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
>> > > > > wa_masked_en(wal,
>> > > > > GFX_MODE_GEN7,
>> > > > > @@ -1953,7 +1953,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > > > GEN6_WIZ_HASHING_16x4);
>> > > > > }
>> > > > >
>> > > > > - if (IS_GEN_RANGE(i915, 6, 7))
>> > > > > + if (IS_GRAPHICS_VER(i915, 6, 7))
>> > > > > /*
>> > > > > * We need to disable the AsyncFlip performance optimisations in
>> > > > > * order to use MI_WAIT_FOR_EVENT within the CS. It should
>> > > > > @@ -1965,7 +1965,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > > > MI_MODE,
>> > > > > ASYNC_FLIP_PERF_DISABLE);
>> > > > >
>> > > > > - if (IS_GEN(i915, 6)) {
>> > > > > + if (GRAPHICS_VER(i915) == 6) {
>> > > > > /*
>> > > > > * Required for the hardware to program scanline values for
>> > > > > * waiting
>> > > > > @@ -2019,14 +2019,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > > > CM0_STC_EVICT_DISABLE_LRA_SNB);
>> > > > > }
>> > > > >
>> > > > > - if (IS_GEN_RANGE(i915, 4, 6))
>> > > > > + if (IS_GRAPHICS_VER(i915, 4, 6))
>> > > > > /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
>> > > > > wa_add(wal, MI_MODE,
>> > > > > 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
>> > > > > /* XXX bit doesn't stick on Broadwater */
>> > > > > IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH);
>> > > > >
>> > > > > - if (IS_GEN(i915, 4))
>> > > > > + if (GRAPHICS_VER(i915) == 4)
>> > > > > /*
>> > > > > * Disable CONSTANT_BUFFER before it is loaded from the context
>> > > > > * image. For as it is loaded, it is executed and the stored
>> > > > > @@ -2058,7 +2058,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > > > static void
>> > > > > engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>> > > > > {
>> > > > > - if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4))
>> > > > > + if (I915_SELFTEST_ONLY(GRAPHICS_VER(engine->i915) < 4))
>> > > > > return;
>> > > > >
>> > > > > if (engine->class == RENDER_CLASS)
>> > > > > @@ -2071,7 +2071,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
>> > > > > {
>> > > > > struct i915_wa_list *wal = &engine->wa_list;
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) < 4)
>> > > > > + if (GRAPHICS_VER(engine->i915) < 4)
>> > > > > return;
>> > > > >
>> > > > > wa_init_start(wal, "engine", engine->name);
>> > > > > @@ -2112,9 +2112,9 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
>> > > > > const struct mcr_range *mcr_ranges;
>> > > > > int i;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 12)
>> > > > > + if (GRAPHICS_VER(i915) >= 12)
>> > > > > mcr_ranges = mcr_ranges_gen12;
>> > > > > - else if (INTEL_GEN(i915) >= 8)
>> > > > > + else if (GRAPHICS_VER(i915) >= 8)
>> > > > > mcr_ranges = mcr_ranges_gen8;
>> > > > > else
>> > > > > return false;
>> > > > > @@ -2143,7 +2143,7 @@ wa_list_srm(struct i915_request *rq,
>> > > > > u32 srm, *cs;
>> > > > >
>> > > > > srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
>> > > > > - if (INTEL_GEN(i915) >= 8)
>> > > > > + if (GRAPHICS_VER(i915) >= 8)
>> > > > > srm++;
>> > > > >
>> > > > > for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>> > > > > index 3453eb77c498..64abf5feabfa 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>> > > > > @@ -52,7 +52,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
>> > > > > return PTR_ERR(cs);
>> > > > >
>> > > > > cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
>> > > > > - if (INTEL_GEN(rq->engine->i915) >= 8)
>> > > > > + if (GRAPHICS_VER(rq->engine->i915) >= 8)
>> > > > > cmd++;
>> > > > > *cs++ = cmd;
>> > > > > *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
>> > > > > @@ -125,7 +125,7 @@ static int perf_mi_bb_start(void *arg)
>> > > > > enum intel_engine_id id;
>> > > > > int err = 0;
>> > > > >
>> > > > > - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
>> > > > > + if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
>> > > > > return 0;
>> > > > >
>> > > > > perf_begin(gt);
>> > > > > @@ -249,7 +249,7 @@ static int perf_mi_noop(void *arg)
>> > > > > enum intel_engine_id id;
>> > > > > int err = 0;
>> > > > >
>> > > > > - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
>> > > > > + if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
>> > > > > return 0;
>> > > > >
>> > > > > perf_begin(gt);
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
>> > > > > index 2c898622bdfb..72cca3f0da21 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
>> > > > > @@ -198,7 +198,7 @@ static int live_engine_timestamps(void *arg)
>> > > > > * the same CS clock.
>> > > > > */
>> > > > >
>> > > > > - if (INTEL_GEN(gt->i915) < 8)
>> > > > > + if (GRAPHICS_VER(gt->i915) < 8)
>> > > > > return 0;
>> > > > >
>> > > > > for_each_engine(engine, gt, id) {
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c
>> > > > > index 1f93591a8c69..ea2203af0764 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c
>> > > > > @@ -3269,7 +3269,7 @@ static int live_preempt_user(void *arg)
>> > > > > if (!intel_engine_has_preemption(engine))
>> > > > > continue;
>> > > > >
>> > > > > - if (IS_GEN(gt->i915, 8) && engine->class != RENDER_CLASS)
>> > > > > + if (GRAPHICS_VER(gt->i915) == 8 && engine->class != RENDER_CLASS)
>> > > > > continue; /* we need per-context GPR */
>> > > > >
>> > > > > if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {
>> > > > > @@ -4293,7 +4293,7 @@ static int live_virtual_preserved(void *arg)
>> > > > > return 0;
>> > > > >
>> > > > > /* As we use CS_GPR we cannot run before they existed on all engines. */
>> > > > > - if (INTEL_GEN(gt->i915) < 9)
>> > > > > + if (GRAPHICS_VER(gt->i915) < 9)
>> > > > > return 0;
>> > > > >
>> > > > > for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
>> > > > > index c0845bf72dd3..b9441217ca3d 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
>> > > > > @@ -74,10 +74,10 @@ static int live_gt_clocks(void *arg)
>> > > > > return 0;
>> > > > > }
>> > > > >
>> > > > > - if (INTEL_GEN(gt->i915) < 4) /* Any CS_TIMESTAMP? */
>> > > > > + if (GRAPHICS_VER(gt->i915) < 4) /* Any CS_TIMESTAMP? */
>> > > > > return 0;
>> > > > >
>> > > > > - if (IS_GEN(gt->i915, 5))
>> > > > > + if (GRAPHICS_VER(gt->i915) == 5)
>> > > > > /*
>> > > > > * XXX CS_TIMESTAMP low dword is dysfunctional?
>> > > > > *
>> > > > > @@ -86,7 +86,7 @@ static int live_gt_clocks(void *arg)
>> > > > > */
>> > > > > return 0;
>> > > > >
>> > > > > - if (IS_GEN(gt->i915, 4))
>> > > > > + if (GRAPHICS_VER(gt->i915) == 4)
>> > > > > /*
>> > > > > * XXX CS_TIMESTAMP appears gibberish
>> > > > > *
>> > > > > @@ -105,7 +105,7 @@ static int live_gt_clocks(void *arg)
>> > > > > u64 time;
>> > > > > u64 dt;
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) < 7 && engine->id != RCS0)
>> > > > > + if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0)
>> > > > > continue;
>> > > > >
>> > > > > measure_clocks(engine, &cycles, &dt);
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
>> > > > > index 5b63d4df8c93..853246fad05f 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
>> > > > > @@ -180,7 +180,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>> > > > > goto cancel_rq;
>> > > > >
>> > > > > batch = h->batch;
>> > > > > - if (INTEL_GEN(gt->i915) >= 8) {
>> > > > > + if (GRAPHICS_VER(gt->i915) >= 8) {
>> > > > > *batch++ = MI_STORE_DWORD_IMM_GEN4;
>> > > > > *batch++ = lower_32_bits(hws_address(hws, rq));
>> > > > > *batch++ = upper_32_bits(hws_address(hws, rq));
>> > > > > @@ -194,7 +194,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>> > > > > *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
>> > > > > *batch++ = lower_32_bits(vma->node.start);
>> > > > > *batch++ = upper_32_bits(vma->node.start);
>> > > > > - } else if (INTEL_GEN(gt->i915) >= 6) {
>> > > > > + } else if (GRAPHICS_VER(gt->i915) >= 6) {
>> > > > > *batch++ = MI_STORE_DWORD_IMM_GEN4;
>> > > > > *batch++ = 0;
>> > > > > *batch++ = lower_32_bits(hws_address(hws, rq));
>> > > > > @@ -207,7 +207,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>> > > > > *batch++ = MI_NOOP;
>> > > > > *batch++ = MI_BATCH_BUFFER_START | 1 << 8;
>> > > > > *batch++ = lower_32_bits(vma->node.start);
>> > > > > - } else if (INTEL_GEN(gt->i915) >= 4) {
>> > > > > + } else if (GRAPHICS_VER(gt->i915) >= 4) {
>> > > > > *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> > > > > *batch++ = 0;
>> > > > > *batch++ = lower_32_bits(hws_address(hws, rq));
>> > > > > @@ -243,7 +243,7 @@ hang_create_request(struct hang *h, struct intel_engine_cs *engine)
>> > > > > }
>> > > > >
>> > > > > flags = 0;
>> > > > > - if (INTEL_GEN(gt->i915) <= 5)
>> > > > > + if (GRAPHICS_VER(gt->i915) <= 5)
>> > > > > flags |= I915_DISPATCH_SECURE;
>> > > > >
>> > > > > err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
>> > > > > index 94006f117bbd..459b775f163a 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_llc.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
>> > > > > @@ -44,7 +44,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
>> > > > > if (found != ia_freq) {
>> > > > > pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected CPU freq, found %d, expected %d\n",
>> > > > > gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
>> > > > > - intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
>> > > > > + intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
>> > > > > found, ia_freq);
>> > > > > err = -EINVAL;
>> > > > > break;
>> > > > > @@ -54,7 +54,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
>> > > > > if (found != ring_freq) {
>> > > > > pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected ring freq, found %d, expected %d\n",
>> > > > > gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
>> > > > > - intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
>> > > > > + intel_gpu_freq(rps, gpu_freq * (GRAPHICS_VER(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
>> > > > > found, ring_freq);
>> > > > > err = -EINVAL;
>> > > > > break;
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> > > > > index d8f6623524e8..3119016d9910 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> > > > > @@ -584,7 +584,7 @@ static int __live_lrc_gpr(struct intel_engine_cs *engine,
>> > > > > int err;
>> > > > > int n;
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) < 9 && engine->class != RENDER_CLASS)
>> > > > > + if (GRAPHICS_VER(engine->i915) < 9 && engine->class != RENDER_CLASS)
>> > > > > return 0; /* GPR only on rcs0 for gen8 */
>> > > > >
>> > > > > err = gpr_make_dirty(engine->kernel_context);
>> > > > > @@ -1389,10 +1389,10 @@ static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
>> > > > >
>> > > > > static bool skip_isolation(const struct intel_engine_cs *engine)
>> > > > > {
>> > > > > - if (engine->class == COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) == 9)
>> > > > > + if (engine->class == COPY_ENGINE_CLASS && GRAPHICS_VER(engine->i915) == 9)
>> > > > > return true;
>> > > > >
>> > > > > - if (engine->class == RENDER_CLASS && INTEL_GEN(engine->i915) == 11)
>> > > > > + if (engine->class == RENDER_CLASS && GRAPHICS_VER(engine->i915) == 11)
>> > > > > return true;
>> > > > >
>> > > > > return false;
>> > > > > @@ -1551,7 +1551,7 @@ static int __live_lrc_indirect_ctx_bb(struct intel_engine_cs *engine)
>> > > > > /* We use the already reserved extra page in context state */
>> > > > > if (!a->wa_bb_page) {
>> > > > > GEM_BUG_ON(b->wa_bb_page);
>> > > > > - GEM_BUG_ON(INTEL_GEN(engine->i915) == 12);
>> > > > > + GEM_BUG_ON(GRAPHICS_VER(engine->i915) == 12);
>> > > > > goto unpin_b;
>> > > > > }
>> > > > >
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
>> > > > > index e55a887d11e2..b9bb0e6e97f7 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
>> > > > > @@ -183,7 +183,7 @@ static bool mcr_range(struct drm_i915_private *i915, u32 offset)
>> > > > > * which only controls CPU initiated MMIO. Routing does not
>> > > > > * work for CS access so we cannot verify them on this path.
>> > > > > */
>> > > > > - return INTEL_GEN(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
>> > > > > + return GRAPHICS_VER(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
>> > > > > }
>> > > > >
>> > > > > static int check_l3cc_table(struct intel_engine_cs *engine,
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
>> > > > > index 710f825f6e5a..8c70b7e12074 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
>> > > > > @@ -140,7 +140,7 @@ static const u32 *__live_rc6_ctx(struct intel_context *ce)
>> > > > > }
>> > > > >
>> > > > > cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
>> > > > > - if (INTEL_GEN(rq->engine->i915) >= 8)
>> > > > > + if (GRAPHICS_VER(rq->engine->i915) >= 8)
>> > > > > cmd++;
>> > > > >
>> > > > > *cs++ = cmd;
>> > > > > @@ -193,7 +193,7 @@ int live_rc6_ctx_wa(void *arg)
>> > > > > int err = 0;
>> > > > >
>> > > > > /* A read of CTX_INFO upsets rc6. Poke the bear! */
>> > > > > - if (INTEL_GEN(gt->i915) < 8)
>> > > > > + if (GRAPHICS_VER(gt->i915) < 8)
>> > > > > return 0;
>> > > > >
>> > > > > engines = randomised_engines(gt, &prng, &count);
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
>> > > > > index c12e74171b63..041954408d0f 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_ring_submission.c
>> > > > > @@ -41,10 +41,10 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
>> > > > > return ERR_CAST(cs);
>> > > > > }
>> > > > >
>> > > > > - if (INTEL_GEN(engine->i915) >= 6) {
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 6) {
>> > > > > *cs++ = MI_STORE_DWORD_IMM_GEN4;
>> > > > > *cs++ = 0;
>> > > > > - } else if (INTEL_GEN(engine->i915) >= 4) {
>> > > > > + } else if (GRAPHICS_VER(engine->i915) >= 4) {
>> > > > > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> > > > > *cs++ = 0;
>> > > > > } else {
>> > > > > @@ -266,7 +266,7 @@ static int live_ctx_switch_wa(void *arg)
>> > > > > if (!intel_engine_can_store_dword(engine))
>> > > > > continue;
>> > > > >
>> > > > > - if (IS_GEN_RANGE(gt->i915, 4, 5))
>> > > > > + if (IS_GRAPHICS_VER(gt->i915, 4, 5))
>> > > > > continue; /* MI_STORE_DWORD is privileged! */
>> > > > >
>> > > > > saved_wa = fetch_and_zero(&engine->wa_ctx.vma);
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
>> > > > > index 3ca1bd5793c3..7ee2513e15f9 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_rps.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
>> > > > > @@ -204,7 +204,7 @@ static void show_pstate_limits(struct intel_rps *rps)
>> > > > > i915_mmio_reg_offset(BXT_RP_STATE_CAP),
>> > > > > intel_uncore_read(rps_to_uncore(rps),
>> > > > > BXT_RP_STATE_CAP));
>> > > > > - } else if (IS_GEN(i915, 9)) {
>> > > > > + } else if (GRAPHICS_VER(i915) == 9) {
>> > > > > pr_info("P_STATE_LIMITS[%x]: 0x%08x\n",
>> > > > > i915_mmio_reg_offset(GEN9_RP_STATE_LIMITS),
>> > > > > intel_uncore_read(rps_to_uncore(rps),
>> > > > > @@ -222,7 +222,7 @@ int live_rps_clock_interval(void *arg)
>> > > > > struct igt_spinner spin;
>> > > > > int err = 0;
>> > > > >
>> > > > > - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
>> > > > > + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
>> > > > > return 0;
>> > > > >
>> > > > > if (igt_spinner_init(&spin, gt))
>> > > > > @@ -506,7 +506,7 @@ static void show_pcu_config(struct intel_rps *rps)
>> > > > >
>> > > > > min_gpu_freq = rps->min_freq;
>> > > > > max_gpu_freq = rps->max_freq;
>> > > > > - if (INTEL_GEN(i915) >= 9) {
>> > > > > + if (GRAPHICS_VER(i915) >= 9) {
>> > > > > /* Convert GT frequency to 50 HZ units */
>> > > > > min_gpu_freq /= GEN9_FREQ_SCALER;
>> > > > > max_gpu_freq /= GEN9_FREQ_SCALER;
>> > > > > @@ -614,7 +614,7 @@ int live_rps_frequency_cs(void *arg)
>> > > > > if (!intel_rps_is_enabled(rps))
>> > > > > return 0;
>> > > > >
>> > > > > - if (INTEL_GEN(gt->i915) < 8) /* for CS simplicity */
>> > > > > + if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
>> > > > > return 0;
>> > > > >
>> > > > > if (CPU_LATENCY >= 0)
>> > > > > @@ -755,7 +755,7 @@ int live_rps_frequency_srm(void *arg)
>> > > > > if (!intel_rps_is_enabled(rps))
>> > > > > return 0;
>> > > > >
>> > > > > - if (INTEL_GEN(gt->i915) < 8) /* for CS simplicity */
>> > > > > + if (GRAPHICS_VER(gt->i915) < 8) /* for CS simplicity */
>> > > > > return 0;
>> > > > >
>> > > > > if (CPU_LATENCY >= 0)
>> > > > > @@ -1031,7 +1031,7 @@ int live_rps_interrupt(void *arg)
>> > > > > * First, let's check whether or not we are receiving interrupts.
>> > > > > */
>> > > > >
>> > > > > - if (!intel_rps_has_interrupts(rps) || INTEL_GEN(gt->i915) < 6)
>> > > > > + if (!intel_rps_has_interrupts(rps) || GRAPHICS_VER(gt->i915) < 6)
>> > > > > return 0;
>> > > > >
>> > > > > intel_gt_pm_get(gt);
>> > > > > @@ -1136,7 +1136,7 @@ int live_rps_power(void *arg)
>> > > > > * that theory.
>> > > > > */
>> > > > >
>> > > > > - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
>> > > > > + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
>> > > > > return 0;
>> > > > >
>> > > > > if (!librapl_supported(gt->i915))
>> > > > > @@ -1240,7 +1240,7 @@ int live_rps_dynamic(void *arg)
>> > > > > * moving parts into dynamic reclocking based on load.
>> > > > > */
>> > > > >
>> > > > > - if (!intel_rps_is_enabled(rps) || INTEL_GEN(gt->i915) < 6)
>> > > > > + if (!intel_rps_is_enabled(rps) || GRAPHICS_VER(gt->i915) < 6)
>> > > > > return 0;
>> > > > >
>> > > > > if (igt_spinner_init(&spin, gt))
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> > > > > index 9adbd9d147be..64da0c91dec1 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> > > > > @@ -457,12 +457,12 @@ static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
>> > > > > if (IS_ERR(cs))
>> > > > > return PTR_ERR(cs);
>> > > > >
>> > > > > - if (INTEL_GEN(rq->engine->i915) >= 8) {
>> > > > > + if (GRAPHICS_VER(rq->engine->i915) >= 8) {
>> > > > > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> > > > > *cs++ = addr;
>> > > > > *cs++ = 0;
>> > > > > *cs++ = value;
>> > > > > - } else if (INTEL_GEN(rq->engine->i915) >= 4) {
>> > > > > + } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
>> > > > > *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> > > > > *cs++ = 0;
>> > > > > *cs++ = addr;
>> > > > > @@ -992,7 +992,7 @@ static int live_hwsp_read(void *arg)
>> > > > > * even across multiple wraps.
>> > > > > */
>> > > > >
>> > > > > - if (INTEL_GEN(gt->i915) < 8) /* CS convenience [SRM/LRM] */
>> > > > > + if (GRAPHICS_VER(gt->i915) < 8) /* CS convenience [SRM/LRM] */
>> > > > > return 0;
>> > > > >
>> > > > > tl = intel_timeline_create(gt);
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
>> > > > > index 64937ec3f2dc..c30754daf4b1 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
>> > > > > @@ -145,7 +145,7 @@ read_nonprivs(struct intel_context *ce)
>> > > > > goto err_req;
>> > > > >
>> > > > > srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
>> > > > > - if (INTEL_GEN(engine->i915) >= 8)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 8)
>> > > > > srm++;
>> > > > >
>> > > > > cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS);
>> > > > > @@ -546,7 +546,7 @@ static int check_dirty_whitelist(struct intel_context *ce)
>> > > > >
>> > > > > srm = MI_STORE_REGISTER_MEM;
>> > > > > lrm = MI_LOAD_REGISTER_MEM;
>> > > > > - if (INTEL_GEN(engine->i915) >= 8)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 8)
>> > > > > lrm++, srm++;
>> > > > >
>> > > > > pr_debug("%s: Writing garbage to %x\n",
>> > > > > @@ -749,7 +749,7 @@ static int live_dirty_whitelist(void *arg)
>> > > > >
>> > > > > /* Can the user write to the whitelisted registers? */
>> > > > >
>> > > > > - if (INTEL_GEN(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */
>> > > > > + if (GRAPHICS_VER(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */
>> > > > > return 0;
>> > > > >
>> > > > > for_each_engine(engine, gt, id) {
>> > > > > @@ -829,7 +829,7 @@ static int read_whitelisted_registers(struct intel_context *ce,
>> > > > > goto err_req;
>> > > > >
>> > > > > srm = MI_STORE_REGISTER_MEM;
>> > > > > - if (INTEL_GEN(engine->i915) >= 8)
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 8)
>> > > > > srm++;
>> > > > >
>> > > > > cs = intel_ring_begin(rq, 4 * engine->whitelist.count);
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> > > > > index adae04c47aab..84f806911370 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>> > > > > @@ -60,7 +60,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
>> > > > > enum forcewake_domains fw_domains = 0;
>> > > > > unsigned int i;
>> > > > >
>> > > > > - if (INTEL_GEN(gt->i915) >= 11) {
>> > > > > + if (GRAPHICS_VER(gt->i915) >= 11) {
>> > > > > guc->send_regs.base =
>> > > > > i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
>> > > > > guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
>> > > > > @@ -176,7 +176,7 @@ void intel_guc_init_early(struct intel_guc *guc)
>> > > > >
>> > > > > mutex_init(&guc->send_mutex);
>> > > > > spin_lock_init(&guc->irq_lock);
>> > > > > - if (INTEL_GEN(i915) >= 11) {
>> > > > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > > > guc->notify_reg = GEN11_GUC_HOST_INTERRUPT;
>> > > > > guc->interrupts.reset = gen11_reset_guc_interrupts;
>> > > > > guc->interrupts.enable = gen11_enable_guc_interrupts;
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> > > > > index 17526717368c..b32fafba2a90 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>> > > > > @@ -162,7 +162,7 @@ static void __guc_ads_init(struct intel_guc *guc)
>> > > > > blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK] =
>> > > > > gt->info.vdbox_sfc_access;
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 12 && !IS_DGFX(i915)) {
>> > > > > + if (GRAPHICS_VER(i915) >= 12 && !IS_DGFX(i915)) {
>> > > > > u32 distdbreg = intel_uncore_read(gt->uncore,
>> > > > > GEN12_DIST_DBS_POPULATED);
>> > > > > blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI] =
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> > > > > index 2270d6b3b272..76fe766ad1bc 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> > > > > @@ -30,7 +30,7 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
>> > > > > else
>> > > > > intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
>> > > > >
>> > > > > - if (IS_GEN(uncore->i915, 9)) {
>> > > > > + if (GRAPHICS_VER(uncore->i915) == 9) {
>> > > > > /* DOP Clock Gating Enable for GuC clocks */
>> > > > > intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
>> > > > > 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> > > > > index 335719f17490..541f6da1ec47 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> > > > > @@ -438,7 +438,7 @@ static void guc_interrupts_capture(struct intel_gt *gt)
>> > > > > u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
>> > > > > u32 dmask = irqs << 16 | irqs;
>> > > > >
>> > > > > - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
>> > > > > + GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
>> > > > >
>> > > > > /* Don't handle the ctx switch interrupt in GuC submission mode */
>> > > > > intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask, 0);
>> > > > > @@ -451,7 +451,7 @@ static void guc_interrupts_release(struct intel_gt *gt)
>> > > > > u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
>> > > > > u32 dmask = irqs << 16 | irqs;
>> > > > >
>> > > > > - GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
>> > > > > + GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
>> > > > >
>> > > > > /* Handle ctx switch interrupts again */
>> > > > > intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0, dmask);
>> > > > > @@ -648,7 +648,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>> > > > > engine->emit_flush = gen8_emit_flush_xcs;
>> > > > > engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
>> > > > > engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs;
>> > > > > - if (INTEL_GEN(engine->i915) >= 12) {
>> > > > > + if (GRAPHICS_VER(engine->i915) >= 12) {
>> > > > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_xcs;
>> > > > > engine->emit_flush = gen12_emit_flush_xcs;
>> > > > > }
>> > > > > @@ -670,7 +670,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>> > > > >
>> > > > > static void rcs_submission_override(struct intel_engine_cs *engine)
>> > > > > {
>> > > > > - switch (INTEL_GEN(engine->i915)) {
>> > > > > + switch (GRAPHICS_VER(engine->i915)) {
>> > > > > case 12:
>> > > > > engine->emit_flush = gen12_emit_flush_rcs;
>> > > > > engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb_rcs;
>> > > > > @@ -700,7 +700,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
>> > > > > * The setup relies on several assumptions (e.g. irqs always enabled)
>> > > > > * that are only valid on gen11+
>> > > > > */
>> > > > > - GEM_BUG_ON(INTEL_GEN(i915) < 11);
>> > > > > + GEM_BUG_ON(GRAPHICS_VER(i915) < 11);
>> > > > >
>> > > > > tasklet_setup(&engine->execlists.tasklet, guc_submission_tasklet);
>> > > > >
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>> > > > > index 56d2144dc6a0..fc5387b410a2 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>> > > > > @@ -43,7 +43,7 @@ void intel_huc_init_early(struct intel_huc *huc)
>> > > > >
>> > > > > intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC);
>> > > > >
>> > > > > - if (INTEL_GEN(i915) >= 11) {
>> > > > > + if (GRAPHICS_VER(i915) >= 11) {
>> > > > > huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
>> > > > > huc->status.mask = HUC_LOAD_SUCCESSFUL;
>> > > > > huc->status.value = HUC_LOAD_SUCCESSFUL;
>> > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> > > > > index 6abb8f2dc33d..6c2bf4b6bc10 100644
>> > > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> > > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> > > > > @@ -23,7 +23,7 @@ static void uc_expand_default_options(struct intel_uc *uc)
>> > > > > return;
>> > > > >
>> > > > > /* Don't enable GuC/HuC on pre-Gen12 */
>> > > > > - if (INTEL_GEN(i915) < 12) {
>> > > > > + if (GRAPHICS_VER(i915) < 12) {
>> > > > > i915->params.enable_guc = 0;
>> > > > > return;
>> > > > > }
>> > > > > @@ -467,7 +467,7 @@ static int __uc_init_hw(struct intel_uc *uc)
>> > > > >
>> > > > > /* WaEnableuKernelHeaderValidFix:skl */
>> > > > > /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
>> > > > > - if (IS_GEN(i915, 9))
>> > > > > + if (GRAPHICS_VER(i915) == 9)
>> > > > > attempts = 3;
>> > > > > else
>> > > > > attempts = 1;
>> > > > > --
>> > > > > 2.31.1
>> > > > >
>> > > >
>> > > > --
>> > > > Matt Roper
>> > > > Graphics Software Engineer
>> > > > VTT-OSGC Platform Enablement
>> > > > Intel Corporation
>> > > > (916) 356-2795
>> >
>> > --
>> > Matt Roper
>> > Graphics Software Engineer
>> > VTT-OSGC Platform Enablement
>> > Intel Corporation
>> > (916) 356-2795
>
>--
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
2021-06-01 20:39 ` Matt Roper
2021-06-01 20:53 ` Lucas De Marchi
@ 2021-06-02 6:34 ` Lucas De Marchi
2021-06-02 16:00 ` Matt Roper
1 sibling, 1 reply; 20+ messages in thread
From: Lucas De Marchi @ 2021-06-02 6:34 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Tue, Jun 01, 2021 at 01:39:25PM -0700, Matt Roper wrote:
>On Tue, Jun 01, 2021 at 12:13:17PM -0700, Lucas De Marchi wrote:
>> On Tue, Jun 01, 2021 at 10:30:55AM -0700, Matt Roper wrote:
>> > On Tue, Jun 01, 2021 at 10:15:14AM -0700, Lucas De Marchi wrote:
>> > > On Tue, Jun 01, 2021 at 09:58:34AM -0700, Matt Roper wrote:
>> > > > On Thu, May 27, 2021 at 11:16:54AM -0700, Lucas De Marchi wrote:
>> > > > > This was done by the following semantic patch:
>> > > >
>> > > > Is the commit message here out-of-date? The cocci doesn't appear to
>> > > > match the diff anymore. IS_GRAPHICS_VER() is the range macro now and
>> > > > IS_GEN is being replaced with a direct "==" comparison.
>> > >
>> > > not necessarily, it's included in "and friends...". Maybe rewording to
>> > > something like "replace gen-based macros with new ver-based ones" would
>> > > make it clearer?
>> >
>> > I mean that running the coccinelle rules below through spatch won't
>> > generate the code diff here; it would generate a completely different
>> > patch (that I don't think would build properly either).
>>
>> oh, ok. I fixed the issues in the .cocci and forgot to update the commit
>> message. Thanks.
>>
>> Lucas De Marchi
>
>Aside from the commit messages needing updated Coccinelle rules, the
>code deltas look correct to me.
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
humn... is that to the series or only this commit?
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER
2021-06-02 6:34 ` Lucas De Marchi
@ 2021-06-02 16:00 ` Matt Roper
0 siblings, 0 replies; 20+ messages in thread
From: Matt Roper @ 2021-06-02 16:00 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, Jun 01, 2021 at 11:34:39PM -0700, Lucas De Marchi wrote:
> On Tue, Jun 01, 2021 at 01:39:25PM -0700, Matt Roper wrote:
> > On Tue, Jun 01, 2021 at 12:13:17PM -0700, Lucas De Marchi wrote:
> > > On Tue, Jun 01, 2021 at 10:30:55AM -0700, Matt Roper wrote:
> > > > On Tue, Jun 01, 2021 at 10:15:14AM -0700, Lucas De Marchi wrote:
> > > > > On Tue, Jun 01, 2021 at 09:58:34AM -0700, Matt Roper wrote:
> > > > > > On Thu, May 27, 2021 at 11:16:54AM -0700, Lucas De Marchi wrote:
> > > > > > > This was done by the following semantic patch:
> > > > > >
> > > > > > Is the commit message here out-of-date? The cocci doesn't appear to
> > > > > > match the diff anymore. IS_GRAPHICS_VER() is the range macro now and
> > > > > > IS_GEN is being replaced with a direct "==" comparison.
> > > > >
> > > > > not necessarily, it's included in "and friends...". Maybe rewording to
> > > > > something like "replace gen-based macros with new ver-based ones" would
> > > > > make it clearer?
> > > >
> > > > I mean that running the coccinelle rules below through spatch won't
> > > > generate the code diff here; it would generate a completely different
> > > > patch (that I don't think would build properly either).
> > >
> > > oh, ok. I fixed the issues in the .cocci and forgot to update the commit
> > > message. Thanks.
> > >
> > > Lucas De Marchi
> >
> > Aside from the commit messages needing updated Coccinelle rules, the
> > code deltas look correct to me.
> >
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> humn... is that to the series or only this commit?
Sorry, that was meant for the whole series.
Matt
>
> Lucas De Marchi
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2021-06-02 16:00 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-27 18:16 [Intel-gfx] [PATCH 0/7] Finish conversion to GRAPHICS_VER Lucas De Marchi
2021-05-27 18:16 ` [Intel-gfx] [PATCH 1/7] drm/i915/gt: replace IS_GEN and friends with IS_GRAPHICS_VER Lucas De Marchi
2021-06-01 16:58 ` Matt Roper
2021-06-01 17:15 ` Lucas De Marchi
2021-06-01 17:30 ` Matt Roper
2021-06-01 19:13 ` Lucas De Marchi
2021-06-01 20:39 ` Matt Roper
2021-06-01 20:53 ` Lucas De Marchi
2021-06-02 6:34 ` Lucas De Marchi
2021-06-02 16:00 ` Matt Roper
2021-05-27 18:16 ` [Intel-gfx] [PATCH 2/7] drm/i915/gt: Add remaining conversions to GRAPHICS_VER Lucas De Marchi
2021-05-27 18:16 ` [Intel-gfx] [PATCH 3/7] drm/i915/gem: replace IS_GEN and friends with IS_GRAPHICS_VER Lucas De Marchi
2021-05-27 18:16 ` [Intel-gfx] [PATCH 4/7] drm/i915/gvt: " Lucas De Marchi
2021-05-27 18:16 ` [Intel-gfx] [PATCH 5/7] drm/i915: " Lucas De Marchi
2021-05-27 18:16 ` [Intel-gfx] [PATCH 6/7] drm/i915: Add remaining conversions to GRAPHICS_VER Lucas De Marchi
2021-05-27 18:17 ` [Intel-gfx] [PATCH 7/7] drm/i915/display: replace IS_GEN() in commented code Lucas De Marchi
2021-05-27 21:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Finish conversion to GRAPHICS_VER Patchwork
2021-05-27 21:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-27 21:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-28 19:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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