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From: matheus.ferst@eldorado.org.br
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: richard.henderson@linaro.org, f4bug@amsat.org, groug@kaod.org,
	luis.pires@eldorado.org.br, lagarcia@br.ibm.com,
	Matheus Ferst <matheus.ferst@eldorado.org.br>,
	david@gibson.dropbear.id.au
Subject: [PATCH v6 13/14] target/ppc: Move addpcis to decodetree
Date: Tue,  1 Jun 2021 16:35:27 -0300	[thread overview]
Message-ID: <20210601193528.2533031-14-matheus.ferst@eldorado.org.br> (raw)
In-Reply-To: <20210601193528.2533031-1-matheus.ferst@eldorado.org.br>

From: Matheus Ferst <matheus.ferst@eldorado.org.br>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/insn32.decode                   | 6 ++++++
 target/ppc/translate.c                     | 9 ---------
 target/ppc/translate/fixedpoint-impl.c.inc | 7 +++++++
 3 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 77edf407ab..93e5d44d9e 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -23,6 +23,10 @@
 %ds_si          2:s14  !function=times_4
 @DS             ...... rt:5 ra:5 .............. ..      &D si=%ds_si
 
+&DX             rt d
+%dx_d           6:s10 16:5 0:1
+@DX             ...... rt:5  ..... .......... ..... .   &DX d=%dx_d
+
 &VX             vrt vra vrb
 @VX             ...... vrt:5 vra:5 vrb:5 .......... .   &VX
 
@@ -90,6 +94,8 @@ STDUX           011111 ..... ..... ..... 0010110101 -   @X
 ADDI            001110 ..... ..... ................     @D
 ADDIS           001111 ..... ..... ................     @D
 
+ADDPCIS         010011 ..... ..... .......... 00010 .   @DX
+
 ## Fixed-Point Logical Instructions
 
 CFUGED          011111 ..... ..... ..... 0011011100 -   @X
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ed5515f8e2..35d8831d44 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1779,14 +1779,6 @@ static void gen_addic_(DisasContext *ctx)
     gen_op_addic(ctx, 1);
 }
 
-/* addpcis */
-static void gen_addpcis(DisasContext *ctx)
-{
-    target_long d = DX(ctx->opcode);
-
-    tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
-}
-
 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
                                      TCGv arg2, int sign, int compute_ov)
 {
@@ -7659,7 +7651,6 @@ GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
-GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 50933a3b9d..2713366791 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -194,6 +194,13 @@ static bool trans_ADDIS(DisasContext *ctx, arg_D *a)
     return trans_ADDI(ctx, a);
 }
 
+static bool trans_ADDPCIS(DisasContext *ctx, arg_DX *a)
+{
+    REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+    tcg_gen_movi_tl(cpu_gpr[a->rt], ctx->base.pc_next + (a->d << 16));
+    return true;
+}
+
 static bool trans_INVALID(DisasContext *ctx, arg_INVALID *a)
 {
     gen_invalid(ctx);
-- 
2.25.1



  parent reply	other threads:[~2021-06-01 19:51 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-01 19:35 [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions matheus.ferst
2021-06-01 19:35 ` [PATCH v6 01/14] target/ppc: Introduce macros to check isa extensions matheus.ferst
2021-06-01 19:35 ` [PATCH v6 02/14] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
2021-06-01 19:35 ` [PATCH v6 03/14] target/ppc: Add infrastructure for prefixed insns matheus.ferst
2021-06-01 19:35 ` [PATCH v6 04/14] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
2021-06-01 19:35 ` [PATCH v6 05/14] target/ppc: Implement PNOP matheus.ferst
2021-06-01 19:35 ` [PATCH v6 06/14] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
2021-06-01 19:35 ` [PATCH v6 07/14] target/ppc: Implement prefixed integer load instructions matheus.ferst
2021-06-01 19:35 ` [PATCH v6 08/14] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
2021-06-01 19:35 ` [PATCH v6 09/14] target/ppc: Implement prefixed integer store instructions matheus.ferst
2021-06-01 19:35 ` [PATCH v6 10/14] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
2021-06-01 19:35 ` [PATCH v6 11/14] target/ppc: Implement cfuged instruction matheus.ferst
2021-06-01 21:02   ` Richard Henderson
2021-06-01 19:35 ` [PATCH v6 12/14] target/ppc: Implement vcfuged instruction matheus.ferst
2021-06-01 21:09   ` Richard Henderson
2021-06-02  8:51     ` David Gibson
2021-06-01 19:35 ` matheus.ferst [this message]
2021-06-01 19:35 ` [PATCH v6 14/14] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree matheus.ferst
2021-06-01 20:57   ` Richard Henderson
2021-06-02  8:53     ` David Gibson
2021-06-02  8:53 ` [PATCH v6 00/14] Base for adding PowerPC 64-bit instructions David Gibson

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