From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4AFEC47092 for ; Wed, 2 Jun 2021 20:10:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C37A4613EB for ; Wed, 2 Jun 2021 20:10:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229724AbhFBUMV (ORCPT ); Wed, 2 Jun 2021 16:12:21 -0400 Received: from mail-ot1-f48.google.com ([209.85.210.48]:41912 "EHLO mail-ot1-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229467AbhFBUMU (ORCPT ); Wed, 2 Jun 2021 16:12:20 -0400 Received: by mail-ot1-f48.google.com with SMTP id 36-20020a9d0ba70000b02902e0a0a8fe36so3586168oth.8; Wed, 02 Jun 2021 13:10:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=KJXe/j4S+tTBfupUvcLNtHwssps3qp4qDEKF4hgTJ3E=; b=N9tzQSR5uVjPnsM5DTEDzDE7f/qxbn85rgWUaCnR/kEYCd2nHWoimYXxe+YhA/u2Ai Zw3/s5vDVAuPAmNoVj3Mtw3XorE/xfTP0CVvmIR4wCOVPJe9VK0WPpTAQnlQQipKsNLe mNOTcTMcwpfyHPO/B4OnVmp0bmUQAoAfapuYkzkD7o8Ed3WPXT69akMcG21BumIFZuKl WKCsqEMs9E6I73nQ+kwoYN4VHhJhxKhD9DotFT/USSHvAsx0+59xeso0cd+xV/3amfdE jIsNu4vG/i0GIcJP+ylibS7YCNTtJvZcdFtAsp9xRnnWI5oly+MoQUl4keJYBwXGCdRf 5qkg== X-Gm-Message-State: AOAM530DxvHh1g8Js8Va9Ymaf+0c8w2m8+4ReMbhLH7C2fbrryPKDuDm chHOKkqOoTUTQ8D9fIk+PpHLnKPCOQ== X-Google-Smtp-Source: ABdhPJx4iZCcx1NuCo6GfI2rKBzE1Fi8O4daJSQD2hB9/vnoJOnXkkRiZa8E39kJeTxqN6ge2Z8eQA== X-Received: by 2002:a05:6830:164c:: with SMTP id h12mr27991909otr.321.1622664623785; Wed, 02 Jun 2021 13:10:23 -0700 (PDT) Received: from robh.at.kernel.org (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id h9sm189017otn.56.2021.06.02.13.10.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 13:10:22 -0700 (PDT) Received: (nullmailer pid 3907739 invoked by uid 1000); Wed, 02 Jun 2021 20:10:21 -0000 Date: Wed, 2 Jun 2021 15:10:21 -0500 From: Rob Herring To: Steven Lee Cc: Linus Walleij , Bartosz Golaszewski , Joel Stanley , Andrew Jeffery , "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , open list , Hongweiz@ami.com, ryan_chen@aspeedtech.com, billy_tsai@aspeedtech.com Subject: Re: [PATCH v2 1/4] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml. Message-ID: <20210602201021.GA3900491@robh.at.kernel.org> References: <20210527005455.25758-1-steven_lee@aspeedtech.com> <20210527005455.25758-2-steven_lee@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210527005455.25758-2-steven_lee@aspeedtech.com> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Thu, May 27, 2021 at 08:54:50AM +0800, Steven Lee wrote: > SGPIO bindings should be converted as yaml format. > In addition to the file conversion, a new property max-ngpios is > added in the yaml file as well. > The new property is required by the enhanced sgpio driver for > making the configuration of the max number of gpio pins more flexible. The rest of the binding looks fine. Make this property a separate patch if you don't end up dropping it. > > Signed-off-by: Steven Lee > --- > .../bindings/gpio/aspeed,sgpio.yaml | 91 +++++++++++++++++++ > .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ---------- > 2 files changed, 91 insertions(+), 46 deletions(-) > create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml > delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt > > diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml > new file mode 100644 > index 000000000000..02eb0c5023e9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml > @@ -0,0 +1,91 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Aspeed SGPIO controller > + > +maintainers: > + - Andrew Jeffery > + > +description: > + This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC, > + AST2600 have two sgpio master one with 128 pins another one with 80 pins, > + AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial > + GPIO pins can be programmed to support the following options > + - Support interrupt option for each input port and various interrupt > + sensitivity option (level-high, level-low, edge-high, edge-low) > + - Support reset tolerance option for each output port > + - Directly connected to APB bus and its shift clock is from APB bus clock > + divided by a programmable value. > + - Co-work with external signal-chained TTL components (74LV165/74LV595) > + > +properties: > + compatible: > + enum: > + - aspeed,ast2400-sgpiom > + - aspeed,ast2500-sgpiom > + - aspeed,ast2600-sgpiom > + > + reg: > + maxItems: 1 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 > + > + interrupts: > + maxItems: 1 > + > + interrupt-controller: true > + > + clocks: > + maxItems: 1 > + > + ngpios: > + minimum: 0 > + maximum: 128 > + > + max-ngpios: > + description: > + represents the number of actual hardware-supported GPIOs (ie, > + slots within the clocked serial GPIO data). Since each HW GPIO is both an > + input and an output, we provide max_ngpios * 2 lines on our gpiochip > + device. We also use it to define the split between the inputs and > + outputs; the inputs start at line 0, the outputs start at max_ngpios. > + minimum: 0 > + maximum: 128 > + > + bus-frequency: true > + > +required: > + - compatible > + - reg > + - gpio-controller > + - '#gpio-cells' > + - interrupts > + - interrupt-controller > + - ngpios > + - max-ngpios > + - clocks > + - bus-frequency > + > +additionalProperties: false > + > +examples: > + - | > + #include > + sgpio: sgpio@1e780200 { > + #gpio-cells = <2>; > + compatible = "aspeed,ast2500-sgpiom"; > + gpio-controller; > + interrupts = <40>; > + reg = <0x1e780200 0x0100>; > + clocks = <&syscon ASPEED_CLK_APB>; > + interrupt-controller; > + ngpios = <8>; > + max-ngpios = <80>; > + bus-frequency = <12000000>; > + }; > diff --git a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt > deleted file mode 100644 > index be329ea4794f..000000000000 > --- a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt > +++ /dev/null > @@ -1,46 +0,0 @@ > -Aspeed SGPIO controller Device Tree Bindings > --------------------------------------------- > - > -This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full > -featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to > -support the following options: > -- Support interrupt option for each input port and various interrupt > - sensitivity option (level-high, level-low, edge-high, edge-low) > -- Support reset tolerance option for each output port > -- Directly connected to APB bus and its shift clock is from APB bus clock > - divided by a programmable value. > -- Co-work with external signal-chained TTL components (74LV165/74LV595) > - > -Required properties: > - > -- compatible : Should be one of > - "aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio" > -- #gpio-cells : Should be 2, see gpio.txt > -- reg : Address and length of the register set for the device > -- gpio-controller : Marks the device node as a GPIO controller > -- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt > -- interrupt-controller : Mark the GPIO controller as an interrupt-controller > -- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose > - 2 software GPIOs per hardware GPIO: one for hardware input, one for hardware > - output. Up to 80 pins, must be a multiple of 8. > -- clocks : A phandle to the APB clock for SGPM clock division > -- bus-frequency : SGPM CLK frequency > - > -The sgpio and interrupt properties are further described in their respective > -bindings documentation: > - > -- Documentation/devicetree/bindings/gpio/gpio.txt > -- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt > - > - Example: > - sgpio: sgpio@1e780200 { > - #gpio-cells = <2>; > - compatible = "aspeed,ast2500-sgpio"; > - gpio-controller; > - interrupts = <40>; > - reg = <0x1e780200 0x0100>; > - clocks = <&syscon ASPEED_CLK_APB>; > - interrupt-controller; > - ngpios = <8>; > - bus-frequency = <12000000>; > - }; > -- > 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F6CAC4708F for ; Wed, 2 Jun 2021 20:12:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D440C613B1 for ; Wed, 2 Jun 2021 20:12:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D440C613B1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=EVyMvsw0NLA7Nzj24/7Ei9kIvapYAnsVnokSoRezkf4=; b=3ZQw1qaU2Va+Rl z142whUUJCVfnvauiI+6qq7xkplbMrkI14w2Hql96Vy6ojOzElwH3g4IcRJLtovsjojaTffJp4LjB lTT87KPgJZHEwnOGv/LU7dj2KV91Q1ahOSiY8DDCjb6uA1ka8y951+a6zaYPrZoDCWmBaxPwfq4gI 0flGChBmm1vZ1SEdTd1ELCSTyd31W37LQRYHb4T6pbN28mufAheb0C6R40kJJF3XSMtlR0Gpx/dGq Ae9Nl6LZdn3fvqv3+h+HmMVUgD4I7w0JOkwHNn73U4qOkm6hZmMjqzbykvK6zVEXNwFM69phglmT0 tqWkocBcQ+UKd4Yg0E6A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1loXC8-0065Dp-Pr; Wed, 02 Jun 2021 20:10:28 +0000 Received: from mail-ot1-f44.google.com ([209.85.210.44]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1loXC4-00657r-Ff for linux-arm-kernel@lists.infradead.org; Wed, 02 Jun 2021 20:10:26 +0000 Received: by mail-ot1-f44.google.com with SMTP id v19-20020a0568301413b0290304f00e3d88so3593464otp.4 for ; Wed, 02 Jun 2021 13:10:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=KJXe/j4S+tTBfupUvcLNtHwssps3qp4qDEKF4hgTJ3E=; b=pGJyNx+w5Rs+uIDXAXZBVD9eocfd4tkQMrGLGBKH9gza8TWEmpUIRfoyPxnHtikTG4 pmQvP8A5W2YnHXlgHT1ObFTMhkTzmccQ6IsdJ6ORwxTyEQ3QM/DCpOrYEX9E7GLNrGSM rsREUxqkmctUHjDn8SgMfNQho8Vf907Pzd508hsUklh8MRTTkA6jLtOOPXvweNFjuGpo 6a9fKrRL+iO+RPboICK7UMkDTC8VLrq98PhqRKKKOG6EWF1iI65GZaQOgbD3i+iI5mXo vUctjIzUBRm6/d+rKoR0aW34ihZXliwoMTXc9oOi5Z5Pl9nxHESY8TQE3LOi5BR82vZv JAZg== X-Gm-Message-State: AOAM532136/QbbhmgOl0PAm+VsCPum/8bzPwfhgMU7LzPtXo640M6W24 5h2bLPDWtYiGNznieWdSrA== X-Google-Smtp-Source: ABdhPJx4iZCcx1NuCo6GfI2rKBzE1Fi8O4daJSQD2hB9/vnoJOnXkkRiZa8E39kJeTxqN6ge2Z8eQA== X-Received: by 2002:a05:6830:164c:: with SMTP id h12mr27991909otr.321.1622664623785; Wed, 02 Jun 2021 13:10:23 -0700 (PDT) Received: from robh.at.kernel.org (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id h9sm189017otn.56.2021.06.02.13.10.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Jun 2021 13:10:22 -0700 (PDT) Received: (nullmailer pid 3907739 invoked by uid 1000); Wed, 02 Jun 2021 20:10:21 -0000 Date: Wed, 2 Jun 2021 15:10:21 -0500 From: Rob Herring To: Steven Lee Cc: Linus Walleij , Bartosz Golaszewski , Joel Stanley , Andrew Jeffery , "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , open list , Hongweiz@ami.com, ryan_chen@aspeedtech.com, billy_tsai@aspeedtech.com Subject: Re: [PATCH v2 1/4] dt-bindings: aspeed-sgpio: Convert txt bindings to yaml. Message-ID: <20210602201021.GA3900491@robh.at.kernel.org> References: <20210527005455.25758-1-steven_lee@aspeedtech.com> <20210527005455.25758-2-steven_lee@aspeedtech.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210527005455.25758-2-steven_lee@aspeedtech.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210602_131024_570605_5F2A64C6 X-CRM114-Status: GOOD ( 33.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, May 27, 2021 at 08:54:50AM +0800, Steven Lee wrote: > SGPIO bindings should be converted as yaml format. > In addition to the file conversion, a new property max-ngpios is > added in the yaml file as well. > The new property is required by the enhanced sgpio driver for > making the configuration of the max number of gpio pins more flexible. The rest of the binding looks fine. Make this property a separate patch if you don't end up dropping it. > > Signed-off-by: Steven Lee > --- > .../bindings/gpio/aspeed,sgpio.yaml | 91 +++++++++++++++++++ > .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ---------- > 2 files changed, 91 insertions(+), 46 deletions(-) > create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml > delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt > > diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml > new file mode 100644 > index 000000000000..02eb0c5023e9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml > @@ -0,0 +1,91 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Aspeed SGPIO controller > + > +maintainers: > + - Andrew Jeffery > + > +description: > + This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC, > + AST2600 have two sgpio master one with 128 pins another one with 80 pins, > + AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial > + GPIO pins can be programmed to support the following options > + - Support interrupt option for each input port and various interrupt > + sensitivity option (level-high, level-low, edge-high, edge-low) > + - Support reset tolerance option for each output port > + - Directly connected to APB bus and its shift clock is from APB bus clock > + divided by a programmable value. > + - Co-work with external signal-chained TTL components (74LV165/74LV595) > + > +properties: > + compatible: > + enum: > + - aspeed,ast2400-sgpiom > + - aspeed,ast2500-sgpiom > + - aspeed,ast2600-sgpiom > + > + reg: > + maxItems: 1 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 > + > + interrupts: > + maxItems: 1 > + > + interrupt-controller: true > + > + clocks: > + maxItems: 1 > + > + ngpios: > + minimum: 0 > + maximum: 128 > + > + max-ngpios: > + description: > + represents the number of actual hardware-supported GPIOs (ie, > + slots within the clocked serial GPIO data). Since each HW GPIO is both an > + input and an output, we provide max_ngpios * 2 lines on our gpiochip > + device. We also use it to define the split between the inputs and > + outputs; the inputs start at line 0, the outputs start at max_ngpios. > + minimum: 0 > + maximum: 128 > + > + bus-frequency: true > + > +required: > + - compatible > + - reg > + - gpio-controller > + - '#gpio-cells' > + - interrupts > + - interrupt-controller > + - ngpios > + - max-ngpios > + - clocks > + - bus-frequency > + > +additionalProperties: false > + > +examples: > + - | > + #include > + sgpio: sgpio@1e780200 { > + #gpio-cells = <2>; > + compatible = "aspeed,ast2500-sgpiom"; > + gpio-controller; > + interrupts = <40>; > + reg = <0x1e780200 0x0100>; > + clocks = <&syscon ASPEED_CLK_APB>; > + interrupt-controller; > + ngpios = <8>; > + max-ngpios = <80>; > + bus-frequency = <12000000>; > + }; > diff --git a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt > deleted file mode 100644 > index be329ea4794f..000000000000 > --- a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt > +++ /dev/null > @@ -1,46 +0,0 @@ > -Aspeed SGPIO controller Device Tree Bindings > --------------------------------------------- > - > -This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full > -featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to > -support the following options: > -- Support interrupt option for each input port and various interrupt > - sensitivity option (level-high, level-low, edge-high, edge-low) > -- Support reset tolerance option for each output port > -- Directly connected to APB bus and its shift clock is from APB bus clock > - divided by a programmable value. > -- Co-work with external signal-chained TTL components (74LV165/74LV595) > - > -Required properties: > - > -- compatible : Should be one of > - "aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio" > -- #gpio-cells : Should be 2, see gpio.txt > -- reg : Address and length of the register set for the device > -- gpio-controller : Marks the device node as a GPIO controller > -- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt > -- interrupt-controller : Mark the GPIO controller as an interrupt-controller > -- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose > - 2 software GPIOs per hardware GPIO: one for hardware input, one for hardware > - output. Up to 80 pins, must be a multiple of 8. > -- clocks : A phandle to the APB clock for SGPM clock division > -- bus-frequency : SGPM CLK frequency > - > -The sgpio and interrupt properties are further described in their respective > -bindings documentation: > - > -- Documentation/devicetree/bindings/gpio/gpio.txt > -- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt > - > - Example: > - sgpio: sgpio@1e780200 { > - #gpio-cells = <2>; > - compatible = "aspeed,ast2500-sgpio"; > - gpio-controller; > - interrupts = <40>; > - reg = <0x1e780200 0x0100>; > - clocks = <&syscon ASPEED_CLK_APB>; > - interrupt-controller; > - ngpios = <8>; > - bus-frequency = <12000000>; > - }; > -- > 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel