From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1286C47097 for ; Thu, 3 Jun 2021 12:59:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8B763613B4 for ; Thu, 3 Jun 2021 12:59:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231173AbhFCNAt (ORCPT ); Thu, 3 Jun 2021 09:00:49 -0400 Received: from foss.arm.com ([217.140.110.172]:40942 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229950AbhFCNAs (ORCPT ); Thu, 3 Jun 2021 09:00:48 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B34BC1063; Thu, 3 Jun 2021 05:59:03 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.3.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4929C3F774; Thu, 3 Jun 2021 05:58:59 -0700 (PDT) Date: Thu, 3 Jun 2021 13:58:56 +0100 From: Mark Rutland To: Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Catalin Marinas , Marc Zyngier , Greg Kroah-Hartman , Peter Zijlstra , Morten Rasmussen , Qais Yousef , Suren Baghdasaryan , Quentin Perret , Tejun Heo , Johannes Weiner , Ingo Molnar , Juri Lelli , Vincent Guittot , "Rafael J. Wysocki" , Dietmar Eggemann , Daniel Bristot de Oliveira , Valentin Schneider , kernel-team@android.com Subject: Re: [PATCH v8 15/19] arm64: Prevent offlining first CPU with 32-bit EL0 on mismatched system Message-ID: <20210603125856.GC48596@C02TD0UTHF1T.local> References: <20210602164719.31777-1-will@kernel.org> <20210602164719.31777-16-will@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210602164719.31777-16-will@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jun 02, 2021 at 05:47:15PM +0100, Will Deacon wrote: > If we want to support 32-bit applications, then when we identify a CPU > with mismatched 32-bit EL0 support we must ensure that we will always > have an active 32-bit CPU available to us from then on. This is important > for the scheduler, because is_cpu_allowed() will be constrained to 32-bit > CPUs for compat tasks and forced migration due to a hotplug event will > hang if no 32-bit CPUs are available. > > On detecting a mismatch, prevent offlining of either the mismatching CPU > if it is 32-bit capable, or find the first active 32-bit capable CPU > otherwise. > > Reviewed-by: Catalin Marinas > Signed-off-by: Will Deacon > --- > arch/arm64/kernel/cpufeature.c | 20 +++++++++++++++++++- > 1 file changed, 19 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 4194a47de62d..b31d7a1eaed6 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2877,15 +2877,33 @@ void __init setup_cpu_features(void) > > static int enable_mismatched_32bit_el0(unsigned int cpu) > { > + static int lucky_winner = -1; This is cute, but could we please give it a meaningful name, e.g. `pinned_cpu` ? > + > struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); > bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); > > if (cpu_32bit) { > cpumask_set_cpu(cpu, cpu_32bit_el0_mask); > static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); > - setup_elf_hwcaps(compat_elf_hwcaps); > } > > + if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) > + return 0; > + > + if (lucky_winner >= 0) > + return 0; > + > + /* > + * We've detected a mismatch. We need to keep one of our CPUs with > + * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting > + * every CPU in the system for a 32-bit task. > + */ > + lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, > + cpu_active_mask); > + get_cpu_device(lucky_winner)->offline_disabled = true; > + setup_elf_hwcaps(compat_elf_hwcaps); > + pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", > + cpu, lucky_winner); > return 0; > } I guess this is going to play havoc with kexec and hibernate. :/ Thanks, Mark. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14E55C47096 for ; Thu, 3 Jun 2021 13:01:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C7C00613F3 for ; Thu, 3 Jun 2021 13:01:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C7C00613F3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pfGpxXfykrwIsZjeRKA7kP7iAHBEGzSFQz4+pdM4SLM=; b=4vg4HFEWkVx71s cHjRMMQduJcR9nh7ZRdSeENVDKTjElGlK3sHpa+7/Ev1hnQNEP5861EdKTJ16+qFCnV0IKeZSt2MN 81xr5XfcbcstY5/KlHiOeYLOotL2yUEieJKaN/1ZFg91lQlgitURCYLsA3+R9ouhwsYypI24k9T85 wTBe0NbQFk4Y7XcClKrh/kTWDMLnEqdJD9umxkXXyfu/HyqaISkglwlepZvIPp/YQbUqcvyz1rp1G SgIy8PvMTzAKvrn3B0FFsi2SV7tmfp0FyaqUhBZ0a9H3AhZasc4ZhXSqhmdhyNgOAyx/dBxTLRCAI tULf1KmErpCQ38me7XRQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lomwQ-008oDl-0v; Thu, 03 Jun 2021 12:59:19 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lomwF-008oBy-8t for linux-arm-kernel@lists.infradead.org; Thu, 03 Jun 2021 12:59:08 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B34BC1063; Thu, 3 Jun 2021 05:59:03 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.3.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4929C3F774; Thu, 3 Jun 2021 05:58:59 -0700 (PDT) Date: Thu, 3 Jun 2021 13:58:56 +0100 From: Mark Rutland To: Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Catalin Marinas , Marc Zyngier , Greg Kroah-Hartman , Peter Zijlstra , Morten Rasmussen , Qais Yousef , Suren Baghdasaryan , Quentin Perret , Tejun Heo , Johannes Weiner , Ingo Molnar , Juri Lelli , Vincent Guittot , "Rafael J. Wysocki" , Dietmar Eggemann , Daniel Bristot de Oliveira , Valentin Schneider , kernel-team@android.com Subject: Re: [PATCH v8 15/19] arm64: Prevent offlining first CPU with 32-bit EL0 on mismatched system Message-ID: <20210603125856.GC48596@C02TD0UTHF1T.local> References: <20210602164719.31777-1-will@kernel.org> <20210602164719.31777-16-will@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210602164719.31777-16-will@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210603_055907_437754_BBB91BA0 X-CRM114-Status: GOOD ( 27.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jun 02, 2021 at 05:47:15PM +0100, Will Deacon wrote: > If we want to support 32-bit applications, then when we identify a CPU > with mismatched 32-bit EL0 support we must ensure that we will always > have an active 32-bit CPU available to us from then on. This is important > for the scheduler, because is_cpu_allowed() will be constrained to 32-bit > CPUs for compat tasks and forced migration due to a hotplug event will > hang if no 32-bit CPUs are available. > > On detecting a mismatch, prevent offlining of either the mismatching CPU > if it is 32-bit capable, or find the first active 32-bit capable CPU > otherwise. > > Reviewed-by: Catalin Marinas > Signed-off-by: Will Deacon > --- > arch/arm64/kernel/cpufeature.c | 20 +++++++++++++++++++- > 1 file changed, 19 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 4194a47de62d..b31d7a1eaed6 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2877,15 +2877,33 @@ void __init setup_cpu_features(void) > > static int enable_mismatched_32bit_el0(unsigned int cpu) > { > + static int lucky_winner = -1; This is cute, but could we please give it a meaningful name, e.g. `pinned_cpu` ? > + > struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); > bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); > > if (cpu_32bit) { > cpumask_set_cpu(cpu, cpu_32bit_el0_mask); > static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); > - setup_elf_hwcaps(compat_elf_hwcaps); > } > > + if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) > + return 0; > + > + if (lucky_winner >= 0) > + return 0; > + > + /* > + * We've detected a mismatch. We need to keep one of our CPUs with > + * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting > + * every CPU in the system for a 32-bit task. > + */ > + lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, > + cpu_active_mask); > + get_cpu_device(lucky_winner)->offline_disabled = true; > + setup_elf_hwcaps(compat_elf_hwcaps); > + pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", > + cpu, lucky_winner); > return 0; > } I guess this is going to play havoc with kexec and hibernate. :/ Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel