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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id q16sm392945lfn.220.2021.06.03.09.36.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 09:36:45 -0700 (PDT) Date: Thu, 3 Jun 2021 18:36:45 +0200 From: "Edgar E. Iglesias" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Subject: Re: [PATCH 5/6] target/microblaze: Replace magic values by proper definitions Message-ID: <20210603163645.GL477672@toto> References: <20210603090310.2749892-1-f4bug@amsat.org> <20210603090310.2749892-6-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210603090310.2749892-6-f4bug@amsat.org> Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Jun 03, 2021 at 11:03:09AM +0200, Philippe Mathieu-Daudé wrote: > Use the Exception Status Register definitions from "cpu.h". > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias > --- > target/microblaze/helper.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c > index 20dbd673136..d537f300ca6 100644 > --- a/target/microblaze/helper.c > +++ b/target/microblaze/helper.c > @@ -99,14 +99,22 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > mmu_idx, address); > > env->ear = address; > + > + env->esr = (access_type == MMU_DATA_STORE) ? ESR_S : 0; > switch (lu.err) { > case ERR_PROT: > - env->esr = access_type == MMU_INST_FETCH ? 17 : 16; > - env->esr |= (access_type == MMU_DATA_STORE) << 10; > + if (access_type == MMU_INST_FETCH) { > + env->esr |= ESR_EC_INSN_STORAGE; > + } else { > + env->esr |= ESR_EC_DATA_STORAGE; > + } > break; > case ERR_MISS: > - env->esr = access_type == MMU_INST_FETCH ? 19 : 18; > - env->esr |= (access_type == MMU_DATA_STORE) << 10; > + if (access_type == MMU_INST_FETCH) { > + env->esr |= ESR_EC_INSN_TLB; > + } else { > + env->esr |= ESR_EC_DATA_TLB; > + } > break; > default: > abort(); > -- > 2.26.3 >