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From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
	qemu-arm@nongnu.org,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Claudio Fontana" <cfontana@suse.de>,
	"Peter Maydell" <peter.maydell@linaro.org>
Subject: [PATCH v16 40/99] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code
Date: Fri,  4 Jun 2021 16:52:13 +0100	[thread overview]
Message-ID: <20210604155312.15902-41-alex.bennee@linaro.org> (raw)
In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org>

From: Claudio Fontana <cfontana@suse.de>

and arm_phys_excp_target_el since it is tied up inside the
same #ifdef block.

aarch64_sync_32_to_64 and aarch64_sync_64_to_32 are
mixed in with the TCG helpers, but they shouldn't, as they
are needed for KVM too.

kvm_arch_get_registers()
{
    if (!is_a64(env)) {
        aarch64_sync_64_to_32(env);
    }
    write_kvmstate_to_list(cpu);
    write_list_to_cpustate(cpu);
    ...
}

kvm_arch_put_registers()
{
    if (!is_a64(env)) {
        aarch64_sync_32_to_64(env);
    }
    write_cpustate_to_list(cpu, true);
    write_list_to_kvmstate(cpu, level)
    ...
}

Move to the cpu module.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 target/arm/cpu-sysemu.c | 215 +++++++++++++++++++++++++++++++++++++
 target/arm/cpu-user.c   |  11 ++
 target/arm/tcg/helper.c | 232 +---------------------------------------
 3 files changed, 229 insertions(+), 229 deletions(-)

diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c
index 3add2c2439..7a314bf805 100644
--- a/target/arm/cpu-sysemu.c
+++ b/target/arm/cpu-sysemu.c
@@ -133,3 +133,218 @@ void switch_mode(CPUARMState *env, int mode)
     env->banked_r14[r14_bank_number(old_mode)] = env->regs[14];
     env->regs[14] = env->banked_r14[r14_bank_number(mode)];
 }
+
+/*
+ * Function used to synchronize QEMU's AArch64 register set with AArch32
+ * register set.  This is necessary when switching between AArch32 and AArch64
+ * execution state.
+ */
+void aarch64_sync_32_to_64(CPUARMState *env)
+{
+    int i;
+    uint32_t mode = env->uncached_cpsr & CPSR_M;
+
+    /* We can blanket copy R[0:7] to X[0:7] */
+    for (i = 0; i < 8; i++) {
+        env->xregs[i] = env->regs[i];
+    }
+
+    /*
+     * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
+     * Otherwise, they come from the banked user regs.
+     */
+    if (mode == ARM_CPU_MODE_FIQ) {
+        for (i = 8; i < 13; i++) {
+            env->xregs[i] = env->usr_regs[i - 8];
+        }
+    } else {
+        for (i = 8; i < 13; i++) {
+            env->xregs[i] = env->regs[i];
+        }
+    }
+
+    /*
+     * Registers x13-x23 are the various mode SP and FP registers. Registers
+     * r13 and r14 are only copied if we are in that mode, otherwise we copy
+     * from the mode banked register.
+     */
+    if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
+        env->xregs[13] = env->regs[13];
+        env->xregs[14] = env->regs[14];
+    } else {
+        env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
+        /* HYP is an exception in that it is copied from r14 */
+        if (mode == ARM_CPU_MODE_HYP) {
+            env->xregs[14] = env->regs[14];
+        } else {
+            env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)];
+        }
+    }
+
+    if (mode == ARM_CPU_MODE_HYP) {
+        env->xregs[15] = env->regs[13];
+    } else {
+        env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
+    }
+
+    if (mode == ARM_CPU_MODE_IRQ) {
+        env->xregs[16] = env->regs[14];
+        env->xregs[17] = env->regs[13];
+    } else {
+        env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)];
+        env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
+    }
+
+    if (mode == ARM_CPU_MODE_SVC) {
+        env->xregs[18] = env->regs[14];
+        env->xregs[19] = env->regs[13];
+    } else {
+        env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)];
+        env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
+    }
+
+    if (mode == ARM_CPU_MODE_ABT) {
+        env->xregs[20] = env->regs[14];
+        env->xregs[21] = env->regs[13];
+    } else {
+        env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)];
+        env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
+    }
+
+    if (mode == ARM_CPU_MODE_UND) {
+        env->xregs[22] = env->regs[14];
+        env->xregs[23] = env->regs[13];
+    } else {
+        env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)];
+        env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
+    }
+
+    /*
+     * Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
+     * mode, then we can copy from r8-r14.  Otherwise, we copy from the
+     * FIQ bank for r8-r14.
+     */
+    if (mode == ARM_CPU_MODE_FIQ) {
+        for (i = 24; i < 31; i++) {
+            env->xregs[i] = env->regs[i - 16];   /* X[24:30] <- R[8:14] */
+        }
+    } else {
+        for (i = 24; i < 29; i++) {
+            env->xregs[i] = env->fiq_regs[i - 24];
+        }
+        env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
+        env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)];
+    }
+
+    env->pc = env->regs[15];
+}
+
+/*
+ * Function used to synchronize QEMU's AArch32 register set with AArch64
+ * register set.  This is necessary when switching between AArch32 and AArch64
+ * execution state.
+ */
+void aarch64_sync_64_to_32(CPUARMState *env)
+{
+    int i;
+    uint32_t mode = env->uncached_cpsr & CPSR_M;
+
+    /* We can blanket copy X[0:7] to R[0:7] */
+    for (i = 0; i < 8; i++) {
+        env->regs[i] = env->xregs[i];
+    }
+
+    /*
+     * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
+     * Otherwise, we copy x8-x12 into the banked user regs.
+     */
+    if (mode == ARM_CPU_MODE_FIQ) {
+        for (i = 8; i < 13; i++) {
+            env->usr_regs[i - 8] = env->xregs[i];
+        }
+    } else {
+        for (i = 8; i < 13; i++) {
+            env->regs[i] = env->xregs[i];
+        }
+    }
+
+    /*
+     * Registers r13 & r14 depend on the current mode.
+     * If we are in a given mode, we copy the corresponding x registers to r13
+     * and r14.  Otherwise, we copy the x register to the banked r13 and r14
+     * for the mode.
+     */
+    if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
+        env->regs[13] = env->xregs[13];
+        env->regs[14] = env->xregs[14];
+    } else {
+        env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
+
+        /*
+         * HYP is an exception in that it does not have its own banked r14 but
+         * shares the USR r14
+         */
+        if (mode == ARM_CPU_MODE_HYP) {
+            env->regs[14] = env->xregs[14];
+        } else {
+            env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
+        }
+    }
+
+    if (mode == ARM_CPU_MODE_HYP) {
+        env->regs[13] = env->xregs[15];
+    } else {
+        env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
+    }
+
+    if (mode == ARM_CPU_MODE_IRQ) {
+        env->regs[14] = env->xregs[16];
+        env->regs[13] = env->xregs[17];
+    } else {
+        env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
+        env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
+    }
+
+    if (mode == ARM_CPU_MODE_SVC) {
+        env->regs[14] = env->xregs[18];
+        env->regs[13] = env->xregs[19];
+    } else {
+        env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
+        env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
+    }
+
+    if (mode == ARM_CPU_MODE_ABT) {
+        env->regs[14] = env->xregs[20];
+        env->regs[13] = env->xregs[21];
+    } else {
+        env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
+        env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
+    }
+
+    if (mode == ARM_CPU_MODE_UND) {
+        env->regs[14] = env->xregs[22];
+        env->regs[13] = env->xregs[23];
+    } else {
+        env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
+        env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
+    }
+
+    /*
+     * Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
+     * mode, then we can copy to r8-r14.  Otherwise, we copy to the
+     * FIQ bank for r8-r14.
+     */
+    if (mode == ARM_CPU_MODE_FIQ) {
+        for (i = 24; i < 31; i++) {
+            env->regs[i - 16] = env->xregs[i];   /* X[24:30] -> R[8:14] */
+        }
+    } else {
+        for (i = 24; i < 29; i++) {
+            env->fiq_regs[i - 24] = env->xregs[i];
+        }
+        env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
+        env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
+    }
+
+    env->regs[15] = env->pc;
+}
diff --git a/target/arm/cpu-user.c b/target/arm/cpu-user.c
index a72b7f5703..0225089e46 100644
--- a/target/arm/cpu-user.c
+++ b/target/arm/cpu-user.c
@@ -22,3 +22,14 @@ void switch_mode(CPUARMState *env, int mode)
         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
     }
 }
+
+void aarch64_sync_64_to_32(CPUARMState *env)
+{
+    g_assert_not_reached();
+}
+
+uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
+                                 uint32_t cur_el, bool secure)
+{
+    return 1;
+}
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index 0e3f403e56..9dd83911f2 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -590,22 +590,10 @@ uint32_t HELPER(rbit)(uint32_t x)
     return revbit32(x);
 }
 
-#ifdef CONFIG_USER_ONLY
-
-uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
-                                 uint32_t cur_el, bool secure)
-{
-    return 1;
-}
-
-void aarch64_sync_64_to_32(CPUARMState *env)
-{
-    g_assert_not_reached();
-}
-
-#else
+#ifndef CONFIG_USER_ONLY
 
-/* Physical Interrupt Target EL Lookup Table
+/*
+ * Physical Interrupt Target EL Lookup Table
  *
  * [ From ARM ARM section G1.13.4 (Table G1-15) ]
  *
@@ -754,220 +742,6 @@ void arm_log_exception(int idx)
     }
 }
 
-/*
- * Function used to synchronize QEMU's AArch64 register set with AArch32
- * register set.  This is necessary when switching between AArch32 and AArch64
- * execution state.
- */
-void aarch64_sync_32_to_64(CPUARMState *env)
-{
-    int i;
-    uint32_t mode = env->uncached_cpsr & CPSR_M;
-
-    /* We can blanket copy R[0:7] to X[0:7] */
-    for (i = 0; i < 8; i++) {
-        env->xregs[i] = env->regs[i];
-    }
-
-    /*
-     * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
-     * Otherwise, they come from the banked user regs.
-     */
-    if (mode == ARM_CPU_MODE_FIQ) {
-        for (i = 8; i < 13; i++) {
-            env->xregs[i] = env->usr_regs[i - 8];
-        }
-    } else {
-        for (i = 8; i < 13; i++) {
-            env->xregs[i] = env->regs[i];
-        }
-    }
-
-    /*
-     * Registers x13-x23 are the various mode SP and FP registers. Registers
-     * r13 and r14 are only copied if we are in that mode, otherwise we copy
-     * from the mode banked register.
-     */
-    if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
-        env->xregs[13] = env->regs[13];
-        env->xregs[14] = env->regs[14];
-    } else {
-        env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
-        /* HYP is an exception in that it is copied from r14 */
-        if (mode == ARM_CPU_MODE_HYP) {
-            env->xregs[14] = env->regs[14];
-        } else {
-            env->xregs[14] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)];
-        }
-    }
-
-    if (mode == ARM_CPU_MODE_HYP) {
-        env->xregs[15] = env->regs[13];
-    } else {
-        env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
-    }
-
-    if (mode == ARM_CPU_MODE_IRQ) {
-        env->xregs[16] = env->regs[14];
-        env->xregs[17] = env->regs[13];
-    } else {
-        env->xregs[16] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)];
-        env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
-    }
-
-    if (mode == ARM_CPU_MODE_SVC) {
-        env->xregs[18] = env->regs[14];
-        env->xregs[19] = env->regs[13];
-    } else {
-        env->xregs[18] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)];
-        env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
-    }
-
-    if (mode == ARM_CPU_MODE_ABT) {
-        env->xregs[20] = env->regs[14];
-        env->xregs[21] = env->regs[13];
-    } else {
-        env->xregs[20] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)];
-        env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
-    }
-
-    if (mode == ARM_CPU_MODE_UND) {
-        env->xregs[22] = env->regs[14];
-        env->xregs[23] = env->regs[13];
-    } else {
-        env->xregs[22] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)];
-        env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
-    }
-
-    /*
-     * Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
-     * mode, then we can copy from r8-r14.  Otherwise, we copy from the
-     * FIQ bank for r8-r14.
-     */
-    if (mode == ARM_CPU_MODE_FIQ) {
-        for (i = 24; i < 31; i++) {
-            env->xregs[i] = env->regs[i - 16];   /* X[24:30] <- R[8:14] */
-        }
-    } else {
-        for (i = 24; i < 29; i++) {
-            env->xregs[i] = env->fiq_regs[i - 24];
-        }
-        env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
-        env->xregs[30] = env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)];
-    }
-
-    env->pc = env->regs[15];
-}
-
-/*
- * Function used to synchronize QEMU's AArch32 register set with AArch64
- * register set.  This is necessary when switching between AArch32 and AArch64
- * execution state.
- */
-void aarch64_sync_64_to_32(CPUARMState *env)
-{
-    int i;
-    uint32_t mode = env->uncached_cpsr & CPSR_M;
-
-    /* We can blanket copy X[0:7] to R[0:7] */
-    for (i = 0; i < 8; i++) {
-        env->regs[i] = env->xregs[i];
-    }
-
-    /*
-     * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
-     * Otherwise, we copy x8-x12 into the banked user regs.
-     */
-    if (mode == ARM_CPU_MODE_FIQ) {
-        for (i = 8; i < 13; i++) {
-            env->usr_regs[i - 8] = env->xregs[i];
-        }
-    } else {
-        for (i = 8; i < 13; i++) {
-            env->regs[i] = env->xregs[i];
-        }
-    }
-
-    /*
-     * Registers r13 & r14 depend on the current mode.
-     * If we are in a given mode, we copy the corresponding x registers to r13
-     * and r14.  Otherwise, we copy the x register to the banked r13 and r14
-     * for the mode.
-     */
-    if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
-        env->regs[13] = env->xregs[13];
-        env->regs[14] = env->xregs[14];
-    } else {
-        env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
-
-        /*
-         * HYP is an exception in that it does not have its own banked r14 but
-         * shares the USR r14
-         */
-        if (mode == ARM_CPU_MODE_HYP) {
-            env->regs[14] = env->xregs[14];
-        } else {
-            env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
-        }
-    }
-
-    if (mode == ARM_CPU_MODE_HYP) {
-        env->regs[13] = env->xregs[15];
-    } else {
-        env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
-    }
-
-    if (mode == ARM_CPU_MODE_IRQ) {
-        env->regs[14] = env->xregs[16];
-        env->regs[13] = env->xregs[17];
-    } else {
-        env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
-        env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
-    }
-
-    if (mode == ARM_CPU_MODE_SVC) {
-        env->regs[14] = env->xregs[18];
-        env->regs[13] = env->xregs[19];
-    } else {
-        env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
-        env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
-    }
-
-    if (mode == ARM_CPU_MODE_ABT) {
-        env->regs[14] = env->xregs[20];
-        env->regs[13] = env->xregs[21];
-    } else {
-        env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
-        env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
-    }
-
-    if (mode == ARM_CPU_MODE_UND) {
-        env->regs[14] = env->xregs[22];
-        env->regs[13] = env->xregs[23];
-    } else {
-        env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
-        env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
-    }
-
-    /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
-     * mode, then we can copy to r8-r14.  Otherwise, we copy to the
-     * FIQ bank for r8-r14.
-     */
-    if (mode == ARM_CPU_MODE_FIQ) {
-        for (i = 24; i < 31; i++) {
-            env->regs[i - 16] = env->xregs[i];   /* X[24:30] -> R[8:14] */
-        }
-    } else {
-        for (i = 24; i < 29; i++) {
-            env->fiq_regs[i - 24] = env->xregs[i];
-        }
-        env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
-        env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
-    }
-
-    env->regs[15] = env->pc;
-}
-
 static void take_aarch32_exception(CPUARMState *env, int new_mode,
                                    uint32_t mask, uint32_t offset,
                                    uint32_t newpc)
-- 
2.20.1



  parent reply	other threads:[~2021-06-04 17:11 UTC|newest]

Thread overview: 207+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-04 15:51 [PATCH v16 00/99] arm tcg/kvm refactor and split with kvm only support Alex Bennée
2021-06-04 15:51 ` [PATCH v16 01/99] MAINTAINERS: Add qtest/arm-cpu-features.c to ARM TCG CPUs section Alex Bennée
2021-06-04 18:26   ` Richard Henderson
2021-06-04 15:51 ` [PATCH v16 02/99] accel: Introduce 'query-accels' QMP command Alex Bennée
2021-06-07 13:07   ` Thomas Huth
2021-06-08  9:07     ` Philippe Mathieu-Daudé
2021-06-08 15:41   ` Markus Armbruster
2021-06-08 15:43     ` Philippe Mathieu-Daudé
2021-06-04 15:51 ` [PATCH v16 03/99] qtest: Add qtest_has_accel() method Alex Bennée
2021-06-07 13:16   ` Thomas Huth
2021-06-08  9:48     ` Philippe Mathieu-Daudé
2021-06-04 15:51 ` [PATCH v16 04/99] qtest/arm-cpu-features: Use generic qtest_has_accel() to check for KVM Alex Bennée
2021-06-04 21:01   ` Richard Henderson
2021-06-07 13:22   ` Thomas Huth
2021-06-08  8:22     ` Philippe Mathieu-Daudé
2021-06-08 10:49       ` Philippe Mathieu-Daudé
2021-06-08 12:39         ` Philippe Mathieu-Daudé
2021-06-08 14:28           ` Eric Blake
2021-06-08 17:20           ` Claudio Fontana
2021-06-04 15:51 ` [PATCH v16 05/99] qtest/arm-cpu-features: Restrict sve_tests_sve_off_kvm test to KVM Alex Bennée
2021-06-04 21:02   ` Richard Henderson
2021-06-04 15:51 ` [PATCH v16 06/99] qtest/arm-cpu-features: Remove TCG fallback to KVM specific tests Alex Bennée
2021-06-04 21:03   ` Richard Henderson
2021-06-07 13:28   ` Thomas Huth
2021-06-08  8:23     ` Philippe Mathieu-Daudé
2021-06-04 15:51 ` [PATCH v16 07/99] qtest/arm-cpu-features: Use generic qtest_has_accel() to check for TCG Alex Bennée
2021-06-04 21:04   ` Richard Henderson
2021-06-07 13:32   ` Thomas Huth
2021-06-04 15:51 ` [PATCH v16 08/99] qtest/migration-test: Skip tests if KVM not builtin on s390x/ppc64 Alex Bennée
2021-06-04 21:11   ` Richard Henderson
2021-06-08  8:26     ` Philippe Mathieu-Daudé
2021-06-07 13:33   ` Thomas Huth
2021-06-04 15:51 ` [PATCH v16 09/99] qtest/bios-tables-test: Rename tests not TCG specific Alex Bennée
2021-06-07 13:39   ` Thomas Huth
2021-06-08  8:33     ` Philippe Mathieu-Daudé
2021-06-04 15:51 ` [PATCH v16 10/99] qtest/bios-tables-test: Rename TCG specific tests Alex Bennée
2021-06-07 13:44   ` Thomas Huth
2021-06-04 15:51 ` [PATCH v16 11/99] qtest/bios-tables-test: Make test build-independent from accelerator Alex Bennée
2021-06-04 21:14   ` Richard Henderson
2021-06-07 13:47   ` Thomas Huth
2021-06-04 15:51 ` [PATCH v16 12/99] qtest: Do not restrict bios-tables-test to Aarch64 hosts anymore Alex Bennée
2021-06-04 21:15   ` Richard Henderson
2021-06-07 13:48   ` Thomas Huth
2021-06-04 15:51 ` [PATCH v16 13/99] meson: add target_user_arch Alex Bennée
2021-06-04 18:01   ` Philippe Mathieu-Daudé
2021-06-04 15:51 ` [PATCH v16 14/99] accel: add cpu_reset Alex Bennée
2021-06-04 15:51   ` Alex Bennée
2021-06-04 21:23   ` Richard Henderson
2021-06-04 21:23     ` Richard Henderson
2021-06-04 15:51 ` [PATCH v16 15/99] target/arm: move translate modules to tcg/ Alex Bennée
2021-06-04 15:51 ` [PATCH v16 16/99] target/arm: move helpers " Alex Bennée
2021-06-04 15:51 ` [PATCH v16 17/99] arm: tcg: only build under CONFIG_TCG Alex Bennée
2021-06-04 15:51 ` [PATCH v16 18/99] target/arm: tcg: add sysemu and user subdirs Alex Bennée
2021-06-04 15:51 ` [PATCH v16 19/99] target/arm: tcg: split mte_helper user-only and sysemu code Alex Bennée
2021-06-04 15:51 ` [PATCH v16 20/99] target/arm: tcg: move sysemu-only parts of debug_helper Alex Bennée
2021-06-04 15:51 ` [PATCH v16 21/99] target/arm: tcg: split tlb_helper user-only and sysemu-only parts Alex Bennée
2021-06-04 15:51 ` [PATCH v16 22/99] target/arm: tcg: split m_helper " Alex Bennée
2021-06-04 15:51 ` [PATCH v16 23/99] target/arm: only build psci for TCG Alex Bennée
2021-06-04 15:51 ` [PATCH v16 24/99] target/arm: split off cpu-sysemu.c Alex Bennée
2021-06-04 15:51 ` [PATCH v16 25/99] target/arm: tcg: fix comment style before move to cpu-mmu Alex Bennée
2021-06-04 15:51 ` [PATCH v16 26/99] target/arm: move physical address translation " Alex Bennée
2021-06-04 15:52 ` [PATCH v16 27/99] target/arm: fix style in preparation of new cpregs module Alex Bennée
2021-06-04 15:52 ` [PATCH v16 28/99] target/arm: split cpregs from tcg/helper.c Alex Bennée
2021-06-04 15:52 ` [PATCH v16 29/99] target/arm: move cpu definitions to common cpu module Alex Bennée
2021-06-04 15:52 ` [PATCH v16 30/99] target/arm: only perform TCG cpu and machine inits if TCG enabled Alex Bennée
2021-06-04 15:52   ` Alex Bennée
2021-06-04 15:52 ` [PATCH v16 31/99] target/arm: tcg: add stubs for some helpers for non-tcg builds Alex Bennée
2021-06-04 15:52 ` [PATCH v16 32/99] target/arm: move cpsr_read, cpsr_write to cpu_common Alex Bennée
2021-06-04 15:52 ` [PATCH v16 33/99] target/arm: add temporary stub for arm_rebuild_hflags Alex Bennée
2021-06-04 15:52 ` [PATCH v16 34/99] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu Alex Bennée
2021-06-04 15:52 ` [PATCH v16 35/99] target/arm: split vfp state setting from tcg helpers Alex Bennée
2021-06-04 15:52 ` [PATCH v16 36/99] target/arm: move arm_mmu_idx* to cpu-mmu Alex Bennée
2021-06-04 15:52 ` [PATCH v16 37/99] target/arm: move sve_zcr_len_for_el to common_cpu Alex Bennée
2021-06-04 22:22   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 38/99] target/arm: move arm_sctlr away from tcg helpers Alex Bennée
2021-06-04 22:27   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 39/99] target/arm: move arm_cpu_list to common_cpu Alex Bennée
2021-06-04 15:52 ` Alex Bennée [this message]
2021-06-04 15:52 ` [PATCH v16 41/99] target/arm: new cpu32 ARM 32 bit CPU Class Alex Bennée
2021-06-04 22:53   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 42/99] target/arm: split 32bit and 64bit arm dump state Alex Bennée
2021-06-04 22:59   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 43/99] target/arm: move a15 cpu model away from the TCG-only models Alex Bennée
2021-06-05  0:27   ` Richard Henderson
2021-06-17 18:01     ` Alex Bennée
2021-06-17 20:35       ` Claudio Fontana
2021-06-04 15:52 ` [PATCH v16 44/99] target/arm: fixup sve_exception_el code style before move Alex Bennée
2021-06-04 15:52 ` [PATCH v16 45/99] target/arm: move sve_exception_el out of TCG helpers Alex Bennée
2021-06-04 15:52 ` [PATCH v16 46/99] target/arm: fix comments style of fp_exception_el before moving it Alex Bennée
2021-06-05  0:32   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 47/99] target/arm: move fp_exception_el out of TCG helpers Alex Bennée
2021-06-05  0:35   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 48/99] target/arm: remove now useless ifndef from fp_exception_el Alex Bennée
2021-06-05  0:35   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 49/99] target/arm: make further preparation for the exception code to move Alex Bennée
2021-06-05  1:34   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 50/99] target/arm: fix style of arm_cpu_do_interrupt functions before move Alex Bennée
2021-06-04 15:52 ` [PATCH v16 51/99] target/arm: move exception code out of tcg/helper.c Alex Bennée
2021-06-05  2:19   ` Richard Henderson
2021-06-05  5:56   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 52/99] target/arm: rename handle_semihosting to tcg_handle_semihosting Alex Bennée
2021-06-05  2:22   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 53/99] target/arm: replace CONFIG_TCG with tcg_enabled Alex Bennée
2021-06-05  2:24   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 54/99] target/arm: move TCGCPUOps to tcg/tcg-cpu.c Alex Bennée
2021-06-05  3:39   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 55/99] target/arm: move cpu_tcg to tcg/tcg-cpu-models.c Alex Bennée
2021-06-04 15:52 ` [PATCH v16 56/99] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Alex Bennée
2021-06-04 15:52 ` [PATCH v16 57/99] target/arm: remove kvm include file for PSCI and arm-powerctl Alex Bennée
2021-06-04 15:52 ` [PATCH v16 58/99] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Alex Bennée
2021-06-04 15:52 ` [PATCH v16 59/99] MAINTAINERS: update arm kvm maintained files to all in target/arm/kvm/ Alex Bennée
2021-06-05  3:52   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 60/99] target/arm: cleanup cpu includes Alex Bennée
2021-06-04 15:52 ` [PATCH v16 61/99] target/arm: remove broad "else" statements when checking accels Alex Bennée
2021-06-05 16:13   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 62/99] target/arm: remove kvm-stub.c Alex Bennée
2021-06-04 15:52 ` [PATCH v16 63/99] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Alex Bennée
2021-06-05 16:24   ` Richard Henderson
2021-06-18 15:25     ` Alex Bennée
2021-06-04 15:52 ` [PATCH v16 64/99] tests: do not run test-hmp on all machines for ARM KVM-only Alex Bennée
2021-06-05 16:28   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 65/99] tests: device-introspect-test: cope with ARM TCG-only devices Alex Bennée
2021-06-05 16:31   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 66/99] tests: do not run qom-test on all machines for ARM KVM-only Alex Bennée
2021-06-05 16:32   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 67/99] target/arm: create kvm cpu accel class Alex Bennée
2021-06-04 15:52 ` [PATCH v16 68/99] target/arm: move kvm post init initialization to kvm cpu accel Alex Bennée
2021-06-04 15:52 ` [PATCH v16 69/99] target/arm: add tcg cpu accel class Alex Bennée
2021-06-05 16:54   ` Richard Henderson
2021-06-24 10:52     ` Alex Bennée
2021-06-04 15:52 ` [PATCH v16 70/99] target/arm: move TCG gt timer creation code in tcg/ Alex Bennée
2021-06-04 15:52 ` [PATCH v16 71/99] target/arm: cpu-sve: new module Alex Bennée
2021-06-05 18:13   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 72/99] target/arm: cpu-sve: rename functions according to module prefix Alex Bennée
2021-06-05 18:39   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 73/99] target/arm: cpu-sve: split TCG and KVM functionality Alex Bennée
2021-06-05 19:31   ` Richard Henderson
2021-06-05 19:52   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 74/99] target/arm: cpu-sve: make cpu_sve_finalize_features return bool Alex Bennée
2021-06-05 18:57   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 75/99] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Alex Bennée
2021-06-05 20:00   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 76/99] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64 Alex Bennée
2021-06-05 20:06   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 77/99] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Alex Bennée
2021-06-05 20:30   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 78/99] target/arm: cpu-exceptions, cpu-exceptions-aa64: new modules Alex Bennée
2021-06-05 20:50   ` Richard Henderson
2021-06-10  8:45     ` Claudio Fontana
2021-06-10  9:01       ` Peter Maydell
2021-06-10  9:24         ` Claudio Fontana
2021-06-05 20:57   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 79/99] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Alex Bennée
2021-06-05 20:59   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 80/99] target/arm: tcg-sve: import narrow_vq and change_el functions Alex Bennée
2021-06-05 21:10   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 81/99] target/arm: tcg-sve: rename the " Alex Bennée
2021-06-04 15:52 ` [PATCH v16 82/99] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve Alex Bennée
2021-06-05 21:37   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 83/99] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el Alex Bennée
2021-06-04 15:52 ` [PATCH v16 84/99] target/arm: cpu-common: wrap a64-only check with is_a64 Alex Bennée
2021-06-05 21:55   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 85/99] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Alex Bennée
2021-06-05 22:06   ` Richard Henderson
2021-06-04 15:52 ` [PATCH v16 86/99] target/arm: cpu-pauth: change arm_cpu_pauth_finalize name and sig Alex Bennée
2021-06-05 22:09   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 87/99] target/arm: move arm_cpu_finalize_features into cpu64 Alex Bennée
2021-06-05 22:14   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 88/99] target/arm: cpu64: rename arm_cpu_finalize_features Alex Bennée
2021-06-05 22:14   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 89/99] target/arm: cpu64: some final cleanup on aarch64_cpu_finalize_features Alex Bennée
2021-06-05 22:20   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 90/99] XXX target/arm: experiment refactoring cpu "max" Alex Bennée
2021-06-04 15:53 ` [PATCH v16 91/99] target/arm: tcg: remove superfluous CONFIG_TCG check Alex Bennée
2021-06-04 15:53 ` [PATCH v16 92/99] target/arm: remove v7m stub function for !CONFIG_TCG Alex Bennée
2021-06-05 22:26   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 93/99] meson: Introduce target-specific Kconfig Alex Bennée
2021-06-05 22:33   ` Richard Henderson
2021-06-18 16:31     ` Alex Bennée
2021-06-04 15:53 ` [PATCH v16 94/99] target/arm: move CONFIG_V7M out of default-devices Alex Bennée
2021-06-05 22:41   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 95/99] hw/arm: add dependency on OR_IRQ for XLNX_VERSAL Alex Bennée
2021-06-05 22:43   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 96/99] tests/qtest: split the cdrom-test into arm/aarch64 Alex Bennée
2021-06-05 22:47   ` Richard Henderson
2021-06-08 14:27     ` Alex Bennée
2021-06-08 14:42       ` Thomas Huth
2021-06-08 14:57       ` Richard Henderson
2021-06-08 15:01       ` Thomas Huth
2021-06-08 15:35         ` Alex Bennée
2021-06-08 17:23           ` Thomas Huth
2021-06-08 15:36         ` John Snow
2021-06-08 13:42   ` John Snow
2021-06-08 14:36     ` Thomas Huth
2021-06-08 14:41       ` Alex Bennée
2021-06-08 14:45         ` Thomas Huth
2021-06-04 15:53 ` [PATCH v16 97/99] tests/qtest: make xlnx-can-test conditional on being configured Alex Bennée
2021-06-05 22:48   ` Richard Henderson
2021-06-04 15:53 ` [PATCH v16 98/99] configure: allow the overriding of default-config in the build Alex Bennée
2021-06-05 23:01   ` Richard Henderson
2021-06-08 13:03   ` Philippe Mathieu-Daudé
2021-06-04 15:53 ` [PATCH v16 99/99] gitlab: defend the new stripped down arm64 configs Alex Bennée
2021-06-05 23:03   ` Richard Henderson
2021-06-08  8:44 ` [PATCH v16 00/99] arm tcg/kvm refactor and split with kvm only support Philippe Mathieu-Daudé
2021-06-08  8:50   ` Philippe Mathieu-Daudé
2021-09-20 16:24 ` Liang Yan
2021-09-20 16:27   ` Alex Bennée

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