[Intel-gfx] [CI 0/4] Pipe DMC Support

[Intel-gfx] [CI 0/4] Pipe DMC Support

[Anusha Srivatsa]

With all DMC cleanup patches merged, sending the
rebased version of actual Pipe DMC bits.

One change from previous verison is a fix of SKL
regression. Corner cases for stepping-substepping
combination was missing from fw_info_matches_stepping()
helper. Luckily SKL was the only platform in CI that came
under this category and DMC refused to load.

This fix is tested on SKL.

Anusha Srivatsa (4):
  drm/i915/dmc: Introduce DMC_FW_MAIN
  xdrm/i915/xelpd: Pipe A DMC plugging
  drm/i915/adl_p: Pipe B DMC Support
  drm/i915/adl_p: Load DMC

 .../drm/i915/display/intel_display_debugfs.c  |   6 +-
 .../drm/i915/display/intel_display_power.c    |   5 +-
 drivers/gpu/drm/i915/display/intel_dmc.c      | 170 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_dmc.h      |  23 ++-
 drivers/gpu/drm/i915/i915_reg.h               |   2 +-
 5 files changed, 127 insertions(+), 79 deletions(-)

-- 
2.25.0

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[Intel-gfx] [CI 1/4] drm/i915/dmc: Introduce DMC_FW_MAIN

[Anusha Srivatsa]

This is a prep patch for Pipe DMC plugging.

Add dmc_info struct in intel_dmc to have all common fields
shared between all DMC's in the package.
Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.

v2: Remove dmc_offset and start_mmioaddr from dmc_info struct (Jose)

Cc: Souza, Jose <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 44 +++++++++++-------------
 drivers/gpu/drm/i915/display/intel_dmc.h | 18 +++++++---
 2 files changed, 33 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 97308da28059..b78cb44731fe 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -239,7 +239,7 @@ struct stepping_info {
 
 bool intel_dmc_has_payload(struct drm_i915_private *i915)
 {
-	return i915->dmc.dmc_payload;
+	return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
 }
 
 static const struct stepping_info skl_stepping_info[] = {
@@ -316,7 +316,8 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
  */
 void intel_dmc_load_program(struct drm_i915_private *dev_priv)
 {
-	u32 *payload = dev_priv->dmc.dmc_payload;
+	struct intel_dmc *dmc = &dev_priv->dmc;
+	struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
 	u32 i, fw_size;
 
 	if (!HAS_DMC(dev_priv)) {
@@ -325,26 +326,26 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
 		return;
 	}
 
-	if (!intel_dmc_has_payload(dev_priv)) {
+	if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
 		drm_err(&dev_priv->drm,
 			"Tried to program CSR with empty payload\n");
 		return;
 	}
 
-	fw_size = dev_priv->dmc.dmc_fw_size;
+	fw_size = dmc_info->dmc_fw_size;
 	assert_rpm_wakelock_held(&dev_priv->runtime_pm);
 
 	preempt_disable();
 
 	for (i = 0; i < fw_size; i++)
 		intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
-				      payload[i]);
+				      dmc_info->payload[i]);
 
 	preempt_enable();
 
-	for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
-		intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
-			       dev_priv->dmc.mmiodata[i]);
+	for (i = 0; i < dmc_info->mmio_count; i++) {
+		intel_de_write(dev_priv, dmc_info->mmioaddr[i],
+			       dmc_info->mmiodata[i]);
 	}
 
 	dev_priv->dmc.dc_state = 0;
@@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 			       size_t rem_size)
 {
 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+	struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
 	unsigned int header_len_bytes, dmc_header_size, payload_size, i;
 	const u32 *mmioaddr, *mmiodata;
 	u32 mmio_count, mmio_count_max;
 	u8 *payload;
 
-	BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
-		     ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
+	BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
+		     ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
 
 	/*
 	 * Check if we can access common fields, we will checkc again below
@@ -463,16 +465,10 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 	}
 
 	for (i = 0; i < mmio_count; i++) {
-		if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
-		    mmioaddr[i] > DMC_MMIO_END_RANGE) {
-			drm_err(&i915->drm, "DMC firmware has wrong mmio address 0x%x\n",
-				mmioaddr[i]);
-			return 0;
-		}
-		dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
-		dmc->mmiodata[i] = mmiodata[i];
+		dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
+		dmc_info->mmiodata[i] = mmiodata[i];
 	}
-	dmc->mmio_count = mmio_count;
+	dmc_info->mmio_count = mmio_count;
 
 	rem_size -= header_len_bytes;
 
@@ -485,14 +481,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 		drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size);
 		return 0;
 	}
-	dmc->dmc_fw_size = dmc_header->fw_size;
+	dmc_info->dmc_fw_size = dmc_header->fw_size;
 
-	dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
-	if (!dmc->dmc_payload)
+	dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
+	if (!dmc_info->payload)
 		return 0;
 
 	payload = (u8 *)(dmc_header) + header_len_bytes;
-	memcpy(dmc->dmc_payload, payload, payload_size);
+	memcpy(dmc_info->payload, payload, payload_size);
 
 	return header_len_bytes + payload_size;
 
@@ -827,5 +823,5 @@ void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
 	intel_dmc_ucode_suspend(dev_priv);
 	drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
 
-	kfree(dev_priv->dmc.dmc_payload);
+	kfree(dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 4c22f567b61b..b872f3a4fd03 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -16,17 +16,25 @@ struct drm_i915_private;
 #define DMC_VERSION_MAJOR(version)	((version) >> 16)
 #define DMC_VERSION_MINOR(version)	((version) & 0xffff)
 
+enum {
+	DMC_FW_MAIN = 0,
+	DMC_FW_MAX
+};
+
 struct intel_dmc {
 	struct work_struct work;
 	const char *fw_path;
 	u32 required_version;
 	u32 max_fw_size; /* bytes */
-	u32 *dmc_payload;
-	u32 dmc_fw_size; /* dwords */
 	u32 version;
-	u32 mmio_count;
-	i915_reg_t mmioaddr[20];
-	u32 mmiodata[20];
+	struct dmc_fw_info {
+		u32 mmio_count;
+		i915_reg_t mmioaddr[20];
+		u32 mmiodata[20];
+		u32 dmc_fw_size; /*dwords */
+		u32 *payload;
+	} dmc_info[DMC_FW_MAX];
+
 	u32 dc_state;
 	u32 target_dc_state;
 	u32 allowed_dc_mask;
-- 
2.25.0

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[Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging

[Anusha Srivatsa]

This patch adds Pipe A plumbing to the already
existing parsing and loading functions which is
taken care of in the prep patches. Adding MAX_DMC_FW
to keep track for both Main and Pipe A DMC while loading
the respective blobs.

Also adding present field in dmc_info.
s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add
fw_info_matches_stepping() helper. CSR_PROGRAM() should now
take the starting address of the particular blob (Main or Pipe)
and not hardcode it.

v2: Add dmc_offset and start_mmioaddr fields for dmc_info struct.

v3: Add a missing corner cases of stepping-substepping combination in
fw_info_matches_stepping() helper.

Cc: Souza, Jose <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  |   4 +-
 .../drm/i915/display/intel_display_power.c    |   5 +-
 drivers/gpu/drm/i915/display/intel_dmc.c      | 130 +++++++++++-------
 drivers/gpu/drm/i915/display/intel_dmc.h      |   4 +
 drivers/gpu/drm/i915/i915_reg.h               |   2 +-
 5 files changed, 89 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 88bb05d5c483..2a1c39a0e56e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -544,6 +544,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 
 	seq_printf(m, "fw loaded: %s\n", yesno(intel_dmc_has_payload(dev_priv)));
 	seq_printf(m, "path: %s\n", dmc->fw_path);
+	seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >= 12));
+	seq_printf(m, "Pipe A fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
 
 	if (!intel_dmc_has_payload(dev_priv))
 		goto out;
@@ -582,7 +584,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 
 out:
 	seq_printf(m, "program base: 0x%08x\n",
-		   intel_de_read(dev_priv, DMC_PROGRAM(0)));
+		   intel_de_read(dev_priv, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
 	seq_printf(m, "ssp base: 0x%08x\n",
 		   intel_de_read(dev_priv, DMC_SSP_BASE));
 	seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3e1f6ec61514..b7d4993feca6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -961,8 +961,9 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
 {
 	drm_WARN_ONCE(&dev_priv->drm,
-		      !intel_de_read(dev_priv, DMC_PROGRAM(0)),
-		      "DMC program storage start is NULL\n");
+		      !intel_de_read(dev_priv,
+				     DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+				     "DMC program storage start is NULL\n");
 	drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
 		      "DMC SSP Base Not fine\n");
 	drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index b78cb44731fe..09f65ad71f7e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -317,8 +317,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 void intel_dmc_load_program(struct drm_i915_private *dev_priv)
 {
 	struct intel_dmc *dmc = &dev_priv->dmc;
-	struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
-	u32 i, fw_size;
+	u32 id, i;
 
 	if (!HAS_DMC(dev_priv)) {
 		drm_err(&dev_priv->drm,
@@ -332,20 +331,25 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
 		return;
 	}
 
-	fw_size = dmc_info->dmc_fw_size;
 	assert_rpm_wakelock_held(&dev_priv->runtime_pm);
 
 	preempt_disable();
 
-	for (i = 0; i < fw_size; i++)
-		intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
-				      dmc_info->payload[i]);
+	for (id = 0; id < DMC_FW_MAX; id++) {
+		for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) {
+			intel_uncore_write_fw(&dev_priv->uncore,
+					      DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i),
+					      dmc->dmc_info[id].payload[i]);
+		}
+	}
 
 	preempt_enable();
 
-	for (i = 0; i < dmc_info->mmio_count; i++) {
-		intel_de_write(dev_priv, dmc_info->mmioaddr[i],
-			       dmc_info->mmiodata[i]);
+	for (id = 0; id < DMC_FW_MAX; id++) {
+		for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) {
+			intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i],
+				       dmc->dmc_info[id].mmiodata[i]);
+		}
 	}
 
 	dev_priv->dmc.dc_state = 0;
@@ -353,59 +357,72 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
 	gen9_set_dc_state_debugmask(dev_priv);
 }
 
+static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
+				     const struct stepping_info *si)
+{
+	if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) ||
+	    (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) ||
+	    /*
+	     * If we don't find a more specific one from above two checks, we
+	     * then check for the generic one to be sure to work even with
+	     * "broken firmware"
+	     */
+	    (si->stepping == '*' && si->substepping == fw_info->substepping) ||
+	    (fw_info->stepping == '*' && fw_info->substepping == '*'))
+		return true;
+
+	return false;
+}
+
 /*
  * Search fw_info table for dmc_offset to find firmware binary: num_entries is
  * already sanitized.
  */
-static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
+static void dmc_set_fw_offset(struct intel_dmc *dmc,
+			      const struct intel_fw_info *fw_info,
 			      unsigned int num_entries,
 			      const struct stepping_info *si,
 			      u8 package_ver)
 {
-	u32 dmc_offset = DMC_DEFAULT_FW_OFFSET;
-	unsigned int i;
+	unsigned int i, id;
 
-	for (i = 0; i < num_entries; i++) {
-		if (package_ver > 1 && fw_info[i].dmc_id != 0)
-			continue;
+	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
 
-		if (fw_info[i].substepping == '*' &&
-		    si->stepping == fw_info[i].stepping) {
-			dmc_offset = fw_info[i].offset;
-			break;
+	for (i = 0; i < num_entries; i++) {
+		if (package_ver > 1) {
+			if (fw_info[i].dmc_id >= DMC_FW_MAX || fw_info[i].dmc_id < DMC_FW_MAIN) {
+				drm_notice(&i915->drm, "Invalid firmware id: %d\n", fw_info[i].dmc_id);
+				continue;
+			} else {
+				id = fw_info[i].dmc_id;
+			}
+		} else {
+			id = DMC_FW_MAIN;
 		}
 
-		if (si->stepping == fw_info[i].stepping &&
-		    si->substepping == fw_info[i].substepping) {
-			dmc_offset = fw_info[i].offset;
-			break;
-		}
+		/* More specific versions come first, so we don't even have to
+		 * check for the stepping since we already found a previous FW
+		 * for this id.
+		 */
+		if (dmc->dmc_info[id].present)
+			continue;
 
-		if (fw_info[i].stepping == '*' &&
-		    fw_info[i].substepping == '*') {
-			/*
-			 * In theory we should stop the search as generic
-			 * entries should always come after the more specific
-			 * ones, but let's continue to make sure to work even
-			 * with "broken" firmwares. If we don't find a more
-			 * specific one, then we use this entry
-			 */
-			dmc_offset = fw_info[i].offset;
+		if (fw_info_matches_stepping(&fw_info[i], si)) {
+			dmc->dmc_info[id].present = true;
+			dmc->dmc_info[id].dmc_offset = fw_info[i].offset;
 		}
 	}
-
-	return dmc_offset;
 }
 
 static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 			       const struct intel_dmc_header_base *dmc_header,
-			       size_t rem_size)
+			       size_t rem_size, u8 dmc_id)
 {
 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
-	struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
+	struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
 	unsigned int header_len_bytes, dmc_header_size, payload_size, i;
 	const u32 *mmioaddr, *mmiodata;
-	u32 mmio_count, mmio_count_max;
+	u32 mmio_count, mmio_count_max, start_mmioaddr;
 	u8 *payload;
 
 	BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
@@ -432,6 +449,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 		mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
 		/* header_len is in dwords */
 		header_len_bytes = dmc_header->header_len * 4;
+		start_mmioaddr = v3->start_mmioaddr;
 		dmc_header_size = sizeof(*v3);
 	} else if (dmc_header->header_ver == 1) {
 		const struct intel_dmc_header_v1 *v1 =
@@ -445,6 +463,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 		mmio_count = v1->mmio_count;
 		mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
 		header_len_bytes = dmc_header->header_len;
+		start_mmioaddr = 0x80000;
 		dmc_header_size = sizeof(*v1);
 	} else {
 		drm_err(&i915->drm, "Unknown DMC fw header version: %u\n",
@@ -469,6 +488,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 		dmc_info->mmiodata[i] = mmiodata[i];
 	}
 	dmc_info->mmio_count = mmio_count;
+	dmc_info->start_mmioaddr = start_mmioaddr;
 
 	rem_size -= header_len_bytes;
 
@@ -505,7 +525,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
 {
 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
 	u32 package_size = sizeof(struct intel_package_header);
-	u32 num_entries, max_entries, dmc_offset;
+	u32 num_entries, max_entries;
 	const struct intel_fw_info *fw_info;
 
 	if (rem_size < package_size)
@@ -541,16 +561,11 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
 
 	fw_info = (const struct intel_fw_info *)
 		((u8 *)package_header + sizeof(*package_header));
-	dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
-					package_header->header_ver);
-	if (dmc_offset == DMC_DEFAULT_FW_OFFSET) {
-		drm_err(&i915->drm, "DMC firmware not supported for %c stepping\n",
-			si->stepping);
-		return 0;
-	}
+	dmc_set_fw_offset(dmc, fw_info, num_entries, si,
+			  package_header->header_ver);
 
 	/* dmc_offset is in dwords */
-	return package_size + dmc_offset * 4;
+	return package_size;
 
 error_truncated:
 	drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
@@ -602,7 +617,8 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
 	struct intel_dmc *dmc = &dev_priv->dmc;
 	const struct stepping_info *si = intel_get_stepping_info(dev_priv);
 	u32 readcount = 0;
-	u32 r;
+	u32 r, offset;
+	int id;
 
 	if (!fw)
 		return;
@@ -623,9 +639,19 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
 
 	readcount += r;
 
-	/* Extract dmc_header information */
-	dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
-	parse_dmc_fw_header(dmc, dmc_header, fw->size - readcount);
+	for (id = 0; id < DMC_FW_MAX; id++) {
+		if (!dev_priv->dmc.dmc_info[id].present)
+			continue;
+
+		offset = readcount + dmc->dmc_info[id].dmc_offset * 4;
+		if (fw->size - offset < 0) {
+			drm_err(&dev_priv->drm, "Reading beyond the fw_size\n");
+			continue;
+		}
+
+		dmc_header = (struct intel_dmc_header_base *)&fw->data[offset];
+		parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, id);
+	}
 }
 
 static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index b872f3a4fd03..007a284b0ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -18,6 +18,7 @@ struct drm_i915_private;
 
 enum {
 	DMC_FW_MAIN = 0,
+	DMC_FW_PIPEA,
 	DMC_FW_MAX
 };
 
@@ -31,8 +32,11 @@ struct intel_dmc {
 		u32 mmio_count;
 		i915_reg_t mmioaddr[20];
 		u32 mmiodata[20];
+		u32 dmc_offset;
+		u32 start_mmioaddr;
 		u32 dmc_fw_size; /*dwords */
 		u32 *payload;
+		bool present;
 	} dmc_info[DMC_FW_MAX];
 
 	u32 dc_state;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24307c49085f..912b2d553bc4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7751,7 +7751,7 @@ enum {
 #define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED	(3 << 0) /* icl + */
 
 /* DMC */
-#define DMC_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
+#define DMC_PROGRAM(addr, i)	_MMIO((addr) + (i) * 4)
 #define DMC_SSP_BASE_ADDR_GEN9	0x00002FC0
 #define DMC_HTP_ADDR_SKL	0x00500034
 #define DMC_SSP_BASE		_MMIO(0x8F074)
-- 
2.25.0

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[Intel-gfx] [CI 3/4] drm/i915/adl_p: Pipe B DMC Support

[Anusha Srivatsa]

ADLP requires us to load both Pipe A and Pipe B.
Plug Pipe B loading support.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 ++
 drivers/gpu/drm/i915/display/intel_dmc.h             | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 2a1c39a0e56e..db38891a9ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -546,6 +546,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	seq_printf(m, "path: %s\n", dmc->fw_path);
 	seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >= 12));
 	seq_printf(m, "Pipe A fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
+	seq_printf(m, "Pipe B fw support: %s\n", yesno(IS_ALDERLAKE_P(dev_priv)));
+	seq_printf(m, "Pipe B fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEB].payload));
 
 	if (!intel_dmc_has_payload(dev_priv))
 		goto out;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 007a284b0ef0..c3c00ff03869 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -19,6 +19,7 @@ struct drm_i915_private;
 enum {
 	DMC_FW_MAIN = 0,
 	DMC_FW_PIPEA,
+	DMC_FW_PIPEB,
 	DMC_FW_MAX
 };
 
-- 
2.25.0

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[Intel-gfx] [CI 4/4] drm/i915/adl_p: Load DMC

[Anusha Srivatsa]

Load DMC v2.10 on ADLP. The release notes mention that
this version enables few power savings features.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 09f65ad71f7e..52cedd5ea48e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -45,6 +45,10 @@
 
 #define GEN12_DMC_MAX_FW_SIZE		ICL_DMC_MAX_FW_SIZE
 
+#define ADLP_DMC_PATH			"i915/adlp_dmc_ver2_10.bin"
+#define ADLP_DMC_VERSION_REQUIRED	DMC_VERSION(2, 10)
+MODULE_FIRMWARE(ADLP_DMC_PATH);
+
 #define ADLS_DMC_PATH			DMC_PATH(adls, 2, 01)
 #define ADLS_DMC_VERSION_REQUIRED	DMC_VERSION(2, 1)
 MODULE_FIRMWARE(ADLS_DMC_PATH);
@@ -727,7 +731,11 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
 	 */
 	intel_dmc_runtime_pm_get(dev_priv);
 
-	if (IS_ALDERLAKE_S(dev_priv)) {
+	if (IS_ALDERLAKE_P(dev_priv)) {
+		dmc->fw_path = ADLP_DMC_PATH;
+		dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
+		dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+	} else if (IS_ALDERLAKE_S(dev_priv)) {
 		dmc->fw_path = ADLS_DMC_PATH;
 		dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
 		dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
-- 
2.25.0

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Pipe DMC Support (rev5)

[Patchwork]

== Series Details ==

Series: Pipe DMC Support (rev5)
URL   : https://patchwork.freedesktop.org/series/90445/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
fa1bf3879c91 drm/i915/dmc: Introduce DMC_FW_MAIN
2cdba84cf8be drm/i915/xelpd: Pipe A DMC plugging
-:45: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#45: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:587:
+		   intel_de_read(dev_priv, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));

-:60: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#60: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:965:
+				     DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),

-:160: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#160: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:394:
+				drm_notice(&i915->drm, "Invalid firmware id: %d\n", fw_info[i].dmc_id);

total: 0 errors, 3 warnings, 0 checks, 275 lines checked
e5635428cc51 drm/i915/adl_p: Pipe B DMC Support
7c1b64175b3c drm/i915/adl_p: Load DMC


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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Pipe DMC Support (rev5)

[Patchwork]

== Series Details ==

Series: Pipe DMC Support (rev5)
URL   : https://patchwork.freedesktop.org/series/90445/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1893:21:    expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1893:21:    got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1893:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1207:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


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[Intel-gfx] ✓ Fi.CI.BAT: success for Pipe DMC Support (rev5)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 7199 bytes --]

== Series Details ==

Series: Pipe DMC Support (rev5)
URL   : https://patchwork.freedesktop.org/series/90445/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10171 -> Patchwork_20286
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/index.html

Known issues
------------

  Here are the changes found in Patchwork_20286 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_gttfill@basic:
    - fi-bsw-n3050:       NOTRUN -> [SKIP][1] ([fdo#109271])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-bsw-n3050/igt@gem_exec_gttfill@basic.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-bsw-n3050:       NOTRUN -> [INCOMPLETE][2] ([i915#3159])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-bsw-n3050/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_huc_copy@huc-copy:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-bxt-dsi/igt@gem_huc_copy@huc-copy.html

  * igt@i915_selftest@live@execlists:
    - fi-bxt-dsi:         NOTRUN -> [DMESG-FAIL][4] ([i915#3462])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-bxt-dsi/igt@i915_selftest@live@execlists.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-bxt-dsi/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][6] ([fdo#109271]) +10 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-bxt-dsi/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-bxt-dsi:         NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#533])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-bxt-dsi/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  
#### Possible fixes ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          [DMESG-WARN][8] ([i915#2868]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Warnings ####

  * igt@i915_selftest@live@execlists:
    - fi-cml-s:           [DMESG-FAIL][10] ([i915#3462]) -> [INCOMPLETE][11] ([i915#3462])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/fi-cml-s/igt@i915_selftest@live@execlists.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-cml-s/igt@i915_selftest@live@execlists.html

  * igt@runner@aborted:
    - fi-kbl-x1275:       [FAIL][12] ([i915#1436] / [i915#3363]) -> [FAIL][13] ([i915#1436] / [i915#2426] / [i915#3363])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/fi-kbl-x1275/igt@runner@aborted.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-kbl-x1275/igt@runner@aborted.html
    - fi-glk-dsi:         [FAIL][14] ([i915#2426] / [i915#3363] / [k.org#202321]) -> [FAIL][15] ([i915#3363] / [k.org#202321])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/fi-glk-dsi/igt@runner@aborted.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-glk-dsi/igt@runner@aborted.html
    - fi-kbl-r:           [FAIL][16] ([i915#1436] / [i915#3363]) -> [FAIL][17] ([i915#1436] / [i915#2426] / [i915#3363])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/fi-kbl-r/igt@runner@aborted.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-kbl-r/igt@runner@aborted.html
    - fi-kbl-7500u:       [FAIL][18] ([i915#1436] / [i915#3363]) -> [FAIL][19] ([i915#1436] / [i915#2426] / [i915#3363])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/fi-kbl-7500u/igt@runner@aborted.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-kbl-7500u/igt@runner@aborted.html
    - fi-cml-u2:          [FAIL][20] ([i915#3363] / [i915#3462]) -> [FAIL][21] ([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/fi-cml-u2/igt@runner@aborted.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-cml-u2/igt@runner@aborted.html
    - fi-bxt-dsi:         [FAIL][22] ([i915#2426] / [i915#3363]) -> [FAIL][23] ([i915#3363])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/fi-bxt-dsi/igt@runner@aborted.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-bxt-dsi/igt@runner@aborted.html
    - fi-cml-s:           [FAIL][24] ([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462]) -> [FAIL][25] ([i915#3363] / [i915#3462])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/fi-cml-s/igt@runner@aborted.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-cml-s/igt@runner@aborted.html
    - fi-cfl-guc:         [FAIL][26] ([i915#2426] / [i915#3363]) -> [FAIL][27] ([i915#3363])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/fi-cfl-guc/igt@runner@aborted.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/fi-cfl-guc/igt@runner@aborted.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868
  [i915#3159]: https://gitlab.freedesktop.org/drm/intel/issues/3159
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (43 -> 40)
------------------------------

  Additional (1): fi-bsw-n3050 
  Missing    (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u 


Build changes
-------------

  * Linux: CI_DRM_10171 -> Patchwork_20286

  CI-20190529: 20190529
  CI_DRM_10171: d297e8e1d96bf631f5d61085954244591896b447 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6098: 1fbc1e7d602f96a7f4e2b95057eef994656b8e74 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_20286: 7c1b64175b3cedd6fe143a3341059fc26e9d1ece @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7c1b64175b3c drm/i915/adl_p: Load DMC
e5635428cc51 drm/i915/adl_p: Pipe B DMC Support
2cdba84cf8be drm/i915/xelpd: Pipe A DMC plugging
fa1bf3879c91 drm/i915/dmc: Introduce DMC_FW_MAIN

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for Pipe DMC Support (rev5)

[Patchwork]

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== Series Details ==

Series: Pipe DMC Support (rev5)
URL   : https://patchwork.freedesktop.org/series/90445/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10171_full -> Patchwork_20286_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_20286_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20286_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_20286_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_big_fb@linear-16bpp-rotate-180:
    - shard-iclb:         [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-iclb8/igt@kms_big_fb@linear-16bpp-rotate-180.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-iclb2/igt@kms_big_fb@linear-16bpp-rotate-180.html

  
Known issues
------------

  Here are the changes found in Patchwork_20286_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_create@create-massive:
    - shard-apl:          NOTRUN -> [DMESG-WARN][3] ([i915#3002])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl6/igt@gem_create@create-massive.html

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
    - shard-kbl:          [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +6 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@vcs0.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@vcs0.html

  * igt@gem_ctx_persistence@legacy-engines-persistence:
    - shard-snb:          NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-snb5/igt@gem_ctx_persistence@legacy-engines-persistence.html

  * igt@gem_ctx_persistence@many-contexts:
    - shard-tglb:         [PASS][7] -> [FAIL][8] ([i915#2410])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-tglb6/igt@gem_ctx_persistence@many-contexts.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-tglb7/igt@gem_ctx_persistence@many-contexts.html

  * igt@gem_ctx_ringsize@active@bcs0:
    - shard-skl:          [PASS][9] -> [INCOMPLETE][10] ([i915#3316])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-skl9/igt@gem_ctx_ringsize@active@bcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl5/igt@gem_ctx_ringsize@active@bcs0.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [PASS][11] -> [FAIL][12] ([i915#2846])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-glk3/igt@gem_exec_fair@basic-deadline.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-glk9/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-tglb:         [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-tglb7/igt@gem_exec_fair@basic-pace@rcs0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-tglb6/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][15] ([i915#2842])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_reloc@basic-wide-active@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][16] ([i915#2389])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-iclb4/igt@gem_exec_reloc@basic-wide-active@vcs1.html

  * igt@gem_huc_copy@huc-copy:
    - shard-kbl:          NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl3/igt@gem_huc_copy@huc-copy.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-apl:          NOTRUN -> [WARN][18] ([i915#2658])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl1/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-apl:          NOTRUN -> [FAIL][19] ([i915#3318])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl6/igt@gem_userptr_blits@vma-merge.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [PASS][20] -> [FAIL][21] ([i915#454])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-iclb6/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_selftest@live@execlists:
    - shard-kbl:          NOTRUN -> [INCOMPLETE][22] ([i915#2782] / [i915#3462] / [i915#794])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl3/igt@i915_selftest@live@execlists.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-0:
    - shard-skl:          [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-skl4/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl9/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html

  * igt@kms_ccs@pipe-c-missing-ccs-buffer:
    - shard-skl:          NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111304])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl9/igt@kms_ccs@pipe-c-missing-ccs-buffer.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][26] ([fdo#109271] / [fdo#111827]) +15 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl1/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-hpd-storm-disable:
    - shard-skl:          NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl9/igt@kms_chamelium@hdmi-hpd-storm-disable.html

  * igt@kms_chamelium@hdmi-hpd-with-enabled-mode:
    - shard-snb:          NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +7 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-snb5/igt@kms_chamelium@hdmi-hpd-with-enabled-mode.html

  * igt@kms_color_chamelium@pipe-c-ctm-max:
    - shard-kbl:          NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +9 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl1/igt@kms_color_chamelium@pipe-c-ctm-max.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-kbl:          NOTRUN -> [TIMEOUT][30] ([i915#1319])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl3/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          [PASS][31] -> [FAIL][32] ([i915#2346] / [i915#533])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled:
    - shard-snb:          NOTRUN -> [SKIP][33] ([fdo#109271]) +135 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-snb5/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html

  * igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][34] -> [FAIL][35] ([i915#2122])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@dpms-off-confusion-interruptible@a-edp1:
    - shard-skl:          NOTRUN -> [DMESG-WARN][36] ([i915#1982])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl9/igt@kms_flip@dpms-off-confusion-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1:
    - shard-apl:          [PASS][37] -> [FAIL][38] ([i915#79])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-apl:          [PASS][39] -> [DMESG-WARN][40] ([i915#180]) +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
    - shard-skl:          [PASS][41] -> [FAIL][42] ([i915#2122])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
    - shard-skl:          NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#2642])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
    - shard-kbl:          NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#2642])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
    - shard-kbl:          NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#2672])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
    - shard-skl:          NOTRUN -> [SKIP][46] ([fdo#109271]) +35 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-kbl:          NOTRUN -> [SKIP][47] ([fdo#109271]) +68 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][48] -> [FAIL][49] ([i915#1188])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-d:
    - shard-apl:          NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#533]) +2 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl2/igt@kms_pipe_crc_basic@read-crc-pipe-d.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
    - shard-kbl:          NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#533])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][52] ([i915#265])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
    - shard-kbl:          NOTRUN -> [FAIL][53] ([fdo#108145] / [i915#265])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - shard-apl:          NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-apl:          NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#2733])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-1:
    - shard-skl:          NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#658])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl9/igt@kms_psr2_sf@plane-move-sf-dmg-area-1.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3:
    - shard-kbl:          NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#658])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
    - shard-apl:          NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#658]) +4 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [PASS][59] -> [SKIP][60] ([fdo#109441])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_writeback@writeback-check-output:
    - shard-apl:          NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#2437]) +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl1/igt@kms_writeback@writeback-check-output.html

  * igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
    - shard-apl:          NOTRUN -> [SKIP][62] ([fdo#109271]) +165 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl3/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html

  * igt@sysfs_clients@fair-0:
    - shard-kbl:          NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#2994])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl3/igt@sysfs_clients@fair-0.html

  * igt@sysfs_clients@recycle-many:
    - shard-apl:          NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#2994]) +3 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl6/igt@sysfs_clients@recycle-many.html

  
#### Possible fixes ####

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          [FAIL][65] ([i915#2842]) -> [PASS][66] +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [FAIL][67] ([i915#2842]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-iclb:         [FAIL][69] ([i915#2842]) -> [PASS][70] +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-iclb6/igt@gem_exec_fair@basic-pace@vcs0.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          [FAIL][71] ([i915#2842]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-glk6/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_mmap_gtt@cpuset-big-copy:
    - shard-skl:          [FAIL][73] ([i915#307]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-skl10/igt@gem_mmap_gtt@cpuset-big-copy.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl5/igt@gem_mmap_gtt@cpuset-big-copy.html
    - shard-iclb:         [FAIL][75] ([i915#307]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-iclb4/igt@gem_mmap_gtt@cpuset-big-copy.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-kbl:          [DMESG-WARN][77] ([i915#180]) -> [PASS][78] +2 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl3/igt@gem_workarounds@suspend-resume-fd.html

  * igt@i915_pm_dc@dc5-dpms:
    - shard-skl:          [INCOMPLETE][79] ([i915#198]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-skl4/igt@i915_pm_dc@dc5-dpms.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl9/igt@i915_pm_dc@dc5-dpms.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x64-offscreen:
    - shard-skl:          [FAIL][81] ([i915#3444]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-skl8/igt@kms_cursor_crc@pipe-a-cursor-64x64-offscreen.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-64x64-offscreen.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][83] ([i915#79]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [SKIP][85] ([fdo#109441]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-iclb8/igt@kms_psr@psr2_sprite_blt.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html

  * igt@perf_pmu@rc6-suspend:
    - shard-apl:          [DMESG-WARN][87] ([i915#180]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-apl3/igt@perf_pmu@rc6-suspend.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl2/igt@perf_pmu@rc6-suspend.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][89] ([i915#1804] / [i915#2684]) -> [WARN][90] ([i915#2684]) +1 similar issue
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-iclb3/igt@i915_pm_rc6_residency@rc6-fence.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_selftest@live@execlists:
    - shard-tglb:         [INCOMPLETE][91] ([i915#3462]) -> [DMESG-FAIL][92] ([i915#3462])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-tglb1/igt@i915_selftest@live@execlists.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-tglb8/igt@i915_selftest@live@execlists.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][93], [FAIL][94], [FAIL][95], [FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602] / [i915#92]) -> ([FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602] / [i915#92])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-kbl3/igt@runner@aborted.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-kbl1/igt@runner@aborted.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-kbl1/igt@runner@aborted.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-kbl7/igt@runner@aborted.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-kbl4/igt@runner@aborted.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-kbl7/igt@runner@aborted.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-kbl4/igt@runner@aborted.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-kbl7/igt@runner@aborted.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl4/igt@runner@aborted.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl4/igt@runner@aborted.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl7/igt@runner@aborted.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl4/igt@runner@aborted.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl7/igt@runner@aborted.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl4/igt@runner@aborted.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl2/igt@runner@aborted.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl1/igt@runner@aborted.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl3/igt@runner@aborted.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl2/igt@runner@aborted.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-kbl1/igt@runner@aborted.html
    - shard-iclb:         ([FAIL][112], [FAIL][113], [FAIL][114]) ([i915#2426] / [i915#2782] / [i915#3002]) -> ([FAIL][115], [FAIL][116], [FAIL][117]) ([i915#2782] / [i915#3002])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-iclb7/igt@runner@aborted.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-iclb4/igt@runner@aborted.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-iclb7/igt@runner@aborted.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-iclb3/igt@runner@aborted.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-iclb5/igt@runner@aborted.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-iclb6/igt@runner@aborted.html
    - shard-apl:          ([FAIL][118], [FAIL][119], [FAIL][120]) ([i915#1610] / [i915#180] / [i915#2292] / [i915#3002] / [i915#3363]) -> ([FAIL][121], [FAIL][122]) ([i915#180] / [i915#3002] / [i915#3363])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-apl8/igt@runner@aborted.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-apl8/igt@runner@aborted.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-apl3/igt@runner@aborted.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl6/igt@runner@aborted.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-apl8/igt@runner@aborted.html
    - shard-tglb:         ([FAIL][123], [FAIL][124], [FAIL][125]) ([i915#1436] / [i915#2966] / [i915#3002]) -> ([FAIL][126], [FAIL][127], [FAIL][128]) ([i915#1436] / [i915#2426] / [i915#2966] / [i915#3002])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-tglb1/igt@runner@aborted.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-tglb7/igt@runner@aborted.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-tglb8/igt@runner@aborted.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-tglb2/igt@runner@aborted.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-tglb5/igt@runner@aborted.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-tglb8/igt@runner@aborted.html
    - shard-skl:          ([FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132]) ([i915#1436] / [i915#2426] / [i915#3002] / [i915#3363]) -> ([FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136]) ([i915#1436] / [i915#3002] / [i915#3363])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-skl2/igt@runner@aborted.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-skl1/igt@runner@aborted.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-skl2/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10171/shard-skl8/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl10/igt@runner@aborted.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl4/igt@runner@aborted.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl2/igt@runner@aborted.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/shard-skl3/igt@runner@aborted.html

  
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#111304]: https://bugs.freedesktop.org/show_bug.cgi?id=111304
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2292]: https://gitlab.freedesktop.org/drm/intel/issues/2292
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
  [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2642]: https://gitlab.freedesktop.org/drm/intel/issues/2642
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
  [i915#2733]: https://gitlab.freedesktop.org/drm/intel/issues/2733
  [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#307]: https://gitlab.freedesktop.org/drm/intel/issues/307
  [i915#3316]: https://gitlab.freedesktop.org/drm/intel/issues/3316
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3444]: https://gitlab.freedesktop.org/drm/intel/issues/3444
  [i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_10171 -> Patchwork_20286

  CI-20190529: 20190529
  CI_DRM_10171: d297e8e1d96bf631f5d61085954244591896b447 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6098: 1fbc1e7d602f96a7f4e2b95057eef994656b8e74 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_20286: 7c1b64175b3cedd6fe143a3341059fc26e9d1ece @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20286/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [CI 1/4] drm/i915/dmc: Introduce DMC_FW_MAIN

[Lucas De Marchi]

On Fri, Jun 04, 2021 at 12:01:25PM -0700, Anusha Srivatsa wrote:
>This is a prep patch for Pipe DMC plugging.
>
>Add dmc_info struct in intel_dmc to have all common fields
>shared between all DMC's in the package.
>Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
>
>v2: Remove dmc_offset and start_mmioaddr from dmc_info struct (Jose)
>
>Cc: Souza, Jose <jose.souza@intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_dmc.c | 44 +++++++++++-------------
> drivers/gpu/drm/i915/display/intel_dmc.h | 18 +++++++---
> 2 files changed, 33 insertions(+), 29 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index 97308da28059..b78cb44731fe 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -239,7 +239,7 @@ struct stepping_info {
>
> bool intel_dmc_has_payload(struct drm_i915_private *i915)
> {
>-	return i915->dmc.dmc_payload;
>+	return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
> }
>
> static const struct stepping_info skl_stepping_info[] = {
>@@ -316,7 +316,8 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
>  */
> void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> {
>-	u32 *payload = dev_priv->dmc.dmc_payload;
>+	struct intel_dmc *dmc = &dev_priv->dmc;
>+	struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
> 	u32 i, fw_size;
>
> 	if (!HAS_DMC(dev_priv)) {
>@@ -325,26 +326,26 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> 		return;
> 	}
>
>-	if (!intel_dmc_has_payload(dev_priv)) {
>+	if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
> 		drm_err(&dev_priv->drm,
> 			"Tried to program CSR with empty payload\n");
> 		return;
> 	}
>
>-	fw_size = dev_priv->dmc.dmc_fw_size;
>+	fw_size = dmc_info->dmc_fw_size;
> 	assert_rpm_wakelock_held(&dev_priv->runtime_pm);
>
> 	preempt_disable();
>
> 	for (i = 0; i < fw_size; i++)
> 		intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
>-				      payload[i]);
>+				      dmc_info->payload[i]);
>
> 	preempt_enable();
>
>-	for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
>-		intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
>-			       dev_priv->dmc.mmiodata[i]);
>+	for (i = 0; i < dmc_info->mmio_count; i++) {
>+		intel_de_write(dev_priv, dmc_info->mmioaddr[i],
>+			       dmc_info->mmiodata[i]);
> 	}
>
> 	dev_priv->dmc.dc_state = 0;
>@@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> 			       size_t rem_size)
> {
> 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
>+	struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
> 	unsigned int header_len_bytes, dmc_header_size, payload_size, i;
> 	const u32 *mmioaddr, *mmiodata;
> 	u32 mmio_count, mmio_count_max;
> 	u8 *payload;
>
>-	BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
>-		     ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
>+	BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
>+		     ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
>
> 	/*
> 	 * Check if we can access common fields, we will checkc again below
>@@ -463,16 +465,10 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> 	}
>
> 	for (i = 0; i < mmio_count; i++) {
>-		if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
>-		    mmioaddr[i] > DMC_MMIO_END_RANGE) {
>-			drm_err(&i915->drm, "DMC firmware has wrong mmio address 0x%x\n",
>-				mmioaddr[i]);
>-			return 0;
>-		}

this code here should not be dropped. Yes, after the last patch the
hardcoded value may not make sense, but patches should be split
appropriately.

with this change removed,


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

thanks
Lucas De Marchi


>-		dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
>-		dmc->mmiodata[i] = mmiodata[i];
>+		dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
>+		dmc_info->mmiodata[i] = mmiodata[i];
> 	}
>-	dmc->mmio_count = mmio_count;
>+	dmc_info->mmio_count = mmio_count;
>
> 	rem_size -= header_len_bytes;
>
>@@ -485,14 +481,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> 		drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size);
> 		return 0;
> 	}
>-	dmc->dmc_fw_size = dmc_header->fw_size;
>+	dmc_info->dmc_fw_size = dmc_header->fw_size;
>
>-	dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
>-	if (!dmc->dmc_payload)
>+	dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
>+	if (!dmc_info->payload)
> 		return 0;
>
> 	payload = (u8 *)(dmc_header) + header_len_bytes;
>-	memcpy(dmc->dmc_payload, payload, payload_size);
>+	memcpy(dmc_info->payload, payload, payload_size);
>
> 	return header_len_bytes + payload_size;
>
>@@ -827,5 +823,5 @@ void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
> 	intel_dmc_ucode_suspend(dev_priv);
> 	drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
>
>-	kfree(dev_priv->dmc.dmc_payload);
>+	kfree(dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload);
> }
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
>index 4c22f567b61b..b872f3a4fd03 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.h
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
>@@ -16,17 +16,25 @@ struct drm_i915_private;
> #define DMC_VERSION_MAJOR(version)	((version) >> 16)
> #define DMC_VERSION_MINOR(version)	((version) & 0xffff)
>
>+enum {
>+	DMC_FW_MAIN = 0,
>+	DMC_FW_MAX
>+};
>+
> struct intel_dmc {
> 	struct work_struct work;
> 	const char *fw_path;
> 	u32 required_version;
> 	u32 max_fw_size; /* bytes */
>-	u32 *dmc_payload;
>-	u32 dmc_fw_size; /* dwords */
> 	u32 version;
>-	u32 mmio_count;
>-	i915_reg_t mmioaddr[20];
>-	u32 mmiodata[20];
>+	struct dmc_fw_info {
>+		u32 mmio_count;
>+		i915_reg_t mmioaddr[20];
>+		u32 mmiodata[20];
>+		u32 dmc_fw_size; /*dwords */
>+		u32 *payload;
>+	} dmc_info[DMC_FW_MAX];
>+
> 	u32 dc_state;
> 	u32 target_dc_state;
> 	u32 allowed_dc_mask;
>-- 
>2.25.0
>
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Re: [Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging

[Lucas De Marchi]

On Fri, Jun 04, 2021 at 12:01:26PM -0700, Anusha Srivatsa wrote:
>This patch adds Pipe A plumbing to the already
>existing parsing and loading functions which is
>taken care of in the prep patches. Adding MAX_DMC_FW
>to keep track for both Main and Pipe A DMC while loading
>the respective blobs.
>
>Also adding present field in dmc_info.
>s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add
>fw_info_matches_stepping() helper. CSR_PROGRAM() should now
>take the starting address of the particular blob (Main or Pipe)
>and not hardcode it.
>
>v2: Add dmc_offset and start_mmioaddr fields for dmc_info struct.
>
>v3: Add a missing corner cases of stepping-substepping combination in
>fw_info_matches_stepping() helper.
>
>Cc: Souza, Jose <jose.souza@intel.com>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> .../drm/i915/display/intel_display_debugfs.c  |   4 +-
> .../drm/i915/display/intel_display_power.c    |   5 +-
> drivers/gpu/drm/i915/display/intel_dmc.c      | 130 +++++++++++-------
> drivers/gpu/drm/i915/display/intel_dmc.h      |   4 +
> drivers/gpu/drm/i915/i915_reg.h               |   2 +-
> 5 files changed, 89 insertions(+), 56 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>index 88bb05d5c483..2a1c39a0e56e 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>@@ -544,6 +544,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>
> 	seq_printf(m, "fw loaded: %s\n", yesno(intel_dmc_has_payload(dev_priv)));
> 	seq_printf(m, "path: %s\n", dmc->fw_path);
>+	seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >= 12));
>+	seq_printf(m, "Pipe A fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
>
> 	if (!intel_dmc_has_payload(dev_priv))
> 		goto out;
>@@ -582,7 +584,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>
> out:
> 	seq_printf(m, "program base: 0x%08x\n",
>-		   intel_de_read(dev_priv, DMC_PROGRAM(0)));
>+		   intel_de_read(dev_priv, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> 	seq_printf(m, "ssp base: 0x%08x\n",
> 		   intel_de_read(dev_priv, DMC_SSP_BASE));
> 	seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>index 3e1f6ec61514..b7d4993feca6 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>@@ -961,8 +961,9 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
> static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
> {
> 	drm_WARN_ONCE(&dev_priv->drm,
>-		      !intel_de_read(dev_priv, DMC_PROGRAM(0)),
>-		      "DMC program storage start is NULL\n");
>+		      !intel_de_read(dev_priv,
>+				     DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
>+				     "DMC program storage start is NULL\n");
> 	drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
> 		      "DMC SSP Base Not fine\n");
> 	drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index b78cb44731fe..09f65ad71f7e 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -317,8 +317,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
> void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> {
> 	struct intel_dmc *dmc = &dev_priv->dmc;
>-	struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
>-	u32 i, fw_size;
>+	u32 id, i;
>
> 	if (!HAS_DMC(dev_priv)) {
> 		drm_err(&dev_priv->drm,
>@@ -332,20 +331,25 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> 		return;
> 	}
>
>-	fw_size = dmc_info->dmc_fw_size;
> 	assert_rpm_wakelock_held(&dev_priv->runtime_pm);
>
> 	preempt_disable();
>
>-	for (i = 0; i < fw_size; i++)
>-		intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
>-				      dmc_info->payload[i]);
>+	for (id = 0; id < DMC_FW_MAX; id++) {
>+		for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) {
>+			intel_uncore_write_fw(&dev_priv->uncore,
>+					      DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i),
>+					      dmc->dmc_info[id].payload[i]);
>+		}
>+	}
>
> 	preempt_enable();
>
>-	for (i = 0; i < dmc_info->mmio_count; i++) {
>-		intel_de_write(dev_priv, dmc_info->mmioaddr[i],
>-			       dmc_info->mmiodata[i]);
>+	for (id = 0; id < DMC_FW_MAX; id++) {
>+		for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) {
>+			intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i],
>+				       dmc->dmc_info[id].mmiodata[i]);
>+		}
> 	}
>
> 	dev_priv->dmc.dc_state = 0;
>@@ -353,59 +357,72 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> 	gen9_set_dc_state_debugmask(dev_priv);
> }
>
>+static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
>+				     const struct stepping_info *si)
>+{
>+	if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) ||
>+	    (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) ||
>+	    /*
>+	     * If we don't find a more specific one from above two checks, we
>+	     * then check for the generic one to be sure to work even with
>+	     * "broken firmware"
>+	     */
>+	    (si->stepping == '*' && si->substepping == fw_info->substepping) ||
>+	    (fw_info->stepping == '*' && fw_info->substepping == '*'))
>+		return true;
>+
>+	return false;
>+}
>+
> /*
>  * Search fw_info table for dmc_offset to find firmware binary: num_entries is
>  * already sanitized.
>  */
>-static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
>+static void dmc_set_fw_offset(struct intel_dmc *dmc,
>+			      const struct intel_fw_info *fw_info,
> 			      unsigned int num_entries,
> 			      const struct stepping_info *si,
> 			      u8 package_ver)
> {
>-	u32 dmc_offset = DMC_DEFAULT_FW_OFFSET;
>-	unsigned int i;
>+	unsigned int i, id;
>
>-	for (i = 0; i < num_entries; i++) {
>-		if (package_ver > 1 && fw_info[i].dmc_id != 0)
>-			continue;
>+	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
>
>-		if (fw_info[i].substepping == '*' &&
>-		    si->stepping == fw_info[i].stepping) {
>-			dmc_offset = fw_info[i].offset;
>-			break;
>+	for (i = 0; i < num_entries; i++) {
>+		if (package_ver > 1) {
>+			if (fw_info[i].dmc_id >= DMC_FW_MAX || fw_info[i].dmc_id < DMC_FW_MAIN) {

checking fw_info[i].dmc_id < DMC_FW_MAIN doesn't make sense as dmc_id is
unsigned and DMC_FW_MAIN is 0.

>+				drm_notice(&i915->drm, "Invalid firmware id: %d\n", fw_info[i].dmc_id);
>+				continue;
>+			} else {
>+				id = fw_info[i].dmc_id;
>+			}
>+		} else {
>+			id = DMC_FW_MAIN;

this would reduce the indentation a bit and make it more readable IMO


	for (i = 0; i < num_entries; i++) {
		id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;

		if (id >= DMC_FW_MAX) {
			drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", id);
			continue;
		}

		...

Thinking about the upgradability of the firmware, as can be seen above
I'd downgrade the message to drm_dbg(). We are doing the check even
before checking fw_info_matches_stepping() anyway.


> 		}
>
>-		if (si->stepping == fw_info[i].stepping &&
>-		    si->substepping == fw_info[i].substepping) {
>-			dmc_offset = fw_info[i].offset;
>-			break;
>-		}
>+		/* More specific versions come first, so we don't even have to
>+		 * check for the stepping since we already found a previous FW
>+		 * for this id.
>+		 */
>+		if (dmc->dmc_info[id].present)
>+			continue;
>
>-		if (fw_info[i].stepping == '*' &&
>-		    fw_info[i].substepping == '*') {
>-			/*
>-			 * In theory we should stop the search as generic
>-			 * entries should always come after the more specific
>-			 * ones, but let's continue to make sure to work even
>-			 * with "broken" firmwares. If we don't find a more
>-			 * specific one, then we use this entry
>-			 */
>-			dmc_offset = fw_info[i].offset;
>+		if (fw_info_matches_stepping(&fw_info[i], si)) {
>+			dmc->dmc_info[id].present = true;
>+			dmc->dmc_info[id].dmc_offset = fw_info[i].offset;
> 		}
> 	}
>-
>-	return dmc_offset;
> }
>
> static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> 			       const struct intel_dmc_header_base *dmc_header,
>-			       size_t rem_size)
>+			       size_t rem_size, u8 dmc_id)
> {
> 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
>-	struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
>+	struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
> 	unsigned int header_len_bytes, dmc_header_size, payload_size, i;
> 	const u32 *mmioaddr, *mmiodata;
>-	u32 mmio_count, mmio_count_max;
>+	u32 mmio_count, mmio_count_max, start_mmioaddr;
> 	u8 *payload;
>
> 	BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
>@@ -432,6 +449,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> 		mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
> 		/* header_len is in dwords */
> 		header_len_bytes = dmc_header->header_len * 4;
>+		start_mmioaddr = v3->start_mmioaddr;
> 		dmc_header_size = sizeof(*v3);
> 	} else if (dmc_header->header_ver == 1) {
> 		const struct intel_dmc_header_v1 *v1 =
>@@ -445,6 +463,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> 		mmio_count = v1->mmio_count;
> 		mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
> 		header_len_bytes = dmc_header->header_len;
>+		start_mmioaddr = 0x80000;

instead of the naked/magic number, maybe:

#define DMC_V1_MMIO_START_RANGE 0x80000 and use it.

> 		dmc_header_size = sizeof(*v1);
> 	} else {
> 		drm_err(&i915->drm, "Unknown DMC fw header version: %u\n",
>@@ -469,6 +488,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> 		dmc_info->mmiodata[i] = mmiodata[i];
> 	}
> 	dmc_info->mmio_count = mmio_count;
>+	dmc_info->start_mmioaddr = start_mmioaddr;

now that you are assigning the start_mmioaddr according to the package
version, instead of have removed the sanity check in patch 1, you could
use this field for the sanity check.


Lucas De Marchi

>
> 	rem_size -= header_len_bytes;
>
>@@ -505,7 +525,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
> {
> 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
> 	u32 package_size = sizeof(struct intel_package_header);
>-	u32 num_entries, max_entries, dmc_offset;
>+	u32 num_entries, max_entries;
> 	const struct intel_fw_info *fw_info;
>
> 	if (rem_size < package_size)
>@@ -541,16 +561,11 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
>
> 	fw_info = (const struct intel_fw_info *)
> 		((u8 *)package_header + sizeof(*package_header));
>-	dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
>-					package_header->header_ver);
>-	if (dmc_offset == DMC_DEFAULT_FW_OFFSET) {
>-		drm_err(&i915->drm, "DMC firmware not supported for %c stepping\n",
>-			si->stepping);
>-		return 0;
>-	}
>+	dmc_set_fw_offset(dmc, fw_info, num_entries, si,
>+			  package_header->header_ver);
>
> 	/* dmc_offset is in dwords */
>-	return package_size + dmc_offset * 4;
>+	return package_size;
>
> error_truncated:
> 	drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
>@@ -602,7 +617,8 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
> 	struct intel_dmc *dmc = &dev_priv->dmc;
> 	const struct stepping_info *si = intel_get_stepping_info(dev_priv);
> 	u32 readcount = 0;
>-	u32 r;
>+	u32 r, offset;
>+	int id;
>
> 	if (!fw)
> 		return;
>@@ -623,9 +639,19 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
>
> 	readcount += r;
>
>-	/* Extract dmc_header information */
>-	dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
>-	parse_dmc_fw_header(dmc, dmc_header, fw->size - readcount);
>+	for (id = 0; id < DMC_FW_MAX; id++) {
>+		if (!dev_priv->dmc.dmc_info[id].present)
>+			continue;
>+
>+		offset = readcount + dmc->dmc_info[id].dmc_offset * 4;
>+		if (fw->size - offset < 0) {
>+			drm_err(&dev_priv->drm, "Reading beyond the fw_size\n");
>+			continue;
>+		}
>+
>+		dmc_header = (struct intel_dmc_header_base *)&fw->data[offset];
>+		parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, id);
>+	}
> }
>
> static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv)
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
>index b872f3a4fd03..007a284b0ef0 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.h
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
>@@ -18,6 +18,7 @@ struct drm_i915_private;
>
> enum {
> 	DMC_FW_MAIN = 0,
>+	DMC_FW_PIPEA,
> 	DMC_FW_MAX
> };
>
>@@ -31,8 +32,11 @@ struct intel_dmc {
> 		u32 mmio_count;
> 		i915_reg_t mmioaddr[20];
> 		u32 mmiodata[20];
>+		u32 dmc_offset;
>+		u32 start_mmioaddr;
> 		u32 dmc_fw_size; /*dwords */
> 		u32 *payload;
>+		bool present;
> 	} dmc_info[DMC_FW_MAX];
>
> 	u32 dc_state;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 24307c49085f..912b2d553bc4 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7751,7 +7751,7 @@ enum {
> #define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED	(3 << 0) /* icl + */
>
> /* DMC */
>-#define DMC_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
>+#define DMC_PROGRAM(addr, i)	_MMIO((addr) + (i) * 4)
> #define DMC_SSP_BASE_ADDR_GEN9	0x00002FC0
> #define DMC_HTP_ADDR_SKL	0x00500034
> #define DMC_SSP_BASE		_MMIO(0x8F074)
>-- 
>2.25.0
>
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Re: [Intel-gfx] [CI 3/4] drm/i915/adl_p: Pipe B DMC Support

[Lucas De Marchi]

On Fri, Jun 04, 2021 at 12:01:27PM -0700, Anusha Srivatsa wrote:
>ADLP requires us to load both Pipe A and Pipe B.
>Plug Pipe B loading support.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 ++
> drivers/gpu/drm/i915/display/intel_dmc.h             | 1 +
> 2 files changed, 3 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>index 2a1c39a0e56e..db38891a9ef0 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>@@ -546,6 +546,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> 	seq_printf(m, "path: %s\n", dmc->fw_path);
> 	seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >= 12));
> 	seq_printf(m, "Pipe A fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
>+	seq_printf(m, "Pipe B fw support: %s\n", yesno(IS_ALDERLAKE_P(dev_priv)));

this is smelling lots of updates down the road :(. Anyway,


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

but this depends on the previous patch being changed.


Lucas De Marchi


>+	seq_printf(m, "Pipe B fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEB].payload));
>
> 	if (!intel_dmc_has_payload(dev_priv))
> 		goto out;
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
>index 007a284b0ef0..c3c00ff03869 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.h
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
>@@ -19,6 +19,7 @@ struct drm_i915_private;
> enum {
> 	DMC_FW_MAIN = 0,
> 	DMC_FW_PIPEA,
>+	DMC_FW_PIPEB,
> 	DMC_FW_MAX
> };
>
>-- 
>2.25.0
>
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Re: [Intel-gfx] [CI 4/4] drm/i915/adl_p: Load DMC

[Lucas De Marchi]

On Fri, Jun 04, 2021 at 12:01:28PM -0700, Anusha Srivatsa wrote:
>Load DMC v2.10 on ADLP. The release notes mention that
>this version enables few power savings features.
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Clint Taylor <clinton.a.taylor@intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_dmc.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index 09f65ad71f7e..52cedd5ea48e 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -45,6 +45,10 @@
>
> #define GEN12_DMC_MAX_FW_SIZE		ICL_DMC_MAX_FW_SIZE
>
>+#define ADLP_DMC_PATH			"i915/adlp_dmc_ver2_10.bin"

see below... should use DMC_PATH() helper

Lucas De Marchi

>+#define ADLP_DMC_VERSION_REQUIRED	DMC_VERSION(2, 10)
>+MODULE_FIRMWARE(ADLP_DMC_PATH);
>+
> #define ADLS_DMC_PATH			DMC_PATH(adls, 2, 01)
> #define ADLS_DMC_VERSION_REQUIRED	DMC_VERSION(2, 1)
> MODULE_FIRMWARE(ADLS_DMC_PATH);
>@@ -727,7 +731,11 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
> 	 */
> 	intel_dmc_runtime_pm_get(dev_priv);
>
>-	if (IS_ALDERLAKE_S(dev_priv)) {
>+	if (IS_ALDERLAKE_P(dev_priv)) {
>+		dmc->fw_path = ADLP_DMC_PATH;
>+		dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
>+		dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
>+	} else if (IS_ALDERLAKE_S(dev_priv)) {
> 		dmc->fw_path = ADLS_DMC_PATH;
> 		dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
> 		dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
>-- 
>2.25.0
>
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Re: [Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging

[Srivatsa, Anusha]

> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Wednesday, June 9, 2021 11:22 PM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging
> 
> On Fri, Jun 04, 2021 at 12:01:26PM -0700, Anusha Srivatsa wrote:
> >This patch adds Pipe A plumbing to the already existing parsing and
> >loading functions which is taken care of in the prep patches. Adding
> >MAX_DMC_FW to keep track for both Main and Pipe A DMC while loading
> the
> >respective blobs.
> >
> >Also adding present field in dmc_info.
> >s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add
> >fw_info_matches_stepping() helper. CSR_PROGRAM() should now take
> the
> >starting address of the particular blob (Main or Pipe) and not hardcode
> >it.
> >
> >v2: Add dmc_offset and start_mmioaddr fields for dmc_info struct.
> >
> >v3: Add a missing corner cases of stepping-substepping combination in
> >fw_info_matches_stepping() helper.
> >
> >Cc: Souza, Jose <jose.souza@intel.com>
> >Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> >Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >---
> > .../drm/i915/display/intel_display_debugfs.c  |   4 +-
> > .../drm/i915/display/intel_display_power.c    |   5 +-
> > drivers/gpu/drm/i915/display/intel_dmc.c      | 130 +++++++++++-------
> > drivers/gpu/drm/i915/display/intel_dmc.h      |   4 +
> > drivers/gpu/drm/i915/i915_reg.h               |   2 +-
> > 5 files changed, 89 insertions(+), 56 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >index 88bb05d5c483..2a1c39a0e56e 100644
> >--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> >@@ -544,6 +544,8 @@ static int i915_dmc_info(struct seq_file *m, void
> >*unused)
> >
> > 	seq_printf(m, "fw loaded: %s\n",
> yesno(intel_dmc_has_payload(dev_priv)));
> > 	seq_printf(m, "path: %s\n", dmc->fw_path);
> >+	seq_printf(m, "Pipe A fw support: %s\n",
> yesno(INTEL_GEN(dev_priv) >= 12));
> >+	seq_printf(m, "Pipe A fw loaded: %s\n",
> >+yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
> >
> > 	if (!intel_dmc_has_payload(dev_priv))
> > 		goto out;
> >@@ -582,7 +584,7 @@ static int i915_dmc_info(struct seq_file *m, void
> >*unused)
> >
> > out:
> > 	seq_printf(m, "program base: 0x%08x\n",
> >-		   intel_de_read(dev_priv, DMC_PROGRAM(0)));
> >+		   intel_de_read(dev_priv,
> >+DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> > 	seq_printf(m, "ssp base: 0x%08x\n",
> > 		   intel_de_read(dev_priv, DMC_SSP_BASE));
> > 	seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv,
> DMC_HTP_SKL));
> >diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> >b/drivers/gpu/drm/i915/display/intel_display_power.c
> >index 3e1f6ec61514..b7d4993feca6 100644
> >--- a/drivers/gpu/drm/i915/display/intel_display_power.c
> >+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> >@@ -961,8 +961,9 @@ static void bxt_disable_dc9(struct drm_i915_private
> >*dev_priv)  static void assert_dmc_loaded(struct drm_i915_private
> >*dev_priv)  {
> > 	drm_WARN_ONCE(&dev_priv->drm,
> >-		      !intel_de_read(dev_priv, DMC_PROGRAM(0)),
> >-		      "DMC program storage start is NULL\n");
> >+		      !intel_de_read(dev_priv,
> >+				     DMC_PROGRAM(dev_priv-
> >dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
> >+				     "DMC program storage start is NULL\n");
> > 	drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv,
> DMC_SSP_BASE),
> > 		      "DMC SSP Base Not fine\n");
> > 	drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv,
> DMC_HTP_SKL),
> >diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> >b/drivers/gpu/drm/i915/display/intel_dmc.c
> >index b78cb44731fe..09f65ad71f7e 100644
> >--- a/drivers/gpu/drm/i915/display/intel_dmc.c
> >+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> >@@ -317,8 +317,7 @@ static void gen9_set_dc_state_debugmask(struct
> >drm_i915_private *dev_priv)  void intel_dmc_load_program(struct
> >drm_i915_private *dev_priv)  {
> > 	struct intel_dmc *dmc = &dev_priv->dmc;
> >-	struct dmc_fw_info *dmc_info = &dmc-
> >dmc_info[DMC_FW_MAIN];
> >-	u32 i, fw_size;
> >+	u32 id, i;
> >
> > 	if (!HAS_DMC(dev_priv)) {
> > 		drm_err(&dev_priv->drm,
> >@@ -332,20 +331,25 @@ void intel_dmc_load_program(struct
> drm_i915_private *dev_priv)
> > 		return;
> > 	}
> >
> >-	fw_size = dmc_info->dmc_fw_size;
> > 	assert_rpm_wakelock_held(&dev_priv->runtime_pm);
> >
> > 	preempt_disable();
> >
> >-	for (i = 0; i < fw_size; i++)
> >-		intel_uncore_write_fw(&dev_priv->uncore,
> DMC_PROGRAM(i),
> >-				      dmc_info->payload[i]);
> >+	for (id = 0; id < DMC_FW_MAX; id++) {
> >+		for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) {
> >+			intel_uncore_write_fw(&dev_priv->uncore,
> >+					      DMC_PROGRAM(dmc-
> >dmc_info[id].start_mmioaddr, i),
> >+					      dmc->dmc_info[id].payload[i]);
> >+		}
> >+	}
> >
> > 	preempt_enable();
> >
> >-	for (i = 0; i < dmc_info->mmio_count; i++) {
> >-		intel_de_write(dev_priv, dmc_info->mmioaddr[i],
> >-			       dmc_info->mmiodata[i]);
> >+	for (id = 0; id < DMC_FW_MAX; id++) {
> >+		for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) {
> >+			intel_de_write(dev_priv, dmc-
> >dmc_info[id].mmioaddr[i],
> >+				       dmc->dmc_info[id].mmiodata[i]);
> >+		}
> > 	}
> >
> > 	dev_priv->dmc.dc_state = 0;
> >@@ -353,59 +357,72 @@ void intel_dmc_load_program(struct
> drm_i915_private *dev_priv)
> > 	gen9_set_dc_state_debugmask(dev_priv);
> > }
> >
> >+static bool fw_info_matches_stepping(const struct intel_fw_info
> *fw_info,
> >+				     const struct stepping_info *si) {
> >+	if ((fw_info->substepping == '*' && si->stepping == fw_info-
> >stepping) ||
> >+	    (si->stepping == fw_info->stepping && si->substepping ==
> fw_info->substepping) ||
> >+	    /*
> >+	     * If we don't find a more specific one from above two checks, we
> >+	     * then check for the generic one to be sure to work even with
> >+	     * "broken firmware"
> >+	     */
> >+	    (si->stepping == '*' && si->substepping == fw_info->substepping)
> ||
> >+	    (fw_info->stepping == '*' && fw_info->substepping == '*'))
> >+		return true;
> >+
> >+	return false;
> >+}
> >+
> > /*
> >  * Search fw_info table for dmc_offset to find firmware binary:
> >num_entries is
> >  * already sanitized.
> >  */
> >-static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
> >+static void dmc_set_fw_offset(struct intel_dmc *dmc,
> >+			      const struct intel_fw_info *fw_info,
> > 			      unsigned int num_entries,
> > 			      const struct stepping_info *si,
> > 			      u8 package_ver)
> > {
> >-	u32 dmc_offset = DMC_DEFAULT_FW_OFFSET;
> >-	unsigned int i;
> >+	unsigned int i, id;
> >
> >-	for (i = 0; i < num_entries; i++) {
> >-		if (package_ver > 1 && fw_info[i].dmc_id != 0)
> >-			continue;
> >+	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915),
> >+dmc);
> >
> >-		if (fw_info[i].substepping == '*' &&
> >-		    si->stepping == fw_info[i].stepping) {
> >-			dmc_offset = fw_info[i].offset;
> >-			break;
> >+	for (i = 0; i < num_entries; i++) {
> >+		if (package_ver > 1) {
> >+			if (fw_info[i].dmc_id >= DMC_FW_MAX ||
> fw_info[i].dmc_id <
> >+DMC_FW_MAIN) {
> 
> checking fw_info[i].dmc_id < DMC_FW_MAIN doesn't make sense as
> dmc_id is unsigned and DMC_FW_MAIN is 0.
> 
> >+				drm_notice(&i915->drm, "Invalid firmware id:
> %d\n", fw_info[i].dmc_id);
> >+				continue;
> >+			} else {
> >+				id = fw_info[i].dmc_id;
> >+			}
> >+		} else {
> >+			id = DMC_FW_MAIN;
> 
> this would reduce the indentation a bit and make it more readable IMO
> 
> 
> 	for (i = 0; i < num_entries; i++) {
> 		id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
> 
> 		if (id >= DMC_FW_MAX) {
> 			drm_dbg(&i915->drm, "Unsupported firmware id:
> %u\n", id);
> 			continue;
> 		}
> 
> 		...
> 
> Thinking about the upgradability of the firmware, as can be seen above I'd
> downgrade the message to drm_dbg(). We are doing the check even before
> checking fw_info_matches_stepping() anyway.
> 
> 
> > 		}
> >
> >-		if (si->stepping == fw_info[i].stepping &&
> >-		    si->substepping == fw_info[i].substepping) {
> >-			dmc_offset = fw_info[i].offset;
> >-			break;
> >-		}
> >+		/* More specific versions come first, so we don't even have
> to
> >+		 * check for the stepping since we already found a previous
> FW
> >+		 * for this id.
> >+		 */
> >+		if (dmc->dmc_info[id].present)
> >+			continue;
> >
> >-		if (fw_info[i].stepping == '*' &&
> >-		    fw_info[i].substepping == '*') {
> >-			/*
> >-			 * In theory we should stop the search as generic
> >-			 * entries should always come after the more specific
> >-			 * ones, but let's continue to make sure to work even
> >-			 * with "broken" firmwares. If we don't find a more
> >-			 * specific one, then we use this entry
> >-			 */
> >-			dmc_offset = fw_info[i].offset;
> >+		if (fw_info_matches_stepping(&fw_info[i], si)) {
> >+			dmc->dmc_info[id].present = true;
> >+			dmc->dmc_info[id].dmc_offset = fw_info[i].offset;
> > 		}
> > 	}
> >-
> >-	return dmc_offset;
> > }
> >
> > static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> > 			       const struct intel_dmc_header_base
> *dmc_header,
> >-			       size_t rem_size)
> >+			       size_t rem_size, u8 dmc_id)
> > {
> > 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915),
> dmc);
> >-	struct dmc_fw_info *dmc_info = &dmc-
> >dmc_info[DMC_FW_MAIN];
> >+	struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
> > 	unsigned int header_len_bytes, dmc_header_size, payload_size, i;
> > 	const u32 *mmioaddr, *mmiodata;
> >-	u32 mmio_count, mmio_count_max;
> >+	u32 mmio_count, mmio_count_max, start_mmioaddr;
> > 	u8 *payload;
> >
> > 	BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) <
> DMC_V3_MAX_MMIO_COUNT
> >|| @@ -432,6 +449,7 @@ static u32 parse_dmc_fw_header(struct
> intel_dmc *dmc,
> > 		mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
> > 		/* header_len is in dwords */
> > 		header_len_bytes = dmc_header->header_len * 4;
> >+		start_mmioaddr = v3->start_mmioaddr;
> > 		dmc_header_size = sizeof(*v3);
> > 	} else if (dmc_header->header_ver == 1) {
> > 		const struct intel_dmc_header_v1 *v1 = @@ -445,6 +463,7
> @@ static
> >u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> > 		mmio_count = v1->mmio_count;
> > 		mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
> > 		header_len_bytes = dmc_header->header_len;
> >+		start_mmioaddr = 0x80000;
> 
> instead of the naked/magic number, maybe:
> 
> #define DMC_V1_MMIO_START_RANGE 0x80000 and use it.
> 
> > 		dmc_header_size = sizeof(*v1);
> > 	} else {
> > 		drm_err(&i915->drm, "Unknown DMC fw header version:
> %u\n", @@ -469,6
> >+488,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> > 		dmc_info->mmiodata[i] = mmiodata[i];
> > 	}
> > 	dmc_info->mmio_count = mmio_count;
> >+	dmc_info->start_mmioaddr = start_mmioaddr;
> 
> now that you are assigning the start_mmioaddr according to the package
> version, instead of have removed the sanity check in patch 1, you could use
> this field for the sanity check.

Actually it Is better to remove this sanity check. In the above code segment we are dong MMIO of the DMC control registers represented by mmio_count, mmioaddr and mmiodata where we copy mmiodata[i] to mmioaddr[i] and there are of mmiocount in number. The start_mmioaddr on the other hand is the starting range for DMC non control registers (other part of firmware). It made sense to have this sanity check because we had all platform with both control and non control registers to be within this range. But we now have platforms which have these to parts of the firmware not really in this range.

Anusha
> 
> Lucas De Marchi
> 
> >
> > 	rem_size -= header_len_bytes;
> >
> >@@ -505,7 +525,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,  {
> > 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915),
> dmc);
> > 	u32 package_size = sizeof(struct intel_package_header);
> >-	u32 num_entries, max_entries, dmc_offset;
> >+	u32 num_entries, max_entries;
> > 	const struct intel_fw_info *fw_info;
> >
> > 	if (rem_size < package_size)
> >@@ -541,16 +561,11 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
> >
> > 	fw_info = (const struct intel_fw_info *)
> > 		((u8 *)package_header + sizeof(*package_header));
> >-	dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
> >-					package_header->header_ver);
> >-	if (dmc_offset == DMC_DEFAULT_FW_OFFSET) {
> >-		drm_err(&i915->drm, "DMC firmware not supported for %c
> stepping\n",
> >-			si->stepping);
> >-		return 0;
> >-	}
> >+	dmc_set_fw_offset(dmc, fw_info, num_entries, si,
> >+			  package_header->header_ver);
> >
> > 	/* dmc_offset is in dwords */
> >-	return package_size + dmc_offset * 4;
> >+	return package_size;
> >
> > error_truncated:
> > 	drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); @@ -
> 602,7
> >+617,8 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
> > 	struct intel_dmc *dmc = &dev_priv->dmc;
> > 	const struct stepping_info *si = intel_get_stepping_info(dev_priv);
> > 	u32 readcount = 0;
> >-	u32 r;
> >+	u32 r, offset;
> >+	int id;
> >
> > 	if (!fw)
> > 		return;
> >@@ -623,9 +639,19 @@ static void parse_dmc_fw(struct drm_i915_private
> >*dev_priv,
> >
> > 	readcount += r;
> >
> >-	/* Extract dmc_header information */
> >-	dmc_header = (struct intel_dmc_header_base *)&fw-
> >data[readcount];
> >-	parse_dmc_fw_header(dmc, dmc_header, fw->size - readcount);
> >+	for (id = 0; id < DMC_FW_MAX; id++) {
> >+		if (!dev_priv->dmc.dmc_info[id].present)
> >+			continue;
> >+
> >+		offset = readcount + dmc->dmc_info[id].dmc_offset * 4;
> >+		if (fw->size - offset < 0) {
> >+			drm_err(&dev_priv->drm, "Reading beyond the
> fw_size\n");
> >+			continue;
> >+		}
> >+
> >+		dmc_header = (struct intel_dmc_header_base *)&fw-
> >data[offset];
> >+		parse_dmc_fw_header(dmc, dmc_header, fw->size - offset,
> id);
> >+	}
> > }
> >
> > static void intel_dmc_runtime_pm_get(struct drm_i915_private
> >*dev_priv) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h
> >b/drivers/gpu/drm/i915/display/intel_dmc.h
> >index b872f3a4fd03..007a284b0ef0 100644
> >--- a/drivers/gpu/drm/i915/display/intel_dmc.h
> >+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> >@@ -18,6 +18,7 @@ struct drm_i915_private;
> >
> > enum {
> > 	DMC_FW_MAIN = 0,
> >+	DMC_FW_PIPEA,
> > 	DMC_FW_MAX
> > };
> >
> >@@ -31,8 +32,11 @@ struct intel_dmc {
> > 		u32 mmio_count;
> > 		i915_reg_t mmioaddr[20];
> > 		u32 mmiodata[20];
> >+		u32 dmc_offset;
> >+		u32 start_mmioaddr;
> > 		u32 dmc_fw_size; /*dwords */
> > 		u32 *payload;
> >+		bool present;
> > 	} dmc_info[DMC_FW_MAX];
> >
> > 	u32 dc_state;
> >diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >b/drivers/gpu/drm/i915/i915_reg.h index 24307c49085f..912b2d553bc4
> >100644
> >--- a/drivers/gpu/drm/i915/i915_reg.h
> >+++ b/drivers/gpu/drm/i915/i915_reg.h
> >@@ -7751,7 +7751,7 @@ enum {
> > #define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED	(3 <<
> 0) /* icl + */
> >
> > /* DMC */
> >-#define DMC_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
> >+#define DMC_PROGRAM(addr, i)	_MMIO((addr) + (i) * 4)
> > #define DMC_SSP_BASE_ADDR_GEN9	0x00002FC0
> > #define DMC_HTP_ADDR_SKL	0x00500034
> > #define DMC_SSP_BASE		_MMIO(0x8F074)
> >--
> >2.25.0
> >
> >_______________________________________________
> >Intel-gfx mailing list
> >Intel-gfx@lists.freedesktop.org
> >https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [CI 0/4] Pipe DMC Support

[Anusha Srivatsa]

One change from previous verison is a fix of SKL
regression. Corner cases for stepping-substepping
combination was missing from fw_info_matches_stepping()
helper. Luckily SKL was the only platform in CI that came
under this category and DMC refused to load.

v2: SKL fix tested on SKL.

v3: Minor changes in Pipe DMC plugging patch
as suggested by Lucas
 
v4: Remove the sanity check for MMIO that no longer
apply to newer platforms.(Anusha)

Anusha Srivatsa (4):
  drm/i915/dmc: Introduce DMC_FW_MAIN
  drm/i915/xelpd: Pipe A DMC plugging
  drm/i915/adl_p: Pipe B DMC Support
  drm/i915/adl_p: Load DMC

 .../drm/i915/display/intel_display_debugfs.c  |   6 +-
 .../drm/i915/display/intel_display_power.c    |   5 +-
 drivers/gpu/drm/i915/display/intel_dmc.c      | 165 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_dmc.h      |  23 ++-
 drivers/gpu/drm/i915/i915_reg.h               |   2 +-
 5 files changed, 123 insertions(+), 78 deletions(-)

-- 
2.25.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [CI 0/4] Pipe DMC Support

[Anusha Srivatsa]

One change from previous verison is a fix of SKL
regression. Corner cases for stepping-substepping
combination was missing from fw_info_matches_stepping()
helper. Luckily SKL was the only platform in CI that came
under this category and DMC refused to load.

v2: SKL fix tested on SKL.

v3: Minor changes in Pipe DMC plugging patch
as suggested by Lucas
 
v4: Remove the sanity check for MMIO that no longer
apply to newer platforms.(Anusha)

Anusha Srivatsa (4):
  drm/i915/dmc: Introduce DMC_FW_MAIN
  drm/i915/xelpd: Pipe A DMC plugging
  drm/i915/adl_p: Pipe B DMC Support
  drm/i915/adl_p: Load DMC

 .../drm/i915/display/intel_display_debugfs.c  |   6 +-
 .../drm/i915/display/intel_display_power.c    |   5 +-
 drivers/gpu/drm/i915/display/intel_dmc.c      | 165 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_dmc.h      |  23 ++-
 drivers/gpu/drm/i915/i915_reg.h               |   2 +-
 5 files changed, 123 insertions(+), 78 deletions(-)

-- 
2.25.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [CI 0/4] Pipe DMC Support

[Anusha Srivatsa]

With all DMC cleanup patches merged, sending the
rebased version of actual Pipe DMC bits.

One change from previous verison is a fix of SKL
regression. Corner cases for stepping-substepping
combination was missing from fw_info_matches_stepping()
helper. Luckily SKL was the only platform in CI that came
under this category and DMC refused to load.

v2: SKL fix tested on SKL.

v3: Minor changes in Pipe DMC plugging patch
as suggested by Lucas


Anusha Srivatsa (4):
  drm/i915/dmc: Introduce DMC_FW_MAIN
  drm/i915/xelpd: Pipe A DMC plugging
  drm/i915/adl_p: Pipe B DMC Support
  drm/i915/adl_p: Load DMC

 .../drm/i915/display/intel_display_debugfs.c  |   6 +-
 .../drm/i915/display/intel_display_power.c    |   5 +-
 drivers/gpu/drm/i915/display/intel_dmc.c      | 162 +++++++++++-------
 drivers/gpu/drm/i915/display/intel_dmc.h      |  23 ++-
 drivers/gpu/drm/i915/i915_reg.h               |   2 +-
 5 files changed, 124 insertions(+), 74 deletions(-)

-- 
2.25.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [CI 0/4] Pipe DMC Support

[Anusha Srivatsa]

With all DMC cleanup patches merged, sending the
rebased version of actual Pipe DMC bits.

One change from previous verison is a fix of SKL
regression. Corner cases for stepping-substepping
combination was missing from fw_info_matches_stepping()
helper. Luckily SKL was the only platform in CI that came
under this category and DMC refused to load.

This fix is tested on SKL.

Anusha Srivatsa (4):
  drm/i915/dmc: Introduce DMC_FW_MAIN
  xdrm/i915/xelpd: Pipe A DMC plugging
  drm/i915/adl_p: Pipe B DMC Support
  drm/i915/adl_p: Load DMC

 .../drm/i915/display/intel_display_debugfs.c  |   6 +-
 .../drm/i915/display/intel_display_power.c    |   5 +-
 drivers/gpu/drm/i915/display/intel_dmc.c      | 170 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_dmc.h      |  23 ++-
 drivers/gpu/drm/i915/i915_reg.h               |   2 +-
 5 files changed, 127 insertions(+), 79 deletions(-)

-- 
2.25.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx