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Sun, 6 Jun 2021 08:22:34 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 6 Jun 2021 08:22:34 +0000 Received: from buildserver-hdc-comms.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 6 Jun 2021 08:22:30 +0000 From: Om Prakash Singh To: , , , , , , CC: , , , , , Om Prakash Singh Subject: [PATCH V2 4/5] PCI: tegra: Don't allow suspend when Tegra PCIe is in EP mode Date: Sun, 6 Jun 2021 13:52:03 +0530 Message-ID: <20210606082204.14222-5-omp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210606082204.14222-1-omp@nvidia.com> References: <20210606082204.14222-1-omp@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a9fd0506-24ca-4fb8-e241-08d928c43cc2 X-MS-TrafficTypeDiagnostic: BN6PR12MB1442: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2021 08:22:34.5113 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a9fd0506-24ca-4fb8-e241-08d928c43cc2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.36];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1442 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org When Tegra PCIe is in endpoint mode it should be available for root port. PCIe link up by root port fails if it is in suspend state. So, don't allow Tegra to suspend when endpoint mode is enabled. Signed-off-by: Om Prakash Singh --- Changes in V2: - Update return value and error log as per comment from Krzysztof Wilczyński drivers/pci/controller/dwc/pcie-tegra194.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 64ec0da31b5b..ae4c0a29818d 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2276,6 +2276,11 @@ static int tegra_pcie_dw_suspend_late(struct device *dev) struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); u32 val; + if (pcie->mode == DW_PCIE_EP_TYPE) { + dev_err(dev, "Suspend is not supported in EP mode"); + return -ENOTSUPP; + } + if (!pcie->link_state) return 0; -- 2.17.1