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[88.4.247.113]) by smtp.gmail.com with ESMTPSA id n9sm11724427wmc.20.2021.06.06.09.14.01 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 06 Jun 2021 09:14:01 -0700 (PDT) From: Sergio Paracuellos To: linux-staging@lists.linux.dev Cc: gregkh@linuxfoundation.org, neil@brown.name Subject: [PATCH v2 1/6] staging: mt7621-pci: make cleaner 'mt7621_pcie_enable_ports' Date: Sun, 6 Jun 2021 18:13:53 +0200 Message-Id: <20210606161358.7114-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210606161358.7114-1-sergio.paracuellos@gmail.com> References: <20210606161358.7114-1-sergio.paracuellos@gmail.com> X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Function 'mt7621_pcie_enable_ports' call 'mt7621_pcie_enable_port' for each available pcie port. Instead of having two for loops there just move needed initialization. There is one setting that can be removed which is the set for 'PCI_COMMAND_MASTER' bit. Pci drivers are in charge of set that bit if it is really needed and should be not a mission of the controller to do that. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index fe1945819d25..c14fc48e74fc 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -499,15 +499,18 @@ static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port) /* configure class code and revision ID */ pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID, offset + RALINK_PCI_CLASS); + + /* configure RC FTS number to 250 when it leaves L0s */ + val = read_config(pcie, slot, PCIE_FTS_NUM); + val &= ~PCIE_FTS_NUM_MASK; + val |= PCIE_FTS_NUM_L0(0x50); + write_config(pcie, slot, PCIE_FTS_NUM, val); } static int mt7621_pcie_enable_ports(struct mt7621_pcie *pcie) { struct device *dev = pcie->dev; struct mt7621_pcie_port *port; - u8 num_slots_enabled = 0; - u32 slot; - u32 val; int err; /* Setup MEMWIN and IOWIN */ @@ -518,27 +521,16 @@ static int mt7621_pcie_enable_ports(struct mt7621_pcie *pcie) if (port->enabled) { err = clk_prepare_enable(port->clk); if (err) { - dev_err(dev, "enabling clk pcie%d\n", slot); + dev_err(dev, "enabling clk pcie%d\n", + port->slot); return err; } mt7621_pcie_enable_port(port); dev_info(dev, "PCIE%d enabled\n", port->slot); - num_slots_enabled++; } } - for (slot = 0; slot < num_slots_enabled; slot++) { - val = read_config(pcie, slot, PCI_COMMAND); - val |= PCI_COMMAND_MASTER; - write_config(pcie, slot, PCI_COMMAND, val); - /* configure RC FTS number to 250 when it leaves L0s */ - val = read_config(pcie, slot, PCIE_FTS_NUM); - val &= ~PCIE_FTS_NUM_MASK; - val |= PCIE_FTS_NUM_L0(0x50); - write_config(pcie, slot, PCIE_FTS_NUM, val); - } - return 0; } -- 2.25.1