From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A3E070 for ; Mon, 7 Jun 2021 06:27:04 +0000 (UTC) Received: by verein.lst.de (Postfix, from userid 2407) id 3212967373; Mon, 7 Jun 2021 08:27:01 +0200 (CEST) Date: Mon, 7 Jun 2021 08:27:01 +0200 From: Christoph Hellwig To: Guo Ren Cc: Nick Kossifidis , Christoph Hellwig , Drew Fustini , Anup Patel , Palmer Dabbelt , wefu@redhat.com, Wei Wu =?utf-8?B?KOWQtOS8nyk=?= , linux-riscv , Linux Kernel Mailing List , linux-arch , linux-sunxi@lists.linux.dev, Guo Ren , Paul Walmsley , Benjamin Koch , Matteo Croce , Wei Fu Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support Message-ID: <20210607062701.GB24060@lst.de> References: <1621400656-25678-1-git-send-email-guoren@kernel.org> <20210519052048.GA24853@lst.de> <20210519064435.GA3076809@x1> <20210519065352.GA31590@lst.de> <29733b0931d9dd6a2f0b6919067c7efe@mailhost.ics.forth.gr> X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.17 (2007-11-01) On Mon, Jun 07, 2021 at 11:19:03AM +0800, Guo Ren wrote: > >From Linux non-coherency view, we need: > - Non-cache + Strong Order PTE attributes to deal with drivers' DMA descriptors > - Non-cache + weak order to deal with framebuffer drivers > - CMO dma_sync to sync cache with DMA devices This is not strictly true. At the very minimum you only need cache invalidation and writeback instructions. For example early parisc CPUs and some m68knommu SOCs have no support for uncached areas at all, and Linux works. But to be fair this is very painful and supports only very limited periphals. So for modern full Linux support some uncahed memory is advisable. But that doesn't have to be using PTE attributes. It could also be physical memory regions that are either totally fixed or somewhat dynamic. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FFA0C47082 for ; Mon, 7 Jun 2021 06:27:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 18AC9610C9 for ; Mon, 7 Jun 2021 06:27:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 18AC9610C9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=lst.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=W0Z2M5fdiFdvRVI9Vnb3xJ35AZHi9Zi6mNJSSi9p3dw=; b=M2cbzQeKNWM+n/ HXTmac8xL8VPDNn0dyO2qf2f8gu8g3QvetxLkgA0nKpqT7rtpvgHAb0xHIf4IN7fDcKcNjyAQpbTJ z9TtBnD8+wbJ05WA2eRlwvUbwbQIAKz69m38PTv3wXkLwT540h4mOPd2YhRRwCXWmpMFUQ50CNSWm HmBOtv2G3Zi/HY+4s1mvQgyrMqvvQGi+oM+bgd6LyCmEiBjTYL7sVlI/TPWSfQjndAZ++dUtyBDSE WnD/xxNu7PCrv2GuGy54PRyFVHomtpD2Mv/q9OALMzVE97/ZydhK8wzZtR7Prlj3MKFxURHBTVI+/ cRsPl476ig3KjLzQJ5uw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lq8j5-001hEQ-30; Mon, 07 Jun 2021 06:27:07 +0000 Received: from verein.lst.de ([213.95.11.211]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lq8j2-001hDc-Dq for linux-riscv@lists.infradead.org; Mon, 07 Jun 2021 06:27:05 +0000 Received: by verein.lst.de (Postfix, from userid 2407) id 3212967373; Mon, 7 Jun 2021 08:27:01 +0200 (CEST) Date: Mon, 7 Jun 2021 08:27:01 +0200 From: Christoph Hellwig To: Guo Ren Cc: Nick Kossifidis , Christoph Hellwig , Drew Fustini , Anup Patel , Palmer Dabbelt , wefu@redhat.com, Wei Wu =?utf-8?B?KOWQtOS8nyk=?= , linux-riscv , Linux Kernel Mailing List , linux-arch , linux-sunxi@lists.linux.dev, Guo Ren , Paul Walmsley , Benjamin Koch , Matteo Croce , Wei Fu Subject: Re: [PATCH RFC 0/3] riscv: Add DMA_COHERENT support Message-ID: <20210607062701.GB24060@lst.de> References: <1621400656-25678-1-git-send-email-guoren@kernel.org> <20210519052048.GA24853@lst.de> <20210519064435.GA3076809@x1> <20210519065352.GA31590@lst.de> <29733b0931d9dd6a2f0b6919067c7efe@mailhost.ics.forth.gr> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.17 (2007-11-01) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210606_232704_643613_B87ECE5C X-CRM114-Status: GOOD ( 12.19 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Jun 07, 2021 at 11:19:03AM +0800, Guo Ren wrote: > >From Linux non-coherency view, we need: > - Non-cache + Strong Order PTE attributes to deal with drivers' DMA descriptors > - Non-cache + weak order to deal with framebuffer drivers > - CMO dma_sync to sync cache with DMA devices This is not strictly true. At the very minimum you only need cache invalidation and writeback instructions. For example early parisc CPUs and some m68knommu SOCs have no support for uncached areas at all, and Linux works. But to be fair this is very painful and supports only very limited periphals. So for modern full Linux support some uncahed memory is advisable. But that doesn't have to be using PTE attributes. It could also be physical memory regions that are either totally fixed or somewhat dynamic. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv