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Mon, 7 Jun 2021 13:45:14 +0000 Received: from grasider-dev.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.4; Mon, 7 Jun 2021 08:45:13 -0500 From: Graham Sider To: Subject: [PATCH v5 2/9] drm/amd/pm: Add ASIC independent throttle bits Date: Mon, 7 Jun 2021 09:44:32 -0400 Message-ID: <20210607134439.28542-2-Graham.Sider@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210607134439.28542-1-Graham.Sider@amd.com> References: <20210607134439.28542-1-Graham.Sider@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 14a03b06-af6f-49c6-be38-08d929ba7a8b X-MS-TrafficTypeDiagnostic: BYAPR12MB3559: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2657; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2021 13:45:14.5831 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14a03b06-af6f-49c6-be38-08d929ba7a8b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3559 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Harish.Kasiviswanathan@amd.com, Graham Sider , Elena.Sakhnovitch@amd.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Add new defines for thermal throttle status bits which are ASIC independent. This bit field will be visible to userspace via gpu_metrics alongside the previous ASIC dependent bit fields. Seperated into four 16-bit types: power throttlers, current throttlers, temperature, other. Signed-off-by: Graham Sider --- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 41 +++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h index 71adb9e76a95..829fd8651221 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h @@ -35,6 +35,47 @@ #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) +// Power Throttlers +#define SMU_THROTTLER_PPT0_BIT 0 +#define SMU_THROTTLER_PPT1_BIT 1 +#define SMU_THROTTLER_PPT2_BIT 2 +#define SMU_THROTTLER_PPT3_BIT 3 +#define SMU_THROTTLER_SPL_BIT 4 +#define SMU_THROTTLER_FPPT_BIT 5 +#define SMU_THROTTLER_SPPT_BIT 6 +#define SMU_THROTTLER_SPPT_APU_BIT 7 + +// Current Throttlers +#define SMU_THROTTLER_TDC_GFX_BIT 16 +#define SMU_THROTTLER_TDC_SOC_BIT 17 +#define SMU_THROTTLER_TDC_MEM_BIT 18 +#define SMU_THROTTLER_TDC_VDD_BIT 19 +#define SMU_THROTTLER_TDC_CVIP_BIT 20 +#define SMU_THROTTLER_EDC_CPU_BIT 21 +#define SMU_THROTTLER_EDC_GFX_BIT 22 +#define SMU_THROTTLER_APCC_BIT 23 + +// Temperature +#define SMU_THROTTLER_TEMP_GPU_BIT 32 +#define SMU_THROTTLER_TEMP_CORE_BIT 33 +#define SMU_THROTTLER_TEMP_MEM_BIT 34 +#define SMU_THROTTLER_TEMP_EDGE_BIT 35 +#define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 +#define SMU_THROTTLER_TEMP_VR_GFX_BIT 37 +#define SMU_THROTTLER_TEMP_VR_SOC_BIT 38 +#define SMU_THROTTLER_TEMP_VR_MEM0_BIT 39 +#define SMU_THROTTLER_TEMP_VR_MEM1_BIT 40 +#define SMU_THROTTLER_TEMP_LIQUID0_BIT 41 +#define SMU_THROTTLER_TEMP_LIQUID1_BIT 42 +#define SMU_THROTTLER_VRHOT0_BIT 43 +#define SMU_THROTTLER_VRHOT1_BIT 44 +#define SMU_THROTTLER_PROCHOT_CPU_BIT 45 +#define SMU_THROTTLER_PROCHOT_GFX_BIT 46 + +// Other +#define SMU_THROTTLER_PPM_BIT 48 +#define SMU_THROTTLER_FIT_BIT 49 + struct smu_hw_power_state { unsigned int magic; }; -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx