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Subject: [PATCH v10 0/2] PCI: keembay: Add support for Intel Keem Bay
Date: Mon,  7 Jun 2021 21:10:42 +0530	[thread overview]
Message-ID: <> (raw)

From: Srikanth Thokala <>


The first patch is to document DT bindings for Keem Bay PCIe controller
for both Root Complex and Endpoint modes.

The second patch is the driver file, a glue driver. Keem Bay PCIe
controller is based on DesignWare PCIe IP.

The patch was tested with Keem Bay evaluation module board, with B0

Kindly review.


Changes since v9:
- Add 'Reviewed-by: Krzysztof Wilczyński <>', thanks to Krzysztof.
- Rebased to v5.13-rc5.

Changes since v8:
- Use chained IRQ to handle MSIs, as suggested by Lorenzo Pieralisi.
- Rename *_setup_irq() to *_setup_msi_irq() to be more meaningful.
- Move *_setup_msi_irq() call to *_add_pcie_port() to make it invoke
  only when controller is in Root Complex mode. In Endpoint mode,
  IRQ will be setup by the respective driver which will be based on
  PCIe End Point Framework.

Changes since v7:
- Rename keembay_pcie_ltssm_enable() to align to its functionality.
- Fix other minor comments from "Krzysztof Wilczyński <>"

Changes since v6:
- Arrange SoB in chronological order.
- Alphabetized and modified status of entry in MAINTAINERS.
- Added a comment to specify the PCIe spec section about the delay.

Changes since v5:
- Rebased to v5.11-rc4.
- Updated maintainers to add myself in DT binding documents.
- Fix checkpatch issues.

Changes since v4:
- Rebased to v5.11-rc1 and retest.

Changes since v3:
- Add Reviewed-by: Rob Herring <> tag in dt-bindings
- Remove the keembay_pcie_{readl,writel} wrappers. And replace them with
  readl() and writel().
- Remove the dead code related to unused irqs.
- Remove unused definition for unused irqs.
- In keembay_pcie_ep_init(), initialize enabled interrupts to known state.
- Rebased to next-20201215.

Changes since v2:
- In keembay_pcie_probe(), use return keembay_pcie_add_pcie_port(pcie,
  pdev); statement and remove return 0; at the end of the function.

Changes since v1:
- In dt-bindings patch.
  - Fixed indent warning for compatible property.
  - Rename interrupt-names to pcie, pcie_ev, pcie_err and
    pcie_mem_access, similar to the name used in datasheet.
  - Remove device_type, #address-cells and #size-cells property.
  - Remove num-viewport, num-ib-windows and num-ob-windows property.
  - Replace additionalProperties with unevaluatedProperties, for RC
  - Add dbi2 and atu property.
  - Remove description for regs and interrupts property.
  - Change enum value for num-lanes to 1 and 2 only.
- In driver patch.
  - In Kconfig file, remove dependency on ARM64.
  - Add new define, PCIE_REGS_PCIE_SII_LINK_UP.
  - Remove PCIE_DBI2_MASK.
  - In struct keembay_pcie, declare pci member as struct, not pointer.
    And remove irq number members.
  - Rename and rework keembay_pcie_establish_link(), to
  - Remove unneeded BAR disable steps.
  - Remove unused interrupt handlers; keembay_pcie_ev_irq_handler(),
  - Remove keembay_pcie_enable_interrupts().
  - Rework keembay_pcie_setup_irq() and call it from
  - Remove keembay_pcie_host_init() and make keembay_pcie_host_ops
  - Keep and rework keembay_pcie_add_pcie_port() a little.
  - Remove keembay_pcie_add_pcie_ep() and call dw_pcie_ep_init() from
  - In keembay_pcie_probe(), remove dbi setup as it will be handled in
    dwc common code.
  - In keembay_pcie_link_up(), use return (val &
  - In keembay_pcie_ep_raise_irq(), rework error message for
    PCI_EPC_IRQ_LEGACY and default cases.
- Rebased to next-20201124, that has dwc pci refactoring,

Srikanth Thokala (2):
  dt-bindings: PCI: Add Intel Keem Bay PCIe controller
  PCI: keembay: Add support for Intel Keem Bay

 .../bindings/pci/intel,keembay-pcie-ep.yaml   |  69 +++
 .../bindings/pci/intel,keembay-pcie.yaml      |  97 ++++
 MAINTAINERS                                   |   7 +
 drivers/pci/controller/dwc/Kconfig            |  28 ++
 drivers/pci/controller/dwc/Makefile           |   1 +
 drivers/pci/controller/dwc/pcie-keembay.c     | 451 ++++++++++++++++++
 6 files changed, 653 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml
 create mode 100644 Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml
 create mode 100644 drivers/pci/controller/dwc/pcie-keembay.c

base-commit: 614124bea77e452aa6df7a8714e8bc820b489922

             reply	other threads:[~2021-06-07  7:46 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-07 15:40 srikanth.thokala [this message]
2021-06-07 15:40 ` [PATCH v10 1/2] dt-bindings: PCI: Add Intel Keem Bay PCIe controller srikanth.thokala
2021-06-07 15:40 ` [PATCH v10 2/2] PCI: keembay: Add support for Intel Keem Bay srikanth.thokala
2021-06-15 21:09   ` Rob Herring
2021-06-16  7:49     ` Thokala, Srikanth
2021-06-21 16:53   ` Lorenzo Pieralisi
2021-06-25  3:23     ` Thokala, Srikanth
2021-07-07 11:54       ` Thokala, Srikanth
2021-07-26  6:30         ` Thokala, Srikanth
2021-07-26  8:00       ` Marc Zyngier
2021-07-27 16:26         ` Thokala, Srikanth
2021-06-15 14:38 ` [PATCH v10 0/2] " Thokala, Srikanth

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