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From: Stylon Wang <stylon.wang@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Stylon Wang <stylon.wang@amd.com>,
	Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>,
	Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Qingqing.Zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	Nikola Cornij <nikola.cornij@amd.com>,
	Anson.Jacob@amd.com, Aurabindo.Pillai@amd.com,
	Bhawanpreet.Lakha@amd.com, bindu.r@amd.com
Subject: [PATCH 04/30] drm/amd/display: Fix DCN 3.01 DSCCLK validation
Date: Tue, 8 Jun 2021 00:46:48 +0800	[thread overview]
Message-ID: <20210607164714.311325-5-stylon.wang@amd.com> (raw)
In-Reply-To: <20210607164714.311325-1-stylon.wang@amd.com>

From: Nikola Cornij <nikola.cornij@amd.com>

[why]
DSCCLK validation is not necessary because DSCCLK is derrived from
DISPCLK, therefore if DISPCLK validation passes, DSCCLK is valid, too.
Doing DSCLK validation in addition to DISPCLK leads to modes being
wrongly rejected when DSCCLK was incorrectly set outside of DML.

[how]
Remove DSCCLK validation because it's implicitly validated under DISPCLK

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
---
 .../dc/dml/dcn30/display_mode_vba_30.c        | 64 ++++++-------------
 1 file changed, 21 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index ec56210b6180..bd657029f8c9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -64,6 +64,7 @@ typedef struct {
 #define BPP_INVALID 0
 #define BPP_BLENDED_PIPE 0xffffffff
 #define DCN30_MAX_DSC_IMAGE_WIDTH 5184
+#define DCN30_MAX_FMT_420_BUFFER_WIDTH 4096
 
 static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
 static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
@@ -3987,19 +3988,30 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 				} else if (v->PlaneRequiredDISPCLKWithoutODMCombine > v->MaxDispclkRoundedDownToDFSGranularity) {
 					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
 					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
-				} else if (v->DSCEnabled[k] && (v->HActive[k] > DCN30_MAX_DSC_IMAGE_WIDTH)) {
-					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
-					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
 				} else {
 					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
 					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
-					/*420 format workaround*/
-					if (v->HActive[k] > 4096 && v->OutputFormat[k] == dm_420) {
+				}
+				if (v->DSCEnabled[k] && v->HActive[k] > DCN30_MAX_DSC_IMAGE_WIDTH
+						&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
+					if (v->HActive[k] / 2 > DCN30_MAX_DSC_IMAGE_WIDTH) {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
+					} else {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
+					}
+				}
+				if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN30_MAX_FMT_420_BUFFER_WIDTH
+						&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
+					if (v->HActive[k] / 2 > DCN30_MAX_FMT_420_BUFFER_WIDTH) {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
+					} else {
 						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
 						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
 					}
 				}
-
 				if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
 					v->MPCCombine[i][j][k] = false;
 					v->NoOfDPP[i][j][k] = 4;
@@ -4281,42 +4293,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 		}
 	}
 
-	for (i = 0; i < v->soc.num_states; i++) {
-		v->DSCCLKRequiredMoreThanSupported[i] = false;
-		for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
-			if (v->BlendingAndTiming[k] == k) {
-				if (v->Output[k] == dm_dp || v->Output[k] == dm_edp) {
-					if (v->OutputFormat[k] == dm_420) {
-						v->DSCFormatFactor = 2;
-					} else if (v->OutputFormat[k] == dm_444) {
-						v->DSCFormatFactor = 1;
-					} else if (v->OutputFormat[k] == dm_n422) {
-						v->DSCFormatFactor = 2;
-					} else {
-						v->DSCFormatFactor = 1;
-					}
-					if (v->RequiresDSC[i][k] == true) {
-						if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
-							if (v->PixelClockBackEnd[k] / 12.0 / v->DSCFormatFactor
-									> (1.0 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * v->MaxDSCCLK[i]) {
-								v->DSCCLKRequiredMoreThanSupported[i] = true;
-							}
-						} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
-							if (v->PixelClockBackEnd[k] / 6.0 / v->DSCFormatFactor
-									> (1.0 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * v->MaxDSCCLK[i]) {
-								v->DSCCLKRequiredMoreThanSupported[i] = true;
-							}
-						} else {
-							if (v->PixelClockBackEnd[k] / 3.0 / v->DSCFormatFactor
-									> (1.0 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * v->MaxDSCCLK[i]) {
-								v->DSCCLKRequiredMoreThanSupported[i] = true;
-							}
-						}
-					}
-				}
-			}
-		}
-	}
+	/* Skip dscclk validation: as long as dispclk is supported, dscclk is also implicitly supported */
+
 	for (i = 0; i < v->soc.num_states; i++) {
 		v->NotEnoughDSCUnits[i] = false;
 		v->TotalDSCUnitsRequired = 0.0;
@@ -5319,7 +5297,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 		for (j = 0; j < 2; j++) {
 			if (v->ScaleRatioAndTapsSupport == 1 && v->SourceFormatPixelAndScanSupport == 1 && v->ViewportSizeSupport[i][j] == 1
 					&& v->DIOSupport[i] == 1 && v->ODMCombine4To1SupportCheckOK[i] == 1
-					&& v->NotEnoughDSCUnits[i] == 0 && v->DSCCLKRequiredMoreThanSupported[i] == 0
+					&& v->NotEnoughDSCUnits[i] == 0
 					&& v->DTBCLKRequiredMoreThanSupported[i] == 0
 					&& v->ROBSupport[i][j] == 1 && v->DISPCLK_DPPCLK_Support[i][j] == 1 && v->TotalAvailablePipesSupport[i][j] == 1
 					&& EnoughWritebackUnits == 1 && WritebackModeSupport == 1
-- 
2.25.1

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  parent reply	other threads:[~2021-06-07 16:48 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-07 16:46 [PATCH 00/30] DC Patches June, 7, 2021 Stylon Wang
2021-06-07 16:46 ` [PATCH 01/30] drm/amd/display: Trigger full update after DCC on/off Stylon Wang
2021-06-07 16:46 ` [PATCH 02/30] drm/amd/display: Enabling PSR support for multiple panels Stylon Wang
2021-06-07 16:46 ` [PATCH 03/30] drm/amd/display: delay 100ms before restart after failing to read CP_IRQ Stylon Wang
2021-06-07 16:46 ` Stylon Wang [this message]
2021-06-07 16:46 ` [PATCH 05/30] drm/amd/display: Control power gating by driver Stylon Wang
2021-06-07 16:46 ` [PATCH 06/30] drm/amd/display: Refactor visual confirm Stylon Wang
2021-06-07 16:46 ` [PATCH 07/30] drm/amd/display: add visual confirm colors to differentiate layer_index > 0 Stylon Wang
2021-06-07 16:46 ` [PATCH 08/30] drm/amd/display: Revert "Fix clock table filling logic" Stylon Wang
2021-06-07 16:46 ` [PATCH 09/30] drm/amd/display: Expand DP module equalization API Stylon Wang
2021-06-07 16:46 ` [PATCH 10/30] drm/amd/display: Support mappable encoders when transmitting training patterns Stylon Wang
2021-06-07 16:46 ` [PATCH 11/30] drm/amd/display: Update scaling settings on modeset Stylon Wang
2021-06-07 16:46 ` [PATCH 12/30] drm/amd/display: Remove unused definition of DMUB SET_CONFIG Stylon Wang
2021-06-07 16:46 ` [PATCH 13/30] drm/amd/display: Return last used DRR VTOTAL from DC Stylon Wang
2021-06-07 16:46 ` [PATCH 14/30] drm/amd/display: Enable PSR Residency for multiple panels Stylon Wang
2021-06-07 16:46 ` [PATCH 15/30] drm/amd/display: Release MST resources on switch from MST to SST Stylon Wang
2021-06-07 16:47 ` [PATCH 16/30] drm/amd/display: Change default policy for MPO with multidisplay Stylon Wang
2021-06-07 16:47 ` [PATCH 17/30] drm/amd/display: [FW Promotion] Release 0.0.68 Stylon Wang
2021-06-07 16:47 ` [PATCH 18/30] drm/amd/display: 3.2.138 Stylon Wang
2021-06-07 16:47 ` [PATCH 19/30] drm/amd/display: Add Interface to set FIFO ERRDET SW Override Stylon Wang
2021-06-07 16:47 ` [PATCH 20/30] drm/amd/display: Add interface for ADD & DROP PIXEL Registers Stylon Wang
2021-06-07 16:47 ` [PATCH 21/30] drm/amd/display: Set DISPCLK_MAX_ERRDET_CYCLES to 7 Stylon Wang
2021-06-07 16:47 ` [PATCH 22/30] drm/amd/display: Fix off-by-one error in DML Stylon Wang
2021-06-07 16:47 ` [PATCH 23/30] drm/amd/display: Fix crash during MPO + ODM combine mode recalculation Stylon Wang
2021-06-07 16:47 ` [PATCH 24/30] drm/amd/display: Add debugfs entry for dsc passthrough Stylon Wang
2021-06-07 16:47 ` [PATCH 25/30] drm/amd/display: Revert "Disconnect non-DP with no EDID" Stylon Wang
2021-06-07 16:47 ` [PATCH 26/30] drm/amd/display: Updates for ODM Transition Test Stylon Wang
2021-06-07 16:47 ` [PATCH 27/30] drm/amd/display: force CP to DESIRED when removing display Stylon Wang
2021-06-07 16:47 ` [PATCH 28/30] drm/amd/display: Add swizzle visual confirm mode Stylon Wang
2021-06-07 16:47 ` [PATCH 29/30] drm/amd/display: [FW Promotion] Release 0.0.69 Stylon Wang
2021-06-07 16:47 ` [PATCH 30/30] drm/amd/display: 3.2.139 Stylon Wang
2021-06-08 14:00 ` [PATCH 00/30] DC Patches June, 7, 2021 Wheeler, Daniel

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