From: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
To: u-boot@lists.denx.de
Cc: michal.simek@xilinx.com,
Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Subject: [PATCH] [ZynqMP] Writing correct value to ANALOG_BUS.
Date: Mon, 7 Jun 2021 19:53:46 +0200 [thread overview]
Message-ID: <20210607175345.37227-1-adrian.fiergolski@fastree3d.com> (raw)
The default register configuration after powerup for PSSYSMON_ANALOG_BUS
register is incorrect. Hence, fix this in SPL by writing correct fixed
value. It follows UG1085 chapter 'PS SYSMON Analog_Bus' and reflects commit
sw_apps:zynq ("056ca65d44549ce27f716d423e8dfdefeee7440c")
in Xilinx:embeddedsw[1].
[1] https://github.com/Xilinx/embeddedsw
Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
%% original patch: 0001-zynqmp-Writing-correct-value-to-ANALOG_BUS.patch
---
arch/arm/mach-zynqmp/include/mach/hardware.h | 5 +++++
board/xilinx/zynqmp/zynqmp.c | 11 +++++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h
index a0acfa2ff1..4774ed4089 100644
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@@ -15,6 +15,11 @@
#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0
#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8
+#define ZYNQMP_AMS_PS_SYSMON_BASEADDR 0XFFA50800
+#define ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS ((ZYNQMP_AMS_PS_SYSMON_BASEADDR) \
+ + 0x00000114)
+#define ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL 0x00003210
+
#define PS_MODE0 BIT(0)
#define PS_MODE1 BIT(1)
#define PS_MODE2 BIT(2)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 8acd871ec2..9e7475dfaa 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -272,6 +272,17 @@ int board_early_init_f(void)
#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
ret = psu_init();
+
+ /*
+ * PS_SYSMON_ANALOG_BUS register determines mapping between SysMon
+ * supply sense channel to SysMon supply registers inside the IP.
+ * This register must be programmed to complete SysMon IP
+ * configuration. The default register configuration after
+ * power-up is incorrect. Hence, fix this by writing the
+ * correct value - 0x3210.
+ */
+ writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL,
+ ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS);
#endif
return ret;
--
2.31.1
next reply other threads:[~2021-06-07 17:54 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-07 17:53 Adrian Fiergolski [this message]
2021-06-08 7:17 ` [PATCH] [ZynqMP] Writing correct value to ANALOG_BUS Michal Simek
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