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[2603:6081:7b01:cbda:a887:7949:d39f:5384]) by smtp.gmail.com with ESMTPSA id y1sm11168803qkp.21.2021.06.07.16.16.51 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 Jun 2021 16:16:52 -0700 (PDT) Date: Mon, 7 Jun 2021 19:16:50 -0400 From: Tom Rini To: Patrick Delaunay Cc: u-boot@lists.denx.de, Andy Shevchenko , Etienne Carriere , Masahiro Yamada , Pali =?iso-8859-1?Q?Roh=E1r?= , Patrice Chotard , Patrick Delaunay , Simon Glass , Stefan Roese , Tero Kristo , U-Boot STM32 , Wasim Khan , chenshuo Subject: Re: [PATCH v4 0/7] arm: cache: cp15: don't map reserved region with no-map property Message-ID: <20210607231650.GA4481@bill-the-cat> References: <20210507125035.1594-1-patrick.delaunay@foss.st.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="FL5UXtIhxfXey3p5" Content-Disposition: inline In-Reply-To: <20210507125035.1594-1-patrick.delaunay@foss.st.com> X-Clacks-Overhead: GNU Terry Pratchett User-Agent: Mutt/1.9.4 (2018-02-28) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean --FL5UXtIhxfXey3p5 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, May 07, 2021 at 02:50:28PM +0200, Patrick Delaunay wrote: > Hi, >=20 > It it the v4 serie of [1]. >=20 > This v4 serie is rebased on top of master branch with update after Simon > Glass review and added tags. >=20 > On STM32MP15x platform we can use OP-TEE, loaded in DDR in a region > protected by a firewall. This region is reserved in the device with > the "no-map" property as defined in the binding file > doc/device-tree-bindings/reserved-memory/reserved-memory.txt. >=20 > Sometime the platform boot failed in U-Boot on a Cortex A7 access to > this region (depending of the binary and the issue can change with compil= er > version or with code alignment), then the firewall raise an error, > for example: >=20 > E/TC:0 tzc_it_handler:19 TZC permission failure > E/TC:0 dump_fail_filter:420 Permission violation on filter 0 > E/TC:0 dump_fail_filter:425 Violation @0xde5c6bf0, non-secure privilege= d read, > AXI ID 5c0 > E/TC:0 Panic >=20 > After investigation, the forbidden access is a speculative request perfor= med > by the Cortex A7 because all the DDR is mapped as MEMORY with CACHEABLE > property. >=20 > The issue is solved only when the region reserved by OP-TEE is no more > mapped in U-Boot as it is already done in Linux kernel. >=20 > Tested on DK2 board with OP-TEE 3.12 / TF-A 2.4: >=20 > With hard-coded address for OP-TEE reserved memory, > the error doesn't occur. >=20 > void dram_bank_mmu_setup(int bank) > { > .... >=20 > for (i =3D start >> MMU_SECTION_SHIFT; > i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); > i++) { > option =3D DCACHE_DEFAULT_OPTION; > if (i >=3D 0xde0) > option =3D INVALID_ENTRY; > set_section_dcache(i, option); > } > } >=20 > Just by modifying the test on 0xde0 to 0xdf0, the OP-TEE memory protected > by firewall is mapped cacheable and the error occurs. >=20 > I think that it can be a general issue for ARM architecture: the "no-map"= tag > of reserved memory in device should be respected by U-Boot if firewall > is configured before U-Boot execution. >=20 > But I don't propose a generic solution in > arm/lib/cache-cp15.c:dram_bank_mmu_setup() > because the device tree parsing done in lmb_init_and_reserve() takes a > long time when it is executed without data cache. >=20 > =3D> the previous path 7/7 of v2 series is dropped to avoid > performance issue on other ARM target. >=20 > To avoid this performance issue on stm32mp32mp platform, the lmb > initialization is done in enable_caches() when dcache is still enable. >=20 > This v3 series is composed by 7 patches > - 1..3/7: preliminary steps to support flags in library in lmb > (as it is done in memblock.c in Linux) > - 4/7: unitary test on the added feature in lmb lib > - 5/7: save the no-map flags in lmb when the device tree is parsed > - 6/7: solve issue for the size of cacheable area in pre-reloc case > - 7/7: update the stm32mp mmu support >=20 > See also [2] which handle same speculative access on armv8 for area > with Executable attribute. >=20 > [1] http://patchwork.ozlabs.org/project/uboot/list/?series=3D241122&state= =3D* > [2] http://patchwork.ozlabs.org/project/uboot/patch/20200903000106.5016-1= -marek.bykowski@gmail.com/ For the series, applied to u-boot/next, and I've taken the above and reworked it slightly to use as the merge commit message. Thanks! --=20 Tom --FL5UXtIhxfXey3p5 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmC+qNYACgkQFHw5/5Y0 tyxYXAv/b475dhqXlmy0IGUBLe31Sgl3zDACvw9wWN/wE+RjKDbf/BB3Lx66J0Cr gz1CKlN99SyG/uYGnjYyFw9FKkZEtaaAGjnWOS/VYEb9r2NHnZENA50LOg7DteKT G4M2HtWhiPweqeanehGN91KaHL+j71MVHa91NJkdggOSWNMBcvRlzQEv9Ak8w1Xk nSrgDl+lM/eHhwCh+btf1f+4YA7z+sh0DLsKMh5CEAFLM9RoOJNdVHMOO6cnDz08 LcqGUDBlTgzi2mcljNJba72iwmZ9TdKi/msEgLv78JMxezFVTUxwjN2XYRcX1rk+ okIZLNF8nvVAWfL8eCy1QZ4NYJh9iRIbdeSil/LbyuqJ3h8dc4mK9Sbt3Zu89VIM XUNyP0aUjNmml/eJOzQFUU5CuTUZSk18wrUWqoXNqI0kyZJUVK6hOhAVnhhXWGs4 iSl5+w7JlO1QynOHVx4GUjpqcWFugYntZsIBYGZs9er+AkKHaqf8EmhT/E/sSqzW tqoD+dud =svFm -----END PGP SIGNATURE----- --FL5UXtIhxfXey3p5--