From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3E5CC47094 for ; Tue, 8 Jun 2021 00:48:00 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 18DB061059 for ; Tue, 8 Jun 2021 00:48:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 18DB061059 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:36704 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqPuR-0006va-Af for qemu-devel@archiver.kernel.org; Mon, 07 Jun 2021 20:47:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45190) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqPeu-0003A3-Cd for qemu-devel@nongnu.org; Mon, 07 Jun 2021 20:31:56 -0400 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:19707) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqPen-0004b7-35 for qemu-devel@nongnu.org; Mon, 07 Jun 2021 20:31:56 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1623112307; x=1654648307; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0vsObJKhkVcyvOm8yGo9Ac1Y67ddd0MZhJkDMdr7C74=; b=AmbVbnYdmyjG/fwdYxo6PfeDAfI4OEp8fpyywVyTiAW06hE9lwrhFYbZ mhEnL7GsGg1sV3iCSgsqvzmeL0EJ9NF2N1iYIXam/N0mIuU1TXzwOgRtN UMkCqL8iK1KuCiPqThvbhN1D/Zqc9AEFnQNnmwhxymZQz3GmlGyXSOzYm ZKvM1t/tU7FNstccQf4I88Uecv2s0YYo4WkXNW44Ct7a8uz3ZJyjPaR/q NfS7PbCdv1/3zuJe9XQ0jXzWvX5qYtNy41Z1pHEEWukiDzRFcvAi48lGI SZxT9oRSurszD8awbNaGPtkQ27vyrPL7A8l6JC0UIT0G2k8CyGiiu6Xgf A==; IronPort-SDR: QATGaiw9AvmiuEQteT1h2Jox+4aTrfJKmgLeh1ha2yGUE4MID+TIJjdDLXWEp5TqQlg7dMQO5v oPmDBBoAooExZqBrKOycbh4xdl2L5SboHwBw3kN7neKa6KpIYnRHkt7gC6DbGFJYHNRz9jT1pq +w5zBOEX7/dKlQQ/Mmk4RlqC+c19LLtBkQa8zix9ywP7N7Jr1f84IzvbHvpv//o3yLGnrJ/XUr s1R116qB0TgrW+m4ssm+Ws6APQxZtHhxi3OOfDrQVQORnxPo1lWzfURvPrFPgXtRAbFvefo0JD TxA= X-IronPort-AV: E=Sophos;i="5.83,256,1616428800"; d="scan'208";a="171087443" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 08 Jun 2021 08:31:32 +0800 IronPort-SDR: nTeeNyddrEdRXDt8yczeMYVIG3O6pMQdGa8tbmVuErJ/auO+wBYh3k+CGKG5jU6QvOxEiWDcmi QkZMVWL7lb2RjtVuKRtkx95HZpMzXGfoDHzUl/LPpgNjwJdmHSJNN2xeN6DgAeLT7drPPsl8GX HpqW3Xwr1etW7qI5aYnkN6uO9keyEF1IOUG7RU19OKaTHmkTBBlK2brHf6FuK/tW1QXvUugKLY uX4etOutplEMyxVQ25twgdOjk2A1LNooCBwsqlCVGXy+4UnrZK5wg/fofUBh91FDF3vDPHVTSB rgmbdvBQ4Y5a62QFr5uocB2m Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2021 17:10:39 -0700 IronPort-SDR: PrY3pM+plTRdJp5ENIuQDfY7gN5PHQEKWS1Qhbem0NEz7KCJ9bPwxf6ybPsJpENEEm9dl/fb+e oEIaItpmO2tswEZM9Ck6K3KXfPL+/8UGzGM6IjrC85CCa0koOTxB7QJQhjgG0lY5zBn5pbjKfh HPcngd4ObHyaiYB4IO/BQAAYcuBxgsBYFBhznK3Hq+upX1b5hb605twL9ldguVTxtTb1YfMyRR voorTEWnDxKpH9X6SAL+JFLs58/J4RgQnnkQQ52ukG8wqUr776pTH6b2QNEkhS/1vYi6/XwiKo wHQ= WDCIronportException: Internal Received: from unknown (HELO localhost.localdomain) ([10.225.165.82]) by uls-op-cesaip02.wdc.com with ESMTP; 07 Jun 2021 17:31:29 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 24/32] target/riscv: rvb: single-bit instructions Date: Tue, 8 Jun 2021 10:29:39 +1000 Message-Id: <20210608002947.1649775-25-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210608002947.1649775-1-alistair.francis@wdc.com> References: <20210608002947.1649775-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=7863c9c60=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , alistair23@gmail.com, Kito Cheng , Richard Henderson , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20210505160620.15723-10-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 17 +++++ target/riscv/translate.c | 61 ++++++++++++++++ target/riscv/insn_trans/trans_rvb.c.inc | 97 +++++++++++++++++++++++++ 3 files changed, 175 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 9361984634..433b601b93 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -676,6 +676,15 @@ min 0000101 .......... 100 ..... 0110011 @r minu 0000101 .......... 101 ..... 0110011 @r max 0000101 .......... 110 ..... 0110011 @r maxu 0000101 .......... 111 ..... 0110011 @r +bset 0010100 .......... 001 ..... 0110011 @r +bclr 0100100 .......... 001 ..... 0110011 @r +binv 0110100 .......... 001 ..... 0110011 @r +bext 0100100 .......... 101 ..... 0110011 @r + +bseti 00101. ........... 001 ..... 0010011 @sh +bclri 01001. ........... 001 ..... 0010011 @sh +binvi 01101. ........... 001 ..... 0010011 @sh +bexti 01001. ........... 101 ..... 0010011 @sh # *** RV64B Standard Extension (in addition to RV32B) *** clzw 0110000 00000 ..... 001 ..... 0011011 @r2 @@ -684,3 +693,11 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r +bsetw 0010100 .......... 001 ..... 0111011 @r +bclrw 0100100 .......... 001 ..... 0111011 @r +binvw 0110100 .......... 001 ..... 0111011 @r +bextw 0100100 .......... 101 ..... 0111011 @r + +bsetiw 0010100 .......... 001 ..... 0011011 @sh5 +bclriw 0100100 .......... 001 ..... 0011011 @sh5 +binviw 0110100 .......... 001 ..... 0011011 @sh5 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 292cf09932..e12240d125 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -571,6 +571,48 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(t); } +static void gen_sbop_mask(TCGv ret, TCGv shamt) +{ + tcg_gen_movi_tl(ret, 1); + tcg_gen_shl_tl(ret, ret, shamt); +} + +static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt) +{ + TCGv t = tcg_temp_new(); + + gen_sbop_mask(t, shamt); + tcg_gen_or_tl(ret, arg1, t); + + tcg_temp_free(t); +} + +static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt) +{ + TCGv t = tcg_temp_new(); + + gen_sbop_mask(t, shamt); + tcg_gen_andc_tl(ret, arg1, t); + + tcg_temp_free(t); +} + +static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt) +{ + TCGv t = tcg_temp_new(); + + gen_sbop_mask(t, shamt); + tcg_gen_xor_tl(ret, arg1, t); + + tcg_temp_free(t); +} + +static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) +{ + tcg_gen_shr_tl(ret, arg1, shamt); + tcg_gen_andi_tl(ret, ret, 1); +} + static void gen_ctzw(TCGv ret, TCGv arg1) { tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); @@ -673,6 +715,25 @@ static bool gen_shifti(DisasContext *ctx, arg_shift *a, return true; } +static bool gen_shiftw(DisasContext *ctx, arg_r *a, + void(*func)(TCGv, TCGv, TCGv)) +{ + TCGv source1 = tcg_temp_new(); + TCGv source2 = tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + gen_get_gpr(source2, a->rs2); + + tcg_gen_andi_tl(source2, source2, 31); + (*func)(source1, source1, source2); + tcg_gen_ext32s_tl(source1, source1); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + tcg_temp_free(source2); + return true; +} + static bool gen_shiftiw(DisasContext *ctx, arg_shift *a, void(*func)(TCGv, TCGv, TCGv)) { diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 3d594e8cb4..69e5af44a1 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -107,6 +107,54 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a) return gen_unary(ctx, a, tcg_gen_ext16s_tl); } +static bool trans_bset(DisasContext *ctx, arg_bset *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, gen_bset); +} + +static bool trans_bseti(DisasContext *ctx, arg_bseti *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, gen_bset); +} + +static bool trans_bclr(DisasContext *ctx, arg_bclr *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, gen_bclr); +} + +static bool trans_bclri(DisasContext *ctx, arg_bclri *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, gen_bclr); +} + +static bool trans_binv(DisasContext *ctx, arg_binv *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, gen_binv); +} + +static bool trans_binvi(DisasContext *ctx, arg_binvi *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, gen_binv); +} + +static bool trans_bext(DisasContext *ctx, arg_bext *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, gen_bext); +} + +static bool trans_bexti(DisasContext *ctx, arg_bexti *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, gen_bext); +} + static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); @@ -141,3 +189,52 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a) REQUIRE_EXT(ctx, RVB); return gen_arith(ctx, a, gen_packuw); } + +static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_bset); +} + +static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, gen_bset); +} + +static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_bclr); +} + +static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, gen_bclr); +} + +static bool trans_binvw(DisasContext *ctx, arg_binvw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_binv); +} + +static bool trans_binviw(DisasContext *ctx, arg_binviw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, gen_binv); +} + +static bool trans_bextw(DisasContext *ctx, arg_bextw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_bext); +} -- 2.31.1