[PATCH 0/5] remoteproc: pru: Add remoteproc support for AM65 PRUSS

[PATCH 0/5] remoteproc: pru: Add remoteproc support for AM65 PRUSS

[Lokesh Vutla]

This series adds support for remoteproc driver for PRUSS in AM65 SoCs.

Keerthy (2):
  soc: ti: pruss: Add a platform driver for PRUSS in TI SoCs
  remoteproc: pru: Add support for various PRU cores on K3 AM65x SoCs

Lokesh Vutla (3):
  arm: dts: k3-am654-base-board: Add r5 specific u-boot dtsi
  arm: dts: ti: k3-am65-main: Add ICSSG nodes
  configs: am65x_evm_a53: Enable PRUSS remoteproc

 arch/arm/dts/k3-am65-main.dtsi                | 463 ++++++++++++++++++
 arch/arm/dts/k3-am654-base-board-u-boot.dtsi  | 191 ++------
 .../dts/k3-am654-r5-base-board-u-boot.dtsi    | 193 ++++++++
 arch/arm/dts/k3-am654-r5-base-board.dts       |   2 -
 configs/am65x_evm_a53_defconfig               |   2 +
 drivers/remoteproc/Kconfig                    |  11 +
 drivers/remoteproc/Makefile                   |   1 +
 drivers/remoteproc/pru_rproc.c                | 461 +++++++++++++++++
 drivers/soc/ti/Kconfig                        |  11 +
 drivers/soc/ti/Makefile                       |   1 +
 drivers/soc/ti/pruss.c                        | 217 ++++++++
 include/linux/pruss_driver.h                  | 227 +++++++++
 12 files changed, 1625 insertions(+), 155 deletions(-)
 create mode 100644 arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
 create mode 100644 drivers/remoteproc/pru_rproc.c
 create mode 100644 drivers/soc/ti/pruss.c
 create mode 100644 include/linux/pruss_driver.h

-- 
2.31.1

[PATCH 1/5] soc: ti: pruss: Add a platform driver for PRUSS in TI SoCs

[Lokesh Vutla]

From: Keerthy <j-keerthy@ti.com>

The Programmable Real-Time Unit - Industrial Communication
Subsystem (PRU-ICSS) is present of various TI SoCs such as
AM335x or AM437x or the AM654x family. Each SoC can have
one or more PRUSS instances that may or may not be identical.

The PRUSS consists of dual 32-bit RISC cores called the
Programmable Real-Time Units (PRUs), some shared, data and
instruction memories, some internal peripheral modules, and
an interrupt controller. The programmable nature of the PRUs
provide flexibility to implement custom peripheral interfaces,
fast real-time responses, or specialized data handling.

Add support for pruss driver. Currently am654x family
is supported.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 drivers/soc/ti/Kconfig       |  11 ++
 drivers/soc/ti/Makefile      |   1 +
 drivers/soc/ti/pruss.c       | 217 +++++++++++++++++++++++++++++++++
 include/linux/pruss_driver.h | 227 +++++++++++++++++++++++++++++++++++
 4 files changed, 456 insertions(+)
 create mode 100644 drivers/soc/ti/pruss.c
 create mode 100644 include/linux/pruss_driver.h

diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig
index e4f8834448..0ee21f9904 100644
--- a/drivers/soc/ti/Kconfig
+++ b/drivers/soc/ti/Kconfig
@@ -23,4 +23,15 @@ config TI_KEYSTONE_SERDES
 	 SerDes driver for Keystone SoC used for ethernet support on TI
 	 K2 platforms.
 
+config TI_PRUSS
+	bool "Support for TI's K3 based Pruss driver"
+	depends on DM
+	depends on ARCH_K3
+	depends on OF_CONTROL
+	depends on SYSCON
+	help
+	  Support for TI PRU-ICSSG subsystem.
+	  Currently supported on AM65xx SoCs Say Y here to support the
+	  Programmable Realtime Unit (PRU).
+
 endif # SOC_TI
diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile
index 4ec04ee125..34f80aad29 100644
--- a/drivers/soc/ti/Makefile
+++ b/drivers/soc/ti/Makefile
@@ -2,3 +2,4 @@
 
 obj-$(CONFIG_TI_K3_NAVSS_RINGACC)	+= k3-navss-ringacc.o
 obj-$(CONFIG_TI_KEYSTONE_SERDES)	+= keystone_serdes.o
+obj-$(CONFIG_TI_PRUSS)	+= pruss.o
diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c
new file mode 100644
index 0000000000..461390925d
--- /dev/null
+++ b/drivers/soc/ti/pruss.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PRU-ICSS platform driver for various TI SoCs
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/of_access.h>
+#include <errno.h>
+#include <clk.h>
+#include <reset.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <power-domain.h>
+#include <linux/pruss_driver.h>
+#include <dm/device_compat.h>
+
+#define PRUSS_CFG_IEPCLK	0x30
+#define ICSSG_CFG_CORE_SYNC	0x3c
+
+#define ICSSG_TASK_MGR_OFFSET	0x2a000
+
+/* PRUSS_IEPCLK register bits */
+#define PRUSS_IEPCLK_IEP_OCP_CLK_EN		BIT(0)
+
+/* ICSSG CORE_SYNC register bits */
+#define ICSSG_CORE_VBUSP_SYNC_EN		BIT(0)
+
+/*
+ * pruss_request_tm_region() - Request pruss for task manager region
+ * @dev:	corresponding k3 device
+ * @loc:	the task manager physical address
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+int pruss_request_tm_region(struct udevice *dev, phys_addr_t *loc)
+{
+	struct pruss *priv;
+
+	priv = dev_get_priv(dev);
+	if (!priv || !priv->mem_regions[PRUSS_MEM_DRAM0].pa)
+		return -EINVAL;
+
+	*loc = priv->mem_regions[PRUSS_MEM_DRAM0].pa + ICSSG_TASK_MGR_OFFSET;
+
+	return 0;
+}
+
+/**
+ * pruss_request_mem_region() - request a memory resource
+ * @dev: the pruss device
+ * @mem_id: the memory resource id
+ * @region: pointer to memory region structure to be filled in
+ *
+ * This function allows a client driver to request a memory resource,
+ * and if successful, will let the client driver own the particular
+ * memory region until released using the pruss_release_mem_region()
+ * API.
+ *
+ * Returns the memory region if requested resource is available, an
+ * error otherwise
+ */
+int pruss_request_mem_region(struct udevice *dev, enum pruss_mem mem_id,
+			     struct pruss_mem_region *region)
+{
+	struct pruss *pruss;
+
+	pruss = dev_get_priv(dev);
+	if (!pruss || !region)
+		return -EINVAL;
+
+	if (mem_id >= PRUSS_MEM_MAX)
+		return -EINVAL;
+
+	if (pruss->mem_in_use[mem_id])
+		return -EBUSY;
+
+	*region = pruss->mem_regions[mem_id];
+	pruss->mem_in_use[mem_id] = region;
+
+	return 0;
+}
+
+/**
+ * pruss_release_mem_region() - release a memory resource
+ * @dev: the pruss device
+ * @region: the memory region to release
+ *
+ * This function is the complimentary function to
+ * pruss_request_mem_region(), and allows the client drivers to
+ * release back a memory resource.
+ *
+ * Returns 0 on success, an error code otherwise
+ */
+int pruss_release_mem_region(struct udevice *dev,
+			     struct pruss_mem_region *region)
+{
+	struct pruss *pruss;
+	int id;
+
+	pruss = dev_get_priv(dev);
+	if (!pruss || !region)
+		return -EINVAL;
+
+	/* find out the memory region being released */
+	for (id = 0; id < PRUSS_MEM_MAX; id++) {
+		if (pruss->mem_in_use[id] == region)
+			break;
+	}
+
+	if (id == PRUSS_MEM_MAX)
+		return -EINVAL;
+
+	pruss->mem_in_use[id] = NULL;
+
+	return 0;
+}
+
+/**
+ * pruss_cfg_update() - configure a PRUSS CFG sub-module register
+ * @dev: the pruss device
+ * @reg: register offset within the CFG sub-module
+ * @mask: bit mask to use for programming the @val
+ * @val: value to write
+ *
+ * Programs a given register within the PRUSS CFG sub-module
+ *
+ * Returns 0 on success, or an error code otherwise
+ */
+int pruss_cfg_update(struct udevice *dev, unsigned int reg,
+		     unsigned int mask, unsigned int val)
+{
+	struct pruss *pruss;
+
+	pruss = dev_get_priv(dev);
+	if (IS_ERR_OR_NULL(pruss))
+		return -EINVAL;
+
+	return regmap_update_bits(pruss->cfg, reg, mask, val);
+}
+
+/**
+ * pruss_probe() - Basic probe
+ * @dev:	corresponding k3 device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int pruss_probe(struct udevice *dev)
+{
+	const char *mem_names[PRUSS_MEM_MAX] = { "dram0", "dram1", "shrdram2" };
+	ofnode sub_node, node, memories;
+	struct udevice *syscon;
+	struct pruss *priv;
+	int ret, idx, i;
+
+	priv = dev_get_priv(dev);
+	node = dev_ofnode(dev);
+	priv->dev = dev;
+	memories = ofnode_find_subnode(node, "memories");
+
+	for (i = 0; i < ARRAY_SIZE(mem_names); i++) {
+		idx = ofnode_stringlist_search(memories, "reg-names", mem_names[i]);
+		priv->mem_regions[i].pa = ofnode_get_addr_size_index(memories, idx,
+						       (u64 *)&priv->mem_regions[i].size);
+	}
+
+	sub_node = ofnode_find_subnode(node, "cfg");
+	ret = uclass_get_device_by_ofnode(UCLASS_SYSCON, sub_node,
+					  &syscon);
+
+	priv->cfg = syscon_get_regmap(syscon);
+	if (IS_ERR(priv->cfg)) {
+		dev_err(dev, "unable to get cfg regmap (%ld)\n",
+			PTR_ERR(priv->cfg));
+		return -ENODEV;
+	}
+
+	/*
+	 * ToDo: To be modelled as clocks.
+	 * The CORE block uses two multiplexers to allow software to
+	 * select one of three source clocks (ICSSGn_CORE_CLK, ICSSGn_ICLK or
+	 * ICSSGn_IEP_CLK) for the final clock source of the CORE block.
+	 * The user needs to configure ICSSG_CORE_SYNC_REG[0] CORE_VBUSP_SYNC_EN
+	 * bit & ICSSG_IEPCLK_REG[0] IEP_OCP_CLK_EN bit in order to select the
+	 * clock source to the CORE block.
+	 */
+	ret = regmap_update_bits(priv->cfg, ICSSG_CFG_CORE_SYNC,
+				 ICSSG_CORE_VBUSP_SYNC_EN,
+				 ICSSG_CORE_VBUSP_SYNC_EN);
+	if (ret)
+		return ret;
+	ret = regmap_update_bits(priv->cfg, PRUSS_CFG_IEPCLK,
+				 PRUSS_IEPCLK_IEP_OCP_CLK_EN,
+				 PRUSS_IEPCLK_IEP_OCP_CLK_EN);
+	if (ret)
+		return ret;
+
+	dev_dbg(dev, "pruss successfully probed %s\n", dev->name);
+
+	return 0;
+}
+
+static const struct udevice_id pruss_ids[] = {
+	{ .compatible = "ti,am654-icssg"},
+	{}
+};
+
+U_BOOT_DRIVER(pruss) = {
+	.name = "pruss",
+	.of_match = pruss_ids,
+	.id = UCLASS_MISC,
+	.probe = pruss_probe,
+	.priv_auto = sizeof(struct pruss),
+};
diff --git a/include/linux/pruss_driver.h b/include/linux/pruss_driver.h
new file mode 100644
index 0000000000..1408111118
--- /dev/null
+++ b/include/linux/pruss_driver.h
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#ifndef __TI_PRUSS_H
+#define __TI_PRUSS_H
+
+/*
+ * PRU_ICSS_CFG registers
+ * SYSCFG, ISRP, ISP, IESP, IECP, SCRP applicable on AMxxxx devices only
+ */
+#define PRUSS_CFG_REVID		0x00
+#define PRUSS_CFG_SYSCFG	0x04
+#define PRUSS_CFG_GPCFG(x)	(0x08 + (x) * 4)
+#define PRUSS_CFG_CGR		0x10
+#define PRUSS_CFG_ISRP		0x14
+#define PRUSS_CFG_ISP		0x18
+#define PRUSS_CFG_IESP		0x1C
+#define PRUSS_CFG_IECP		0x20
+#define PRUSS_CFG_SCRP		0x24
+#define PRUSS_CFG_PMAO		0x28
+#define PRUSS_CFG_MII_RT	0x2C
+#define PRUSS_CFG_IEPCLK	0x30
+#define PRUSS_CFG_SPP		0x34
+#define PRUSS_CFG_PIN_MX	0x40
+
+/* PRUSS_GPCFG register bits */
+#define PRUSS_GPCFG_PRU_GPO_SH_SEL		BIT(25)
+
+#define PRUSS_GPCFG_PRU_DIV1_SHIFT		20
+#define PRUSS_GPCFG_PRU_DIV1_MASK		GENMASK(24, 20)
+
+#define PRUSS_GPCFG_PRU_DIV0_SHIFT		15
+#define PRUSS_GPCFG_PRU_DIV0_MASK		GENMASK(15, 19)
+
+#define PRUSS_GPCFG_PRU_GPO_MODE		BIT(14)
+#define PRUSS_GPCFG_PRU_GPO_MODE_DIRECT		0
+#define PRUSS_GPCFG_PRU_GPO_MODE_SERIAL		BIT(14)
+
+#define PRUSS_GPCFG_PRU_GPI_SB			BIT(13)
+
+#define PRUSS_GPCFG_PRU_GPI_DIV1_SHIFT		8
+#define PRUSS_GPCFG_PRU_GPI_DIV1_MASK		GENMASK(12, 8)
+
+#define PRUSS_GPCFG_PRU_GPI_DIV0_SHIFT		3
+#define PRUSS_GPCFG_PRU_GPI_DIV0_MASK		GENMASK(7, 3)
+
+#define PRUSS_GPCFG_PRU_GPI_CLK_MODE_POSITIVE	0
+#define PRUSS_GPCFG_PRU_GPI_CLK_MODE_NEGATIVE	BIT(2)
+#define PRUSS_GPCFG_PRU_GPI_CLK_MODE		BIT(2)
+
+#define PRUSS_GPCFG_PRU_GPI_MODE_MASK		GENMASK(1, 0)
+#define PRUSS_GPCFG_PRU_GPI_MODE_SHIFT		0
+
+#define PRUSS_GPCFG_PRU_MUX_SEL_SHIFT		26
+#define PRUSS_GPCFG_PRU_MUX_SEL_MASK		GENMASK(29, 26)
+
+/* PRUSS_MII_RT register bits */
+#define PRUSS_MII_RT_EVENT_EN			BIT(0)
+
+/* PRUSS_SPP register bits */
+#define PRUSS_SPP_PRU1_PAD_HP_EN		BIT(0)
+#define PRUSS_SPP_XFER_SHIFT_EN			BIT(1)
+#define PRUSS_SPP_XFR_BYTE_SHIFT_EN		BIT(2)
+#define PRUSS_SPP_RTU_XFR_SHIFT_EN		BIT(3)
+
+/**
+ * enum pruss_gp_mux_sel - PRUSS GPI/O Mux modes for the
+ * PRUSS_GPCFG0/1 registers
+ *
+ * NOTE: The below defines are the most common values, but there
+ * are some exceptions like on 66AK2G, where the RESERVED and MII2
+ * values are interchanged. Also, this bit-field does not exist on
+ * AM335x SoCs
+ */
+enum pruss_gp_mux_sel {
+	PRUSS_GP_MUX_SEL_GP = 0,
+	PRUSS_GP_MUX_SEL_ENDAT,
+	PRUSS_GP_MUX_SEL_RESERVED,
+	PRUSS_GP_MUX_SEL_SD,
+	PRUSS_GP_MUX_SEL_MII2,
+	PRUSS_GP_MUX_SEL_MAX,
+};
+
+/**
+ * enum pruss_gpi_mode - PRUSS GPI configuration modes, used
+ *			 to program the PRUSS_GPCFG0/1 registers
+ */
+enum pruss_gpi_mode {
+	PRUSS_GPI_MODE_DIRECT = 0,
+	PRUSS_GPI_MODE_PARALLEL,
+	PRUSS_GPI_MODE_28BIT_SHIFT,
+	PRUSS_GPI_MODE_MII,
+};
+
+/**
+ * enum pruss_pru_id - PRU core identifiers
+ */
+enum pruss_pru_id {
+	PRUSS_PRU0 = 0,
+	PRUSS_PRU1,
+	PRUSS_NUM_PRUS,
+};
+
+/**
+ * enum pru_ctable_idx - Configurable Constant table index identifiers
+ */
+enum pru_ctable_idx {
+	PRU_C24 = 0,
+	PRU_C25,
+	PRU_C26,
+	PRU_C27,
+	PRU_C28,
+	PRU_C29,
+	PRU_C30,
+	PRU_C31,
+};
+
+/**
+ * enum pruss_mem - PRUSS memory range identifiers
+ */
+enum pruss_mem {
+	PRUSS_MEM_DRAM0 = 0,
+	PRUSS_MEM_DRAM1,
+	PRUSS_MEM_SHRD_RAM2,
+	PRUSS_MEM_MAX,
+};
+
+/**
+ * struct pruss_mem_region - PRUSS memory region structure
+ * @va: kernel virtual address of the PRUSS memory region
+ * @pa: physical (bus) address of the PRUSS memory region
+ * @size: size of the PRUSS memory region
+ */
+struct pruss_mem_region {
+	void __iomem *va;
+	phys_addr_t pa;
+	size_t size;
+};
+
+/**
+ * struct pruss - PRUSS parent structure
+ * @dev: pruss device pointer
+ * @cfg: regmap for config region
+ * @mem_regions: data for each of the PRUSS memory regions
+ * @mem_in_use: to indicate if memory resource is in use
+ */
+struct pruss {
+	struct udevice *dev;
+	struct regmap *cfg;
+	struct pruss_mem_region mem_regions[PRUSS_MEM_MAX];
+	struct pruss_mem_region *mem_in_use[PRUSS_MEM_MAX];
+};
+
+int pruss_request_tm_region(struct udevice *dev, phys_addr_t *loc);
+int pruss_request_mem_region(struct udevice *dev, enum pruss_mem mem_id,
+			     struct pruss_mem_region *region);
+int pruss_release_mem_region(struct udevice *dev, struct pruss_mem_region *region);
+int pruss_cfg_update(struct udevice *dev, unsigned int reg,
+		     unsigned int mask, unsigned int val);
+
+/**
+ * pruss_cfg_gpimode() - set the GPI mode of the PRU
+ * @dev: the pruss device
+ * @pru_id: the rproc instance handle of the PRU
+ * @mode: GPI mode to set
+ *
+ * Sets the GPI mode for a given PRU by programming the
+ * corresponding PRUSS_CFG_GPCFGx register
+ *
+ * Returns 0 on success, or an error code otherwise
+ */
+static inline int pruss_cfg_gpimode(struct udevice *dev, enum pruss_pru_id id,
+				    enum pruss_gpi_mode mode)
+{
+	if (id < 0)
+		return -EINVAL;
+
+	return pruss_cfg_update(dev, PRUSS_CFG_GPCFG(id),
+				PRUSS_GPCFG_PRU_GPI_MODE_MASK,
+				mode << PRUSS_GPCFG_PRU_GPI_MODE_SHIFT);
+}
+
+/**
+ * pruss_cfg_miirt_enable() - Enable/disable MII RT Events
+ * @dev: the pruss device
+ * @enable: enable/disable
+ *
+ * Enable/disable the MII RT Events for the PRUSS.
+ */
+static inline int pruss_cfg_miirt_enable(struct udevice *dev, bool enable)
+{
+	u32 set = enable ? PRUSS_MII_RT_EVENT_EN : 0;
+
+	return pruss_cfg_update(dev, PRUSS_CFG_MII_RT,
+				PRUSS_MII_RT_EVENT_EN, set);
+}
+
+/**
+ * pruss_cfg_xfr_enable() - Enable/disable XIN XOUT shift functionality
+ * @dev: the pruss device
+ * @enable: enable/disable
+ */
+static inline int pruss_cfg_xfr_enable(struct udevice *dev, bool enable)
+{
+	u32 set = enable ? PRUSS_SPP_XFER_SHIFT_EN : 0;
+
+	return pruss_cfg_update(dev, PRUSS_CFG_SPP,
+			PRUSS_SPP_XFER_SHIFT_EN, set);
+}
+
+/**
+ * pruss_cfg_set_gpmux() - set the GPMUX value for a PRU device
+ * @pruss: pruss device
+ * @pru_id: PRU identifier (0-1)
+ * @mux: new mux value for PRU
+ */
+static inline int pruss_cfg_set_gpmux(struct udevice *dev,
+				      enum pruss_pru_id id, u8 mux)
+{
+	if (mux >= PRUSS_GP_MUX_SEL_MAX)
+		return -EINVAL;
+
+	return pruss_cfg_update(dev, PRUSS_CFG_GPCFG(id),
+			PRUSS_GPCFG_PRU_MUX_SEL_MASK,
+			(u32)mux << PRUSS_GPCFG_PRU_MUX_SEL_SHIFT);
+}
+
+#endif /* __TI_PRUSS_H */
-- 
2.31.1

[PATCH 2/5] remoteproc: pru: Add support for various PRU cores on K3 AM65x SoCs

[Lokesh Vutla]

From: Keerthy <j-keerthy@ti.com>

The K3 AM65x family of SoCs have the next generation of the PRU-ICSS
processor subsystem, commonly referred to as ICSSG. Each ICSSG processor
subsystem on AM65x SR1.0 contains two primary PRU cores and two new
auxiliary PRU cores called RTUs. The AM65x SR2.0 SoCs have a revised
ICSSG IP that is based off the subsequent IP revision used on J721E
SoCs. This IP instance has two new custom auxiliary PRU cores called
Transmit PRUs (Tx_PRUs) in addition to the existing PRUs and RTUs.

Each RTU and Tx_PRU cores have their own dedicated IRAM (smaller than
a PRU), Control and debug feature sets, but is different in terms of
sub-modules integrated around it and does not have the full capabilities
associated with a PRU core. The RTU core is typically used to aid a
PRU core in accelerating data transfers, while the Tx_PRU cores is
normally used to control the TX L2 FIFO if enabled in Ethernet
applications. Both can also be used to run independent applications.
The RTU and Tx_PRU cores though share the same Data RAMs as the PRU
cores, so the memories have to be partitioned carefully between different
applications. The new cores also support a new sub-module called Task
Manager to support two different context thread executions.
The driver currently supports the AM65xx SoC

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 drivers/remoteproc/Kconfig     |  11 +
 drivers/remoteproc/Makefile    |   1 +
 drivers/remoteproc/pru_rproc.c | 461 +++++++++++++++++++++++++++++++++
 3 files changed, 473 insertions(+)
 create mode 100644 drivers/remoteproc/pru_rproc.c

diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 7c2e4804b5..24e536463b 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -81,4 +81,15 @@ config REMOTEPROC_TI_POWER
 	help
 	  Say 'y' here to add support for TI power processors such as those
 	  found on certain TI keystone and OMAP generation SoCs.
+
+config REMOTEPROC_TI_PRU
+	bool "Support for TI's K3 based PRU remoteproc driver"
+	select REMOTEPROC
+	depends on DM
+	depends on TI_PRUSS
+	depends on ARCH_K3
+	depends on OF_CONTROL
+	help
+	  Say 'y' here to add support for TI' K3 remoteproc driver.
+
 endmenu
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 69ae7bd1e8..f0e83451d6 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o
 obj-$(CONFIG_REMOTEPROC_TI_K3_DSP) += ti_k3_dsp_rproc.o
 obj-$(CONFIG_REMOTEPROC_TI_K3_R5F) += ti_k3_r5f_rproc.o
 obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o
+obj-$(CONFIG_REMOTEPROC_TI_PRU) += pru_rproc.o
diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
new file mode 100644
index 0000000000..924070a76b
--- /dev/null
+++ b/drivers/remoteproc/pru_rproc.c
@@ -0,0 +1,461 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PRU-RTU remoteproc driver for various SoCs
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Keerthy <j-keerthy@ti.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <elf.h>
+#include <dm/of_access.h>
+#include <remoteproc.h>
+#include <errno.h>
+#include <clk.h>
+#include <reset.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <power-domain.h>
+#include <linux/pruss_driver.h>
+#include <dm/device_compat.h>
+
+/* PRU_ICSS_PRU_CTRL registers */
+#define PRU_CTRL_CTRL		0x0000
+#define PRU_CTRL_STS		0x0004
+#define PRU_CTRL_WAKEUP_EN	0x0008
+#define PRU_CTRL_CYCLE		0x000C
+#define PRU_CTRL_STALL		0x0010
+#define PRU_CTRL_CTBIR0		0x0020
+#define PRU_CTRL_CTBIR1		0x0024
+#define PRU_CTRL_CTPPR0		0x0028
+#define PRU_CTRL_CTPPR1		0x002C
+
+/* CTRL register bit-fields */
+#define CTRL_CTRL_SOFT_RST_N	BIT(0)
+#define CTRL_CTRL_EN		BIT(1)
+#define CTRL_CTRL_SLEEPING	BIT(2)
+#define CTRL_CTRL_CTR_EN	BIT(3)
+#define CTRL_CTRL_SINGLE_STEP	BIT(8)
+#define CTRL_CTRL_RUNSTATE	BIT(15)
+
+#define RPROC_FLAGS_SHIFT	16
+#define RPROC_FLAGS_NONE	0
+#define RPROC_FLAGS_ELF_PHDR	BIT(0 + RPROC_FLAGS_SHIFT)
+#define RPROC_FLAGS_ELF_SHDR	BIT(1 + RPROC_FLAGS_SHIFT)
+
+/**
+ * enum pru_mem - PRU core memory range identifiers
+ */
+enum pru_mem {
+	PRU_MEM_IRAM = 0,
+	PRU_MEM_CTRL,
+	PRU_MEM_DEBUG,
+	PRU_MEM_MAX,
+};
+
+struct pru_privdata {
+	phys_addr_t pru_iram;
+	phys_addr_t pru_ctrl;
+	phys_addr_t pru_debug;
+	fdt_size_t pru_iramsz;
+	fdt_size_t pru_ctrlsz;
+	fdt_size_t pru_debugsz;
+	const char *fw_name;
+	u32 iram_da;
+	u32 pdram_da;
+	u32 sdram_da;
+	u32 shrdram_da;
+	u32 bootaddr;
+	int id;
+	struct pruss *prusspriv;
+};
+
+static inline u32 pru_control_read_reg(struct pru_privdata *pru, unsigned int reg)
+{
+	return readl(pru->pru_ctrl + reg);
+}
+
+static inline
+void pru_control_write_reg(struct pru_privdata *pru, unsigned int reg, u32 val)
+{
+	writel(val, pru->pru_ctrl + reg);
+}
+
+static inline
+void pru_control_set_reg(struct pru_privdata *pru, unsigned int reg,
+			 u32 mask, u32 set)
+{
+	u32 val;
+
+	val = pru_control_read_reg(pru, reg);
+	val &= ~mask;
+	val |= (set & mask);
+	pru_control_write_reg(pru, reg, val);
+}
+
+/**
+ * pru_rproc_set_ctable() - set the constant table index for the PRU
+ * @rproc: the rproc instance of the PRU
+ * @c: constant table index to set
+ * @addr: physical address to set it to
+ */
+static int pru_rproc_set_ctable(struct pru_privdata *pru, enum pru_ctable_idx c, u32 addr)
+{
+	unsigned int reg;
+	u32 mask, set;
+	u16 idx;
+	u16 idx_mask;
+
+	/* pointer is 16 bit and index is 8-bit so mask out the rest */
+	idx_mask = (c >= PRU_C28) ? 0xFFFF : 0xFF;
+
+	/* ctable uses bit 8 and upwards only */
+	idx = (addr >> 8) & idx_mask;
+
+	/* configurable ctable (i.e. C24) starts at PRU_CTRL_CTBIR0 */
+	reg = PRU_CTRL_CTBIR0 + 4 * (c >> 1);
+	mask = idx_mask << (16 * (c & 1));
+	set = idx << (16 * (c & 1));
+
+	pru_control_set_reg(pru, reg, mask, set);
+
+	return 0;
+}
+
+/**
+ * pru_start() - start the pru processor
+ * @dev:	corresponding k3 remote processor device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int pru_start(struct udevice *dev)
+{
+	struct pru_privdata *priv;
+	int val = 0;
+
+	priv = dev_get_priv(dev);
+
+	pru_rproc_set_ctable(priv, PRU_C28, 0x100 << 8);
+
+	val = CTRL_CTRL_EN | ((priv->bootaddr >> 2) << 16);
+	writel(val, priv->pru_ctrl + PRU_CTRL_CTRL);
+
+	return 0;
+}
+
+/**
+ * pru_stop() - Stop pru processor
+ * @dev:	corresponding k3 remote processor device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int pru_stop(struct udevice *dev)
+{
+	struct pru_privdata *priv;
+	int val = 0;
+
+	priv = dev_get_priv(dev);
+
+	val = readl(priv->pru_ctrl + PRU_CTRL_CTRL);
+	val &= ~CTRL_CTRL_EN;
+	writel(val, priv->pru_ctrl + PRU_CTRL_CTRL);
+
+	return 0;
+}
+
+/**
+ * pru_init() - Initialize the remote processor
+ * @dev:	rproc device pointer
+ *
+ * Return: 0 if all went ok, else return appropriate error
+ */
+static int pru_init(struct udevice *dev)
+{
+	return 0;
+}
+
+/*
+ * Convert PRU device address (data spaces only) to kernel virtual address
+ *
+ * Each PRU has access to all data memories within the PRUSS, accessible at
+ * different ranges. So, look through both its primary and secondary Data
+ * RAMs as well as any shared Data RAM to convert a PRU device address to
+ * kernel virtual address. Data RAM0 is primary Data RAM for PRU0 and Data
+ * RAM1 is primary Data RAM for PRU1.
+ */
+static void *pru_d_da_to_pa(struct pru_privdata *priv, u32 da, int len)
+{
+	u32 offset;
+	void *pa = NULL;
+	phys_addr_t dram0, dram1, shrdram2;
+	u32 dram0sz, dram1sz, shrdram2sz;
+
+	if (len <= 0)
+		return NULL;
+
+	dram0 = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM0].pa;
+	dram1 = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].pa;
+	shrdram2 = priv->prusspriv->mem_regions[PRUSS_MEM_SHRD_RAM2].pa;
+	dram0sz = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM0].size;
+	dram1sz = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].size;
+	shrdram2sz = priv->prusspriv->mem_regions[PRUSS_MEM_SHRD_RAM2].size;
+
+	/* PRU1 has its local RAM addresses reversed */
+	if (priv->id == 1) {
+		dram1 = dram0;
+		dram1sz = dram0sz;
+
+		dram0 =  priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].pa;
+		dram0sz = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].size;
+	}
+
+	if (da >= priv->pdram_da && da + len <= priv->pdram_da + dram0sz) {
+		offset = da - priv->pdram_da;
+		pa = (__force void *)(dram0 + offset);
+	} else if (da >= priv->sdram_da &&
+		   da + len <= priv->sdram_da + dram1sz) {
+		offset = da - priv->sdram_da;
+		pa = (__force void *)(dram1 + offset);
+	} else if (da >= priv->shrdram_da &&
+		   da + len <= priv->shrdram_da + shrdram2sz) {
+		offset = da - priv->shrdram_da;
+		pa = (__force void *)(shrdram2 + offset);
+	}
+
+	return pa;
+}
+
+/*
+ * Convert PRU device address (instruction space) to kernel virtual address
+ *
+ * A PRU does not have an unified address space. Each PRU has its very own
+ * private Instruction RAM, and its device address is identical to that of
+ * its primary Data RAM device address.
+ */
+static void *pru_i_da_to_pa(struct pru_privdata *priv, u32 da, int len)
+{
+	u32 offset;
+	void *pa = NULL;
+
+	if (len <= 0)
+		return NULL;
+
+	if (da >= priv->iram_da &&
+	    da + len <= priv->iram_da + priv->pru_iramsz) {
+		offset = da - priv->iram_da;
+		pa = (__force void *)(priv->pru_iram + offset);
+	}
+
+	return pa;
+}
+
+/* PRU-specific address translator */
+static void *pru_da_to_pa(struct pru_privdata *priv, u64 da, int len, u32 flags)
+{
+	void *pa;
+	u32 exec_flag;
+
+	exec_flag = ((flags & RPROC_FLAGS_ELF_SHDR) ? flags & SHF_EXECINSTR :
+		     ((flags & RPROC_FLAGS_ELF_PHDR) ? flags & PF_X : 0));
+
+	if (exec_flag)
+		pa = pru_i_da_to_pa(priv, da, len);
+	else
+		pa = pru_d_da_to_pa(priv, da, len);
+
+	return pa;
+}
+
+/*
+ * Custom memory copy implementation for ICSSG PRU/RTU Cores
+ *
+ * The ICSSG PRU/RTU cores have a memory copying issue with IRAM memories, that
+ * is not seen on previous generation SoCs. The data is reflected properly in
+ * the IRAM memories only for integer (4-byte) copies. Any unaligned copies
+ * result in all the other pre-existing bytes zeroed out within that 4-byte
+ * boundary, thereby resulting in wrong text/code in the IRAMs. Also, the
+ * IRAM memory port interface does not allow any 8-byte copies (as commonly
+ * used by ARM64 memcpy implementation) and throws an exception. The DRAM
+ * memory ports do not show this behavior. Use this custom copying function
+ * to properly load the PRU/RTU firmware images on all memories for simplicity.
+ *
+ * TODO: Improve the function to deal with additional corner cases like
+ * unaligned copy sizes or sub-integer trailing bytes when the need arises.
+ */
+static int pru_rproc_memcpy(void *dest, void *src, size_t count)
+{
+	const int *s = src;
+	int *d = dest;
+	int size = count / 4;
+	int *tmp_src = NULL;
+
+	/* limited to 4-byte aligned addresses and copy sizes */
+	if ((long)dest % 4 || count % 4)
+		return -EINVAL;
+
+	/* src offsets in ELF firmware image can be non-aligned */
+	if ((long)src % 4) {
+		tmp_src = malloc(count);
+		if (!tmp_src)
+			return -ENOMEM;
+
+		memcpy(tmp_src, src, count);
+		s = tmp_src;
+	}
+
+	while (size--)
+		*d++ = *s++;
+
+	kfree(tmp_src);
+
+	return 0;
+}
+
+/**
+ * pru_load() - Load pru firmware
+ * @dev:	corresponding k3 remote processor device
+ * @addr:	Address on the RAM from which firmware is to be loaded
+ * @size:	Size of the pru firmware in bytes
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int pru_load(struct udevice *dev, ulong addr, ulong size)
+{
+	struct pru_privdata *priv;
+	Elf32_Ehdr *ehdr;
+	Elf32_Phdr *phdr;
+	int i, ret = 0;
+
+	priv = dev_get_priv(dev);
+
+	ehdr = (Elf32_Ehdr *)addr;
+	phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff);
+
+	/* go through the available ELF segments */
+	for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
+		u32 da = phdr->p_paddr;
+		u32 memsz = phdr->p_memsz;
+		u32 filesz = phdr->p_filesz;
+		u32 offset = phdr->p_offset;
+		void *ptr;
+
+		if (phdr->p_type != PT_LOAD)
+			continue;
+
+		dev_dbg(dev, "phdr: type %d da 0x%x memsz 0x%x filesz 0x%x\n",
+			phdr->p_type, da, memsz, filesz);
+
+		if (filesz > memsz) {
+			dev_dbg(dev, "bad phdr filesz 0x%x memsz 0x%x\n",
+				filesz, memsz);
+			ret = -EINVAL;
+			break;
+		}
+
+		if (offset + filesz > size) {
+			dev_dbg(dev, "truncated fw: need 0x%x avail 0x%zx\n",
+				offset + filesz, size);
+			ret = -EINVAL;
+			break;
+		}
+
+		/* grab the kernel address for this device address */
+		ptr = pru_da_to_pa(priv, da, memsz,
+				   RPROC_FLAGS_ELF_PHDR | phdr->p_flags);
+		if (!ptr) {
+			dev_dbg(dev, "bad phdr da 0x%x mem 0x%x\n", da, memsz);
+			ret = -EINVAL;
+			break;
+		}
+
+		/* skip the memzero logic performed by remoteproc ELF loader */
+		if (!phdr->p_filesz)
+			continue;
+
+		ret = pru_rproc_memcpy(ptr,
+				       (void *)addr + phdr->p_offset, filesz);
+		if (ret) {
+			dev_dbg(dev, "PRU custom memory copy failed for da 0x%x memsz 0x%x\n",
+				da, memsz);
+			break;
+		}
+	}
+
+	priv->bootaddr = ehdr->e_entry;
+
+	return ret;
+}
+
+static const struct dm_rproc_ops pru_ops = {
+	.init = pru_init,
+	.start = pru_start,
+	.stop = pru_stop,
+	.load = pru_load,
+};
+
+static void pru_set_id(struct pru_privdata *priv, struct udevice *dev)
+{
+	u32 mask2 = 0x38000;
+
+	if (device_is_compatible(dev, "ti,am654-rtu"))
+		mask2 = 0x6000;
+
+	if (device_is_compatible(dev, "ti,am654-tx-pru"))
+		mask2 = 0xc000;
+
+	if ((priv->pru_iram & mask2) == mask2)
+		priv->id = 1;
+	else
+		priv->id = 0;
+}
+
+/**
+ * pru_probe() - Basic probe
+ * @dev:	corresponding k3 remote processor device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static int pru_probe(struct udevice *dev)
+{
+	struct pru_privdata *priv;
+	ofnode node;
+
+	node = dev_ofnode(dev);
+
+	priv = dev_get_priv(dev);
+	priv->prusspriv = dev_get_priv(dev->parent);
+
+	priv->pru_iram = devfdt_get_addr_size_index(dev, PRU_MEM_IRAM,
+						    &priv->pru_iramsz);
+	priv->pru_ctrl = devfdt_get_addr_size_index(dev, PRU_MEM_CTRL,
+						    &priv->pru_ctrlsz);
+	priv->pru_debug = devfdt_get_addr_size_index(dev, PRU_MEM_DEBUG,
+						     &priv->pru_debugsz);
+
+	priv->iram_da = 0;
+	priv->pdram_da = 0;
+	priv->sdram_da = 0x2000;
+	priv->shrdram_da = 0x10000;
+
+	pru_set_id(priv, dev);
+
+	return 0;
+}
+
+static const struct udevice_id pru_ids[] = {
+	{ .compatible = "ti,am654-pru"},
+	{ .compatible = "ti,am654-rtu"},
+	{ .compatible = "ti,am654-tx-pru" },
+	{}
+};
+
+U_BOOT_DRIVER(pru) = {
+	.name = "pru",
+	.of_match = pru_ids,
+	.id = UCLASS_REMOTEPROC,
+	.ops = &pru_ops,
+	.probe = pru_probe,
+	.priv_auto = sizeof(struct pru_privdata),
+};
-- 
2.31.1

[PATCH 3/5] arm: dts: k3-am654-base-board: Add r5 specific u-boot dtsi

[Lokesh Vutla]

So far all the u-boot specific properties for both r5 and a53 are
placed in k3-am654-base-board-u-boot.dtsi. But there are few a53
nodes that should be updated but doesn't belong to r5. So create a
separate r5 specific u-boot dtsi.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/dts/k3-am654-base-board-u-boot.dtsi  | 191 +----------------
 .../dts/k3-am654-r5-base-board-u-boot.dtsi    | 193 ++++++++++++++++++
 arch/arm/dts/k3-am654-r5-base-board.dts       |   2 -
 3 files changed, 195 insertions(+), 191 deletions(-)
 create mode 100644 arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi

diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index b0602d1dad..77b7d3f452 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -1,193 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - http://www.ti.com/
  */
 
-#include <dt-bindings/pinctrl/k3.h>
-#include <dt-bindings/net/ti-dp83867.h>
-
-/ {
-	chosen {
-		stdout-path = "serial2:115200n8";
-	};
-
-	aliases {
-		serial2 = &main_uart0;
-		ethernet0 = &cpsw_port1;
-		usb0 = &usb0;
-		usb1 = &usb1;
-		spi0 = &ospi0;
-		spi1 = &ospi1;
-	};
-};
-
-&cbass_main{
-	u-boot,dm-spl;
-	main-navss {
-		u-boot,dm-spl;
-	};
-};
-
-&cbass_mcu {
-	u-boot,dm-spl;
-
-	mcu-navss {
-		u-boot,dm-spl;
-
-		ringacc@2b800000 {
-			u-boot,dm-spl;
-			ti,dma-ring-reset-quirk;
-		};
-
-		dma-controller@285c0000 {
-			u-boot,dm-spl;
-		};
-	};
-};
-
-&cbass_wakeup {
-	u-boot,dm-spl;
-
-	chipid@43000014 {
-		u-boot,dm-spl;
-	};
-};
-
-&secure_proxy_main {
-	u-boot,dm-spl;
-};
-
-&dmsc {
-	u-boot,dm-spl;
-	k3_sysreset: sysreset-controller {
-		compatible = "ti,sci-sysreset";
-		u-boot,dm-spl;
-	};
-};
-
-&k3_pds {
-	u-boot,dm-spl;
-};
-
-&k3_clks {
-	u-boot,dm-spl;
-};
-
-&k3_reset {
-	u-boot,dm-spl;
-};
-
-&wkup_pmx0 {
-	u-boot,dm-spl;
-
-	wkup_i2c0_pins_default {
-		u-boot,dm-spl;
-	};
-};
-
-&main_pmx0 {
-	u-boot,dm-spl;
-	usb0_pins_default: usb0_pins_default {
-		pinctrl-single,pins = <
-			AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
-		>;
-		u-boot,dm-spl;
-	};
-};
-
-&main_uart0_pins_default {
-	u-boot,dm-spl;
-};
-
-&main_pmx1 {
-	u-boot,dm-spl;
-};
-
-&wkup_pmx0 {
-	mcu-fss0-ospi0-pins-default {
-		u-boot,dm-spl;
-	};
-};
-
-&main_uart0 {
-	u-boot,dm-spl;
-};
-
-&main_mmc0_pins_default {
-	u-boot,dm-spl;
-};
-
-&main_mmc1_pins_default {
-	u-boot,dm-spl;
-};
-
-&sdhci0 {
-	u-boot,dm-spl;
-};
-
-&sdhci1 {
-	u-boot,dm-spl;
-};
-
-&davinci_mdio {
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-		/* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
-		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-	};
-};
-
-&mcu_cpsw {
-	reg = <0x0 0x46000000 0x0 0x200000>,
-	      <0x0 0x40f00200 0x0 0x2>;
-	reg-names = "cpsw_nuss", "mac_efuse";
-	/delete-property/ ranges;
-
-	cpsw-phy-sel@40f04040 {
-		compatible = "ti,am654-cpsw-phy-sel";
-		reg= <0x0 0x40f04040 0x0 0x4>;
-		reg-names = "gmii-sel";
-	};
-};
-
-&wkup_i2c0 {
-	u-boot,dm-spl;
-};
-
-&usb1 {
-	dr_mode = "peripheral";
-};
-
-&fss {
-	u-boot,dm-spl;
-};
-
-&ospi0 {
-	u-boot,dm-spl;
-
-	 flash@0{
-		u-boot,dm-spl;
-	};
-};
-
-&dwc3_0 {
-	status = "okay";
-	u-boot,dm-spl;
-};
-
-&usb0_phy {
-	status = "okay";
-	u-boot,dm-spl;
-};
-
-&usb0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&usb0_pins_default>;
-	dr_mode = "host";
-	u-boot,dm-spl;
-};
-
-&scm_conf {
-	u-boot,dm-spl;
-};
+#include "k3-am654-r5-base-board-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
new file mode 100644
index 0000000000..932a65b906
--- /dev/null
+++ b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+	chosen {
+		stdout-path = "serial2:115200n8";
+	};
+
+	aliases {
+		serial2 = &main_uart0;
+		ethernet0 = &cpsw_port1;
+		usb0 = &usb0;
+		usb1 = &usb1;
+		spi0 = &ospi0;
+		spi1 = &ospi1;
+	};
+};
+
+&cbass_main{
+	u-boot,dm-spl;
+	main-navss {
+		u-boot,dm-spl;
+	};
+};
+
+&cbass_mcu {
+	u-boot,dm-spl;
+
+	mcu-navss {
+		u-boot,dm-spl;
+
+		ringacc@2b800000 {
+			u-boot,dm-spl;
+			ti,dma-ring-reset-quirk;
+		};
+
+		dma-controller@285c0000 {
+			u-boot,dm-spl;
+		};
+	};
+};
+
+&cbass_wakeup {
+	u-boot,dm-spl;
+
+	chipid@43000014 {
+		u-boot,dm-spl;
+	};
+};
+
+&secure_proxy_main {
+	u-boot,dm-spl;
+};
+
+&dmsc {
+	u-boot,dm-spl;
+	k3_sysreset: sysreset-controller {
+		compatible = "ti,sci-sysreset";
+		u-boot,dm-spl;
+	};
+};
+
+&k3_pds {
+	u-boot,dm-spl;
+};
+
+&k3_clks {
+	u-boot,dm-spl;
+};
+
+&k3_reset {
+	u-boot,dm-spl;
+};
+
+&wkup_pmx0 {
+	u-boot,dm-spl;
+
+	wkup_i2c0_pins_default {
+		u-boot,dm-spl;
+	};
+};
+
+&main_pmx0 {
+	u-boot,dm-spl;
+	usb0_pins_default: usb0_pins_default {
+		pinctrl-single,pins = <
+			AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
+		>;
+		u-boot,dm-spl;
+	};
+};
+
+&main_uart0_pins_default {
+	u-boot,dm-spl;
+};
+
+&main_pmx1 {
+	u-boot,dm-spl;
+};
+
+&wkup_pmx0 {
+	mcu-fss0-ospi0-pins-default {
+		u-boot,dm-spl;
+	};
+};
+
+&main_uart0 {
+	u-boot,dm-spl;
+};
+
+&main_mmc0_pins_default {
+	u-boot,dm-spl;
+};
+
+&main_mmc1_pins_default {
+	u-boot,dm-spl;
+};
+
+&sdhci0 {
+	u-boot,dm-spl;
+};
+
+&sdhci1 {
+	u-boot,dm-spl;
+};
+
+&davinci_mdio {
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+		/* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+	};
+};
+
+&mcu_cpsw {
+	reg = <0x0 0x46000000 0x0 0x200000>,
+	      <0x0 0x40f00200 0x0 0x2>;
+	reg-names = "cpsw_nuss", "mac_efuse";
+	/delete-property/ ranges;
+
+	cpsw-phy-sel@40f04040 {
+		compatible = "ti,am654-cpsw-phy-sel";
+		reg= <0x0 0x40f04040 0x0 0x4>;
+		reg-names = "gmii-sel";
+	};
+};
+
+&wkup_i2c0 {
+	u-boot,dm-spl;
+};
+
+&usb1 {
+	dr_mode = "peripheral";
+};
+
+&fss {
+	u-boot,dm-spl;
+};
+
+&ospi0 {
+	u-boot,dm-spl;
+
+	 flash@0{
+		u-boot,dm-spl;
+	};
+};
+
+&dwc3_0 {
+	status = "okay";
+	u-boot,dm-spl;
+};
+
+&usb0_phy {
+	status = "okay";
+	u-boot,dm-spl;
+};
+
+&usb0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_pins_default>;
+	dr_mode = "host";
+	u-boot,dm-spl;
+};
+
+&scm_conf {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts
index 087a3bb3d0..24881c86f2 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -330,5 +330,3 @@
 &scm_conf {
 	u-boot,dm-spl;
 };
-
-#include "k3-am654-base-board-u-boot.dtsi"
-- 
2.31.1

[PATCH 4/5] arm: dts: ti: k3-am65-main: Add ICSSG nodes

[Lokesh Vutla]

Add the DT nodes for the ICSSG0, ICSSG1 and ICSSG2 processor subsystems
that are present on the K3 AM65x SoCs. The three ICSSGs are identical
to each other for the most part, with the ICSSG2 supporting slightly
enhanced features for supporting SGMII PRU Ethernet. Each ICSSG instance
is represented by a PRUSS subsystem node. These nodes are enabled by
default.

DT nodes are fetch from Linux 5.13 Kernel.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 arch/arm/dts/k3-am65-main.dtsi               | 463 +++++++++++++++++++
 arch/arm/dts/k3-am654-base-board-u-boot.dtsi |  72 +++
 2 files changed, 535 insertions(+)

diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index cabdba85e0..669484b0dd 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -926,4 +926,467 @@
 		clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
 		clock-names = "tbclk", "fck";
 	};
+
+	icssg0: icssg@b000000 {
+		compatible = "ti,am654-icssg";
+		reg = <0x00 0xb000000 0x00 0x80000>;
+		power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x00 0xb000000 0x80000>;
+
+		icssg0_mem: memories@0 {
+			reg = <0x0 0x2000>,
+			      <0x2000 0x2000>,
+			      <0x10000 0x10000>;
+			reg-names = "dram0", "dram1",
+				    "shrdram2";
+		};
+
+		icssg0_cfg: cfg@26000 {
+			compatible = "ti,pruss-cfg", "syscon";
+			reg = <0x26000 0x200>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x26000 0x2000>;
+
+			clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				icssg0_coreclk_mux: coreclk-mux@3c {
+					reg = <0x3c>;
+					#clock-cells = <0>;
+					clocks = <&k3_clks 62 19>, /* icssg0_core_clk */
+						 <&k3_clks 62 3>;  /* icssg0_iclk */
+					assigned-clocks = <&icssg0_coreclk_mux>;
+					assigned-clock-parents = <&k3_clks 62 3>;
+				};
+
+				icssg0_iepclk_mux: iepclk-mux@30 {
+					reg = <0x30>;
+					#clock-cells = <0>;
+					clocks = <&k3_clks 62 10>,	/* icssg0_iep_clk */
+						 <&icssg0_coreclk_mux>;	/* core_clk */
+					assigned-clocks = <&icssg0_iepclk_mux>;
+					assigned-clock-parents = <&icssg0_coreclk_mux>;
+				};
+			};
+		};
+
+		icssg0_iep0: iep@2e000 {
+			compatible = "ti,am654-icss-iep";
+			reg = <0x2e000 0x1000>;
+			clocks = <&icssg0_iepclk_mux>;
+		};
+
+		icssg0_iep1: iep@2f000 {
+			compatible = "ti,am654-icss-iep";
+			reg = <0x2f000 0x1000>;
+			clocks = <&icssg0_iepclk_mux>;
+		};
+
+		icssg0_mii_rt: mii-rt@32000 {
+			compatible = "ti,pruss-mii", "syscon";
+			reg = <0x32000 0x100>;
+		};
+
+		icssg0_mii_g_rt: mii-g-rt@33000 {
+			compatible = "ti,pruss-mii-g", "syscon";
+			reg = <0x33000 0x1000>;
+		};
+
+		icssg0_intc: interrupt-controller@20000 {
+			compatible = "ti,icssg-intc";
+			reg = <0x20000 0x2000>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "host_intr0", "host_intr1",
+					  "host_intr2", "host_intr3",
+					  "host_intr4", "host_intr5",
+					  "host_intr6", "host_intr7";
+		};
+
+		pru0_0: pru@34000 {
+			compatible = "ti,am654-pru";
+			reg = <0x34000 0x4000>,
+			      <0x22000 0x100>,
+			      <0x22400 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-pru0_0-fw";
+		};
+
+		rtu0_0: rtu@4000 {
+			compatible = "ti,am654-rtu";
+			reg = <0x4000 0x2000>,
+			      <0x23000 0x100>,
+			      <0x23400 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-rtu0_0-fw";
+		};
+
+		tx_pru0_0: txpru@a000 {
+			compatible = "ti,am654-tx-pru";
+			reg = <0xa000 0x1800>,
+			      <0x25000 0x100>,
+			      <0x25400 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-txpru0_0-fw";
+		};
+
+		pru0_1: pru@38000 {
+			compatible = "ti,am654-pru";
+			reg = <0x38000 0x4000>,
+			      <0x24000 0x100>,
+			      <0x24400 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-pru0_1-fw";
+		};
+
+		rtu0_1: rtu@6000 {
+			compatible = "ti,am654-rtu";
+			reg = <0x6000 0x2000>,
+			      <0x23800 0x100>,
+			      <0x23c00 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-rtu0_1-fw";
+		};
+
+		tx_pru0_1: txpru@c000 {
+			compatible = "ti,am654-tx-pru";
+			reg = <0xc000 0x1800>,
+			      <0x25800 0x100>,
+			      <0x25c00 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-txpru0_1-fw";
+		};
+
+		icssg0_mdio: mdio@32400 {
+			compatible = "ti,davinci_mdio";
+			reg = <0x32400 0x100>;
+			clocks = <&k3_clks 62 3>;
+			clock-names = "fck";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			bus_freq = <1000000>;
+			status = "disabled";
+		};
+	};
+
+	icssg1: icssg@b100000 {
+		compatible = "ti,am654-icssg";
+		reg = <0x00 0xb100000 0x00 0x80000>;
+		power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x00 0xb100000 0x80000>;
+
+		icssg1_mem: memories@0 {
+			reg = <0x0 0x2000>,
+			      <0x2000 0x2000>,
+			      <0x10000 0x10000>;
+			reg-names = "dram0", "dram1",
+				    "shrdram2";
+		};
+
+		icssg1_cfg: cfg@26000 {
+			compatible = "ti,pruss-cfg", "syscon";
+			reg = <0x26000 0x200>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x26000 0x2000>;
+
+			clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				icssg1_coreclk_mux: coreclk-mux@3c {
+					reg = <0x3c>;
+					#clock-cells = <0>;
+					clocks = <&k3_clks 63 19>, /* icssg1_core_clk */
+						 <&k3_clks 63 3>;  /* icssg1_iclk */
+					assigned-clocks = <&icssg1_coreclk_mux>;
+					assigned-clock-parents = <&k3_clks 63 3>;
+				};
+
+				icssg1_iepclk_mux: iepclk-mux@30 {
+					reg = <0x30>;
+					#clock-cells = <0>;
+					clocks = <&k3_clks 63 10>,	/* icssg1_iep_clk */
+						 <&icssg1_coreclk_mux>;	/* core_clk */
+					assigned-clocks = <&icssg1_iepclk_mux>;
+					assigned-clock-parents = <&icssg1_coreclk_mux>;
+				};
+			};
+		};
+
+		icssg1_iep0: iep@2e000 {
+			compatible = "ti,am654-icss-iep";
+			reg = <0x2e000 0x1000>;
+			clocks = <&icssg1_iepclk_mux>;
+		};
+
+		icssg1_iep1: iep@2f000 {
+			compatible = "ti,am654-icss-iep";
+			reg = <0x2f000 0x1000>;
+			clocks = <&icssg1_iepclk_mux>;
+		};
+
+		icssg1_mii_rt: mii-rt@32000 {
+			compatible = "ti,pruss-mii", "syscon";
+			reg = <0x32000 0x100>;
+		};
+
+		icssg1_mii_g_rt: mii-g-rt@33000 {
+			compatible = "ti,pruss-mii-g", "syscon";
+			reg = <0x33000 0x1000>;
+		};
+
+		icssg1_intc: interrupt-controller@20000 {
+			compatible = "ti,icssg-intc";
+			reg = <0x20000 0x2000>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "host_intr0", "host_intr1",
+					  "host_intr2", "host_intr3",
+					  "host_intr4", "host_intr5",
+					  "host_intr6", "host_intr7";
+		};
+
+		pru1_0: pru@34000 {
+			compatible = "ti,am654-pru";
+			reg = <0x34000 0x4000>,
+			      <0x22000 0x100>,
+			      <0x22400 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-pru1_0-fw";
+		};
+
+		rtu1_0: rtu@4000 {
+			compatible = "ti,am654-rtu";
+			reg = <0x4000 0x2000>,
+			      <0x23000 0x100>,
+			      <0x23400 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-rtu1_0-fw";
+		};
+
+		tx_pru1_0: txpru@a000 {
+			compatible = "ti,am654-tx-pru";
+			reg = <0xa000 0x1800>,
+			      <0x25000 0x100>,
+			      <0x25400 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-txpru1_0-fw";
+		};
+
+		pru1_1: pru@38000 {
+			compatible = "ti,am654-pru";
+			reg = <0x38000 0x4000>,
+			      <0x24000 0x100>,
+			      <0x24400 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-pru1_1-fw";
+		};
+
+		rtu1_1: rtu@6000 {
+			compatible = "ti,am654-rtu";
+			reg = <0x6000 0x2000>,
+			      <0x23800 0x100>,
+			      <0x23c00 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-rtu1_1-fw";
+		};
+
+		tx_pru1_1: txpru@c000 {
+			compatible = "ti,am654-tx-pru";
+			reg = <0xc000 0x1800>,
+			      <0x25800 0x100>,
+			      <0x25c00 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-txpru1_1-fw";
+		};
+
+		icssg1_mdio: mdio@32400 {
+			compatible = "ti,davinci_mdio";
+			reg = <0x32400 0x100>;
+			clocks = <&k3_clks 63 3>;
+			clock-names = "fck";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			bus_freq = <1000000>;
+			status = "disabled";
+		};
+	};
+
+	icssg2: icssg@b200000 {
+		compatible = "ti,am654-icssg";
+		reg = <0x00 0xb200000 0x00 0x80000>;
+		power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x00 0xb200000 0x80000>;
+
+		icssg2_mem: memories@0 {
+			reg = <0x0 0x2000>,
+			      <0x2000 0x2000>,
+			      <0x10000 0x10000>;
+			reg-names = "dram0", "dram1",
+				    "shrdram2";
+		};
+
+		icssg2_cfg: cfg@26000 {
+			compatible = "ti,pruss-cfg", "syscon";
+			reg = <0x26000 0x200>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x26000 0x2000>;
+
+			clocks {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				icssg2_coreclk_mux: coreclk-mux@3c {
+					reg = <0x3c>;
+					#clock-cells = <0>;
+					clocks = <&k3_clks 64 19>, /* icssg1_core_clk */
+						 <&k3_clks 64 3>;  /* icssg1_iclk */
+					assigned-clocks = <&icssg2_coreclk_mux>;
+					assigned-clock-parents = <&k3_clks 64 3>;
+				};
+
+				icssg2_iepclk_mux: iepclk-mux@30 {
+					reg = <0x30>;
+					#clock-cells = <0>;
+					clocks = <&k3_clks 64 10>,	/* icssg1_iep_clk */
+						 <&icssg2_coreclk_mux>;	/* core_clk */
+					assigned-clocks = <&icssg2_iepclk_mux>;
+					assigned-clock-parents = <&icssg2_coreclk_mux>;
+				};
+			};
+		};
+
+		icssg2_iep0: iep@2e000 {
+			compatible = "ti,am654-icss-iep";
+			reg = <0x2e000 0x1000>;
+			clocks = <&icssg2_iepclk_mux>;
+		};
+
+		icssg2_iep1: iep@2f000 {
+			compatible = "ti,am654-icss-iep";
+			reg = <0x2f000 0x1000>;
+			clocks = <&icssg2_iepclk_mux>;
+		};
+
+		icssg2_mii_rt: mii-rt@32000 {
+			compatible = "ti,pruss-mii", "syscon";
+			reg = <0x32000 0x100>;
+		};
+
+		icssg2_mii_g_rt: mii-g-rt@33000 {
+			compatible = "ti,pruss-mii-g", "syscon";
+			reg = <0x33000 0x1000>;
+		};
+
+		icssg2_intc: interrupt-controller@20000 {
+			compatible = "ti,icssg-intc";
+			reg = <0x20000 0x2000>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "host_intr0", "host_intr1",
+					  "host_intr2", "host_intr3",
+					  "host_intr4", "host_intr5",
+					  "host_intr6", "host_intr7";
+		};
+
+		pru2_0: pru@34000 {
+			compatible = "ti,am654-pru";
+			reg = <0x34000 0x4000>,
+			      <0x22000 0x100>,
+			      <0x22400 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-pru2_0-fw";
+		};
+
+		rtu2_0: rtu@4000 {
+			compatible = "ti,am654-rtu";
+			reg = <0x4000 0x2000>,
+			      <0x23000 0x100>,
+			      <0x23400 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-rtu2_0-fw";
+		};
+
+		tx_pru2_0: txpru@a000 {
+			compatible = "ti,am654-tx-pru";
+			reg = <0xa000 0x1800>,
+			      <0x25000 0x100>,
+			      <0x25400 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-txpru2_0-fw";
+		};
+
+		pru2_1: pru@38000 {
+			compatible = "ti,am654-pru";
+			reg = <0x38000 0x4000>,
+			      <0x24000 0x100>,
+			      <0x24400 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-pru2_1-fw";
+		};
+
+		rtu2_1: rtu@6000 {
+			compatible = "ti,am654-rtu";
+			reg = <0x6000 0x2000>,
+			      <0x23800 0x100>,
+			      <0x23c00 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-rtu2_1-fw";
+		};
+
+		tx_pru2_1: txpru@c000 {
+			compatible = "ti,am654-tx-pru";
+			reg = <0xc000 0x1800>,
+			      <0x25800 0x100>,
+			      <0x25c00 0x100>;
+			reg-names = "iram", "control", "debug";
+			firmware-name = "am65x-txpru2_1-fw";
+		};
+
+		icssg2_mdio: mdio@32400 {
+			compatible = "ti,davinci_mdio";
+			reg = <0x32400 0x100>;
+			clocks = <&k3_clks 64 3>;
+			clock-names = "fck";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			bus_freq = <1000000>;
+			status = "disabled";
+		};
+	};
+
 };
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 77b7d3f452..df850a2edb 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -4,3 +4,75 @@
  */
 
 #include "k3-am654-r5-base-board-u-boot.dtsi"
+
+&pru0_0 {
+	remoteproc-name = "pru0_0";
+};
+
+&rtu0_0 {
+	remoteproc-name = "rtu0_0";
+};
+
+&tx_pru0_0 {
+	remoteproc-name = "tx_pru0_0";
+};
+
+&pru0_1 {
+	remoteproc-name = "pru0_1";
+};
+
+&rtu0_1 {
+	remoteproc-name = "rtu0_1";
+};
+
+&tx_pru0_1 {
+	remoteproc-name = "tx_pru0_1";
+};
+
+&pru1_0 {
+	remoteproc-name = "pru1_0";
+};
+
+&rtu1_0 {
+	remoteproc-name = "rtu1_0";
+};
+
+&tx_pru1_0 {
+	remoteproc-name = "tx_pru1_0";
+};
+
+&pru1_1 {
+	remoteproc-name = "pru1_1";
+};
+
+&rtu1_1 {
+	remoteproc-name = "rtu1_1";
+};
+
+&tx_pru1_1 {
+	remoteproc-name = "tx_pru1_1";
+};
+
+&pru2_0 {
+	remoteproc-name = "pru2_0";
+};
+
+&rtu2_0 {
+	remoteproc-name = "rtu2_0";
+};
+
+&tx_pru2_0 {
+	remoteproc-name = "tx_pru2_0";
+};
+
+&pru2_1 {
+	remoteproc-name = "pru2_1";
+};
+
+&rtu2_1 {
+	remoteproc-name = "rtu2_1";
+};
+
+&tx_pru2_1 {
+	remoteproc-name = "tx_pru2_1";
+};
-- 
2.31.1

[PATCH 5/5] configs: am65x_evm_a53: Enable PRUSS remoteproc

[Lokesh Vutla]

Enable PRUSS remoteproc driver for AM65

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
 configs/am65x_evm_a53_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 01e027f607..512849f983 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -139,12 +139,14 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_REMOTEPROC_TI_K3_R5F=y
+CONFIG_REMOTEPROC_TI_PRU=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SOC_DEVICE=y
 CONFIG_SOC_DEVICE_TI_K3=y
 CONFIG_SOC_TI=y
+CONFIG_TI_PRUSS=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y
-- 
2.31.1