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* [PATCH] arm: imx: imx8mm: correct unrecognized fracpll frequency
@ 2021-05-01 20:13 Andrey Zhizhikin
  2021-05-02 20:47 ` Fabio Estevam
                   ` (2 more replies)
  0 siblings, 3 replies; 7+ messages in thread
From: Andrey Zhizhikin @ 2021-05-01 20:13 UTC (permalink / raw)
  To: u-boot

Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ()
macro, which expands the value provided to the Hz range without taking into
account the precise Hz setting. This causes the frequency of 266 MHz not ot
be found in the imx8mm_fracpll_tbl, since it is entered there with a
precise Hz value. This in turn causes the boot hang in SPL, as proper DDR
fracpll frequency cannot be determined.

Correct the value in imx8mm_fracpll_tbl to match the one expanded by
MHZ(266) macro, rounding it down to MHz range only.

Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Ye Li <ye.li@nxp.com>
Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m")
---
 arch/arm/mach-imx/imx8m/clock_imx8mm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 029d06f27f..86ff2b9cc9 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -54,7 +54,7 @@ static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
 	PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
 	PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
 	PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
-	PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
+	PLL_1443X_RATE(266000000U, 400, 9, 2, 0),
 	PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
 	PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
 };
@@ -72,7 +72,7 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq)
 	}
 
 	if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
-		printf("No matched freq table %u\n", freq);
+		printf("%s: No matched freq table %u\n", __func__, freq);
 		return -EINVAL;
 	}
 
@@ -148,7 +148,7 @@ void dram_enable_bypass(ulong clk_val)
 	}
 
 	if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
-		printf("No matched freq table %lu\n", clk_val);
+		printf("%s: No matched freq table %lu\n", __func__, clk_val);
 		return;
 	}
 
-- 
2.25.1

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH] arm: imx: imx8mm: correct unrecognized fracpll frequency
  2021-05-01 20:13 [PATCH] arm: imx: imx8mm: correct unrecognized fracpll frequency Andrey Zhizhikin
@ 2021-05-02 20:47 ` Fabio Estevam
  2021-05-02 21:45 ` Fabio Estevam
  2021-05-03  7:59 ` [PATCH v2] " Andrey Zhizhikin
  2 siblings, 0 replies; 7+ messages in thread
From: Fabio Estevam @ 2021-05-02 20:47 UTC (permalink / raw)
  To: u-boot

On Sat, May 1, 2021 at 5:13 PM Andrey Zhizhikin
<andrey.zhizhikin@leica-geosystems.com> wrote:
>
> Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ()
> macro, which expands the value provided to the Hz range without taking into
> account the precise Hz setting. This causes the frequency of 266 MHz not ot
> be found in the imx8mm_fracpll_tbl, since it is entered there with a
> precise Hz value. This in turn causes the boot hang in SPL, as proper DDR
> fracpll frequency cannot be determined.
>
> Correct the value in imx8mm_fracpll_tbl to match the one expanded by
> MHZ(266) macro, rounding it down to MHz range only.
>
> Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Ye Li <ye.li@nxp.com>
> Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m")

Reviewed-by: Fabio Estevam <festevam@gmail.com>

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH] arm: imx: imx8mm: correct unrecognized fracpll frequency
  2021-05-01 20:13 [PATCH] arm: imx: imx8mm: correct unrecognized fracpll frequency Andrey Zhizhikin
  2021-05-02 20:47 ` Fabio Estevam
@ 2021-05-02 21:45 ` Fabio Estevam
  2021-05-03  7:27   ` ZHIZHIKIN Andrey
  2021-05-03  7:59 ` [PATCH v2] " Andrey Zhizhikin
  2 siblings, 1 reply; 7+ messages in thread
From: Fabio Estevam @ 2021-05-02 21:45 UTC (permalink / raw)
  To: u-boot

Hi Andrey,

After re-reading the patch I have some comments:

On Sat, May 1, 2021 at 5:13 PM Andrey Zhizhikin
<andrey.zhizhikin@leica-geosystems.com> wrote:
>
> Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ()
> macro, which expands the value provided to the Hz range without taking into
> account the precise Hz setting. This causes the frequency of 266 MHz not ot
> be found in the imx8mm_fracpll_tbl, since it is entered there with a
> precise Hz value. This in turn causes the boot hang in SPL, as proper DDR
> fracpll frequency cannot be determined.
>
> Correct the value in imx8mm_fracpll_tbl to match the one expanded by
> MHZ(266) macro, rounding it down to MHz range only.
>
> Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Ye Li <ye.li@nxp.com>
> Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m")
> ---
>  arch/arm/mach-imx/imx8m/clock_imx8mm.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> index 029d06f27f..86ff2b9cc9 100644
> --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> @@ -54,7 +54,7 @@ static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
>         PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
>         PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
>         PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
> -       PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
> +       PLL_1443X_RATE(266000000U, 400, 9, 2, 0),

This change looks good.

>         PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
>         PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
>  };
> @@ -72,7 +72,7 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq)
>         }
>
>         if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
> -               printf("No matched freq table %u\n", freq);
> +               printf("%s: No matched freq table %u\n", __func__, freq);
>                 return -EINVAL;
>         }
>
> @@ -148,7 +148,7 @@ void dram_enable_bypass(ulong clk_val)
>         }
>
>         if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
> -               printf("No matched freq table %lu\n", clk_val);
> +               printf("%s: No matched freq table %lu\n", __func__, clk_val);

, but these two I would put them on a separate patch.

Thanks

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH] arm: imx: imx8mm: correct unrecognized fracpll frequency
  2021-05-02 21:45 ` Fabio Estevam
@ 2021-05-03  7:27   ` ZHIZHIKIN Andrey
  0 siblings, 0 replies; 7+ messages in thread
From: ZHIZHIKIN Andrey @ 2021-05-03  7:27 UTC (permalink / raw)
  To: u-boot

Hello Fabio,

> -----Original Message-----
> From: Fabio Estevam <festevam@gmail.com>
> Sent: Sunday, May 2, 2021 11:45 PM
> To: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>
> Cc: U-Boot-Denx <u-boot@lists.denx.de>; Stefano Babic <sbabic@denx.de>;
> NXP i.MX U-Boot Team <uboot-imx@nxp.com>; Peng Fan
> <peng.fan@nxp.com>; Simon Glass <sjg@chromium.org>; Ye Li <ye.li@nxp.com>
> Subject: Re: [PATCH] arm: imx: imx8mm: correct unrecognized fracpll frequency
> 
> 
> Hi Andrey,
> 
> After re-reading the patch I have some comments:
> 
> On Sat, May 1, 2021 at 5:13 PM Andrey Zhizhikin <andrey.zhizhikin@leica-
> geosystems.com> wrote:
> >
> > Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ()
> > macro, which expands the value provided to the Hz range without taking
> > into account the precise Hz setting. This causes the frequency of 266
> > MHz not ot be found in the imx8mm_fracpll_tbl, since it is entered
> > there with a precise Hz value. This in turn causes the boot hang in
> > SPL, as proper DDR fracpll frequency cannot be determined.
> >
> > Correct the value in imx8mm_fracpll_tbl to match the one expanded by
> > MHZ(266) macro, rounding it down to MHz range only.
> >
> > Signed-off-by: Andrey Zhizhikin
> > <andrey.zhizhikin@leica-geosystems.com>
> > Cc: Stefano Babic <sbabic@denx.de>
> > Cc: Fabio Estevam <festevam@gmail.com>
> > Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
> > Cc: Peng Fan <peng.fan@nxp.com>
> > Cc: Simon Glass <sjg@chromium.org>
> > Cc: Ye Li <ye.li@nxp.com>
> > Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m")
> > ---
> >  arch/arm/mach-imx/imx8m/clock_imx8mm.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > index 029d06f27f..86ff2b9cc9 100644
> > --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > @@ -54,7 +54,7 @@ static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[]
> = {
> >         PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
> >         PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
> >         PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
> > -       PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
> > +       PLL_1443X_RATE(266000000U, 400, 9, 2, 0),
> 
> This change looks good.
> 
> >         PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
> >         PLL_1443X_RATE(100000000U, 300, 9, 3, 0),  }; @@ -72,7 +72,7
> > @@ static int fracpll_configure(enum pll_clocks pll, u32 freq)
> >         }
> >
> >         if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
> > -               printf("No matched freq table %u\n", freq);
> > +               printf("%s: No matched freq table %u\n", __func__,
> > + freq);
> >                 return -EINVAL;
> >         }
> >
> > @@ -148,7 +148,7 @@ void dram_enable_bypass(ulong clk_val)
> >         }
> >
> >         if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
> > -               printf("No matched freq table %lu\n", clk_val);
> > +               printf("%s: No matched freq table %lu\n", __func__,
> > + clk_val);
> 
> , but these two I would put them on a separate patch.

Fair enough, thanks for pointing this out!

Even though this helped me originally to pinpoint the issue, looking at this change now I see it does indeed belong to the separate patch as it does not relate to the PLL fix per se.

I would split this into a separate patch, send it separate, and send a V2 for the PLL fix.

> 
> Thanks

Cheers,
Andrey

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v2] arm: imx: imx8mm: correct unrecognized fracpll frequency
  2021-05-01 20:13 [PATCH] arm: imx: imx8mm: correct unrecognized fracpll frequency Andrey Zhizhikin
  2021-05-02 20:47 ` Fabio Estevam
  2021-05-02 21:45 ` Fabio Estevam
@ 2021-05-03  7:59 ` Andrey Zhizhikin
  2021-05-03 10:55   ` Fabio Estevam
  2021-06-09 13:44   ` sbabic
  2 siblings, 2 replies; 7+ messages in thread
From: Andrey Zhizhikin @ 2021-05-03  7:59 UTC (permalink / raw)
  To: u-boot

Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ()
macro, which expands the value provided to the Hz range without taking into
account the precise Hz setting. This causes the frequency of 266 MHz not ot
be found in the imx8mm_fracpll_tbl, since it is entered there with a
precise Hz value. This in turn causes the boot hang in SPL, as proper DDR
fracpll frequency cannot be determined.

Correct the value in imx8mm_fracpll_tbl to match the one expanded by
MHZ(266) macro, rounding it down to MHz range only.

Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Ye Li <ye.li@nxp.com>
Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m")
---

Changes in v2:
- Remove debug message clarifications, they are addressed in a separate
  patch

 arch/arm/mach-imx/imx8m/clock_imx8mm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 029d06f27f..7d0f564a24 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -54,7 +54,7 @@ static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
 	PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
 	PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
 	PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
-	PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
+	PLL_1443X_RATE(266000000U, 400, 9, 2, 0),
 	PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
 	PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
 };
-- 
2.25.1

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH v2] arm: imx: imx8mm: correct unrecognized fracpll frequency
  2021-05-03  7:59 ` [PATCH v2] " Andrey Zhizhikin
@ 2021-05-03 10:55   ` Fabio Estevam
  2021-06-09 13:44   ` sbabic
  1 sibling, 0 replies; 7+ messages in thread
From: Fabio Estevam @ 2021-05-03 10:55 UTC (permalink / raw)
  To: u-boot

On Mon, May 3, 2021 at 5:00 AM Andrey Zhizhikin
<andrey.zhizhikin@leica-geosystems.com> wrote:
>
> Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ()
> macro, which expands the value provided to the Hz range without taking into
> account the precise Hz setting. This causes the frequency of 266 MHz not ot
> be found in the imx8mm_fracpll_tbl, since it is entered there with a
> precise Hz value. This in turn causes the boot hang in SPL, as proper DDR
> fracpll frequency cannot be determined.
>
> Correct the value in imx8mm_fracpll_tbl to match the one expanded by
> MHZ(266) macro, rounding it down to MHz range only.
>
> Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Ye Li <ye.li@nxp.com>
> Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m")

Reviewed-by: Fabio Estevam <festevam@gmail.com>

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v2] arm: imx: imx8mm: correct unrecognized fracpll frequency
  2021-05-03  7:59 ` [PATCH v2] " Andrey Zhizhikin
  2021-05-03 10:55   ` Fabio Estevam
@ 2021-06-09 13:44   ` sbabic
  1 sibling, 0 replies; 7+ messages in thread
From: sbabic @ 2021-06-09 13:44 UTC (permalink / raw)
  To: Andrey Zhizhikin, U-Boot

> Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ()
> macro, which expands the value provided to the Hz range without taking into
> account the precise Hz setting. This causes the frequency of 266 MHz not ot
> be found in the imx8mm_fracpll_tbl, since it is entered there with a
> precise Hz value. This in turn causes the boot hang in SPL, as proper DDR
> fracpll frequency cannot be determined.
> Correct the value in imx8mm_fracpll_tbl to match the one expanded by
> MHZ(266) macro, rounding it down to MHz range only.
> Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Ye Li <ye.li@nxp.com>
> Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m")
> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2021-06-09 13:47 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-01 20:13 [PATCH] arm: imx: imx8mm: correct unrecognized fracpll frequency Andrey Zhizhikin
2021-05-02 20:47 ` Fabio Estevam
2021-05-02 21:45 ` Fabio Estevam
2021-05-03  7:27   ` ZHIZHIKIN Andrey
2021-05-03  7:59 ` [PATCH v2] " Andrey Zhizhikin
2021-05-03 10:55   ` Fabio Estevam
2021-06-09 13:44   ` sbabic

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