From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1615C48BD1 for ; Thu, 10 Jun 2021 08:25:52 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7F4E2613FE for ; Thu, 10 Jun 2021 08:25:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7F4E2613FE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:49818 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lrG0d-00010d-K8 for qemu-devel@archiver.kernel.org; Thu, 10 Jun 2021 04:25:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lrFsl-00005t-Mq; Thu, 10 Jun 2021 04:17:45 -0400 Received: from mail142-28.mail.alibaba.com ([198.11.142.28]:22352) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lrFsj-00084f-Sz; Thu, 10 Jun 2021 04:17:43 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.08967724|-1; CH=blue; DM=|OVERLOAD|false|; DS=CONTINUE|ham_system_inform|0.625056-0.00864608-0.366298; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047198; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KQN5pZK_1623313052; Received: from localhost.localdomain(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KQN5pZK_1623313052) by smtp.aliyun-inc.com(10.147.41.158); Thu, 10 Jun 2021 16:17:32 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions Date: Thu, 10 Jun 2021 15:59:07 +0800 Message-Id: <20210610075908.3305506-37-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210610075908.3305506-1-zhiwei_liu@c-sky.com> References: <20210610075908.3305506-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=198.11.142.28; envelope-from=zhiwei_liu@c-sky.com; helo=mail142-28.mail.alibaba.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, richard.henderson@linaro.org, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Concat two 32-bit elements to form a 64-bit element. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvp.c.inc | 6 ++++ target/riscv/packed_helper.c | 41 +++++++++++++++++++++++++ 4 files changed, 57 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b998c86abf..bfcf0ff761 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1474,3 +1474,8 @@ DEF_HELPER_3(smdrs32, i64, env, i64, i64) DEF_HELPER_3(smxds32, i64, env, i64, i64) DEF_HELPER_3(sraiw_u, i64, env, i64, i64) + +DEF_HELPER_3(pkbb32, i64, env, i64, i64) +DEF_HELPER_3(pkbt32, i64, env, i64, i64) +DEF_HELPER_3(pktt32, i64, env, i64, i64) +DEF_HELPER_3(pktb32, i64, env, i64, i64) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 8e8aca4ea1..65682f70b5 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -1097,3 +1097,8 @@ smdrs32 0110100 ..... ..... 010 ..... 1110111 @r smxds32 0111100 ..... ..... 010 ..... 1110111 @r sraiw_u 0011010 ..... ..... 001 ..... 1110111 @sh5 + +pkbb32 0000111 ..... ..... 010 ..... 1110111 @r +pkbt32 0001111 ..... ..... 010 ..... 1110111 @r +pktt32 0010111 ..... ..... 010 ..... 1110111 @r +pktb32 0011111 ..... ..... 010 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 68c1ef9f48..7505a0f89b 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -1147,3 +1147,9 @@ GEN_RVP64_R_OOL(smxds32); /* (RV64 Only) Non-SIMD 32-bit Shift Instructions */ GEN_RVP64_SHIFTI(sraiw_u, gen_helper_sraiw_u); + +/* (RV64 Only) 32-bit Packing Instructions */ +GEN_RVP64_R_OOL(pkbb32); +GEN_RVP64_R_OOL(pkbt32); +GEN_RVP64_R_OOL(pktt32); +GEN_RVP64_R_OOL(pktb32); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 42f1d96fa5..3f4bc593f9 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -3808,3 +3808,44 @@ static inline void do_sraiw_u(CPURISCVState *env, void *vd, void *va, } RVPR64_64_64(sraiw_u, 1, 8); + +/* (RV64 Only) 32-bit packing instructions here */ +static inline void do_pkbb32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i)]; + d[H4(i + 1)] = a[H4(i)]; +} + +RVPR64_64_64(pkbb32, 2, 4); + +static inline void do_pkbt32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i + 1)]; + d[H4(i + 1)] = a[H4(i)]; +} + +RVPR64_64_64(pkbt32, 2, 4); + +static inline void do_pktb32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i)]; + d[H4(i + 1)] = a[H4(i + 1)]; +} + +RVPR64_64_64(pktb32, 2, 4); + +static inline void do_pktt32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i + 1)]; + d[H4(i + 1)] = a[H4(i + 1)]; +} + +RVPR64_64_64(pktt32, 2, 4); -- 2.25.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1lrFsp-0000C8-8G for mharc-qemu-riscv@gnu.org; Thu, 10 Jun 2021 04:17:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lrFsl-00005t-Mq; Thu, 10 Jun 2021 04:17:45 -0400 Received: from mail142-28.mail.alibaba.com ([198.11.142.28]:22352) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lrFsj-00084f-Sz; Thu, 10 Jun 2021 04:17:43 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.08967724|-1; CH=blue; DM=|OVERLOAD|false|; DS=CONTINUE|ham_system_inform|0.625056-0.00864608-0.366298; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047198; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=7; RT=7; SR=0; TI=SMTPD_---.KQN5pZK_1623313052; Received: from localhost.localdomain(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KQN5pZK_1623313052) by smtp.aliyun-inc.com(10.147.41.158); Thu, 10 Jun 2021 16:17:32 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, richard.henderson@linaro.org, LIU Zhiwei Subject: [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions Date: Thu, 10 Jun 2021 15:59:07 +0800 Message-Id: <20210610075908.3305506-37-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210610075908.3305506-1-zhiwei_liu@c-sky.com> References: <20210610075908.3305506-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=198.11.142.28; envelope-from=zhiwei_liu@c-sky.com; helo=mail142-28.mail.alibaba.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 10 Jun 2021 08:17:46 -0000 Concat two 32-bit elements to form a 64-bit element. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvp.c.inc | 6 ++++ target/riscv/packed_helper.c | 41 +++++++++++++++++++++++++ 4 files changed, 57 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b998c86abf..bfcf0ff761 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1474,3 +1474,8 @@ DEF_HELPER_3(smdrs32, i64, env, i64, i64) DEF_HELPER_3(smxds32, i64, env, i64, i64) DEF_HELPER_3(sraiw_u, i64, env, i64, i64) + +DEF_HELPER_3(pkbb32, i64, env, i64, i64) +DEF_HELPER_3(pkbt32, i64, env, i64, i64) +DEF_HELPER_3(pktt32, i64, env, i64, i64) +DEF_HELPER_3(pktb32, i64, env, i64, i64) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 8e8aca4ea1..65682f70b5 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -1097,3 +1097,8 @@ smdrs32 0110100 ..... ..... 010 ..... 1110111 @r smxds32 0111100 ..... ..... 010 ..... 1110111 @r sraiw_u 0011010 ..... ..... 001 ..... 1110111 @sh5 + +pkbb32 0000111 ..... ..... 010 ..... 1110111 @r +pkbt32 0001111 ..... ..... 010 ..... 1110111 @r +pktt32 0010111 ..... ..... 010 ..... 1110111 @r +pktb32 0011111 ..... ..... 010 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 68c1ef9f48..7505a0f89b 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -1147,3 +1147,9 @@ GEN_RVP64_R_OOL(smxds32); /* (RV64 Only) Non-SIMD 32-bit Shift Instructions */ GEN_RVP64_SHIFTI(sraiw_u, gen_helper_sraiw_u); + +/* (RV64 Only) 32-bit Packing Instructions */ +GEN_RVP64_R_OOL(pkbb32); +GEN_RVP64_R_OOL(pkbt32); +GEN_RVP64_R_OOL(pktt32); +GEN_RVP64_R_OOL(pktb32); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 42f1d96fa5..3f4bc593f9 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -3808,3 +3808,44 @@ static inline void do_sraiw_u(CPURISCVState *env, void *vd, void *va, } RVPR64_64_64(sraiw_u, 1, 8); + +/* (RV64 Only) 32-bit packing instructions here */ +static inline void do_pkbb32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i)]; + d[H4(i + 1)] = a[H4(i)]; +} + +RVPR64_64_64(pkbb32, 2, 4); + +static inline void do_pkbt32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i + 1)]; + d[H4(i + 1)] = a[H4(i)]; +} + +RVPR64_64_64(pkbt32, 2, 4); + +static inline void do_pktb32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i)]; + d[H4(i + 1)] = a[H4(i + 1)]; +} + +RVPR64_64_64(pktb32, 2, 4); + +static inline void do_pktt32(CPURISCVState *env, void *vd, void *va, + void *vb, uint8_t i) +{ + uint32_t *d = vd, *a = va, *b = vb; + d[H4(i)] = b[H4(i + 1)]; + d[H4(i + 1)] = a[H4(i + 1)]; +} + +RVPR64_64_64(pktt32, 2, 4); -- 2.25.1