From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from wout5-smtp.messagingengine.com (wout5-smtp.messagingengine.com [64.147.123.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B84EB2F80 for ; Thu, 10 Jun 2021 12:52:13 +0000 (UTC) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.west.internal (Postfix) with ESMTP id 58E5A2101; Thu, 10 Jun 2021 08:52:12 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute3.internal (MEProxy); Thu, 10 Jun 2021 08:52:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cerno.tech; h= date:from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=fm3; bh=E5Pc7fipEbBuER2SNRqORMg07Xg /kjPfCBgdeNOwwzM=; b=uq6gkHgO9P4locKPO6euSQbmudLsOCueuxjgrVcQzUn jIuPRd0L2ilYFUJM5fDYevFoxX3Q5mZT4EHcO2eeYX/nhzN6C/Bbk5udF9bOecCX IF3ogEnb6EQE9ee8fZfCKU51fxPf1gtLymjRvGXaeSNgZB4jupKyUcK91WFUeY1h C7YQW66FVS8agu5Nf6J3OUodV5qKCNdNlVe/NG7vfcNmUgYFzVTNp+/TeaGL3L/k sn1hCtz9v6+4Up4fLxAnNb7mNqFJA80feYZEe3VdTZFnrthHtWn2m5UwxKDace+M 6xqgi0tqDyxn65Px5GpD4g3Qg2n6D1Pi5o1XTkHzeMA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm3; bh=E5Pc7f ipEbBuER2SNRqORMg07Xg/kjPfCBgdeNOwwzM=; b=ZqXhRvdLv45r+chVTO/7Gn 4rkTQyCMncwDlexzWTVXLDnhXkbbSKs5Xe9MxCsVqpd0TVjcyvUfK4xAtRjSzLRI gl7uAgr9e2S2Ocr9XjLPRkSG6SH1NrKWpp5s3ES8NS5S7CKays9SWhpyBFE4hS77 KVplRntLY+OkP0sUlE0jPpQUnnOuBv3dk87lBosI12nZe2mZKu4kEiYFA7cvzJhf ufH89d4ym7eV5GD8XfnCA0RexPkqAcNKmIfl3Ejr0FeCTncX9O0Y8ybAvyh1xYCe ctIL6Xbo2Ei1SHgo2h9Y7fRF2s0XB19aapdramN8/FEKyvPZQj0SMssjYB8zZPuw == X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduledrfedufedgheeiucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepfffhvffukfhfgggtuggjsehgtderredttddvnecuhfhrohhmpeforgigihhm vgcutfhiphgrrhguuceomhgrgihimhgvsegtvghrnhhordhtvggthheqnecuggftrfgrth htvghrnhepleekgeehhfdutdeljefgleejffehfffgieejhffgueefhfdtveetgeehieeh gedunecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepmh grgihimhgvsegtvghrnhhordhtvggthh X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Thu, 10 Jun 2021 08:52:10 -0400 (EDT) Date: Thu, 10 Jun 2021 14:52:09 +0200 From: Maxime Ripard To: Icenowy Zheng Cc: Chen-Yu Tsai , Jernej Skrabec , Heinrich Schuchardt , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: dts: allwinner: a64-sopine-baseboard: change RGMII mode to TXID Message-ID: <20210610125209.glrd2qlpwqiha24h@gilmour> References: <20210609083843.463750-1-icenowy@aosc.io> X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="io7uwxozpxpfiet4" Content-Disposition: inline In-Reply-To: <20210609083843.463750-1-icenowy@aosc.io> --io7uwxozpxpfiet4 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jun 09, 2021 at 04:38:43PM +0800, Icenowy Zheng wrote: > Although the schematics of Pine A64-LTS and SoPine Baseboard shows both > the RX and TX internal delay are enabled, they're using the same broken > RTL8211E chip batch with Pine A64+, so they should use TXID instead, not > ID. >=20 > In addition, by checking the real components soldered on both a SoPine > Baseboard and a Pine A64-LTS, RX delay is not enabled (GR69 soldered and > GR70 NC) despite the schematics says it's enabled. It's a common > situation for Pine64 boards that the NC information on schematics is not > the same with the board. >=20 > So the RGMII delay mode should be TXID on these boards. >=20 > Fixes: c2b111e59a7b ("arm64: dts: allwinner: A64 Sopine: phy-mode rgmii-i= d") > Signed-off-by: Icenowy Zheng Applied, thanks Maxime --io7uwxozpxpfiet4 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCYMIK+QAKCRDj7w1vZxhR xdspAP9uCPofAxHimp/PmBqZWpgDIoj9Jm6i11JcI3I8w29RPQEAl/hyxPgO52Bq BJlk9Q56TTqTCDsAPS0wOl8F0unSGAg= =DvGq -----END PGP SIGNATURE----- --io7uwxozpxpfiet4-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34C35C47094 for ; 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Thu, 10 Jun 2021 08:52:10 -0400 (EDT) Date: Thu, 10 Jun 2021 14:52:09 +0200 From: Maxime Ripard To: Icenowy Zheng Cc: Chen-Yu Tsai , Jernej Skrabec , Heinrich Schuchardt , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: dts: allwinner: a64-sopine-baseboard: change RGMII mode to TXID Message-ID: <20210610125209.glrd2qlpwqiha24h@gilmour> References: <20210609083843.463750-1-icenowy@aosc.io> MIME-Version: 1.0 In-Reply-To: <20210609083843.463750-1-icenowy@aosc.io> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210610_055218_008981_4A9DA159 X-CRM114-Status: GOOD ( 14.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============8605701367178564406==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============8605701367178564406== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="io7uwxozpxpfiet4" Content-Disposition: inline --io7uwxozpxpfiet4 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jun 09, 2021 at 04:38:43PM +0800, Icenowy Zheng wrote: > Although the schematics of Pine A64-LTS and SoPine Baseboard shows both > the RX and TX internal delay are enabled, they're using the same broken > RTL8211E chip batch with Pine A64+, so they should use TXID instead, not > ID. >=20 > In addition, by checking the real components soldered on both a SoPine > Baseboard and a Pine A64-LTS, RX delay is not enabled (GR69 soldered and > GR70 NC) despite the schematics says it's enabled. It's a common > situation for Pine64 boards that the NC information on schematics is not > the same with the board. >=20 > So the RGMII delay mode should be TXID on these boards. >=20 > Fixes: c2b111e59a7b ("arm64: dts: allwinner: A64 Sopine: phy-mode rgmii-i= d") > Signed-off-by: Icenowy Zheng Applied, thanks Maxime --io7uwxozpxpfiet4 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCYMIK+QAKCRDj7w1vZxhR xdspAP9uCPofAxHimp/PmBqZWpgDIoj9Jm6i11JcI3I8w29RPQEAl/hyxPgO52Bq BJlk9Q56TTqTCDsAPS0wOl8F0unSGAg= =DvGq -----END PGP SIGNATURE----- --io7uwxozpxpfiet4-- --===============8605701367178564406== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============8605701367178564406==--