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From: Rob Herring <robh@kernel.org>
To: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	lorenzo.pieralisi@arm.com, bhelgaas@google.com,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/3] dt-bindings: pci: Add devicetree binding for Qualcomm PCIe EP controller
Date: Thu, 10 Jun 2021 16:46:48 -0500	[thread overview]
Message-ID: <20210610214648.GA2407603@robh.at.kernel.org> (raw)
In-Reply-To: <YLw9de/J7h5KZtHu@builder.lan>

On Sat, Jun 05, 2021 at 10:13:57PM -0500, Bjorn Andersson wrote:
> On Thu 03 Jun 05:38 CDT 2021, Manivannan Sadhasivam wrote:
> 
> > Add devicetree binding for Qualcomm PCIe EP controller used in platforms
> > like SDX55. The EP controller is based on the Designware core with
> > Qualcomm specific wrappers.
> > 
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> >  .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 144 ++++++++++++++++++
> >  1 file changed, 144 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> > new file mode 100644
> > index 000000000000..3e357cb03a5c
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> > @@ -0,0 +1,144 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm PCIe Endpoint Controller binding
> > +
> > +maintainers:
> > +  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > +
> > +allOf:
> > +  - $ref: "pci-ep.yaml#"
> > +
> > +properties:
> > +  compatible:
> > +    const: qcom,sdx55-pcie-ep
> 
> The binding looks good, but this is going to cause us an inevitable
> warning as we'd have to describe the controller twice (rc + ep) in the
> sdx55.dtsi.
> 
> @Rob, what do you suggest we do about this, because it's the same
> problem currently responsible for hundreds of warnings in the case of
> GENI (where each node is duplicated for different functions).

What determines the mode? Assuming it is fixed for a platform, can't you 
just have 2 .dtsi files and include the right one. The SoC file could 
have the common h/w specific parts (clks, resets, etc.) as those 
shouldn't really be different depending on the mode. IIRC, some PCI 
bindings do this by design (meaning there's only one definition).

Rob

  reply	other threads:[~2021-06-10 21:53 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-03 10:38 [PATCH v2 0/3] Add Qualcomm PCIe Endpoint driver support Manivannan Sadhasivam
2021-06-03 10:38 ` [PATCH v2 1/3] dt-bindings: pci: Add devicetree binding for Qualcomm PCIe EP controller Manivannan Sadhasivam
2021-06-06  3:13   ` Bjorn Andersson
2021-06-10 21:46     ` Rob Herring [this message]
2021-06-03 10:38 ` [PATCH v2 2/3] PCI: dwc: Add Qualcomm PCIe Endpoint controller driver Manivannan Sadhasivam
2021-06-05 22:02   ` Stanimir Varbanov
2021-06-09  5:20     ` Manivannan Sadhasivam
2021-06-06  3:07   ` Bjorn Andersson
2021-06-09  8:51     ` Manivannan Sadhasivam
2021-06-11  4:28       ` Bjorn Andersson
2021-06-11  4:44         ` Manivannan Sadhasivam
2021-06-16 18:23       ` Manivannan Sadhasivam
2021-06-15 21:40     ` Rob Herring
2021-06-15 21:57       ` Bjorn Andersson
2021-06-15 22:20         ` Rob Herring
2021-06-15 22:58           ` Bjorn Andersson
2021-06-03 10:38 ` [PATCH v2 3/3] MAINTAINERS: Add entry for Qualcomm PCIe Endpoint driver and binding Manivannan Sadhasivam

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