From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CF57C48BE5 for ; Fri, 11 Jun 2021 23:23:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3402B613C3 for ; Fri, 11 Jun 2021 23:23:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3402B613C3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 62C2D6F3F6; Fri, 11 Jun 2021 23:22:56 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 386026F3EF; Fri, 11 Jun 2021 23:22:55 +0000 (UTC) IronPort-SDR: 5FkdqWJ4kvJfDi3tU/AaDPJDlR1jCgu+41cVx4eB4jP+/rqul5Z1WrVaITYcK12rGysK9mB92G 6Fd+p+Y+Nn9A== X-IronPort-AV: E=McAfee;i="6200,9189,10012"; a="203796921" X-IronPort-AV: E=Sophos;i="5.83,267,1616482800"; d="scan'208";a="203796921" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2021 16:22:55 -0700 IronPort-SDR: 8uEifujiPCwEXJtCZQY8MQYlvCaN0uMMseSV6T6wogn8rDfZrr5pv5TGqD+UgouZmBgPm+D2m0 gqBYx4JhOclw== X-IronPort-AV: E=Sophos;i="5.83,267,1616482800"; d="scan'208";a="638843381" Received: from dhiatt-server.jf.intel.com ([10.54.81.3]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2021 16:22:53 -0700 From: Matthew Brost To: , Subject: [PATCH 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan Date: Fri, 11 Jun 2021 16:40:44 -0700 Message-Id: <20210611234044.853-3-matthew.brost@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210611234044.853-1-matthew.brost@intel.com> References: <20210611234044.853-1-matthew.brost@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.brost@intel.com, tony.ye@intel.com, tvrtko.ursulin@intel.com, daniele.ceraolospurio@intel.com, carl.zhang@intel.com, jason.ekstrand@intel.com, michal.mrozek@intel.com, jon.bloomfield@intel.com, mesa-dev@lists.freedesktop.org, daniel.vetter@intel.com, christian.koenig@amd.com, john.c.harrison@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add entry for i915 new parallel submission uAPI plan. v2: (Daniel Vetter): - Expand logical order explaination - Add dummy header - Only allow N BBs in execbuf IOCTL - Configure parallel submission per slot not per gem context v3: (Marcin Ślusarz): - Lot's of typos / bad english fixed (Tvrtko Ursulin): - Consistent pseudo code, clean up wording in descriptions v4: (Daniel Vetter) - Drop flags - Add kernel doc - Reword a few things / fix typos (Tvrtko) - Reword a few things / fix typos Cc: Tvrtko Ursulin Cc: Tony Ye CC: Carl Zhang Cc: Daniel Vetter Cc: Jason Ekstrand Signed-off-by: Matthew Brost Acked-by: Daniel Vetter --- Documentation/gpu/rfc/i915_parallel_execbuf.h | 117 ++++++++++++++++++ Documentation/gpu/rfc/i915_scheduler.rst | 59 ++++++++- 2 files changed, 175 insertions(+), 1 deletion(-) create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h new file mode 100644 index 000000000000..c22af3a359e4 --- /dev/null +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h @@ -0,0 +1,117 @@ +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */ + +/** + * struct drm_i915_context_engines_parallel_submit - Configure engine for + * parallel submission. + * + * Setup a slot in the context engine map to allow multiple BBs to be submitted + * in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU + * in parallel. Multiple hardware contexts are created internally in the i915 + * run these BBs. Once a slot is configured for N BBs only N BBs can be + * submitted in each execbuf IOCTL and this is implicit behavior e.g. The user + * doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how + * many BBs there are based on the slot's configuration. The N BBs are the last + * N buffer objects or first N if I915_EXEC_BATCH_FIRST is set. + * + * The default placement behavior is to create implicit bonds between each + * context if each context maps to more than 1 physical engine (e.g. context is + * a virtual engine). Also we only allow contexts of same engine class and these + * contexts must be in logically contiguous order. Examples of the placement + * behavior described below. Lastly, the default is to not allow BBs to + * preempted mid BB rather insert coordinated preemption on all hardware + * contexts between each set of BBs. Flags may be added in the future to change + * bott of these default behaviors. + * + * Returns -EINVAL if hardware context placement configuration is invalid or if + * the placement configuration isn't supported on the platform / submission + * interface. + * Returns -ENODEV if extension isn't supported on the platform / submission + * inteface. + * + * .. code-block:: + * + * Example 1 pseudo code: + * CS[X] = generic engine of same class, logical instance X + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID) + * set_parallel(engine_index=0, width=2, num_siblings=1, + * engines=CS[0],CS[1]) + * + * Results in the following valid placement: + * CS[0], CS[1] + * + * Example 2 pseudo code: + * CS[X] = generic engine of same class, logical instance X + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID) + * set_parallel(engine_index=0, width=2, num_siblings=2, + * engines=CS[0],CS[2],CS[1],CS[3]) + * + * Results in the following valid placements: + * CS[0], CS[1] + * CS[2], CS[3] + * + * This can also be thought of as 2 virtual engines described by 2-D array + * in the engines the field with bonds placed between each index of the + * virtual engines. e.g. CS[0] is bonded to CS[1], CS[2] is bonded to + * CS[3]. + * VE[0] = CS[0], CS[2] + * VE[1] = CS[1], CS[3] + * + * Example 3 pseudo code: + * CS[X] = generic engine of same class, logical instance X + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE + * set_engines(INVALID) + * set_parallel(engine_index=0, width=2, num_siblings=2, + * engines=CS[0],CS[1],CS[1],CS[3]) + * + * Results in the following valid and invalid placements: + * CS[0], CS[1] + * CS[1], CS[3] - Not logical contiguous, return -EINVAL + */ +struct drm_i915_context_engines_parallel_submit { + /** + * @base: base user extension. + */ + struct i915_user_extension base; + + /** + * @engine_index: slot for parallel engine + */ + __u16 engine_index; + + /** + * @width: number of contexts per parallel engine + */ + __u16 width; + + /** + * @num_siblings: number of siblings per context + */ + __u16 num_siblings; + + /** + * @mbz16: reserved for future use; must be zero + */ + __u16 mbz16; + + /** + * @flags: all undefined flags must be zero, currently not defined flags + */ + __u64 flags; + + /** + * @mbz64: reserved for future use; must be zero + */ + __u64 mbz64[3]; + + /** + * @engines: 2-d array of engine instances to configure parallel engine + * + * length = width (i) * num_siblings (j) + * index = j + i * num_siblings + */ + struct i915_engine_class_instance engines[0]; + +} __attribute__ ((packed)); + diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst index 7acd386a6b49..63849b50e663 100644 --- a/Documentation/gpu/rfc/i915_scheduler.rst +++ b/Documentation/gpu/rfc/i915_scheduler.rst @@ -88,4 +88,61 @@ Spec references: New parallel submission uAPI ============================ -Details to come in a following patch. +The existing bonding uAPI is completely broken with GuC submission because +whether a submission is a single context submit or parallel submit isn't known +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple +contexts in parallel with the GuC the context must be explicitly registered with +N contexts and all N contexts must be submitted in a single command to the GuC. +The GuC interfaces do not support dynamically changing between N contexts as the +bonding uAPI does. Hence the need for a new parallel submission interface. Also +the legacy bonding uAPI is quite confusing and not intuitive at all. Furthermore +I915_SUBMIT_FENCE is by design a future fence, so not really something we should +continue to support. + +The new parallel submission uAPI consists of 3 parts: + +* Export engines logical mapping +* A 'set_parallel' extension to configure contexts for parallel + submission +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL + +Export engines logical mapping +------------------------------ +Certain use cases require BBs to be placed on engine instances in logical order +(e.g. split-frame on gen11+). The logical mapping of engine instances can change +based on fusing. Rather than making UMDs be aware of fusing, simply expose the +logical mapping with the existing query engine info IOCTL. Also the GuC +submission interface currently only supports submitting multiple contexts to +engines in logical order which is a new requirement compared to execlists. +Lastly, all current platforms have at most 2 engine instances and the logical +order is the same as uAPI order. This will change on platforms with more than 2 +engine instances. + +A single bit will be added to drm_i915_engine_info.flags indicating that the +logical instance has been returned and a new field, +drm_i915_engine_info.logical_instance, returns the logical instance. + +A 'set_parallel' extension to configure contexts for parallel submission +------------------------------------------------------------------------ +The 'set_parallel' extension configures a slot for parallel submission of N BBs. +It is a setup step that must be called before using any of the contexts. See +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for +similar existing examples. Once a slot is configured for parallel submission the +execbuf2 IOCTL can be called submitting N BBs in a single IOCTL. Initially only +supports GuC submission. Execlists supports can be added later if needed. + +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and +drm_i915_context_engines_parallel_submit to the uAPI to implement this +extension. + +.. kernel-doc:: Documentation/gpu/rfc/i915_parallel_execbuf.h + :functions: drm_i915_context_engines_parallel_submit + +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL +------------------------------------------------------------------- +Contexts that have been configured with the 'set_parallel' extension can only +submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N objects +in in the drm_i915_gem_exec_object2 list or the first N if I915_EXEC_BATCH_FIRST +is set. The number of BBs is implicit based on the slot submitted and how it has +been configured by 'set_parallel' or other extensions. No uAPI changes are +required to execbuf2 IOCTL. -- 2.28.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6FE8C48BE5 for ; Fri, 11 Jun 2021 23:23:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 98F0E6124C for ; Fri, 11 Jun 2021 23:23:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 98F0E6124C Authentication-Results: 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charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" QWRkIGVudHJ5IGZvciBpOTE1IG5ldyBwYXJhbGxlbCBzdWJtaXNzaW9uIHVBUEkgcGxhbi4KCnYy OgogKERhbmllbCBWZXR0ZXIpOgogIC0gRXhwYW5kIGxvZ2ljYWwgb3JkZXIgZXhwbGFpbmF0aW9u CiAgLSBBZGQgZHVtbXkgaGVhZGVyCiAgLSBPbmx5IGFsbG93IE4gQkJzIGluIGV4ZWNidWYgSU9D VEwKICAtIENvbmZpZ3VyZSBwYXJhbGxlbCBzdWJtaXNzaW9uIHBlciBzbG90IG5vdCBwZXIgZ2Vt IGNvbnRleHQKdjM6CiAoTWFyY2luIMWabHVzYXJ6KToKICAtIExvdCdzIG9mIHR5cG9zIC8gYmFk IGVuZ2xpc2ggZml4ZWQKIChUdnJ0a28gVXJzdWxpbik6CiAgLSBDb25zaXN0ZW50IHBzZXVkbyBj b2RlLCBjbGVhbiB1cCB3b3JkaW5nIGluIGRlc2NyaXB0aW9ucwp2NDoKIChEYW5pZWwgVmV0dGVy KQogIC0gRHJvcCBmbGFncwogIC0gQWRkIGtlcm5lbCBkb2MKICAtIFJld29yZCBhIGZldyB0aGlu Z3MgLyBmaXggdHlwb3MKIChUdnJ0a28pCiAgLSBSZXdvcmQgYSBmZXcgdGhpbmdzIC8gZml4IHR5 cG9zCgpDYzogVHZydGtvIFVyc3VsaW4gPHR2cnRrby51cnN1bGluQGludGVsLmNvbT4KQ2M6IFRv bnkgWWUgPHRvbnkueWVAaW50ZWwuY29tPgpDQzogQ2FybCBaaGFuZyA8Y2FybC56aGFuZ0BpbnRl bC5jb20+CkNjOiBEYW5pZWwgVmV0dGVyIDxkYW5pZWwudmV0dGVyQGludGVsLmNvbT4KQ2M6IEph c29uIEVrc3RyYW5kIDxqYXNvbkBqbGVrc3RyYW5kLm5ldD4KU2lnbmVkLW9mZi1ieTogTWF0dGhl dyBCcm9zdCA8bWF0dGhldy5icm9zdEBpbnRlbC5jb20+CkFja2VkLWJ5OiBEYW5pZWwgVmV0dGVy IDxkYW5pZWwudmV0dGVyQGZmd2xsLmNoPgotLS0KIERvY3VtZW50YXRpb24vZ3B1L3JmYy9pOTE1 X3BhcmFsbGVsX2V4ZWNidWYuaCB8IDExNyArKysrKysrKysrKysrKysrKysKIERvY3VtZW50YXRp b24vZ3B1L3JmYy9pOTE1X3NjaGVkdWxlci5yc3QgICAgICB8ICA1OSArKysrKysrKy0KIDIgZmls ZXMgY2hhbmdlZCwgMTc1IGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24oLSkKIGNyZWF0ZSBtb2Rl IDEwMDY0NCBEb2N1bWVudGF0aW9uL2dwdS9yZmMvaTkxNV9wYXJhbGxlbF9leGVjYnVmLmgKCmRp ZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2dwdS9yZmMvaTkxNV9wYXJhbGxlbF9leGVjYnVmLmgg Yi9Eb2N1bWVudGF0aW9uL2dwdS9yZmMvaTkxNV9wYXJhbGxlbF9leGVjYnVmLmgKbmV3IGZpbGUg bW9kZSAxMDA2NDQKaW5kZXggMDAwMDAwMDAwMDAwLi5jMjJhZjNhMzU5ZTQKLS0tIC9kZXYvbnVs bAorKysgYi9Eb2N1bWVudGF0aW9uL2dwdS9yZmMvaTkxNV9wYXJhbGxlbF9leGVjYnVmLmgKQEAg LTAsMCArMSwxMTcgQEAKKyNkZWZpbmUgSTkxNV9DT05URVhUX0VOR0lORVNfRVhUX1BBUkFMTEVM X1NVQk1JVCAyIC8qIHNlZSBpOTE1X2NvbnRleHRfZW5naW5lc19wYXJhbGxlbF9zdWJtaXQgKi8K KworLyoqCisgKiBzdHJ1Y3QgZHJtX2k5MTVfY29udGV4dF9lbmdpbmVzX3BhcmFsbGVsX3N1Ym1p dCAtIENvbmZpZ3VyZSBlbmdpbmUgZm9yCisgKiBwYXJhbGxlbCBzdWJtaXNzaW9uLgorICoKKyAq IFNldHVwIGEgc2xvdCBpbiB0aGUgY29udGV4dCBlbmdpbmUgbWFwIHRvIGFsbG93IG11bHRpcGxl IEJCcyB0byBiZSBzdWJtaXR0ZWQKKyAqIGluIGEgc2luZ2xlIGV4ZWNidWYgSU9DVEwuIFRob3Nl IEJCcyB3aWxsIHRoZW4gYmUgc2NoZWR1bGVkIHRvIHJ1biBvbiB0aGUgR1BVCisgKiBpbiBwYXJh bGxlbC4gTXVsdGlwbGUgaGFyZHdhcmUgY29udGV4dHMgYXJlIGNyZWF0ZWQgaW50ZXJuYWxseSBp biB0aGUgaTkxNQorICogcnVuIHRoZXNlIEJCcy4gT25jZSBhIHNsb3QgaXMgY29uZmlndXJlZCBm b3IgTiBCQnMgb25seSBOIEJCcyBjYW4gYmUKKyAqIHN1Ym1pdHRlZCBpbiBlYWNoIGV4ZWNidWYg SU9DVEwgYW5kIHRoaXMgaXMgaW1wbGljaXQgYmVoYXZpb3IgZS5nLiBUaGUgdXNlcgorICogZG9l c24ndCB0ZWxsIHRoZSBleGVjYnVmIElPQ1RMIHRoZXJlIGFyZSBOIEJCcywgdGhlIGV4ZWNidWYg SU9DVEwga25vd3MgaG93CisgKiBtYW55IEJCcyB0aGVyZSBhcmUgYmFzZWQgb24gdGhlIHNsb3Qn cyBjb25maWd1cmF0aW9uLiBUaGUgTiBCQnMgYXJlIHRoZSBsYXN0CisgKiBOIGJ1ZmZlciBvYmpl Y3RzIG9yIGZpcnN0IE4gaWYgSTkxNV9FWEVDX0JBVENIX0ZJUlNUIGlzIHNldC4KKyAqCisgKiBU aGUgZGVmYXVsdCBwbGFjZW1lbnQgYmVoYXZpb3IgaXMgdG8gY3JlYXRlIGltcGxpY2l0IGJvbmRz IGJldHdlZW4gZWFjaAorICogY29udGV4dCBpZiBlYWNoIGNvbnRleHQgbWFwcyB0byBtb3JlIHRo YW4gMSBwaHlzaWNhbCBlbmdpbmUgKGUuZy4gY29udGV4dCBpcworICogYSB2aXJ0dWFsIGVuZ2lu ZSkuIEFsc28gd2Ugb25seSBhbGxvdyBjb250ZXh0cyBvZiBzYW1lIGVuZ2luZSBjbGFzcyBhbmQg dGhlc2UKKyAqIGNvbnRleHRzIG11c3QgYmUgaW4gbG9naWNhbGx5IGNvbnRpZ3VvdXMgb3JkZXIu IEV4YW1wbGVzIG9mIHRoZSBwbGFjZW1lbnQKKyAqIGJlaGF2aW9yIGRlc2NyaWJlZCBiZWxvdy4g TGFzdGx5LCB0aGUgZGVmYXVsdCBpcyB0byBub3QgYWxsb3cgQkJzIHRvCisgKiBwcmVlbXB0ZWQg bWlkIEJCIHJhdGhlciBpbnNlcnQgY29vcmRpbmF0ZWQgcHJlZW1wdGlvbiBvbiBhbGwgaGFyZHdh cmUKKyAqIGNvbnRleHRzIGJldHdlZW4gZWFjaCBzZXQgb2YgQkJzLiBGbGFncyBtYXkgYmUgYWRk ZWQgaW4gdGhlIGZ1dHVyZSB0byBjaGFuZ2UKKyAqIGJvdHQgb2YgdGhlc2UgZGVmYXVsdCBiZWhh dmlvcnMuCisgKgorICogUmV0dXJucyAtRUlOVkFMIGlmIGhhcmR3YXJlIGNvbnRleHQgcGxhY2Vt ZW50IGNvbmZpZ3VyYXRpb24gaXMgaW52YWxpZCBvciBpZgorICogdGhlIHBsYWNlbWVudCBjb25m aWd1cmF0aW9uIGlzbid0IHN1cHBvcnRlZCBvbiB0aGUgcGxhdGZvcm0gLyBzdWJtaXNzaW9uCisg KiBpbnRlcmZhY2UuCisgKiBSZXR1cm5zIC1FTk9ERVYgaWYgZXh0ZW5zaW9uIGlzbid0IHN1cHBv cnRlZCBvbiB0aGUgcGxhdGZvcm0gLyBzdWJtaXNzaW9uCisgKiBpbnRlZmFjZS4KKyAqCisgKiAu LiBjb2RlLWJsb2NrOjoKKyAqCisgKglFeGFtcGxlIDEgcHNldWRvIGNvZGU6CisgKglDU1tYXSA9 IGdlbmVyaWMgZW5naW5lIG9mIHNhbWUgY2xhc3MsIGxvZ2ljYWwgaW5zdGFuY2UgWAorICoJSU5W QUxJRCA9IEk5MTVfRU5HSU5FX0NMQVNTX0lOVkFMSUQsIEk5MTVfRU5HSU5FX0NMQVNTX0lOVkFM SURfTk9ORQorICoJc2V0X2VuZ2luZXMoSU5WQUxJRCkKKyAqCXNldF9wYXJhbGxlbChlbmdpbmVf aW5kZXg9MCwgd2lkdGg9MiwgbnVtX3NpYmxpbmdzPTEsCisgKgkJICAgICBlbmdpbmVzPUNTWzBd LENTWzFdKQorICoKKyAqCVJlc3VsdHMgaW4gdGhlIGZvbGxvd2luZyB2YWxpZCBwbGFjZW1lbnQ6 CisgKglDU1swXSwgQ1NbMV0KKyAqCisgKglFeGFtcGxlIDIgcHNldWRvIGNvZGU6CisgKglDU1tY XSA9IGdlbmVyaWMgZW5naW5lIG9mIHNhbWUgY2xhc3MsIGxvZ2ljYWwgaW5zdGFuY2UgWAorICoJ SU5WQUxJRCA9IEk5MTVfRU5HSU5FX0NMQVNTX0lOVkFMSUQsIEk5MTVfRU5HSU5FX0NMQVNTX0lO VkFMSURfTk9ORQorICoJc2V0X2VuZ2luZXMoSU5WQUxJRCkKKyAqCXNldF9wYXJhbGxlbChlbmdp bmVfaW5kZXg9MCwgd2lkdGg9MiwgbnVtX3NpYmxpbmdzPTIsCisgKgkJICAgICBlbmdpbmVzPUNT WzBdLENTWzJdLENTWzFdLENTWzNdKQorICoKKyAqCVJlc3VsdHMgaW4gdGhlIGZvbGxvd2luZyB2 YWxpZCBwbGFjZW1lbnRzOgorICoJQ1NbMF0sIENTWzFdCisgKglDU1syXSwgQ1NbM10KKyAqCisg KglUaGlzIGNhbiBhbHNvIGJlIHRob3VnaHQgb2YgYXMgMiB2aXJ0dWFsIGVuZ2luZXMgZGVzY3Jp YmVkIGJ5IDItRCBhcnJheQorICoJaW4gdGhlIGVuZ2luZXMgdGhlIGZpZWxkIHdpdGggYm9uZHMg cGxhY2VkIGJldHdlZW4gZWFjaCBpbmRleCBvZiB0aGUKKyAqCXZpcnR1YWwgZW5naW5lcy4gZS5n LiBDU1swXSBpcyBib25kZWQgdG8gQ1NbMV0sIENTWzJdIGlzIGJvbmRlZCB0bworICoJQ1NbM10u CisgKglWRVswXSA9IENTWzBdLCBDU1syXQorICoJVkVbMV0gPSBDU1sxXSwgQ1NbM10KKyAqCisg KglFeGFtcGxlIDMgcHNldWRvIGNvZGU6CisgKglDU1tYXSA9IGdlbmVyaWMgZW5naW5lIG9mIHNh bWUgY2xhc3MsIGxvZ2ljYWwgaW5zdGFuY2UgWAorICoJSU5WQUxJRCA9IEk5MTVfRU5HSU5FX0NM QVNTX0lOVkFMSUQsIEk5MTVfRU5HSU5FX0NMQVNTX0lOVkFMSURfTk9ORQorICoJc2V0X2VuZ2lu ZXMoSU5WQUxJRCkKKyAqCXNldF9wYXJhbGxlbChlbmdpbmVfaW5kZXg9MCwgd2lkdGg9MiwgbnVt X3NpYmxpbmdzPTIsCisgKgkJICAgICBlbmdpbmVzPUNTWzBdLENTWzFdLENTWzFdLENTWzNdKQor ICoKKyAqCVJlc3VsdHMgaW4gdGhlIGZvbGxvd2luZyB2YWxpZCBhbmQgaW52YWxpZCBwbGFjZW1l bnRzOgorICoJQ1NbMF0sIENTWzFdCisgKglDU1sxXSwgQ1NbM10gLSBOb3QgbG9naWNhbCBjb250 aWd1b3VzLCByZXR1cm4gLUVJTlZBTAorICovCitzdHJ1Y3QgZHJtX2k5MTVfY29udGV4dF9lbmdp bmVzX3BhcmFsbGVsX3N1Ym1pdCB7CisJLyoqCisJICogQGJhc2U6IGJhc2UgdXNlciBleHRlbnNp b24uCisJICovCisJc3RydWN0IGk5MTVfdXNlcl9leHRlbnNpb24gYmFzZTsKKworCS8qKgorCSAq IEBlbmdpbmVfaW5kZXg6IHNsb3QgZm9yIHBhcmFsbGVsIGVuZ2luZQorCSAqLworCV9fdTE2IGVu Z2luZV9pbmRleDsKKworCS8qKgorCSAqIEB3aWR0aDogbnVtYmVyIG9mIGNvbnRleHRzIHBlciBw YXJhbGxlbCBlbmdpbmUKKwkgKi8KKwlfX3UxNiB3aWR0aDsKKworCS8qKgorCSAqIEBudW1fc2li bGluZ3M6IG51bWJlciBvZiBzaWJsaW5ncyBwZXIgY29udGV4dAorCSAqLworCV9fdTE2IG51bV9z aWJsaW5nczsKKworCS8qKgorCSAqIEBtYnoxNjogcmVzZXJ2ZWQgZm9yIGZ1dHVyZSB1c2U7IG11 c3QgYmUgemVybworCSAqLworCV9fdTE2IG1iejE2OworCisJLyoqCisJICogQGZsYWdzOiBhbGwg dW5kZWZpbmVkIGZsYWdzIG11c3QgYmUgemVybywgY3VycmVudGx5IG5vdCBkZWZpbmVkIGZsYWdz CisJICovCisJX191NjQgZmxhZ3M7CisKKwkvKioKKwkgKiBAbWJ6NjQ6IHJlc2VydmVkIGZvciBm dXR1cmUgdXNlOyBtdXN0IGJlIHplcm8KKwkgKi8KKwlfX3U2NCBtYno2NFszXTsKKworCS8qKgor CSAqIEBlbmdpbmVzOiAyLWQgYXJyYXkgb2YgZW5naW5lIGluc3RhbmNlcyB0byBjb25maWd1cmUg cGFyYWxsZWwgZW5naW5lCisJICoKKwkgKiBsZW5ndGggPSB3aWR0aCAoaSkgKiBudW1fc2libGlu Z3MgKGopCisJICogaW5kZXggPSBqICsgaSAqIG51bV9zaWJsaW5ncworCSAqLworCXN0cnVjdCBp OTE1X2VuZ2luZV9jbGFzc19pbnN0YW5jZSBlbmdpbmVzWzBdOworCit9IF9fYXR0cmlidXRlX18g KChwYWNrZWQpKTsKKwpkaWZmIC0tZ2l0IGEvRG9jdW1lbnRhdGlvbi9ncHUvcmZjL2k5MTVfc2No ZWR1bGVyLnJzdCBiL0RvY3VtZW50YXRpb24vZ3B1L3JmYy9pOTE1X3NjaGVkdWxlci5yc3QKaW5k ZXggN2FjZDM4NmE2YjQ5Li42Mzg0OWI1MGU2NjMgMTAwNjQ0Ci0tLSBhL0RvY3VtZW50YXRpb24v Z3B1L3JmYy9pOTE1X3NjaGVkdWxlci5yc3QKKysrIGIvRG9jdW1lbnRhdGlvbi9ncHUvcmZjL2k5 MTVfc2NoZWR1bGVyLnJzdApAQCAtODgsNCArODgsNjEgQEAgU3BlYyByZWZlcmVuY2VzOgogCiBO ZXcgcGFyYWxsZWwgc3VibWlzc2lvbiB1QVBJCiA9PT09PT09PT09PT09PT09PT09PT09PT09PT09 Ci1EZXRhaWxzIHRvIGNvbWUgaW4gYSBmb2xsb3dpbmcgcGF0Y2guCitUaGUgZXhpc3RpbmcgYm9u ZGluZyB1QVBJIGlzIGNvbXBsZXRlbHkgYnJva2VuIHdpdGggR3VDIHN1Ym1pc3Npb24gYmVjYXVz ZQord2hldGhlciBhIHN1Ym1pc3Npb24gaXMgYSBzaW5nbGUgY29udGV4dCBzdWJtaXQgb3IgcGFy YWxsZWwgc3VibWl0IGlzbid0IGtub3duCit1bnRpbCBleGVjYnVmIHRpbWUgYWN0aXZhdGVkIHZp YSB0aGUgSTkxNV9TVUJNSVRfRkVOQ0UuIFRvIHN1Ym1pdCBtdWx0aXBsZQorY29udGV4dHMgaW4g cGFyYWxsZWwgd2l0aCB0aGUgR3VDIHRoZSBjb250ZXh0IG11c3QgYmUgZXhwbGljaXRseSByZWdp c3RlcmVkIHdpdGgKK04gY29udGV4dHMgYW5kIGFsbCBOIGNvbnRleHRzIG11c3QgYmUgc3VibWl0 dGVkIGluIGEgc2luZ2xlIGNvbW1hbmQgdG8gdGhlIEd1Qy4KK1RoZSBHdUMgaW50ZXJmYWNlcyBk byBub3Qgc3VwcG9ydCBkeW5hbWljYWxseSBjaGFuZ2luZyBiZXR3ZWVuIE4gY29udGV4dHMgYXMg dGhlCitib25kaW5nIHVBUEkgZG9lcy4gSGVuY2UgdGhlIG5lZWQgZm9yIGEgbmV3IHBhcmFsbGVs IHN1Ym1pc3Npb24gaW50ZXJmYWNlLiBBbHNvCit0aGUgbGVnYWN5IGJvbmRpbmcgdUFQSSBpcyBx dWl0ZSBjb25mdXNpbmcgYW5kIG5vdCBpbnR1aXRpdmUgYXQgYWxsLiBGdXJ0aGVybW9yZQorSTkx NV9TVUJNSVRfRkVOQ0UgaXMgYnkgZGVzaWduIGEgZnV0dXJlIGZlbmNlLCBzbyBub3QgcmVhbGx5 IHNvbWV0aGluZyB3ZSBzaG91bGQKK2NvbnRpbnVlIHRvIHN1cHBvcnQuCisKK1RoZSBuZXcgcGFy YWxsZWwgc3VibWlzc2lvbiB1QVBJIGNvbnNpc3RzIG9mIDMgcGFydHM6CisKKyogRXhwb3J0IGVu Z2luZXMgbG9naWNhbCBtYXBwaW5nCisqIEEgJ3NldF9wYXJhbGxlbCcgZXh0ZW5zaW9uIHRvIGNv bmZpZ3VyZSBjb250ZXh0cyBmb3IgcGFyYWxsZWwKKyAgc3VibWlzc2lvbgorKiBFeHRlbmQgZXhl Y2J1ZjIgSU9DVEwgdG8gc3VwcG9ydCBzdWJtaXR0aW5nIE4gQkJzIGluIGEgc2luZ2xlIElPQ1RM CisKK0V4cG9ydCBlbmdpbmVzIGxvZ2ljYWwgbWFwcGluZworLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tCitDZXJ0YWluIHVzZSBjYXNlcyByZXF1aXJlIEJCcyB0byBiZSBwbGFjZWQgb24g ZW5naW5lIGluc3RhbmNlcyBpbiBsb2dpY2FsIG9yZGVyCisoZS5nLiBzcGxpdC1mcmFtZSBvbiBn ZW4xMSspLiBUaGUgbG9naWNhbCBtYXBwaW5nIG9mIGVuZ2luZSBpbnN0YW5jZXMgY2FuIGNoYW5n ZQorYmFzZWQgb24gZnVzaW5nLiBSYXRoZXIgdGhhbiBtYWtpbmcgVU1EcyBiZSBhd2FyZSBvZiBm dXNpbmcsIHNpbXBseSBleHBvc2UgdGhlCitsb2dpY2FsIG1hcHBpbmcgd2l0aCB0aGUgZXhpc3Rp bmcgcXVlcnkgZW5naW5lIGluZm8gSU9DVEwuIEFsc28gdGhlIEd1Qworc3VibWlzc2lvbiBpbnRl cmZhY2UgY3VycmVudGx5IG9ubHkgc3VwcG9ydHMgc3VibWl0dGluZyBtdWx0aXBsZSBjb250ZXh0 cyB0bworZW5naW5lcyBpbiBsb2dpY2FsIG9yZGVyIHdoaWNoIGlzIGEgbmV3IHJlcXVpcmVtZW50 IGNvbXBhcmVkIHRvIGV4ZWNsaXN0cy4KK0xhc3RseSwgYWxsIGN1cnJlbnQgcGxhdGZvcm1zIGhh dmUgYXQgbW9zdCAyIGVuZ2luZSBpbnN0YW5jZXMgYW5kIHRoZSBsb2dpY2FsCitvcmRlciBpcyB0 aGUgc2FtZSBhcyB1QVBJIG9yZGVyLiBUaGlzIHdpbGwgY2hhbmdlIG9uIHBsYXRmb3JtcyB3aXRo IG1vcmUgdGhhbiAyCitlbmdpbmUgaW5zdGFuY2VzLgorCitBIHNpbmdsZSBiaXQgd2lsbCBiZSBh ZGRlZCB0byBkcm1faTkxNV9lbmdpbmVfaW5mby5mbGFncyBpbmRpY2F0aW5nIHRoYXQgdGhlCits b2dpY2FsIGluc3RhbmNlIGhhcyBiZWVuIHJldHVybmVkIGFuZCBhIG5ldyBmaWVsZCwKK2RybV9p OTE1X2VuZ2luZV9pbmZvLmxvZ2ljYWxfaW5zdGFuY2UsIHJldHVybnMgdGhlIGxvZ2ljYWwgaW5z dGFuY2UuCisKK0EgJ3NldF9wYXJhbGxlbCcgZXh0ZW5zaW9uIHRvIGNvbmZpZ3VyZSBjb250ZXh0 cyBmb3IgcGFyYWxsZWwgc3VibWlzc2lvbgorLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tCitUaGUgJ3NldF9wYXJh bGxlbCcgZXh0ZW5zaW9uIGNvbmZpZ3VyZXMgYSBzbG90IGZvciBwYXJhbGxlbCBzdWJtaXNzaW9u IG9mIE4gQkJzLgorSXQgaXMgYSBzZXR1cCBzdGVwIHRoYXQgbXVzdCBiZSBjYWxsZWQgYmVmb3Jl IHVzaW5nIGFueSBvZiB0aGUgY29udGV4dHMuIFNlZQorSTkxNV9DT05URVhUX0VOR0lORVNfRVhU X0xPQURfQkFMQU5DRSBvciBJOTE1X0NPTlRFWFRfRU5HSU5FU19FWFRfQk9ORCBmb3IKK3NpbWls YXIgZXhpc3RpbmcgZXhhbXBsZXMuIE9uY2UgYSBzbG90IGlzIGNvbmZpZ3VyZWQgZm9yIHBhcmFs bGVsIHN1Ym1pc3Npb24gdGhlCitleGVjYnVmMiBJT0NUTCBjYW4gYmUgY2FsbGVkIHN1Ym1pdHRp bmcgTiBCQnMgaW4gYSBzaW5nbGUgSU9DVEwuIEluaXRpYWxseSBvbmx5CitzdXBwb3J0cyBHdUMg c3VibWlzc2lvbi4gRXhlY2xpc3RzIHN1cHBvcnRzIGNhbiBiZSBhZGRlZCBsYXRlciBpZiBuZWVk ZWQuCisKK0FkZCBJOTE1X0NPTlRFWFRfRU5HSU5FU19FWFRfUEFSQUxMRUxfU1VCTUlUIGFuZAor ZHJtX2k5MTVfY29udGV4dF9lbmdpbmVzX3BhcmFsbGVsX3N1Ym1pdCB0byB0aGUgdUFQSSB0byBp bXBsZW1lbnQgdGhpcworZXh0ZW5zaW9uLgorCisuLiBrZXJuZWwtZG9jOjogRG9jdW1lbnRhdGlv bi9ncHUvcmZjL2k5MTVfcGFyYWxsZWxfZXhlY2J1Zi5oCisgICAgICAgIDpmdW5jdGlvbnM6IGRy bV9pOTE1X2NvbnRleHRfZW5naW5lc19wYXJhbGxlbF9zdWJtaXQKKworRXh0ZW5kIGV4ZWNidWYy IElPQ1RMIHRvIHN1cHBvcnQgc3VibWl0dGluZyBOIEJCcyBpbiBhIHNpbmdsZSBJT0NUTAorLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLQorQ29udGV4dHMgdGhhdCBoYXZlIGJlZW4gY29uZmlndXJlZCB3aXRoIHRoZSAnc2V0 X3BhcmFsbGVsJyBleHRlbnNpb24gY2FuIG9ubHkKK3N1Ym1pdCBOIEJCcyBpbiBhIHNpbmdsZSBl eGVjYnVmMiBJT0NUTC4gVGhlIEJCcyBhcmUgZWl0aGVyIHRoZSBsYXN0IE4gb2JqZWN0cworaW4g aW4gdGhlIGRybV9pOTE1X2dlbV9leGVjX29iamVjdDIgbGlzdCBvciB0aGUgZmlyc3QgTiBpZiBJ OTE1X0VYRUNfQkFUQ0hfRklSU1QKK2lzIHNldC4gVGhlIG51bWJlciBvZiBCQnMgaXMgaW1wbGlj aXQgYmFzZWQgb24gdGhlIHNsb3Qgc3VibWl0dGVkIGFuZCBob3cgaXQgaGFzCitiZWVuIGNvbmZp Z3VyZWQgYnkgJ3NldF9wYXJhbGxlbCcgb3Igb3RoZXIgZXh0ZW5zaW9ucy4gTm8gdUFQSSBjaGFu Z2VzIGFyZQorcmVxdWlyZWQgdG8gZXhlY2J1ZjIgSU9DVEwuCi0tIAoyLjI4LjAKCl9fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWlsaW5n IGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVk ZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo=