From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_2 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F777C48BDF for ; Sun, 13 Jun 2021 22:14:29 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9015861159 for ; Sun, 13 Jun 2021 22:14:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9015861159 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5967F80F34; Mon, 14 Jun 2021 00:14:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 32E2280F3A; Mon, 14 Jun 2021 00:14:24 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 1DE7580A22 for ; Mon, 14 Jun 2021 00:14:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=andre.przywara@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 60E716D; Sun, 13 Jun 2021 15:14:20 -0700 (PDT) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D2FD53F694; Sun, 13 Jun 2021 15:14:19 -0700 (PDT) Date: Sun, 13 Jun 2021 23:14:11 +0100 From: Andre Przywara To: Suniel Mahesh Cc: U-Boot-Denx Subject: Re: Reset cause register for Allwinner H3/R16 SOC's Message-ID: <20210613231411.7d4fb5db@slackpad.fritz.box> In-Reply-To: References: Organization: Arm Ltd. X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On Sat, 12 Jun 2021 10:17:08 +0530 Suniel Mahesh wrote: > Hi All, > > I am working on an Allwinner R16 and H3 based targets and I am implementing > system update. > > Is there any way(or a register) on Allwinner R16/H3 which can tell > what is the cause > of the reset(whether the reset is triggered by a watchdog or thermal > or reset or a POR). I don't think anybody found such an explicit gadget in Allwinner chips before. Besides, what would be the difference between watchdog, thermal and reset? AFAIK those are all the same watchdog triggered reset, in the last two cases deliberately triggered. If you want to convey information across a reset, you can use the RTC data registers: they survive a reset. So you can explicitly write some reset cause indicator value into one of the registers, then read that back after the reset. For power-on-reset there might be some heuristics to tell it apart from a mere reset (temperature, PMIC state, DRAM content?), but in general the RTC register method should also work here. So if you are happy to hack some board specifics into your firmware, it should be doable, but there does not seem to be a generic mechanism implemented into the SoC. Cheers, Andre