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Mon, 14 Jun 2021 03:09:13 -0700 (PDT) Received: from localhost.localdomain ([37.161.140.231]) by smtp.gmail.com with ESMTPSA id o18sm15752254wrx.59.2021.06.14.03.09.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jun 2021 03:09:13 -0700 (PDT) From: Lara Lazier To: qemu-devel@nongnu.org Subject: [PATCH 3/3] target/i386: Added Intercept CR0 writes check Date: Mon, 14 Jun 2021 12:09:02 +0200 Message-Id: <20210614100902.15860-4-laramglazier@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210614100902.15860-1-laramglazier@gmail.com> References: <20210614100902.15860-1-laramglazier@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=laramglazier@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lara Lazier Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" When the selective CR0 write intercept is set, all writes to bits in CR0 other than CR0.TS or CR0.MP cause a VMEXIT. Signed-off-by: Lara Lazier --- target/i386/cpu.h | 2 ++ target/i386/tcg/sysemu/misc_helper.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 46542513cc..ff0ff97ca9 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -228,6 +228,8 @@ typedef enum X86Seg { #define CR0_CD_MASK (1U << 30) #define CR0_PG_MASK (1U << 31) +#define INTERCEPT_SELECTIVE_CR0 (1ULL << 5) + #define CR4_VME_MASK (1U << 0) #define CR4_PVI_MASK (1U << 1) #define CR4_TSD_MASK (1U << 2) diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index 0cef2f1a4c..53117f47de 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -84,6 +84,15 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) { switch (reg) { case 0: + /* + * If we reach this point, the CR0 write intercept is disabled. + * But we could still exit if the hypervisor has requested the selective + * intercept for bits other than TS and MP + */ + if ((env->intercept & INTERCEPT_SELECTIVE_CR0) && + ((env->cr[0] ^ t0) & ~(CR0_TS_MASK | CR0_MP_MASK))) { + cpu_vmexit(env, SVM_EXIT_CR0_SEL_WRITE, 0, GETPC()); + } cpu_x86_update_cr0(env, t0); break; case 3: -- 2.25.1