rebased ASID-based tlbflush

rebased ASID-based tlbflush

[Christoph Hellwig]

Hi all,

this is what I think is a resonable set of patches for the ASID based
flushing, largely based on the work from Guo and thus attributed to him.



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[PATCH 1/2] riscv: pass the mm_struct to __sbi_tlb_flush_range

[Christoph Hellwig]

Move the call mm_cpumask from the callers into __sbi_tlb_flush_range to
reduce a bit of duplicate code and prepare for future changes.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/riscv/mm/tlbflush.c | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index fea45af91f53..b458949fa8df 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -10,13 +10,10 @@ void flush_tlb_all(void)
 	sbi_remote_sfence_vma(NULL, 0, -1);
 }
 
-/*
- * This function must not be called with cmask being null.
- * Kernel may panic if cmask is NULL.
- */
-static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start,
+static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start,
 				  unsigned long size, unsigned long stride)
 {
+	struct cpumask *cmask = mm_cpumask(mm);
 	struct cpumask hmask;
 	unsigned int cpuid;
 
@@ -41,23 +38,23 @@ static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start,
 
 void flush_tlb_mm(struct mm_struct *mm)
 {
-	__sbi_tlb_flush_range(mm_cpumask(mm), 0, -1, PAGE_SIZE);
+	__sbi_tlb_flush_range(mm, 0, -1, PAGE_SIZE);
 }
 
 void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
 {
-	__sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE, PAGE_SIZE);
+	__sbi_tlb_flush_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE);
 }
 
 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 		     unsigned long end)
 {
-	__sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start, PAGE_SIZE);
+	__sbi_tlb_flush_range(vma->vm_mm, start, end - start, PAGE_SIZE);
 }
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
 			unsigned long end)
 {
-	__sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start, PMD_SIZE);
+	__sbi_tlb_flush_range(vma->vm_mm, start, end - start, PMD_SIZE);
 }
 #endif
-- 
2.30.2


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[PATCH 2/2] riscv: add ASID-based tlbflushing methods

[Christoph Hellwig]

From: Guo Ren <guoren@linux.alibaba.com>

Implement optimized version of the tlb flushing routines for systems
using ASIDs. These are behind the use_asid_allocator static branch to
not affect existing systems not using ASIDs.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
[hch: rebased on top of previous cleanups, use the same algorithm as
      the non-ASID based code for local vs global flushes, keep functions
      as local as possible]
Signed-off-by: Christoph Hellwig <hch@lst.de>
---
 arch/riscv/include/asm/mmu_context.h |  2 ++
 arch/riscv/mm/context.c              |  2 +-
 arch/riscv/mm/tlbflush.c             | 47 +++++++++++++++++++++++-----
 3 files changed, 43 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/mmu_context.h
index b0659413a080..7030837adc1a 100644
--- a/arch/riscv/include/asm/mmu_context.h
+++ b/arch/riscv/include/asm/mmu_context.h
@@ -33,6 +33,8 @@ static inline int init_new_context(struct task_struct *tsk,
 	return 0;
 }
 
+DECLARE_STATIC_KEY_FALSE(use_asid_allocator);
+
 #include <asm-generic/mmu_context.h>
 
 #endif /* _ASM_RISCV_MMU_CONTEXT_H */
diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c
index 9bc46ab01c25..6ed696bad558 100644
--- a/arch/riscv/mm/context.c
+++ b/arch/riscv/mm/context.c
@@ -18,7 +18,7 @@
 
 #ifdef CONFIG_MMU
 
-static DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
+DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
 
 static unsigned long asid_bits;
 static unsigned long num_asids;
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index b458949fa8df..64f8201237c2 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -4,6 +4,24 @@
 #include <linux/smp.h>
 #include <linux/sched.h>
 #include <asm/sbi.h>
+#include <asm/mmu_context.h>
+
+static inline void local_flush_tlb_all_asid(unsigned long asid)
+{
+	__asm__ __volatile__ ("sfence.vma x0, %0"
+			:
+			: "r" (asid)
+			: "memory");
+}
+
+static inline void local_flush_tlb_page_asid(unsigned long addr,
+		unsigned long asid)
+{
+	__asm__ __volatile__ ("sfence.vma %0, %1"
+			:
+			: "r" (addr), "r" (asid)
+			: "memory");
+}
 
 void flush_tlb_all(void)
 {
@@ -16,21 +34,36 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start,
 	struct cpumask *cmask = mm_cpumask(mm);
 	struct cpumask hmask;
 	unsigned int cpuid;
+	bool broadcast;
 
 	if (cpumask_empty(cmask))
 		return;
 
 	cpuid = get_cpu();
+	/* check if the tlbflush needs to be sent to other CPUs */
+	broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids;
+	if (static_branch_unlikely(&use_asid_allocator)) {
+		unsigned long asid = atomic_long_read(&mm->context.id);
 
-	if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids) {
-		/* local cpu is the only cpu present in cpumask */
-		if (size <= stride)
+		if (broadcast) {
+			riscv_cpuid_to_hartid_mask(cmask, &hmask);
+			sbi_remote_sfence_vma_asid(cpumask_bits(&hmask),
+						   start, size, asid);
+		} else if (size <= stride) {
+			local_flush_tlb_page_asid(start, asid);
+		} else {
+			local_flush_tlb_all_asid(asid);
+		}
+	} else {
+		if (broadcast) {
+			riscv_cpuid_to_hartid_mask(cmask, &hmask);
+			sbi_remote_sfence_vma(cpumask_bits(&hmask),
+					      start, size);
+		} else if (size <= stride) {
 			local_flush_tlb_page(start);
-		else
+		} else {
 			local_flush_tlb_all();
-	} else {
-		riscv_cpuid_to_hartid_mask(cmask, &hmask);
-		sbi_remote_sfence_vma(cpumask_bits(&hmask), start, size);
+		}
 	}
 
 	put_cpu();
-- 
2.30.2


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Re: [PATCH 1/2] riscv: pass the mm_struct to __sbi_tlb_flush_range

[Guo Ren]

Rebase with "THP supprt for RISCV" & "Add DMA_COHERENT v2" on linux-5.13-rc4.

Tested-by: Guo Ren <guoren@kernel.org>

On Sun, Jun 6, 2021 at 11:21 PM Christoph Hellwig <hch@lst.de> wrote:
>
> Move the call mm_cpumask from the callers into __sbi_tlb_flush_range to
> reduce a bit of duplicate code and prepare for future changes.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
>  arch/riscv/mm/tlbflush.c | 15 ++++++---------
>  1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> index fea45af91f53..b458949fa8df 100644
> --- a/arch/riscv/mm/tlbflush.c
> +++ b/arch/riscv/mm/tlbflush.c
> @@ -10,13 +10,10 @@ void flush_tlb_all(void)
>         sbi_remote_sfence_vma(NULL, 0, -1);
>  }
>
> -/*
> - * This function must not be called with cmask being null.
> - * Kernel may panic if cmask is NULL.
> - */
> -static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start,
> +static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start,
>                                   unsigned long size, unsigned long stride)
>  {
> +       struct cpumask *cmask = mm_cpumask(mm);
>         struct cpumask hmask;
>         unsigned int cpuid;
>
> @@ -41,23 +38,23 @@ static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start,
>
>  void flush_tlb_mm(struct mm_struct *mm)
>  {
> -       __sbi_tlb_flush_range(mm_cpumask(mm), 0, -1, PAGE_SIZE);
> +       __sbi_tlb_flush_range(mm, 0, -1, PAGE_SIZE);
>  }
>
>  void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
>  {
> -       __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE, PAGE_SIZE);
> +       __sbi_tlb_flush_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE);
>  }
>
>  void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
>                      unsigned long end)
>  {
> -       __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start, PAGE_SIZE);
> +       __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PAGE_SIZE);
>  }
>  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
>  void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
>                         unsigned long end)
>  {
> -       __sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start, PMD_SIZE);
> +       __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PMD_SIZE);
>  }
>  #endif
> --
> 2.30.2
>


--
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

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Re: [PATCH 2/2] riscv: add ASID-based tlbflushing methods

[Guo Ren]

Rebase with "THP supprt for RISCV" & "Add DMA_COHERENT v2" on linux-5.13-rc4.

Tested-by: Guo Ren <guoren@kernel.org>

On Sun, Jun 6, 2021 at 11:21 PM Christoph Hellwig <hch@lst.de> wrote:
>
> From: Guo Ren <guoren@linux.alibaba.com>
>
> Implement optimized version of the tlb flushing routines for systems
> using ASIDs. These are behind the use_asid_allocator static branch to
> not affect existing systems not using ASIDs.
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> [hch: rebased on top of previous cleanups, use the same algorithm as
>       the non-ASID based code for local vs global flushes, keep functions
>       as local as possible]
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
>  arch/riscv/include/asm/mmu_context.h |  2 ++
>  arch/riscv/mm/context.c              |  2 +-
>  arch/riscv/mm/tlbflush.c             | 47 +++++++++++++++++++++++-----
>  3 files changed, 43 insertions(+), 8 deletions(-)
>
> diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/mmu_context.h
> index b0659413a080..7030837adc1a 100644
> --- a/arch/riscv/include/asm/mmu_context.h
> +++ b/arch/riscv/include/asm/mmu_context.h
> @@ -33,6 +33,8 @@ static inline int init_new_context(struct task_struct *tsk,
>         return 0;
>  }
>
> +DECLARE_STATIC_KEY_FALSE(use_asid_allocator);
> +
>  #include <asm-generic/mmu_context.h>
>
>  #endif /* _ASM_RISCV_MMU_CONTEXT_H */
> diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c
> index 9bc46ab01c25..6ed696bad558 100644
> --- a/arch/riscv/mm/context.c
> +++ b/arch/riscv/mm/context.c
> @@ -18,7 +18,7 @@
>
>  #ifdef CONFIG_MMU
>
> -static DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
> +DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
>
>  static unsigned long asid_bits;
>  static unsigned long num_asids;
> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> index b458949fa8df..64f8201237c2 100644
> --- a/arch/riscv/mm/tlbflush.c
> +++ b/arch/riscv/mm/tlbflush.c
> @@ -4,6 +4,24 @@
>  #include <linux/smp.h>
>  #include <linux/sched.h>
>  #include <asm/sbi.h>
> +#include <asm/mmu_context.h>
> +
> +static inline void local_flush_tlb_all_asid(unsigned long asid)
> +{
> +       __asm__ __volatile__ ("sfence.vma x0, %0"
> +                       :
> +                       : "r" (asid)
> +                       : "memory");
> +}
> +
> +static inline void local_flush_tlb_page_asid(unsigned long addr,
> +               unsigned long asid)
> +{
> +       __asm__ __volatile__ ("sfence.vma %0, %1"
> +                       :
> +                       : "r" (addr), "r" (asid)
> +                       : "memory");
> +}
>
>  void flush_tlb_all(void)
>  {
> @@ -16,21 +34,36 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start,
>         struct cpumask *cmask = mm_cpumask(mm);
>         struct cpumask hmask;
>         unsigned int cpuid;
> +       bool broadcast;
>
>         if (cpumask_empty(cmask))
>                 return;
>
>         cpuid = get_cpu();
> +       /* check if the tlbflush needs to be sent to other CPUs */
> +       broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids;
> +       if (static_branch_unlikely(&use_asid_allocator)) {
> +               unsigned long asid = atomic_long_read(&mm->context.id);
>
> -       if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids) {
> -               /* local cpu is the only cpu present in cpumask */
> -               if (size <= stride)
> +               if (broadcast) {
> +                       riscv_cpuid_to_hartid_mask(cmask, &hmask);
> +                       sbi_remote_sfence_vma_asid(cpumask_bits(&hmask),
> +                                                  start, size, asid);
> +               } else if (size <= stride) {
> +                       local_flush_tlb_page_asid(start, asid);
> +               } else {
> +                       local_flush_tlb_all_asid(asid);
> +               }
It will reduce efficiency in our system, but I'll add
"local_flush_tlb_range_asid(start, start+size, stride, size)" later.

> +       } else {
> +               if (broadcast) {
> +                       riscv_cpuid_to_hartid_mask(cmask, &hmask);
> +                       sbi_remote_sfence_vma(cpumask_bits(&hmask),
> +                                             start, size);
> +               } else if (size <= stride) {
This logic is from the Atish's patch.
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/arch/riscv/mm/tlbflush.c?h=next-20210604&id=6efb16b1d5514865d0f7a01910648568ad3225d8

I don't know why not use the range? Maybe fix some hardware issues.

>                         local_flush_tlb_page(start);
> -               else
> +               } else {
>                         local_flush_tlb_all();
> -       } else {
> -               riscv_cpuid_to_hartid_mask(cmask, &hmask);
> -               sbi_remote_sfence_vma(cpumask_bits(&hmask), start, size);
> +               }
>         }
>
>         put_cpu();
> --
> 2.30.2
>


-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

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Re: rebased ASID-based tlbflush

[Palmer Dabbelt]

On Sun, 06 Jun 2021 08:20:48 PDT (-0700), Christoph Hellwig wrote:
> Hi all,
>
> this is what I think is a resonable set of patches for the ASID based
> flushing, largely based on the work from Guo and thus attributed to him.

Thanks, these are on for-next.

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Re: rebased ASID-based tlbflush

[Guo Ren]

On Sun, Jun 6, 2021 at 11:21 PM Christoph Hellwig <hch@lst.de> wrote:
>
> Hi all,
>
> this is what I think is a resonable set of patches for the ASID based
> flushing, largely based on the work from Guo and thus attributed to him.
Thanks for the review & modification.

-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

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Re: rebased ASID-based tlbflush

[Guo Ren]

I've just tested your for-next, but:

 LD      .tmp_vmlinux.kallsyms1
/home/guoren/source/buildroot/thead_9xx_compat_5.10_glibc_br_defconfig/host/bin/riscv64-linux-ld:
mm/vmalloc.o: in function `.L0 ':
vmalloc.c:(.text+0x2bd2): undefined reference to `pud_clear_huge'
/home/guoren/source/buildroot/thead_9xx_compat_5.10_glibc_br_defconfig/host/bin/riscv64-linux-ld:
mm/vmalloc.o: in function `.L1225':
vmalloc.c:(.text+0x2cac): undefined reference to `pud_clear_huge'
Makefile:1191: recipe for target 'vmlinux' failed

I quick fixup with the simple patch:
diff --git a/arch/riscv/mm/pgtable.c b/arch/riscv/mm/pgtable.c
index 738dc6f3530f..b1fbd575cbac 100644
--- a/arch/riscv/mm/pgtable.c
+++ b/arch/riscv/mm/pgtable.c
@@ -25,6 +25,14 @@ int pmd_clear_huge(pmd_t *pmd)
 }
 #endif

+int pud_clear_huge(pud_t *pudp)
+{
+       if (!pud_leaf(READ_ONCE(*pudp)))
+               return 0;
+       pud_clear(pudp);
+       return 1;
+}
+
 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
 {
        pte_t *pte;

I think it's from:
commit 14512690a16537527dacf0f5cd3d2263be317f35
Author: Liu Shixin <liushixin2@huawei.com>
Date:   Sat Jun 5 13:48:37 2021 +0800

    riscv: Enable HAVE_ARCH_HUGE_VMAP for 64BIT

    This sets the HAVE_ARCH_HUGE_VMAP option. Enable pmd vmap support and
    define the required page table functions(Currently, riscv has only
    three-level page tables support for 64BIT).

    Signed-off-by: Liu Shixin <liushixin2@huawei.com>
    Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>

On Sun, Jun 13, 2021 at 8:47 AM Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>
> On Sun, 06 Jun 2021 08:20:48 PDT (-0700), Christoph Hellwig wrote:
> > Hi all,
> >
> > this is what I think is a resonable set of patches for the ASID based
> > flushing, largely based on the work from Guo and thus attributed to him.
>
> Thanks, these are on for-next.



-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

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Re: rebased ASID-based tlbflush

[Liu Shixin]

On 2021/6/13 21:08, Guo Ren wrote:
> I've just tested your for-next, but:
>
>  LD      .tmp_vmlinux.kallsyms1
> /home/guoren/source/buildroot/thead_9xx_compat_5.10_glibc_br_defconfig/host/bin/riscv64-linux-ld:
> mm/vmalloc.o: in function `.L0 ':
> vmalloc.c:(.text+0x2bd2): undefined reference to `pud_clear_huge'
> /home/guoren/source/buildroot/thead_9xx_compat_5.10_glibc_br_defconfig/host/bin/riscv64-linux-ld:
> mm/vmalloc.o: in function `.L1225':
> vmalloc.c:(.text+0x2cac): undefined reference to `pud_clear_huge'
> Makefile:1191: recipe for target 'vmlinux' failed
>
> I quick fixup with the simple patch:
> diff --git a/arch/riscv/mm/pgtable.c b/arch/riscv/mm/pgtable.c
> index 738dc6f3530f..b1fbd575cbac 100644
> --- a/arch/riscv/mm/pgtable.c
> +++ b/arch/riscv/mm/pgtable.c
> @@ -25,6 +25,14 @@ int pmd_clear_huge(pmd_t *pmd)
>  }
>  #endif
>
> +int pud_clear_huge(pud_t *pudp)
> +{
> +       if (!pud_leaf(READ_ONCE(*pudp)))
> +               return 0;
> +       pud_clear(pudp);
> +       return 1;
> +}
> +
>  int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
>  {
>         pte_t *pte;
>
> I think it's from:
> commit 14512690a16537527dacf0f5cd3d2263be317f35
> Author: Liu Shixin <liushixin2@huawei.com>
> Date:   Sat Jun 5 13:48:37 2021 +0800
>
>     riscv: Enable HAVE_ARCH_HUGE_VMAP for 64BIT
>
>     This sets the HAVE_ARCH_HUGE_VMAP option. Enable pmd vmap support and
>     define the required page table functions(Currently, riscv has only
>     three-level page tables support for 64BIT).
>
>     Signed-off-by: Liu Shixin <liushixin2@huawei.com>
>     Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is based on linux-next. pud_clear_huge() have been defined in pre-commit
("mm/pgtable: add stubs for {pmd/pub}_{set/clear}_huge") which is not on for-next.
The code is different and thus an error is reported here.
Should I rebase the patch on for-next and resend it?

thanks,
> On Sun, Jun 13, 2021 at 8:47 AM Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>> On Sun, 06 Jun 2021 08:20:48 PDT (-0700), Christoph Hellwig wrote:
>>> Hi all,
>>>
>>> this is what I think is a resonable set of patches for the ASID based
>>> flushing, largely based on the work from Guo and thus attributed to him.
>> Thanks, these are on for-next.
>
>


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Re: rebased ASID-based tlbflush

[Palmer Dabbelt]

On Tue, 15 Jun 2021 04:20:44 PDT (-0700), liushixin2@huawei.com wrote:
> On 2021/6/13 21:08, Guo Ren wrote:
>> I've just tested your for-next, but:
>>
>>  LD      .tmp_vmlinux.kallsyms1
>> /home/guoren/source/buildroot/thead_9xx_compat_5.10_glibc_br_defconfig/host/bin/riscv64-linux-ld:
>> mm/vmalloc.o: in function `.L0 ':
>> vmalloc.c:(.text+0x2bd2): undefined reference to `pud_clear_huge'
>> /home/guoren/source/buildroot/thead_9xx_compat_5.10_glibc_br_defconfig/host/bin/riscv64-linux-ld:
>> mm/vmalloc.o: in function `.L1225':
>> vmalloc.c:(.text+0x2cac): undefined reference to `pud_clear_huge'
>> Makefile:1191: recipe for target 'vmlinux' failed
>>
>> I quick fixup with the simple patch:
>> diff --git a/arch/riscv/mm/pgtable.c b/arch/riscv/mm/pgtable.c
>> index 738dc6f3530f..b1fbd575cbac 100644
>> --- a/arch/riscv/mm/pgtable.c
>> +++ b/arch/riscv/mm/pgtable.c
>> @@ -25,6 +25,14 @@ int pmd_clear_huge(pmd_t *pmd)
>>  }
>>  #endif
>>
>> +int pud_clear_huge(pud_t *pudp)
>> +{
>> +       if (!pud_leaf(READ_ONCE(*pudp)))
>> +               return 0;
>> +       pud_clear(pudp);
>> +       return 1;
>> +}
>> +
>>  int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
>>  {
>>         pte_t *pte;
>>
>> I think it's from:
>> commit 14512690a16537527dacf0f5cd3d2263be317f35
>> Author: Liu Shixin <liushixin2@huawei.com>
>> Date:   Sat Jun 5 13:48:37 2021 +0800
>>
>>     riscv: Enable HAVE_ARCH_HUGE_VMAP for 64BIT
>>
>>     This sets the HAVE_ARCH_HUGE_VMAP option. Enable pmd vmap support and
>>     define the required page table functions(Currently, riscv has only
>>     three-level page tables support for 64BIT).
>>
>>     Signed-off-by: Liu Shixin <liushixin2@huawei.com>
>>     Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
> This commit is based on linux-next. pud_clear_huge() have been defined in pre-commit
> ("mm/pgtable: add stubs for {pmd/pub}_{set/clear}_huge") which is not on for-next.
> The code is different and thus an error is reported here.
> Should I rebase the patch on for-next and resend it?

I can't find that commit anywhere, can you send a series with the 
dependencies?

I've removed the HUGE_VMAP patch from for-next.

>
> thanks,
>> On Sun, Jun 13, 2021 at 8:47 AM Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>>> On Sun, 06 Jun 2021 08:20:48 PDT (-0700), Christoph Hellwig wrote:
>>>> Hi all,
>>>>
>>>> this is what I think is a resonable set of patches for the ASID based
>>>> flushing, largely based on the work from Guo and thus attributed to him.
>>> Thanks, these are on for-next.
>>
>>

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Re: rebased ASID-based tlbflush

[Guo Ren]

On Tue, Jun 15, 2021 at 11:10 PM Palmer Dabbelt
<palmerdabbelt@google.com> wrote:
>
> On Tue, 15 Jun 2021 04:20:44 PDT (-0700), liushixin2@huawei.com wrote:
> > On 2021/6/13 21:08, Guo Ren wrote:
> >> I've just tested your for-next, but:
> >>
> >>  LD      .tmp_vmlinux.kallsyms1
> >> /home/guoren/source/buildroot/thead_9xx_compat_5.10_glibc_br_defconfig/host/bin/riscv64-linux-ld:
> >> mm/vmalloc.o: in function `.L0 ':
> >> vmalloc.c:(.text+0x2bd2): undefined reference to `pud_clear_huge'
> >> /home/guoren/source/buildroot/thead_9xx_compat_5.10_glibc_br_defconfig/host/bin/riscv64-linux-ld:
> >> mm/vmalloc.o: in function `.L1225':
> >> vmalloc.c:(.text+0x2cac): undefined reference to `pud_clear_huge'
> >> Makefile:1191: recipe for target 'vmlinux' failed
> >>
> >> I quick fixup with the simple patch:
> >> diff --git a/arch/riscv/mm/pgtable.c b/arch/riscv/mm/pgtable.c
> >> index 738dc6f3530f..b1fbd575cbac 100644
> >> --- a/arch/riscv/mm/pgtable.c
> >> +++ b/arch/riscv/mm/pgtable.c
> >> @@ -25,6 +25,14 @@ int pmd_clear_huge(pmd_t *pmd)
> >>  }
> >>  #endif
> >>
> >> +int pud_clear_huge(pud_t *pudp)
> >> +{
> >> +       if (!pud_leaf(READ_ONCE(*pudp)))
> >> +               return 0;
> >> +       pud_clear(pudp);
> >> +       return 1;
> >> +}
> >> +
> >>  int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
> >>  {
> >>         pte_t *pte;
> >>
> >> I think it's from:
> >> commit 14512690a16537527dacf0f5cd3d2263be317f35
> >> Author: Liu Shixin <liushixin2@huawei.com>
> >> Date:   Sat Jun 5 13:48:37 2021 +0800
> >>
> >>     riscv: Enable HAVE_ARCH_HUGE_VMAP for 64BIT
> >>
> >>     This sets the HAVE_ARCH_HUGE_VMAP option. Enable pmd vmap support and
> >>     define the required page table functions(Currently, riscv has only
> >>     three-level page tables support for 64BIT).
> >>
> >>     Signed-off-by: Liu Shixin <liushixin2@huawei.com>
> >>     Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
> > This commit is based on linux-next. pud_clear_huge() have been defined in pre-commit
> > ("mm/pgtable: add stubs for {pmd/pub}_{set/clear}_huge") which is not on for-next.
> > The code is different and thus an error is reported here.
> > Should I rebase the patch on for-next and resend it?
>
> I can't find that commit anywhere, can you send a series with the
> dependencies?
https://lore.kernel.org/lkml/5ac5976419350e8e048d463a64cae449eb3ba4b0.1620795204.git.christophe.leroy@csgroup.eu/

>
> I've removed the HUGE_VMAP patch from for-next.
I've rebased my work on that patch, so hope the HUGE_VMAP patch will back soon.

>
> >
> > thanks,
> >> On Sun, Jun 13, 2021 at 8:47 AM Palmer Dabbelt <palmerdabbelt@google.com> wrote:
> >>> On Sun, 06 Jun 2021 08:20:48 PDT (-0700), Christoph Hellwig wrote:
> >>>> Hi all,
> >>>>
> >>>> this is what I think is a resonable set of patches for the ASID based
> >>>> flushing, largely based on the work from Guo and thus attributed to him.
> >>> Thanks, these are on for-next.
> >>
> >>



-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

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[PATCH -next 1/2] mm/pgtable: add stubs for {pmd/pub}_{set/clear}_huge

[Liu Shixin]

From: Christophe Leroy <christophe.leroy@csgroup.eu>

For architectures with no PMD and/or no PUD, add stubs similar to what we
have for architectures without P4D.

Link: https://lkml.kernel.org/r/5ac5976419350e8e048d463a64cae449eb3ba4b0.1620795204.git.christophe.leroy@csgroup.eu
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Mike Kravetz <mike.kravetz@oracle.com>
Cc: Mike Rapoport <rppt@kernel.org>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Uladzislau Rezki <uladzislau.rezki@sony.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
 include/linux/pgtable.h | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h
index 46b13780c2c8..d41474a2d255 100644
--- a/include/linux/pgtable.h
+++ b/include/linux/pgtable.h
@@ -1371,10 +1371,34 @@ static inline int p4d_clear_huge(p4d_t *p4d)
 }
 #endif /* !__PAGETABLE_P4D_FOLDED */
 
+#ifndef __PAGETABLE_PUD_FOLDED
 int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot);
-int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot);
 int pud_clear_huge(pud_t *pud);
+#else
+static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
+{
+	return 0;
+}
+static inline int pud_clear_huge(pud_t *pud)
+{
+	return 0;
+}
+#endif /* !__PAGETABLE_PUD_FOLDED */
+
+#ifndef __PAGETABLE_PMD_FOLDED
+int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot);
 int pmd_clear_huge(pmd_t *pmd);
+#else
+static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
+{
+	return 0;
+}
+static inline int pmd_clear_huge(pmd_t *pmd)
+{
+	return 0;
+}
+#endif /* !__PAGETABLE_PMD_FOLDED */
+
 int p4d_free_pud_page(p4d_t *p4d, unsigned long addr);
 int pud_free_pmd_page(pud_t *pud, unsigned long addr);
 int pmd_free_pte_page(pmd_t *pmd, unsigned long addr);
-- 
2.18.0.huawei.25


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[PATCH -next 2/2] riscv: Enable HAVE_ARCH_HUGE_VMAP for 64BIT

[Liu Shixin]

This sets the HAVE_ARCH_HUGE_VMAP option. Enable pmd vmap support and
define the required page table functions(Currently, riscv has only
three-level page tables support for 64BIT).

Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---
 arch/riscv/Kconfig               |  1 +
 arch/riscv/include/asm/vmalloc.h | 12 ++++++++++
 arch/riscv/mm/Makefile           |  1 +
 arch/riscv/mm/pgtable.c          | 40 ++++++++++++++++++++++++++++++++
 4 files changed, 54 insertions(+)
 create mode 100644 arch/riscv/mm/pgtable.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 1cb3280cc498..227033595994 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -60,6 +60,7 @@ config RISCV
 	select GENERIC_TIME_VSYSCALL if MMU && 64BIT
 	select HANDLE_DOMAIN_IRQ
 	select HAVE_ARCH_AUDITSYSCALL
+	select HAVE_ARCH_HUGE_VMAP if MMU && 64BIT
 	select HAVE_ARCH_JUMP_LABEL
 	select HAVE_ARCH_JUMP_LABEL_RELATIVE
 	select HAVE_ARCH_KASAN if MMU && 64BIT
diff --git a/arch/riscv/include/asm/vmalloc.h b/arch/riscv/include/asm/vmalloc.h
index ff9abc00d139..8f17f421f80c 100644
--- a/arch/riscv/include/asm/vmalloc.h
+++ b/arch/riscv/include/asm/vmalloc.h
@@ -1,4 +1,16 @@
 #ifndef _ASM_RISCV_VMALLOC_H
 #define _ASM_RISCV_VMALLOC_H
 
+#ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
+
+#define IOREMAP_MAX_ORDER (PMD_SHIFT)
+
+#define arch_vmap_pmd_supported	arch_vmap_pmd_supported
+static inline bool __init arch_vmap_pmd_supported(pgprot_t prot)
+{
+	return true;
+}
+
+#endif
+
 #endif /* _ASM_RISCV_VMALLOC_H */
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
index 7ebaef10ea1b..f932b4d69946 100644
--- a/arch/riscv/mm/Makefile
+++ b/arch/riscv/mm/Makefile
@@ -13,6 +13,7 @@ obj-y += extable.o
 obj-$(CONFIG_MMU) += fault.o pageattr.o
 obj-y += cacheflush.o
 obj-y += context.o
+obj-y += pgtable.o
 
 ifeq ($(CONFIG_MMU),y)
 obj-$(CONFIG_SMP) += tlbflush.o
diff --git a/arch/riscv/mm/pgtable.c b/arch/riscv/mm/pgtable.c
new file mode 100644
index 000000000000..738dc6f3530f
--- /dev/null
+++ b/arch/riscv/mm/pgtable.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <asm/pgalloc.h>
+#include <linux/gfp.h>
+#include <linux/kernel.h>
+#include <linux/pgtable.h>
+
+#ifdef CONFIG_HAVE_ARCH_HUGE_VMAP
+
+#ifndef __PAGETABLE_PMD_FOLDED
+int pmd_set_huge(pmd_t *pmd, phys_addr_t phys, pgprot_t prot)
+{
+	pmd_t new_pmd = pfn_pmd(__phys_to_pfn(phys), prot);
+
+	set_pmd(pmd, new_pmd);
+	return 1;
+}
+
+int pmd_clear_huge(pmd_t *pmd)
+{
+	if (!pmd_leaf(READ_ONCE(*pmd)))
+		return 0;
+	pmd_clear(pmd);
+	return 1;
+}
+#endif
+
+int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
+{
+	pte_t *pte;
+
+	pte = (pte_t *)pmd_page_vaddr(*pmd);
+	pmd_clear(pmd);
+
+	flush_tlb_kernel_range(addr, addr + PMD_SIZE);
+	pte_free_kernel(NULL, pte);
+	return 1;
+}
+
+#endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */
-- 
2.18.0.huawei.25


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