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[44.242.66.180]) by smtp.gmail.com with ESMTPSA id dn7sm428872edb.29.2021.06.15.23.27.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 23:27:17 -0700 (PDT) From: Bin Meng To: Palmer Dabbelt , Paul Walmsley , Atish Patra , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Bin Meng Subject: [PATCH] riscv: dts: microchip: Define hart clocks Date: Wed, 16 Jun 2021 14:27:39 +0800 Message-Id: <20210616062739.398790-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Bin Meng Declare that each hart in the DT is clocked by <&clkcfg 0>. Signed-off-by: Bin Meng --- Similar to https://patchwork.kernel.org/project/linux-riscv/patch/1592308864-30205-3-git-send-email-yash.shah@sifive.com/, this adds the same property to PolarFire SoC CPU nodes so that we can calculate the running frequency of the hart. arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index a00d9dc560d3..0659068b62f7 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -24,6 +24,7 @@ cpu@0 { i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + clocks = <&clkcfg 0>; status = "disabled"; cpu0_intc: interrupt-controller { @@ -50,6 +51,7 @@ cpu@1 { reg = <1>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&clkcfg 0>; status = "okay"; cpu1_intc: interrupt-controller { @@ -76,6 +78,7 @@ cpu@2 { reg = <2>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&clkcfg 0>; status = "okay"; cpu2_intc: interrupt-controller { @@ -102,6 +105,7 @@ cpu@3 { reg = <3>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&clkcfg 0>; status = "okay"; cpu3_intc: interrupt-controller { @@ -128,6 +132,7 @@ cpu@4 { reg = <4>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&clkcfg 0>; status = "okay"; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; -- 2.25.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07332C48BE5 for ; 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[44.242.66.180]) by smtp.gmail.com with ESMTPSA id dn7sm428872edb.29.2021.06.15.23.27.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 23:27:17 -0700 (PDT) From: Bin Meng To: Palmer Dabbelt , Paul Walmsley , Atish Patra , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Bin Meng Subject: [PATCH] riscv: dts: microchip: Define hart clocks Date: Wed, 16 Jun 2021 14:27:39 +0800 Message-Id: <20210616062739.398790-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210615_232719_287127_75208183 X-CRM114-Status: UNSURE ( 7.23 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Bin Meng Declare that each hart in the DT is clocked by <&clkcfg 0>. Signed-off-by: Bin Meng --- Similar to https://patchwork.kernel.org/project/linux-riscv/patch/1592308864-30205-3-git-send-email-yash.shah@sifive.com/, this adds the same property to PolarFire SoC CPU nodes so that we can calculate the running frequency of the hart. arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index a00d9dc560d3..0659068b62f7 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -24,6 +24,7 @@ cpu@0 { i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + clocks = <&clkcfg 0>; status = "disabled"; cpu0_intc: interrupt-controller { @@ -50,6 +51,7 @@ cpu@1 { reg = <1>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&clkcfg 0>; status = "okay"; cpu1_intc: interrupt-controller { @@ -76,6 +78,7 @@ cpu@2 { reg = <2>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&clkcfg 0>; status = "okay"; cpu2_intc: interrupt-controller { @@ -102,6 +105,7 @@ cpu@3 { reg = <3>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&clkcfg 0>; status = "okay"; cpu3_intc: interrupt-controller { @@ -128,6 +132,7 @@ cpu@4 { reg = <4>; riscv,isa = "rv64imafdc"; tlb-split; + clocks = <&clkcfg 0>; status = "okay"; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv