[PATCH 0/6] Fixes for the NXP LS1028A-QDS boards

[PATCH 0/6] Fixes for the NXP LS1028A-QDS boards

[Vladimir Oltean]

This series fixes through patches 1, 2 and 6 networking issues seen on
the LS1028A-QDS boards:
- Traffic through the RGMII port enetc-1 does not work
- The switch ports are not probed
- RGMII fixed-link connections do not work

Patches 3 and 4 are dependencies for patch 6, as follows:
- Forcing the MAC speed to equal the RGMII PHY requires having a PHY
  unconditionally in the enetc driver
- Having a PHY unconditionally requires updating the device tree to
  declare fixed PHYs for the internal enetc ports

Finally, patch 5 is a cleanup change, which disables the DSA master port
enetc-2 on LS1028A-QDS boards where the switch is not enabled.

Vladimir Oltean (6):
  arm: dts: ls1028a: enable the switch CPU port for the LS1028A-QDS
  arm: dts: ls1028a: enable internal RGMII delays for the LS1028A-QDS
    AR8035 PHY
  arm: dts: ls1028a: declare the fixed-link speeds for the internal
    ENETC ports
  arm: dts: ls1028a: disable enetc-2 by default
  drivers: net: fsl_enetc: require a PHY device when probing
  drivers: net: fsl_enetc: force the RGMII MAC speed/duplex instead of
    using in-band signaling

 .../dts/fsl-ls1028a-qds-7777-sch-30841.dtsi   |  9 +++
 .../dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi  |  9 +++
 .../fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi  |  9 +++
 .../dts/fsl-ls1028a-qds-9999-sch-24801.dtsi   |  9 +++
 .../fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi  |  9 +++
 .../fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi  |  9 +++
 .../dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi   |  9 +++
 .../dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi   |  9 +++
 arch/arm/dts/fsl-ls1028a-qds.dtsi             |  2 +-
 arch/arm/dts/fsl-ls1028a.dtsi                 | 12 +++-
 drivers/net/fsl_enetc.c                       | 55 +++++++++++++------
 drivers/net/fsl_enetc.h                       |  5 ++
 12 files changed, 126 insertions(+), 20 deletions(-)

-- 
2.25.1

[PATCH 1/6] arm: dts: ls1028a: enable the switch CPU port for the LS1028A-QDS

[Vladimir Oltean]

Due to an upstream change, the ls1028a.dtsi bindings for the mscc_felix
switch got accepted with all ports disabled by default and with no link
to the DSA master - this needs to be done on a per board basis.

Note that enetc-2 is not currently disabled in the ls1028a.dtsi, but
presumably at some point it might become. Explicitly enable it in the
QDS device trees anyway, to proactively avoid issues when that happens.

Fixes: a7fdac7e2a2a ("arm: dts: ls1028a: define QDS networking protocol combinations")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi      | 9 +++++++++
 arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi     | 9 +++++++++
 arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi | 9 +++++++++
 arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi      | 9 +++++++++
 arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi | 9 +++++++++
 arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi | 9 +++++++++
 arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi      | 9 +++++++++
 arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi      | 9 +++++++++
 8 files changed, 72 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
index fb1836a8aef3..5a0f060c16e5 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
@@ -20,6 +20,10 @@
 #include "fsl-sch-30841.dtsi"
 };
 
+&enetc2 {
+	status = "okay";
+};
+
 &mscc_felix {
 	status = "okay";
 };
@@ -47,3 +51,8 @@
 	phy-mode = "sgmii-2500";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
 };
+
+&mscc_felix_port4 {
+	ethernet = <&enetc2>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
index 1d02a3e11def..39a83e10c4ce 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
@@ -9,6 +9,10 @@
 #include "fsl-sch-30841.dtsi"
 };
 
+&enetc2 {
+	status = "okay";
+};
+
 &mscc_felix {
 	status = "okay";
 };
@@ -24,3 +28,8 @@
 	phy-mode = "sgmii-2500";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
 };
+
+&mscc_felix_port4 {
+	ethernet = <&enetc2>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
index c92dd1bd2e95..021fe3fbc67a 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
@@ -34,6 +34,10 @@
 	#include "fsl-sch-24801.dtsi"
 };
 
+&enetc2 {
+	status = "okay";
+};
+
 &mscc_felix {
 	status = "okay";
 };
@@ -61,3 +65,8 @@
 	phy-mode = "sgmii";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
 };
+
+&mscc_felix_port4 {
+	ethernet = <&enetc2>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
index 941f7472eb09..b6704d8089a8 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
@@ -19,6 +19,10 @@
 	#include "fsl-sch-24801.dtsi"
 };
 
+&enetc2 {
+	status = "okay";
+};
+
 &mscc_felix {
 	status = "okay";
 };
@@ -46,3 +50,8 @@
 	phy-mode = "sgmii";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
 };
+
+&mscc_felix_port4 {
+	ethernet = <&enetc2>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
index 7e483e656e28..8c10897e565c 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
@@ -19,6 +19,10 @@
 #include "fsl-sch-30841.dtsi"
 };
 
+&enetc2 {
+	status = "okay";
+};
+
 &mscc_felix {
 	status = "okay";
 };
@@ -46,3 +50,8 @@
 	phy-mode = "usxgmii";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
 };
+
+&mscc_felix_port4 {
+	ethernet = <&enetc2>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
index 49fffdb9cb2a..1d800dacef89 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
@@ -13,6 +13,10 @@
 	#include "fsl-sch-28021.dtsi"
 };
 
+&enetc2 {
+	status = "okay";
+};
+
 &mscc_felix {
 	status = "okay";
 };
@@ -40,3 +44,8 @@
 	phy-mode = "qsgmii";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
 };
+
+&mscc_felix_port4 {
+	ethernet = <&enetc2>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
index 8347462f4cb0..1fb2cdf0c244 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
@@ -9,6 +9,10 @@
 #include "fsl-sch-30842.dtsi"
 };
 
+&enetc2 {
+	status = "okay";
+};
+
 &mscc_felix {
 	status = "okay";
 };
@@ -18,3 +22,8 @@
 	phy-mode = "sgmii-2500";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
 };
+
+&mscc_felix_port4 {
+	ethernet = <&enetc2>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
index 6be3b5094c81..2333f74e5ae1 100644
--- a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
@@ -9,6 +9,10 @@
 #include "fsl-sch-30842.dtsi"
 };
 
+&enetc2 {
+	status = "okay";
+};
+
 &mscc_felix {
 	status = "okay";
 };
@@ -18,3 +22,8 @@
 	phy-mode = "sgmii-2500";
 	phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
 };
+
+&mscc_felix_port4 {
+	ethernet = <&enetc2>;
+	status = "okay";
+};
-- 
2.25.1

[PATCH 2/6] arm: dts: ls1028a: enable internal RGMII delays for the LS1028A-QDS AR8035 PHY

[Vladimir Oltean]

There are no PCB trace delays on this board, so the PHY needs to enable
its internal ones in order to have a proper electrical connection to the
enetc MAC.

Fixes: b32e9a757837 ("arm: dts: ls1028a updates for network interfaces")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 arch/arm/dts/fsl-ls1028a-qds.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi
index da89ff96e98c..69632fa796b5 100644
--- a/arch/arm/dts/fsl-ls1028a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi
@@ -251,7 +251,7 @@
 
 &enetc1 {
 	status = "okay";
-	phy-mode = "rgmii";
+	phy-mode = "rgmii-id";
 	phy-handle = <&qds_phy0>;
 };
 
-- 
2.25.1

[PATCH 3/6] arm: dts: ls1028a: declare the fixed-link speeds for the internal ENETC ports

[Vladimir Oltean]

To comply with the device tree bindings expectations for an Ethernet
controller, as well as to simplify the driver code, declare fixed-link
nodes for the internal ENETC ports (attached to the mscc_felix switch).

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 arch/arm/dts/fsl-ls1028a.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index c7c725a4fc84..21f4ef78a059 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -144,12 +144,22 @@
 			reg = <0x000200 0 0 0 0>;
 			status = "okay";
 			phy-mode = "internal";
+
+			fixed-link {
+				speed = <2500>;
+				full-duplex;
+			};
 		};
 		mdio0: pci@0,3 {
 			#address-cells=<0>;
 			#size-cells=<1>;
 			reg = <0x000300 0 0 0 0>;
 			status = "disabled";
+
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+			};
 		};
 
 		mscc_felix: pci@0,5 {
-- 
2.25.1

[PATCH 4/6] arm: dts: ls1028a: disable enetc-2 by default

[Vladimir Oltean]

The enetc-2 port is used as DSA master (connected back-to-back to
mscc_felix_port4). Since the convention is to not enable ports in the
common SoC dtsi unless they are used on the board, then enable enetc-2
only when mscc_felix_port4 itself is enabled.

All existing device trees appear to adhere to this rule, so disable
enetc-2 in the SoC dtsi.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 arch/arm/dts/fsl-ls1028a.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 21f4ef78a059..50f9b527cde1 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -142,7 +142,7 @@
 		};
 		enetc2: pci@0,2 {
 			reg = <0x000200 0 0 0 0>;
-			status = "okay";
+			status = "disabled";
 			phy-mode = "internal";
 
 			fixed-link {
-- 
2.25.1

[PATCH 5/6] drivers: net: fsl_enetc: require a PHY device when probing

[Vladimir Oltean]

Given that even a fixed-link has an associated phy_device, there is no
reason to operate in a mode when dm_eth_phy_connect fails.

Remove the driver checks for a NULL priv->phy and just return -ENODEV
when that happens.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/fsl_enetc.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
index f6fc7801b95b..5961775024ff 100644
--- a/drivers/net/fsl_enetc.c
+++ b/drivers/net/fsl_enetc.c
@@ -281,21 +281,20 @@ static void enetc_start_pcs(struct udevice *dev)
 }
 
 /* Configure the actual/external ethernet PHY, if one is found */
-static void enetc_config_phy(struct udevice *dev)
+static int enetc_config_phy(struct udevice *dev)
 {
 	struct enetc_priv *priv = dev_get_priv(dev);
 	int supported;
 
 	priv->phy = dm_eth_phy_connect(dev);
-
 	if (!priv->phy)
-		return;
+		return -ENODEV;
 
 	supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
 	priv->phy->supported &= supported;
 	priv->phy->advertising &= supported;
 
-	phy_config(priv->phy);
+	return phy_config(priv->phy);
 }
 
 /*
@@ -335,9 +334,8 @@ static int enetc_probe(struct udevice *dev)
 	dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
 
 	enetc_start_pcs(dev);
-	enetc_config_phy(dev);
 
-	return 0;
+	return enetc_config_phy(dev);
 }
 
 /*
@@ -550,8 +548,7 @@ static int enetc_start(struct udevice *dev)
 
 	enetc_setup_mac_iface(dev);
 
-	if (priv->phy)
-		phy_startup(priv->phy);
+	phy_startup(priv->phy);
 
 	return 0;
 }
-- 
2.25.1

[PATCH 6/6] drivers: net: fsl_enetc: force the RGMII MAC speed/duplex instead of using in-band signaling

[Vladimir Oltean]

The same considerations apply to U-Boot as to Linux:
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c76a97218dcbb2cb7cec1404ace43ef96c87d874

This change is needed in order for enetc to be able to operate in RGMII
fixed-link mode.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
 drivers/net/fsl_enetc.c | 44 ++++++++++++++++++++++++++++++-----------
 drivers/net/fsl_enetc.h |  5 +++++
 2 files changed, 38 insertions(+), 11 deletions(-)

diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
index 5961775024ff..de1e42f907e7 100644
--- a/drivers/net/fsl_enetc.c
+++ b/drivers/net/fsl_enetc.c
@@ -178,21 +178,43 @@ static int enetc_init_sgmii(struct udevice *dev)
 }
 
 /* set up MAC for RGMII */
-static int enetc_init_rgmii(struct udevice *dev)
+static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev)
 {
 	struct enetc_priv *priv = dev_get_priv(dev);
-	u32 if_mode;
+	u32 old_val, val;
 
-	/* enable RGMII AN */
-	if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
-	if_mode |= ENETC_PM_IF_MODE_AN_ENA;
-	enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
+	old_val = val = enetc_read_port(priv, ENETC_PM_IF_MODE);
 
-	return 0;
+	/* disable unreliable RGMII in-band signaling and force the MAC into
+	 * the speed negotiated by the PHY.
+	 */
+	val &= ~ENETC_PM_IF_MODE_AN_ENA;
+
+	if (phydev->speed == SPEED_1000) {
+		val &= ~ENETC_PM_IFM_SSP_MASK;
+		val |= ENETC_PM_IFM_SSP_1000;
+	} else if (phydev->speed == SPEED_100) {
+		val &= ~ENETC_PM_IFM_SSP_MASK;
+		val |= ENETC_PM_IFM_SSP_100;
+	} else if (phydev->speed == SPEED_10) {
+		val &= ~ENETC_PM_IFM_SSP_MASK;
+		val |= ENETC_PM_IFM_SSP_10;
+	}
+
+	if (phydev->duplex == DUPLEX_FULL)
+		val |= ENETC_PM_IFM_FULL_DPX;
+	else
+		val &= ~ENETC_PM_IFM_FULL_DPX;
+
+	if (val == old_val)
+		return;
+
+	enetc_write_port(priv, ENETC_PM_IF_MODE, val);
 }
 
 /* set up MAC configuration for the given interface type */
-static void enetc_setup_mac_iface(struct udevice *dev)
+static void enetc_setup_mac_iface(struct udevice *dev,
+				  struct phy_device *phydev)
 {
 	struct enetc_priv *priv = dev_get_priv(dev);
 	u32 if_mode;
@@ -202,7 +224,7 @@ static void enetc_setup_mac_iface(struct udevice *dev)
 	case PHY_INTERFACE_MODE_RGMII_ID:
 	case PHY_INTERFACE_MODE_RGMII_RXID:
 	case PHY_INTERFACE_MODE_RGMII_TXID:
-		enetc_init_rgmii(dev);
+		enetc_init_rgmii(dev, phydev);
 		break;
 	case PHY_INTERFACE_MODE_XGMII:
 	case PHY_INTERFACE_MODE_USXGMII:
@@ -546,10 +568,10 @@ static int enetc_start(struct udevice *dev)
 	enetc_setup_tx_bdr(dev);
 	enetc_setup_rx_bdr(dev);
 
-	enetc_setup_mac_iface(dev);
-
 	phy_startup(priv->phy);
 
+	enetc_setup_mac_iface(dev, priv->phy);
+
 	return 0;
 }
 
diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h
index 110c1d78fbc6..a4409505e043 100644
--- a/drivers/net/fsl_enetc.h
+++ b/drivers/net/fsl_enetc.h
@@ -77,6 +77,11 @@ enum enetc_bdr_type {TX, RX};
 #define ENETC_PM_IF_MODE		0x8300
 #define  ENETC_PM_IF_MODE_RG		BIT(2)
 #define  ENETC_PM_IF_MODE_AN_ENA	BIT(15)
+#define  ENETC_PM_IFM_SSP_MASK		GENMASK(14, 13)
+#define  ENETC_PM_IFM_SSP_1000		(2 << 13)
+#define  ENETC_PM_IFM_SSP_100		(0 << 13)
+#define  ENETC_PM_IFM_SSP_10		(1 << 13)
+#define  ENETC_PM_IFM_FULL_DPX		BIT(12)
 #define  ENETC_PM_IF_IFMODE_MASK	GENMASK(1, 0)
 
 /* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */
-- 
2.25.1

Re: [PATCH 5/6] drivers: net: fsl_enetc: require a PHY device when probing

[Ramon Fried]

On Thu, Jun 17, 2021 at 5:36 PM Vladimir Oltean <vladimir.oltean@nxp.com> wrote:
>
> Given that even a fixed-link has an associated phy_device, there is no
> reason to operate in a mode when dm_eth_phy_connect fails.
>
> Remove the driver checks for a NULL priv->phy and just return -ENODEV
> when that happens.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
>  drivers/net/fsl_enetc.c | 13 +++++--------
>  1 file changed, 5 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
> index f6fc7801b95b..5961775024ff 100644
> --- a/drivers/net/fsl_enetc.c
> +++ b/drivers/net/fsl_enetc.c
> @@ -281,21 +281,20 @@ static void enetc_start_pcs(struct udevice *dev)
>  }
>
>  /* Configure the actual/external ethernet PHY, if one is found */
> -static void enetc_config_phy(struct udevice *dev)
> +static int enetc_config_phy(struct udevice *dev)
>  {
>         struct enetc_priv *priv = dev_get_priv(dev);
>         int supported;
>
>         priv->phy = dm_eth_phy_connect(dev);
> -
>         if (!priv->phy)
> -               return;
> +               return -ENODEV;
>
>         supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
>         priv->phy->supported &= supported;
>         priv->phy->advertising &= supported;
>
> -       phy_config(priv->phy);
> +       return phy_config(priv->phy);
>  }
>
>  /*
> @@ -335,9 +334,8 @@ static int enetc_probe(struct udevice *dev)
>         dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
>
>         enetc_start_pcs(dev);
> -       enetc_config_phy(dev);
>
> -       return 0;
> +       return enetc_config_phy(dev);
>  }
>
>  /*
> @@ -550,8 +548,7 @@ static int enetc_start(struct udevice *dev)
>
>         enetc_setup_mac_iface(dev);
>
> -       if (priv->phy)
> -               phy_startup(priv->phy);
> +       phy_startup(priv->phy);
>
>         return 0;
>  }
> --
> 2.25.1
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>

Re: [PATCH 6/6] drivers: net: fsl_enetc: force the RGMII MAC speed/duplex instead of using in-band signaling

[Ramon Fried]

On Thu, Jun 17, 2021 at 5:36 PM Vladimir Oltean <vladimir.oltean@nxp.com> wrote:
>
> The same considerations apply to U-Boot as to Linux:
> https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c76a97218dcbb2cb7cec1404ace43ef96c87d874
>
> This change is needed in order for enetc to be able to operate in RGMII
> fixed-link mode.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
>  drivers/net/fsl_enetc.c | 44 ++++++++++++++++++++++++++++++-----------
>  drivers/net/fsl_enetc.h |  5 +++++
>  2 files changed, 38 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
> index 5961775024ff..de1e42f907e7 100644
> --- a/drivers/net/fsl_enetc.c
> +++ b/drivers/net/fsl_enetc.c
> @@ -178,21 +178,43 @@ static int enetc_init_sgmii(struct udevice *dev)
>  }
>
>  /* set up MAC for RGMII */
> -static int enetc_init_rgmii(struct udevice *dev)
> +static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev)
>  {
>         struct enetc_priv *priv = dev_get_priv(dev);
> -       u32 if_mode;
> +       u32 old_val, val;
>
> -       /* enable RGMII AN */
> -       if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
> -       if_mode |= ENETC_PM_IF_MODE_AN_ENA;
> -       enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
> +       old_val = val = enetc_read_port(priv, ENETC_PM_IF_MODE);
>
> -       return 0;
> +       /* disable unreliable RGMII in-band signaling and force the MAC into
> +        * the speed negotiated by the PHY.
> +        */
> +       val &= ~ENETC_PM_IF_MODE_AN_ENA;
> +
> +       if (phydev->speed == SPEED_1000) {
> +               val &= ~ENETC_PM_IFM_SSP_MASK;
> +               val |= ENETC_PM_IFM_SSP_1000;
> +       } else if (phydev->speed == SPEED_100) {
> +               val &= ~ENETC_PM_IFM_SSP_MASK;
> +               val |= ENETC_PM_IFM_SSP_100;
> +       } else if (phydev->speed == SPEED_10) {
> +               val &= ~ENETC_PM_IFM_SSP_MASK;
> +               val |= ENETC_PM_IFM_SSP_10;
> +       }
> +
> +       if (phydev->duplex == DUPLEX_FULL)
> +               val |= ENETC_PM_IFM_FULL_DPX;
> +       else
> +               val &= ~ENETC_PM_IFM_FULL_DPX;
> +
> +       if (val == old_val)
> +               return;
> +
> +       enetc_write_port(priv, ENETC_PM_IF_MODE, val);
>  }
>
>  /* set up MAC configuration for the given interface type */
> -static void enetc_setup_mac_iface(struct udevice *dev)
> +static void enetc_setup_mac_iface(struct udevice *dev,
> +                                 struct phy_device *phydev)
>  {
>         struct enetc_priv *priv = dev_get_priv(dev);
>         u32 if_mode;
> @@ -202,7 +224,7 @@ static void enetc_setup_mac_iface(struct udevice *dev)
>         case PHY_INTERFACE_MODE_RGMII_ID:
>         case PHY_INTERFACE_MODE_RGMII_RXID:
>         case PHY_INTERFACE_MODE_RGMII_TXID:
> -               enetc_init_rgmii(dev);
> +               enetc_init_rgmii(dev, phydev);
>                 break;
>         case PHY_INTERFACE_MODE_XGMII:
>         case PHY_INTERFACE_MODE_USXGMII:
> @@ -546,10 +568,10 @@ static int enetc_start(struct udevice *dev)
>         enetc_setup_tx_bdr(dev);
>         enetc_setup_rx_bdr(dev);
>
> -       enetc_setup_mac_iface(dev);
> -
>         phy_startup(priv->phy);
>
> +       enetc_setup_mac_iface(dev, priv->phy);
> +
>         return 0;
>  }
>
> diff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h
> index 110c1d78fbc6..a4409505e043 100644
> --- a/drivers/net/fsl_enetc.h
> +++ b/drivers/net/fsl_enetc.h
> @@ -77,6 +77,11 @@ enum enetc_bdr_type {TX, RX};
>  #define ENETC_PM_IF_MODE               0x8300
>  #define  ENETC_PM_IF_MODE_RG           BIT(2)
>  #define  ENETC_PM_IF_MODE_AN_ENA       BIT(15)
> +#define  ENETC_PM_IFM_SSP_MASK         GENMASK(14, 13)
> +#define  ENETC_PM_IFM_SSP_1000         (2 << 13)
> +#define  ENETC_PM_IFM_SSP_100          (0 << 13)
> +#define  ENETC_PM_IFM_SSP_10           (1 << 13)
> +#define  ENETC_PM_IFM_FULL_DPX         BIT(12)
>  #define  ENETC_PM_IF_IFMODE_MASK       GENMASK(1, 0)
>
>  /* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */
> --
> 2.25.1
>
Please write the commit message as it was written in Linux, and add a
reference to Linux if needed, don't send us to read the commit from
Linux to understand what's going on.