From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95D71C2B9F4 for ; Thu, 17 Jun 2021 16:57:00 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F165C61042 for ; Thu, 17 Jun 2021 16:56:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F165C61042 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4G5Srl31xcz3cMs for ; Fri, 18 Jun 2021 02:56:55 +1000 (AEST) Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=ozlabs.org (client-ip=2401:3900:2:1::2; helo=ozlabs.org; envelope-from=srs0=k7pz=ll=kernel.crashing.org=segher@ozlabs.org; receiver=) Received: from ozlabs.org (bilbo.ozlabs.org [IPv6:2401:3900:2:1::2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4G5SrN1z6Sz308H for ; Fri, 18 Jun 2021 02:56:36 +1000 (AEST) Received: from ozlabs.org (bilbo.ozlabs.org [IPv6:2401:3900:2:1::2]) by ozlabs.org (Postfix) with ESMTP id 4G5SrH0tbQz9sTD for ; Fri, 18 Jun 2021 02:56:31 +1000 (AEST) Received: by ozlabs.org (Postfix) id 4G5SrH0CZRz9sSn; Fri, 18 Jun 2021 02:56:31 +1000 (AEST) Authentication-Results: ozlabs.org; spf=permerror (SPF Permanent Error: Unknown mechanism found: ip:192.40.192.88/32) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=segher@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by ozlabs.org (Postfix) with ESMTP id 4G5SrG2lr9z9sRf; Fri, 18 Jun 2021 02:56:29 +1000 (AEST) Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id 15HGsPaJ013980; Thu, 17 Jun 2021 11:54:25 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id 15HGsPsR013977; Thu, 17 Jun 2021 11:54:25 -0500 X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Thu, 17 Jun 2021 11:54:25 -0500 From: Segher Boessenkool To: Nicholas Piggin Subject: Re: [PATCH 11/11] powerpc/microwatt: Disable interrupts in boot wrapper main program Message-ID: <20210617165425.GO5077@gate.crashing.org> References: <20210616233739.GN5077@gate.crashing.org> <1623893913.zpw6v9dt4c.astroid@bobo.none> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1623893913.zpw6v9dt4c.astroid@bobo.none> User-Agent: Mutt/1.4.2.3i X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Jun 17, 2021 at 11:40:23AM +1000, Nicholas Piggin wrote: > Excerpts from Segher Boessenkool's message of June 17, 2021 9:37 am: > > On Tue, Jun 15, 2021 at 09:05:27AM +1000, Paul Mackerras wrote: > >> This ensures that we don't get a decrementer interrupt arriving before > >> we have set up a handler for it. > > > > Maybe add a comment saying this is setting MSR[EE]=0 for that? Or do > > other bits here matter as well? > > Hmm, it actually clears MSR[RI] as well. > > __hard_irq_disable() is what we want here, unless the MSR[RI] clearing > is required as well, in which case there is __hard_EE_RI_disable(). I don't think it matters if MSR[RI] is set or not here, nothing will try to recover from an actual reboot I hope :-) Segher