[PATCH 0/9] target/mips: Various fixes & cleanups

[PATCH 0/9] target/mips: Various fixes & cleanups

[Philippe Mathieu-Daudé]

Fixes and cleanup accumulated during the last month.
Nothing particularly exciting :/

Please review,

Phil.

Philippe Mathieu-Daudé (9):
  target/mips: Do not abort on invalid instruction
  target/mips: Fix more TCG temporary leaks in
    gen_pool32a5_nanomips_insn
  target/mips: Move TCG trace events to tcg/ sub directory
  target/mips: Move translate.h to tcg/ sub directory
  target/mips: Restrict some system specific declarations to sysemu
  target/mips: Remove SmartMIPS / MDMX unuseful comments
  target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful cases
  target/mips: Constify host_to_mips_errno[]
  target/mips: Optimize regnames[] arrays

 meson.build                            |  2 +-
 target/mips/cpu.h                      | 10 ++++++---
 target/mips/internal.h                 |  2 +-
 target/mips/tcg/tcg-internal.h         |  6 +++---
 target/mips/{ => tcg}/translate.h      |  0
 target/mips/cpu.c                      |  2 +-
 target/mips/tcg/msa_translate.c        |  4 ++--
 target/mips/tcg/mxu_translate.c        |  6 +++---
 target/mips/tcg/rel6_translate.c       |  2 +-
 target/mips/tcg/sysemu/mips-semi.c     |  2 +-
 target/mips/tcg/translate.c            | 29 +++++++++-----------------
 target/mips/tcg/translate_addr_const.c |  2 +-
 target/mips/tcg/tx79_translate.c       |  2 +-
 target/mips/tcg/txx9_translate.c       |  2 +-
 target/mips/{ => tcg}/trace-events     |  0
 15 files changed, 33 insertions(+), 38 deletions(-)
 rename target/mips/{ => tcg}/translate.h (100%)
 rename target/mips/{ => tcg}/trace-events (100%)

-- 
2.31.1

[PATCH 1/9] target/mips: Do not abort on invalid instruction

[Philippe Mathieu-Daudé]

On real hardware an invalid instruction doesn't halt the world,
but usually triggers a RESERVED INSTRUCTION exception.
TCG guest code shouldn't abort QEMU anyway.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 0954ce0dbc3..b92a473f870 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -12151,8 +12151,8 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
             tcg_gen_lookup_and_goto_ptr();
             break;
         default:
-            fprintf(stderr, "unknown branch 0x%x\n", proc_hflags);
-            abort();
+            LOG_DISAS("unknown branch 0x%x\n", proc_hflags);
+            gen_reserved_instruction(ctx);
         }
     }
 }
-- 
2.31.1

[PATCH 2/9] target/mips: Fix more TCG temporary leaks in gen_pool32a5_nanomips_insn

[Philippe Mathieu-Daudé]

Fix multiple TCG temporary leaks in gen_pool32a5_nanomips_insn().

Fixes: 3285a3e4445 ("target/mips: Add emulation of DSP ASE for nanoMIPS - part 1")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/translate.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index b92a473f870..4b7229a868a 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -20298,6 +20298,10 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
         gen_reserved_instruction(ctx);
         break;
     }
+
+    tcg_temp_free(v2_t);
+    tcg_temp_free(v1_t);
+    tcg_temp_free(t0);
 }
 
 static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
-- 
2.31.1

[PATCH 3/9] target/mips: Move TCG trace events to tcg/ sub directory

[Philippe Mathieu-Daudé]

Commit a2b0a27d33e ("target/mips: Move TCG source files under
tcg/ sub directory") forgot to move the trace-event file.
As it only contains TCG events, move it for consistency.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 meson.build                        | 2 +-
 target/mips/tcg/translate.c        | 1 +
 target/mips/{ => tcg}/trace-events | 0
 3 files changed, 2 insertions(+), 1 deletion(-)
 rename target/mips/{ => tcg}/trace-events (100%)

diff --git a/meson.build b/meson.build
index a2311eda6ec..196adef6f8d 100644
--- a/meson.build
+++ b/meson.build
@@ -1882,7 +1882,7 @@
     'target/hppa',
     'target/i386',
     'target/i386/kvm',
-    'target/mips',
+    'target/mips/tcg',
     'target/ppc',
     'target/riscv',
     'target/s390x',
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 4b7229a868a..a4cab66d338 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -33,6 +33,7 @@
 
 #include "target/mips/trace.h"
 #include "trace-tcg.h"
+#include "trace.h"
 #include "exec/translator.h"
 #include "exec/log.h"
 #include "qemu/qemu-print.h"
diff --git a/target/mips/trace-events b/target/mips/tcg/trace-events
similarity index 100%
rename from target/mips/trace-events
rename to target/mips/tcg/trace-events
-- 
2.31.1

[PATCH 4/9] target/mips: Move translate.h to tcg/ sub directory

[Philippe Mathieu-Daudé]

We moved various TCG source files in commit a2b0a27d33e
("target/mips: Move TCG source files under tcg/ sub directory")
but forgot to move the header declaring their prototypes.
Do it now, since all it declares is TCG specific.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/{ => tcg}/translate.h      | 0
 target/mips/tcg/msa_translate.c        | 2 +-
 target/mips/tcg/mxu_translate.c        | 2 +-
 target/mips/tcg/rel6_translate.c       | 2 +-
 target/mips/tcg/translate.c            | 2 +-
 target/mips/tcg/translate_addr_const.c | 2 +-
 target/mips/tcg/tx79_translate.c       | 2 +-
 target/mips/tcg/txx9_translate.c       | 2 +-
 8 files changed, 7 insertions(+), 7 deletions(-)
 rename target/mips/{ => tcg}/translate.h (100%)

diff --git a/target/mips/translate.h b/target/mips/tcg/translate.h
similarity index 100%
rename from target/mips/translate.h
rename to target/mips/tcg/translate.h
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index ae6587edf69..b3b06352bf2 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -13,7 +13,7 @@
 #include "qemu/osdep.h"
 #include "tcg/tcg-op.h"
 #include "exec/helper-gen.h"
-#include "translate.h"
+#include "tcg/translate.h"
 #include "fpu_helper.h"
 #include "internal.h"
 
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index fb0a811af6c..f70a8ca59f4 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -18,7 +18,7 @@
 #include "qemu/osdep.h"
 #include "tcg/tcg-op.h"
 #include "exec/helper-gen.h"
-#include "translate.h"
+#include "tcg/translate.h"
 
 /*
  *
diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c
index 0354370927d..8289263ada5 100644
--- a/target/mips/tcg/rel6_translate.c
+++ b/target/mips/tcg/rel6_translate.c
@@ -11,7 +11,7 @@
 #include "qemu/osdep.h"
 #include "tcg/tcg-op.h"
 #include "exec/helper-gen.h"
-#include "translate.h"
+#include "tcg/translate.h"
 
 /* Include the auto-generated decoder.  */
 #include "decode-mips32r6.c.inc"
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index a4cab66d338..f0738daa847 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -38,7 +38,7 @@
 #include "exec/log.h"
 #include "qemu/qemu-print.h"
 #include "fpu_helper.h"
-#include "translate.h"
+#include "tcg/translate.h"
 
 /*
  * Many sysemu-only helpers are not reachable for user-only.
diff --git a/target/mips/tcg/translate_addr_const.c b/target/mips/tcg/translate_addr_const.c
index 96f483418eb..3a54749e3bc 100644
--- a/target/mips/tcg/translate_addr_const.c
+++ b/target/mips/tcg/translate_addr_const.c
@@ -12,7 +12,7 @@
  */
 #include "qemu/osdep.h"
 #include "tcg/tcg-op.h"
-#include "translate.h"
+#include "tcg/translate.h"
 
 bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
 {
diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c
index ad83774b977..967969b141a 100644
--- a/target/mips/tcg/tx79_translate.c
+++ b/target/mips/tcg/tx79_translate.c
@@ -9,7 +9,7 @@
 #include "qemu/osdep.h"
 #include "tcg/tcg-op.h"
 #include "exec/helper-gen.h"
-#include "translate.h"
+#include "tcg/translate.h"
 
 /* Include the auto-generated decoder.  */
 #include "decode-tx79.c.inc"
diff --git a/target/mips/tcg/txx9_translate.c b/target/mips/tcg/txx9_translate.c
index 8a2c0b766bd..5f147b89eef 100644
--- a/target/mips/tcg/txx9_translate.c
+++ b/target/mips/tcg/txx9_translate.c
@@ -7,7 +7,7 @@
  */
 
 #include "qemu/osdep.h"
-#include "translate.h"
+#include "tcg/translate.h"
 
 bool decode_ext_txx9(DisasContext *ctx, uint32_t insn)
 {
-- 
2.31.1

[PATCH 5/9] target/mips: Restrict some system specific declarations to sysemu

[Philippe Mathieu-Daudé]

Commit 043715d1e0f ("target/mips: Update ITU to utilize SAARI
and SAAR CP0 registers") declared itc_reconfigure() in public
namespace, while it is restricted to system emulation.

Similarly commit 5679479b9a1 ("target/mips: Move CP0 helpers
to sysemu/cp0.c") restricted cpu_mips_soft_irq() definition to
system emulation, but forgot to restrict its declaration.

Commit a2b0a27d33e ("target/mips: Move TCG source files under
tcg/ sub directory") restricted mips_cpu_do_unaligned_access()
to system emulation but forgot to guard the declaration.

To avoid polluting user-mode emulation with these declarations,
restrict them to sysemu. Also restrict the sysemu ITU/ITC/IRQ
fields from CPUMIPSState.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu.h              | 10 +++++++---
 target/mips/tcg/tcg-internal.h |  6 +++---
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 075c24abdad..1dfe69c6c0c 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1152,13 +1152,13 @@ struct CPUMIPSState {
     CPUMIPSMVPContext *mvp;
 #if !defined(CONFIG_USER_ONLY)
     CPUMIPSTLBContext *tlb;
+    void *irq[8];
+    struct MIPSITUState *itu;
+    MemoryRegion *itc_tag; /* ITC Configuration Tags */
 #endif
 
     const mips_def_t *cpu_model;
-    void *irq[8];
     QEMUTimer *timer; /* Internal timer */
-    struct MIPSITUState *itu;
-    MemoryRegion *itc_tag; /* ITC Configuration Tags */
     target_ulong exception_base; /* ExceptionBase input to the core */
     uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */
 };
@@ -1316,12 +1316,16 @@ uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr);
 bool mips_um_ksegs_enabled(void);
 void mips_um_ksegs_enable(void);
 
+#if !defined(CONFIG_USER_ONLY)
+
 /* mips_int.c */
 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
 
 /* mips_itu.c */
 void itc_reconfigure(struct MIPSITUState *tag);
 
+#endif /* !CONFIG_USER_ONLY */
+
 /* helper.c */
 target_ulong exception_resume_pc(CPUMIPSState *env);
 
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index 81b14eb219e..11d98a717f2 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -23,9 +23,6 @@ bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
 bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        MMUAccessType access_type, int mmu_idx,
                        bool probe, uintptr_t retaddr);
-void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
-                                  MMUAccessType access_type,
-                                  int mmu_idx, uintptr_t retaddr);
 
 const char *mips_exception_name(int32_t exception);
 
@@ -57,6 +54,9 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
                                     MMUAccessType access_type,
                                     int mmu_idx, MemTxAttrs attrs,
                                     MemTxResult response, uintptr_t retaddr);
+void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
+                                  MMUAccessType access_type,
+                                  int mmu_idx, uintptr_t retaddr);
 void cpu_mips_tlb_flush(CPUMIPSState *env);
 
 #endif /* !CONFIG_USER_ONLY */
-- 
2.31.1

[PATCH 6/9] target/mips: Remove SmartMIPS / MDMX unuseful comments

[Philippe Mathieu-Daudé]

These placeholder comments for SmartMIPS and MDMX extensions have
been added commit 3c824109da0 ("target-mips: microMIPS ASE support").
More than 11 years later it is safe to assume there won't be added
soon, so remove these unuseful comments.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/translate.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index f0738daa847..47c7705f051 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -21579,14 +21579,6 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
 }
 
 
-/* SmartMIPS extension to MIPS32 */
-
-#if defined(TARGET_MIPS64)
-
-/* MDMX extension to MIPS64 */
-
-#endif
-
 /* MIPSDSP functions. */
 static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc,
                            int rd, int base, int offset)
-- 
2.31.1

[PATCH 7/9] target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful cases

[Philippe Mathieu-Daudé]

These switch cases for the microMIPS BPOSGE32 / BPOSGE64 opcodes have
been added commit 3c824109da0 ("target-mips: microMIPS ASE support").
More than 11 years later it is safe to assume there won't be added
soon. The cases fall back to the default which generates a RESERVED
INSTRUCTION, so it is safe to remove them.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/translate.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 47c7705f051..5d571d83c54 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -14077,8 +14077,6 @@ enum {
     BGEZALS = 0x13,
     BC2F = 0x14,
     BC2T = 0x15,
-    BPOSGE64 = 0x1a,
-    BPOSGE32 = 0x1b,
     /* These overlap and are distinguished by bit16 of the instruction */
     BC1F = 0x1c,
     BC1T = 0x1d,
@@ -16122,10 +16120,6 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
                 generate_exception_err(ctx, EXCP_CpU, 1);
             }
             break;
-        case BPOSGE64:
-        case BPOSGE32:
-            /* MIPS DSP: not implemented */
-            /* Fall through */
         default:
             MIPS_INVAL("pool32i");
             gen_reserved_instruction(ctx);
-- 
2.31.1

[PATCH 8/9] target/mips: Constify host_to_mips_errno[]

[Philippe Mathieu-Daudé]

Keep host_to_mips_errno[] in .rodata by marking the array const.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/sysemu/mips-semi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/mips/tcg/sysemu/mips-semi.c b/target/mips/tcg/sysemu/mips-semi.c
index 6de60fa6dd7..77108b0b1a9 100644
--- a/target/mips/tcg/sysemu/mips-semi.c
+++ b/target/mips/tcg/sysemu/mips-semi.c
@@ -75,7 +75,7 @@ enum UHIOpenFlags {
 };
 
 /* Errno values taken from asm-mips/errno.h */
-static uint16_t host_to_mips_errno[] = {
+static const uint16_t host_to_mips_errno[] = {
     [ENAMETOOLONG] = 78,
 #ifdef EOVERFLOW
     [EOVERFLOW]    = 79,
-- 
2.31.1

[PATCH 9/9] target/mips: Optimize regnames[] arrays

[Philippe Mathieu-Daudé]

Since all entries are no more than 3/4/6 bytes (including nul
terminator), can save space and pie runtime relocations by
declaring regnames[] as array of 3/4/6 const char.

Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/internal.h          | 2 +-
 target/mips/cpu.c               | 2 +-
 target/mips/tcg/msa_translate.c | 2 +-
 target/mips/tcg/mxu_translate.c | 4 ++--
 target/mips/tcg/translate.c     | 4 ++--
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 18d5da64a57..eecdd101169 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -74,7 +74,7 @@ struct mips_def_t {
     int32_t SAARP;
 };
 
-extern const char regnames[32][4];
+extern const char regnames[32][3];
 extern const char fregnames[32][4];
 
 extern const struct mips_def_t mips_defs[];
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 96236abc006..d426918291a 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -35,7 +35,7 @@
 #include "qapi/qapi-commands-machine-target.h"
 #include "fpu_helper.h"
 
-const char regnames[32][4] = {
+const char regnames[32][3] = {
     "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
     "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
     "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index b3b06352bf2..a2f7d6a1e08 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -255,7 +255,7 @@ enum {
     OPC_BINSRI_df   = (0x7 << 23) | OPC_MSA_BIT_09,
 };
 
-static const char * const msaregnames[] = {
+static const char msaregnames[][6] = {
     "w0.d0",  "w0.d1",  "w1.d0",  "w1.d1",
     "w2.d0",  "w2.d1",  "w3.d0",  "w3.d1",
     "w4.d0",  "w4.d1",  "w5.d0",  "w5.d1",
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index f70a8ca59f4..e336518cdea 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -447,9 +447,9 @@ enum {
 static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
 static TCGv mxu_CR;
 
-static const char * const mxuregnames[] = {
+static const char mxuregnames[][4] = {
     "XR1",  "XR2",  "XR3",  "XR4",  "XR5",  "XR6",  "XR7",  "XR8",
-    "XR9",  "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR",
+    "XR9",  "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "XCR",
 };
 
 void mxu_translate_init(void)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 5d571d83c54..255f97fe9c1 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1281,11 +1281,11 @@ TCGv_i64 fpu_f64[32];
 #define DISAS_STOP       DISAS_TARGET_0
 #define DISAS_EXIT       DISAS_TARGET_1
 
-static const char * const regnames_HI[] = {
+static const char regnames_HI[][4] = {
     "HI0", "HI1", "HI2", "HI3",
 };
 
-static const char * const regnames_LO[] = {
+static const char regnames_LO[][4] = {
     "LO0", "LO1", "LO2", "LO3",
 };
 
-- 
2.31.1

Re: [PATCH 7/9] target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful cases

[Philippe Mathieu-Daudé]

On 6/17/21 7:43 PM, Philippe Mathieu-Daudé wrote:
> These switch cases for the microMIPS BPOSGE32 / BPOSGE64 opcodes have
> been added commit 3c824109da0 ("target-mips: microMIPS ASE support").
> More than 11 years later it is safe to assume there won't be added
> soon. The cases fall back to the default which generates a RESERVED
> INSTRUCTION, so it is safe to remove them.

I'll amend for clarity:

"Functionally speaking, the patch is a no-op."

> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/tcg/translate.c | 6 ------
>  1 file changed, 6 deletions(-)
> 
> diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
> index 47c7705f051..5d571d83c54 100644
> --- a/target/mips/tcg/translate.c
> +++ b/target/mips/tcg/translate.c
> @@ -14077,8 +14077,6 @@ enum {
>      BGEZALS = 0x13,
>      BC2F = 0x14,
>      BC2T = 0x15,
> -    BPOSGE64 = 0x1a,
> -    BPOSGE32 = 0x1b,
>      /* These overlap and are distinguished by bit16 of the instruction */
>      BC1F = 0x1c,
>      BC1T = 0x1d,
> @@ -16122,10 +16120,6 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
>                  generate_exception_err(ctx, EXCP_CpU, 1);
>              }
>              break;
> -        case BPOSGE64:
> -        case BPOSGE32:
> -            /* MIPS DSP: not implemented */
> -            /* Fall through */
>          default:
>              MIPS_INVAL("pool32i");
>              gen_reserved_instruction(ctx);
> 

Re: [PATCH 1/9] target/mips: Do not abort on invalid instruction

[Richard Henderson]

On 6/17/21 10:43 AM, Philippe Mathieu-Daudé wrote:
> On real hardware an invalid instruction doesn't halt the world,
> but usually triggers a RESERVED INSTRUCTION exception.
> TCG guest code shouldn't abort QEMU anyway.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/translate.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Re: [PATCH 2/9] target/mips: Fix more TCG temporary leaks in gen_pool32a5_nanomips_insn

[Richard Henderson]

On 6/17/21 10:43 AM, Philippe Mathieu-Daudé wrote:
> Fix multiple TCG temporary leaks in gen_pool32a5_nanomips_insn().
> 
> Fixes: 3285a3e4445 ("target/mips: Add emulation of DSP ASE for nanoMIPS - part 1")
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/translate.c | 4 ++++
>   1 file changed, 4 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 3/9] target/mips: Move TCG trace events to tcg/ sub directory

[Richard Henderson]

On 6/17/21 10:43 AM, Philippe Mathieu-Daudé wrote:
> Commit a2b0a27d33e ("target/mips: Move TCG source files under
> tcg/ sub directory") forgot to move the trace-event file.
> As it only contains TCG events, move it for consistency.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   meson.build                        | 2 +-
>   target/mips/tcg/translate.c        | 1 +
>   target/mips/{ => tcg}/trace-events | 0
>   3 files changed, 2 insertions(+), 1 deletion(-)
>   rename target/mips/{ => tcg}/trace-events (100%)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 4/9] target/mips: Move translate.h to tcg/ sub directory

[Richard Henderson]

On 6/17/21 10:43 AM, Philippe Mathieu-Daudé wrote:
> diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
> index ae6587edf69..b3b06352bf2 100644
> --- a/target/mips/tcg/msa_translate.c
> +++ b/target/mips/tcg/msa_translate.c
> @@ -13,7 +13,7 @@
>   #include "qemu/osdep.h"
>   #include "tcg/tcg-op.h"
>   #include "exec/helper-gen.h"
> -#include "translate.h"
> +#include "tcg/translate.h"
>   #include "fpu_helper.h"
>   #include "internal.h"

You shouldn't need to make include changes, because the search path for "" begins in the 
$cwd.  But I guess it works.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 5/9] target/mips: Restrict some system specific declarations to sysemu

[Richard Henderson]

On 6/17/21 10:43 AM, Philippe Mathieu-Daudé wrote:
> Commit 043715d1e0f ("target/mips: Update ITU to utilize SAARI
> and SAAR CP0 registers") declared itc_reconfigure() in public
> namespace, while it is restricted to system emulation.
> 
> Similarly commit 5679479b9a1 ("target/mips: Move CP0 helpers
> to sysemu/cp0.c") restricted cpu_mips_soft_irq() definition to
> system emulation, but forgot to restrict its declaration.
> 
> Commit a2b0a27d33e ("target/mips: Move TCG source files under
> tcg/ sub directory") restricted mips_cpu_do_unaligned_access()
> to system emulation but forgot to guard the declaration.

FWIW, I think the unaligned_access tcg_ops hook should be available for user-only as well, 
like for tlb_fill.  That it is sysemu only at the moment is a bug that affects user-only 
atomic access.

Anyway,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

> 
> To avoid polluting user-mode emulation with these declarations,
> restrict them to sysemu. Also restrict the sysemu ITU/ITC/IRQ
> fields from CPUMIPSState.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/cpu.h              | 10 +++++++---
>   target/mips/tcg/tcg-internal.h |  6 +++---
>   2 files changed, 10 insertions(+), 6 deletions(-)

Re: [PATCH 6/9] target/mips: Remove SmartMIPS / MDMX unuseful comments

[Richard Henderson]

On 6/17/21 10:43 AM, Philippe Mathieu-Daudé wrote:
> These placeholder comments for SmartMIPS and MDMX extensions have
> been added commit 3c824109da0 ("target-mips: microMIPS ASE support").
> More than 11 years later it is safe to assume there won't be added
> soon, so remove these unuseful comments.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/translate.c | 8 --------
>   1 file changed, 8 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 7/9] target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful cases

[Richard Henderson]

On 6/17/21 10:43 AM, Philippe Mathieu-Daudé wrote:
> These switch cases for the microMIPS BPOSGE32 / BPOSGE64 opcodes have
> been added commit 3c824109da0 ("target-mips: microMIPS ASE support").
> More than 11 years later it is safe to assume there won't be added
> soon. The cases fall back to the default which generates a RESERVED
> INSTRUCTION, so it is safe to remove them.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/translate.c | 6 ------
>   1 file changed, 6 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 8/9] target/mips: Constify host_to_mips_errno[]

[Richard Henderson]

On 6/17/21 10:43 AM, Philippe Mathieu-Daudé wrote:
> Keep host_to_mips_errno[] in .rodata by marking the array const.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/tcg/sysemu/mips-semi.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 9/9] target/mips: Optimize regnames[] arrays

[Richard Henderson]

On 6/17/21 10:43 AM, Philippe Mathieu-Daudé wrote:
> Since all entries are no more than 3/4/6 bytes (including nul
> terminator), can save space and pie runtime relocations by
> declaring regnames[] as array of 3/4/6 const char.
> 
> Inspired-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/mips/internal.h          | 2 +-
>   target/mips/cpu.c               | 2 +-
>   target/mips/tcg/msa_translate.c | 2 +-
>   target/mips/tcg/mxu_translate.c | 4 ++--
>   target/mips/tcg/translate.c     | 4 ++--
>   5 files changed, 7 insertions(+), 7 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 5/9] target/mips: Restrict some system specific declarations to sysemu

[Philippe Mathieu-Daudé]

On 6/19/21 12:38 AM, Richard Henderson wrote:
> On 6/17/21 10:43 AM, Philippe Mathieu-Daudé wrote:
>> Commit 043715d1e0f ("target/mips: Update ITU to utilize SAARI
>> and SAAR CP0 registers") declared itc_reconfigure() in public
>> namespace, while it is restricted to system emulation.
>>
>> Similarly commit 5679479b9a1 ("target/mips: Move CP0 helpers
>> to sysemu/cp0.c") restricted cpu_mips_soft_irq() definition to
>> system emulation, but forgot to restrict its declaration.
>>
>> Commit a2b0a27d33e ("target/mips: Move TCG source files under
>> tcg/ sub directory") restricted mips_cpu_do_unaligned_access()
>> to system emulation but forgot to guard the declaration.
> 
> FWIW, I think the unaligned_access tcg_ops hook should be available for
> user-only as well, like for tlb_fill.  That it is sysemu only at the
> moment is a bug that affects user-only atomic access.

OK understood, I'll drop that hunk.

> Anyway,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Thanks!

Re: [PATCH 0/9] target/mips: Various fixes & cleanups

[Philippe Mathieu-Daudé]

On 6/17/21 7:43 PM, Philippe Mathieu-Daudé wrote:
> Fixes and cleanup accumulated during the last month.
> Nothing particularly exciting :/
> 
> Please review,
> 
> Phil.
> 
> Philippe Mathieu-Daudé (9):
>   target/mips: Do not abort on invalid instruction
>   target/mips: Fix more TCG temporary leaks in
>     gen_pool32a5_nanomips_insn
>   target/mips: Move TCG trace events to tcg/ sub directory
>   target/mips: Move translate.h to tcg/ sub directory
>   target/mips: Restrict some system specific declarations to sysemu
>   target/mips: Remove SmartMIPS / MDMX unuseful comments
>   target/mips: Remove microMIPS BPOSGE32 / BPOSGE64 unuseful cases
>   target/mips: Constify host_to_mips_errno[]
>   target/mips: Optimize regnames[] arrays

Thanks, applied to mips-next (addressing Richard minor comments).