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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH 1/4] target/mips: Add declarations for generic TCG helpers
Date: Thu, 17 Jun 2021 19:49:04 +0200	[thread overview]
Message-ID: <20210617174907.2904067-2-f4bug@amsat.org> (raw)
In-Reply-To: <20210617174907.2904067-1-f4bug@amsat.org>

To be able to extract the microMIPS ISA and Code Compaction ASE
translation routines to different source files, declare few TCG
helpers which are also used by translate.c in "translate.h".

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/tcg/translate.h | 5 +++++
 target/mips/tcg/translate.c | 9 ++++-----
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 61442590340..c25fad597d5 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -146,6 +146,11 @@ void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
 void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
 int get_fp_bit(int cc);
 
+void gen_ldxs(DisasContext *ctx, int base, int index, int rd);
+void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp);
+void gen_addiupc(DisasContext *ctx, int rx, int imm,
+                 int is_64_bit, int extended);
+
 /*
  * Address Computation and Large Constant Instructions
  */
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 255f97fe9c1..c0ae180969e 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -5630,8 +5630,7 @@ static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
     tcg_temp_free(t0);
 }
 
-static void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt,
-                      int bp)
+void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp)
 {
     gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8);
 }
@@ -12779,8 +12778,8 @@ static void gen_mips16_restore(DisasContext *ctx,
     tcg_temp_free(t2);
 }
 
-static void gen_addiupc(DisasContext *ctx, int rx, int imm,
-                        int is_64_bit, int extended)
+void gen_addiupc(DisasContext *ctx, int rx, int imm,
+                 int is_64_bit, int extended)
 {
     TCGv t0;
 
@@ -14511,7 +14510,7 @@ static void gen_pool16c_r6_insn(DisasContext *ctx)
     }
 }
 
-static void gen_ldxs(DisasContext *ctx, int base, int index, int rd)
+void gen_ldxs(DisasContext *ctx, int base, int index, int rd)
 {
     TCGv t0 = tcg_temp_new();
     TCGv t1 = tcg_temp_new();
-- 
2.31.1



  reply	other threads:[~2021-06-17 17:54 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-17 17:49 [PATCH 0/4] target/mips: Extract microMIPS ISA and Code Compaction ASE apart Philippe Mathieu-Daudé
2021-06-17 17:49 ` Philippe Mathieu-Daudé [this message]
2021-06-18 20:15   ` [PATCH 1/4] target/mips: Add declarations for generic TCG helpers Richard Henderson
2021-06-19  9:26     ` Philippe Mathieu-Daudé
2021-06-19 12:41       ` Richard Henderson
2021-06-28 16:33         ` Philippe Mathieu-Daudé
2021-06-28 21:31           ` Richard Henderson
2021-06-17 17:49 ` [PATCH 2/4] target/mips: Extract Code Compaction ASE translation routines Philippe Mathieu-Daudé
2021-06-17 17:49 ` [PATCH 3/4] target/mips: Extract the microMIPS ISA " Philippe Mathieu-Daudé
2021-06-17 17:49 ` [PATCH 4/4] target/mips: Add declarations for generic DSP TCG helpers Philippe Mathieu-Daudé
2021-06-17 18:25   ` Philippe Mathieu-Daudé
2021-06-18 20:17   ` Richard Henderson
2021-06-29  4:35 ` [PATCH 0/4] target/mips: Extract microMIPS ISA and Code Compaction ASE apart Philippe Mathieu-Daudé

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