From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84D4BC48BDF for ; Fri, 18 Jun 2021 09:25:36 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7400B60C3D for ; Fri, 18 Jun 2021 09:25:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7400B60C3D Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D3E7E82AE1; Fri, 18 Jun 2021 11:25:32 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="h0E+9zkP"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A4D4282A29; Fri, 18 Jun 2021 11:25:30 +0200 (CEST) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A4E9680488 for ; Fri, 18 Jun 2021 11:25:26 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=p.yadav@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 15I9PGi4033530; Fri, 18 Jun 2021 04:25:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1624008316; bh=ArIPt401VVYgCGxcmuyorhn2xHQM4K+ucd/9rQ7wHgI=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=h0E+9zkPUjSaD4J2y/ceaAu3gUvP9yNQrd0DDM4PssIa0njdQaoOPugVoeB7tDzS/ JJHkECjuy1w5FlyFc5CupXicQtp9x5b7V4VUujQ/b+2J/BTTvcJJYpm44ixKMVYVkZ t047Etm5X31DR5npEMFD3F6Ccs/zO0o3cM3DlA9g= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 15I9PGIg073138 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Jun 2021 04:25:16 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Fri, 18 Jun 2021 04:25:16 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Fri, 18 Jun 2021 04:25:16 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 15I9PFkF068112; Fri, 18 Jun 2021 04:25:16 -0500 Date: Fri, 18 Jun 2021 14:55:14 +0530 From: Pratyush Yadav To: CC: , , , , , , , , Subject: Re: [v9,23/28] mtd: spi-nor-core: Perform a Soft Reset on shutdown Message-ID: <20210618092512.grudqq6vjawt3y5w@ti.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi, On 18/06/21 04:55PM, jaimeliao@mxic.com.tw wrote: > > Hi Pratyush > > > +#ifdef CONFIG_SPI_FLASH_SOFT_RESET > +/** > + * spi_nor_soft_reset() - perform the JEDEC Software Reset sequence > + * @nor: the spi_nor structure > + * > + * This function can be used to switch from Octal DTR mode to legacy mode > on a > + * flash that supports it. The soft reset is executed in Octal DTR mode. > + * > + * Return: 0 for success, -errno for failure. > + */ > +static int spi_nor_soft_reset(struct spi_nor *nor) > +{ > + struct spi_mem_op op; > + int ret; > + enum spi_nor_cmd_ext ext; > + > + ext = nor->cmd_ext_type; > + nor->cmd_ext_type = SPI_NOR_EXT_REPEAT; > According JEDEC, cmd_ext_type has two different types, REPEAT and INVERT. > Some Flash vendor using "INVERT" as cmd_ext_type so that it is not > suitable for hard coding the type as REPEAT. > Sending twice reset command with different types is clumsy but useful > before read ID for getting Flash information. > It would be great if you have any other ideas for this part. It is possible to discover the extension type from BFPT (if the flash supports it, that is). But this function is supposed to be called before anything else to make sure the flash is in a sane state. For that reason, I don't think SFDP would be a viable approach. Executing it twice might be a viable option. We need to see how flash that expect invert react to a repeat opcode, and vice versa. Anyway, I don't think this is a problem for now. Both the 8D-8D-8D capable flashes supported with this series expect a repeat opcode. > > + > + op = (struct > spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0), > + SPI_MEM_OP_NO_DUMMY, > + SPI_MEM_OP_NO_ADDR, > + SPI_MEM_OP_NO_DATA); > + spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); > + ret = spi_mem_exec_op(nor->spi, &op); > + if (ret) { > + dev_warn(nor->dev, "Software reset enable > failed: %d\n", ret); > + goto out; > + } > + > + op = (struct > spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0), > + SPI_MEM_OP_NO_DUMMY, > + SPI_MEM_OP_NO_ADDR, > + SPI_MEM_OP_NO_DATA); > + spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); > + ret = spi_mem_exec_op(nor->spi, &op); > + if (ret) { > + dev_warn(nor->dev, "Software reset > failed: %d\n", ret); > + goto out; > + } > + > + /* > + * Software Reset is not instant, and the delay varies > from flash to > + * flash. Looking at a few flashes, most range somewhere > below 100 > + * microseconds. So, wait for 200ms just to be sure. > + */ > + udelay(SPI_NOR_SRST_SLEEP_LEN); > + > +out: > + nor->cmd_ext_type = ext; > + return ret; > +} > > > Thanks > Jaime -- Regards, Pratyush Yadav Texas Instruments Inc.