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From: Bindu Ramamurthy <bindu.r@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>,
	Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Qingqing.Zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	Nikola Cornij <nikola.cornij@amd.com>,
	Anson.Jacob@amd.com, Aurabindo.Pillai@amd.com,
	Bhawanpreet.Lakha@amd.com, bindu.r@amd.com
Subject: [PATCH 02/12] drm/amd/display: Clamp VStartup value at DML calculations time
Date: Fri, 18 Jun 2021 13:35:04 -0400	[thread overview]
Message-ID: <20210618173514.430647-3-bindu.r@amd.com> (raw)
In-Reply-To: <20210618173514.430647-1-bindu.r@amd.com>

From: Nikola Cornij <nikola.cornij@amd.com>

[why]
Some timings with a large VBlank cause the value to overflow the
register related, while also producing other wrong values in DML output.

[how]
Clamp VStartup at the DCN3.1 maximum value

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
---
 .../gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c    | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index 06fac59a3d40..718d5a99dada 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -2668,6 +2668,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 												(double) v->WritebackDelay[v->VoltageLevel][k]
 														/ (v->HTotal[k] / v->PixelClock[k]),
 												1));
+		if (v->MaxVStartupLines[k] > 1023)
+			v->MaxVStartupLines[k] = 1023;
 
 #ifdef __DML_VBA_DEBUG__
 		dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
@@ -5064,6 +5066,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 																/ (v->HTotal[k]
 																		/ v->PixelClock[k]),
 														1.0));
+				if (v->MaximumVStartup[i][j][k] > 1023)
+					v->MaximumVStartup[i][j][k] = 1023;
 				v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
 			}
 		}
-- 
2.25.1

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  parent reply	other threads:[~2021-06-18 17:35 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-18 17:35 [PATCH 00/12] June, 21, 2021 Bindu Ramamurthy
2021-06-18 17:35 ` [PATCH 01/12] drm/amd/display: Multiplane cursor position incorrect when plane rotated Bindu Ramamurthy
2021-06-18 17:35 ` Bindu Ramamurthy [this message]
2021-06-18 17:35 ` [PATCH 03/12] drm/amd/display: Clear lane settings after LTTPRs have been trained Bindu Ramamurthy
2021-06-18 17:35 ` [PATCH 04/12] drm/amd/display: Fix incorrect variable name Bindu Ramamurthy
2021-06-18 17:35 ` [PATCH 05/12] drm/amd/display: get socBB from VBIOS for dcn302 and dcn303 Bindu Ramamurthy
2021-06-18 17:35 ` [PATCH 06/12] drm/amd/display: Delay PSR entry Bindu Ramamurthy
2021-06-18 17:35 ` [PATCH 07/12] drm/amd/display: get refclk from MICROSECOND_TIME_BASE_DIV HW register Bindu Ramamurthy
2021-06-18 18:39 ` [PATCH 00/12] June, 21, 2021 Wheeler, Daniel

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