From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59B41C4743C for ; Mon, 21 Jun 2021 10:11:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3D6F2611C1 for ; Mon, 21 Jun 2021 10:11:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229641AbhFUKNT (ORCPT ); Mon, 21 Jun 2021 06:13:19 -0400 Received: from mail.kernel.org ([198.145.29.99]:58116 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229663AbhFUKNS (ORCPT ); Mon, 21 Jun 2021 06:13:18 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id C41F860FE9; Mon, 21 Jun 2021 10:11:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1624270264; bh=bVbHmO+KD1RJdeZ8rCLmbHPMTnDTtKhwg9BcddwTEwU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=avT6x6VkGk5MZHaL6aTfxrWF7tmL/lqPZr2/16klm8yIwdt1+1jlFalN/qXiBG2u5 7+DsBi3PBzf3Y9/vj0d2I0b1dZMaI2ER7HDUISNzseQnJtiwTmz/e9ulfDzQcSwd07 H+2DkCGabRisfCfE5DqJk1F4/dpcwKrhSGRRQpAuZszgVPTcqfUSKt4woZNYlmcgBx YmnuDqP3B3z6gD3xiBj6OTbzbtSR9de+vZ2BtEAD7g37c8zBQyFmT9h6hJ/MPfvzv2 s2Ld76p3IghlOt9nojHfhXaOWt70pvYm3Ho2QAEmtcLDsmNC9vU25SbLWRBUTWdRiD XMlTI9UPOlQzA== Date: Mon, 21 Jun 2021 11:10:59 +0100 From: Will Deacon To: Daniel Lezcano Cc: Chanwoo Choi , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marek Szyprowski , Krzysztof Kozlowski , Krzysztof Kozlowski , Thomas Gleixner Subject: Re: [PATCH 1/2] clocksource/drivers/exynos_mct: Prioritise Arm arch timer on arm64 Message-ID: <20210621101058.GB28788@willie-the-truck> References: <20210608154341.10794-1-will@kernel.org> <20210608154341.10794-2-will@kernel.org> <466bfc19-2260-87c6-c458-b43cf23617e3@samsung.com> <2a0181ea-a26e-65e9-16f6-cc233b6b296f@linaro.org> <20210617214748.GC25403@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jun 21, 2021 at 11:25:47AM +0200, Daniel Lezcano wrote: > On 17/06/2021 23:47, Will Deacon wrote: > > On Thu, Jun 17, 2021 at 09:58:35AM +0900, Chanwoo Choi wrote: > >> On 6/17/21 12:25 AM, Daniel Lezcano wrote: > >>> On 10/06/2021 03:03, Chanwoo Choi wrote: > >>>> On 6/9/21 12:43 AM, Will Deacon wrote: > >>>>> diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c > >>>>> index fabad79baafc..804d3e01c8f4 100644 > >>>>> --- a/drivers/clocksource/exynos_mct.c > >>>>> +++ b/drivers/clocksource/exynos_mct.c > >>>>> @@ -51,6 +51,15 @@ > >>>>> > >>>>> #define TICK_BASE_CNT 1 > >>>>> > >>>>> +#ifdef CONFIG_ARM > >>>>> +/* Use values higher than ARM arch timer. See 6282edb72bed. */ > >>>>> +#define MCT_CLKSOURCE_RATING 450 > >>>>> +#define MCT_CLKEVENTS_RATING 500 > >>>>> +#else > >>>>> +#define MCT_CLKSOURCE_RATING 350 > >>>>> +#define MCT_CLKEVENTS_RATING 350 > >>>>> +#endif > >>>>> + > >>>>> enum { > >>>>> MCT_INT_SPI, > >>>>> MCT_INT_PPI > >>>>> @@ -206,7 +215,7 @@ static void exynos4_frc_resume(struct clocksource *cs) > >>>>> > >>>>> static struct clocksource mct_frc = { > >>>>> .name = "mct-frc", > >>>>> - .rating = 450, /* use value higher than ARM arch timer */ > >>>>> + .rating = MCT_CLKSOURCE_RATING, > >>>>> .read = exynos4_frc_read, > >>>>> .mask = CLOCKSOURCE_MASK(32), > >>>>> .flags = CLOCK_SOURCE_IS_CONTINUOUS, > >>>>> @@ -457,7 +466,7 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) > >>>>> evt->set_state_oneshot_stopped = set_state_shutdown; > >>>>> evt->tick_resume = set_state_shutdown; > >>>>> evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; > >>>>> - evt->rating = 500; /* use value higher than ARM arch timer */ > >>>>> + evt->rating = MCT_CLKEVENTS_RATING, > >>>>> > >>>>> exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); > >>>>> > >>>>> > >>>> > >>>> I'm not sure that exynos mct is working without problem > >>>> such as the case of 6282edb72bed. > >>>> As described on On ,6282edb72bed the arch timer on exynos SoC > >>>> depends on Exynos MCT device. the arch timer is not able to work > >>>> without Exynos MCT because of using the common module. > >>> > >>> Is it possible to change the DT to have a phandle to the exynos_mct, so > >>> it will be probed before the arch_arm_timer ? > >> > >> I think that DT changes is not proper way to keep the order between > >> exynos_mct and arch timer. > > > > exynos4_mct_frc_start() is called unconditionally from probe via > > exynos4_clocksource_init() so as long as the mct probes first, then the > > arch timer should work, no? The rating shouldn't affect that. > > How do you ensure the exynos mct is probed before the arch timer ? > > The Makefile provides the right order, but the dependency is implicit. Currently, I think it's done by the order of the CPU hotplug notifiers ( see the hunk of 6282edb72bed which touches cpuhotplug.h). Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15447C4743C for ; Mon, 21 Jun 2021 10:12:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CC65960FE9 for ; Mon, 21 Jun 2021 10:12:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CC65960FE9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; 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Mon, 21 Jun 2021 10:11:08 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lvGtU-0033Lt-Li for linux-arm-kernel@lists.infradead.org; Mon, 21 Jun 2021 10:11:06 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id C41F860FE9; Mon, 21 Jun 2021 10:11:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1624270264; bh=bVbHmO+KD1RJdeZ8rCLmbHPMTnDTtKhwg9BcddwTEwU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=avT6x6VkGk5MZHaL6aTfxrWF7tmL/lqPZr2/16klm8yIwdt1+1jlFalN/qXiBG2u5 7+DsBi3PBzf3Y9/vj0d2I0b1dZMaI2ER7HDUISNzseQnJtiwTmz/e9ulfDzQcSwd07 H+2DkCGabRisfCfE5DqJk1F4/dpcwKrhSGRRQpAuZszgVPTcqfUSKt4woZNYlmcgBx YmnuDqP3B3z6gD3xiBj6OTbzbtSR9de+vZ2BtEAD7g37c8zBQyFmT9h6hJ/MPfvzv2 s2Ld76p3IghlOt9nojHfhXaOWt70pvYm3Ho2QAEmtcLDsmNC9vU25SbLWRBUTWdRiD XMlTI9UPOlQzA== Date: Mon, 21 Jun 2021 11:10:59 +0100 From: Will Deacon To: Daniel Lezcano Cc: Chanwoo Choi , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marek Szyprowski , Krzysztof Kozlowski , Krzysztof Kozlowski , Thomas Gleixner Subject: Re: [PATCH 1/2] clocksource/drivers/exynos_mct: Prioritise Arm arch timer on arm64 Message-ID: <20210621101058.GB28788@willie-the-truck> References: <20210608154341.10794-1-will@kernel.org> <20210608154341.10794-2-will@kernel.org> <466bfc19-2260-87c6-c458-b43cf23617e3@samsung.com> <2a0181ea-a26e-65e9-16f6-cc233b6b296f@linaro.org> <20210617214748.GC25403@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210621_031104_786392_49368F89 X-CRM114-Status: GOOD ( 26.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jun 21, 2021 at 11:25:47AM +0200, Daniel Lezcano wrote: > On 17/06/2021 23:47, Will Deacon wrote: > > On Thu, Jun 17, 2021 at 09:58:35AM +0900, Chanwoo Choi wrote: > >> On 6/17/21 12:25 AM, Daniel Lezcano wrote: > >>> On 10/06/2021 03:03, Chanwoo Choi wrote: > >>>> On 6/9/21 12:43 AM, Will Deacon wrote: > >>>>> diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c > >>>>> index fabad79baafc..804d3e01c8f4 100644 > >>>>> --- a/drivers/clocksource/exynos_mct.c > >>>>> +++ b/drivers/clocksource/exynos_mct.c > >>>>> @@ -51,6 +51,15 @@ > >>>>> > >>>>> #define TICK_BASE_CNT 1 > >>>>> > >>>>> +#ifdef CONFIG_ARM > >>>>> +/* Use values higher than ARM arch timer. See 6282edb72bed. */ > >>>>> +#define MCT_CLKSOURCE_RATING 450 > >>>>> +#define MCT_CLKEVENTS_RATING 500 > >>>>> +#else > >>>>> +#define MCT_CLKSOURCE_RATING 350 > >>>>> +#define MCT_CLKEVENTS_RATING 350 > >>>>> +#endif > >>>>> + > >>>>> enum { > >>>>> MCT_INT_SPI, > >>>>> MCT_INT_PPI > >>>>> @@ -206,7 +215,7 @@ static void exynos4_frc_resume(struct clocksource *cs) > >>>>> > >>>>> static struct clocksource mct_frc = { > >>>>> .name = "mct-frc", > >>>>> - .rating = 450, /* use value higher than ARM arch timer */ > >>>>> + .rating = MCT_CLKSOURCE_RATING, > >>>>> .read = exynos4_frc_read, > >>>>> .mask = CLOCKSOURCE_MASK(32), > >>>>> .flags = CLOCK_SOURCE_IS_CONTINUOUS, > >>>>> @@ -457,7 +466,7 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) > >>>>> evt->set_state_oneshot_stopped = set_state_shutdown; > >>>>> evt->tick_resume = set_state_shutdown; > >>>>> evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; > >>>>> - evt->rating = 500; /* use value higher than ARM arch timer */ > >>>>> + evt->rating = MCT_CLKEVENTS_RATING, > >>>>> > >>>>> exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); > >>>>> > >>>>> > >>>> > >>>> I'm not sure that exynos mct is working without problem > >>>> such as the case of 6282edb72bed. > >>>> As described on On ,6282edb72bed the arch timer on exynos SoC > >>>> depends on Exynos MCT device. the arch timer is not able to work > >>>> without Exynos MCT because of using the common module. > >>> > >>> Is it possible to change the DT to have a phandle to the exynos_mct, so > >>> it will be probed before the arch_arm_timer ? > >> > >> I think that DT changes is not proper way to keep the order between > >> exynos_mct and arch timer. > > > > exynos4_mct_frc_start() is called unconditionally from probe via > > exynos4_clocksource_init() so as long as the mct probes first, then the > > arch timer should work, no? The rating shouldn't affect that. > > How do you ensure the exynos mct is probed before the arch timer ? > > The Makefile provides the right order, but the dependency is implicit. Currently, I think it's done by the order of the CPU hotplug notifiers ( see the hunk of 6282edb72bed which touches cpuhotplug.h). Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel