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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n65sm11615496wme.21.2021.06.21.09.28.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Jun 2021 09:28:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 00/57] target-arm queue Date: Mon, 21 Jun 2021 17:27:36 +0100 Message-Id: <20210621162833.32535-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The following changes since commit 53f306f316549d20c76886903181413d20842423: Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210621 for you to fetch changes up to a83f1d9263d281f938a3984cda7104d55affd43a: docs/system: arm: Add nRF boards description (2021-06-21 17:24:33 +0100) ---------------------------------------------------------------- target-arm queue: * Don't require 'virt' board to be compiled in for ACPI GHES code * docs: Document which architecture extensions we emulate * Fix bugs in M-profile FPCXT_NS accesses * First slice of MVE patches * Implement MTE3 * docs/system: arm: Add nRF boards description ---------------------------------------------------------------- Alexandre Iooss (1): docs/system: arm: Add nRF boards description Peter Collingbourne (1): target/arm: Implement MTE3 Peter Maydell (55): hw/acpi: Provide stub version of acpi_ghes_record_errors() hw/acpi: Provide function acpi_ghes_present() target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors docs/system/arm: Document which architecture extensions we emulate target/arm/translate-vfp.c: Whitespace fixes target/arm: Handle FPU being disabled in FPCXT_NS accesses target/arm: Don't NOCP fault for FPCXT_NS accesses target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access target/arm: Factor FP context update code out into helper function target/arm: Split vfp_access_check() into A and M versions target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m() target/arm: Implement MVE VLDR/VSTR (non-widening forms) target/arm: Implement widening/narrowing MVE VLDR/VSTR insns target/arm: Implement MVE VCLZ target/arm: Implement MVE VCLS target/arm: Implement MVE VREV16, VREV32, VREV64 target/arm: Implement MVE VMVN (register) target/arm: Implement MVE VABS target/arm: Implement MVE VNEG tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64 target/arm: Implement MVE VDUP target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR target/arm: Implement MVE VADD, VSUB, VMUL target/arm: Implement MVE VMULH target/arm: Implement MVE VRMULH target/arm: Implement MVE VMAX, VMIN target/arm: Implement MVE VABD target/arm: Implement MVE VHADD, VHSUB target/arm: Implement MVE VMULL target/arm: Implement MVE VMLALDAV target/arm: Implement MVE VMLSLDAV target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH target/arm: Implement MVE VADD (scalar) target/arm: Implement MVE VSUB, VMUL (scalar) target/arm: Implement MVE VHADD, VHSUB (scalar) target/arm: Implement MVE VBRSR target/arm: Implement MVE VPST target/arm: Implement MVE VQADD and VQSUB target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) target/arm: Implement MVE VQDMULL scalar target/arm: Implement MVE VQDMULH, VQRDMULH (vector) target/arm: Implement MVE VQADD, VQSUB (vector) target/arm: Implement MVE VQSHL (vector) target/arm: Implement MVE VQRSHL target/arm: Implement MVE VSHL insn target/arm: Implement MVE VRSHL target/arm: Implement MVE VQDMLADH and VQRDMLADH target/arm: Implement MVE VQDMLSDH and VQRDMLSDH target/arm: Implement MVE VQDMULL (vector) target/arm: Implement MVE VRHADD target/arm: Implement MVE VADC, VSBC target/arm: Implement MVE VCADD target/arm: Implement MVE VHCADD target/arm: Implement MVE VADDV target/arm: Make VMOV scalar <-> gpreg beatwise for MVE docs/system/arm/emulation.rst | 103 ++++ docs/system/arm/nrf.rst | 51 ++ docs/system/target-arm.rst | 7 + include/hw/acpi/ghes.h | 9 + include/tcg/tcg-op.h | 8 + include/tcg/tcg.h | 1 - target/arm/helper-mve.h | 357 +++++++++++++ target/arm/helper.h | 2 + target/arm/internals.h | 11 + target/arm/translate-a32.h | 3 + target/arm/translate.h | 10 + target/arm/m-nocp.decode | 24 + target/arm/mve.decode | 240 +++++++++ target/arm/vfp.decode | 14 - hw/acpi/ghes-stub.c | 22 + hw/acpi/ghes.c | 17 + target/arm/cpu64.c | 2 +- target/arm/kvm64.c | 6 +- target/arm/mte_helper.c | 82 +-- target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++ target/arm/translate-m-nocp.c | 550 +++++++++++++++++++ target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++ target/arm/translate-vfp.c | 741 +++++++------------------- tcg/tcg-op-gvec.c | 20 +- MAINTAINERS | 1 + hw/acpi/meson.build | 6 +- target/arm/meson.build | 1 + 27 files changed, 3578 insertions(+), 629 deletions(-) create mode 100644 docs/system/arm/emulation.rst create mode 100644 docs/system/arm/nrf.rst create mode 100644 target/arm/helper-mve.h create mode 100644 hw/acpi/ghes-stub.c create mode 100644 target/arm/mve_helper.c