From: Will Deacon <email@example.com> To: Frank Li <firstname.lastname@example.org> Cc: Catalin Marinas <email@example.com>, Zhi Li <firstname.lastname@example.org>, Shenwei Wang <email@example.com>, Han Xu <firstname.lastname@example.org>, Nitin Garg <email@example.com>, Jason Liu <firstname.lastname@example.org>, "email@example.com" <firstname.lastname@example.org> Subject: Re: [EXT] Re: The problem about arm64: io: Relax implicit barriers in default I/O accessors Date: Mon, 21 Jun 2021 17:59:42 +0100 [thread overview] Message-ID: <20210621165941.GB29595@willie-the-truck> (raw) In-Reply-To: <20210621162641.GA29595@willie-the-truck> On Mon, Jun 21, 2021 at 05:26:41PM +0100, Will Deacon wrote: > On Mon, Jun 21, 2021 at 04:11:57PM +0000, Frank Li wrote: > > > Oh, interesting. Maybe this is a case where OSH vs SY actually makes a > > > difference. I'm not quite sure what it means for the coherency of normal, > > > non-cacheable accesses (which are outer-shareable) so that probably needs a > > > bit more thought. > > > > > > Can you confirm that the issue *does* still occur if you use dmb(osh) > > > instead of dmb(oshst), please? > > > > After get ARM support https://services.arm.com/support/s/case/5003t00001RuJHw, > > This issue have some progress. > > > > Our system configure SYSBARDISABLE = 0x0, So ARM core barrier propagate to CCI-400 > > > > Our DMA and USB is located below downstream of CCI-400. So USB or DMA is located > > in system shared domain. Only use dmb(st), CCI-400 wait for previous transaction > > Complete. When dma(osh), the response is sent when snoop responses are received for > > all earlier transactions. CCI-400 don't wait for previous write finish. > > Thanks for following up. I'll cook a patch to fix this... ... and in doing so, I realised I still have a question about this. If a CPU is writing to a zero-initialised non-cacheable buffer in memory and does something like: buffer = 1; dma_wmb(); // DMB OSHST buffer = 1; would a non-coherent device reading this be able to see buffer == 1 but buffer = 0? In other words, do we need to upgrade the dmb_* barriers as well as the I/O accessors, or are they still ordered by the bus fabric because all of the accesses are going to the DDR? Will _______________________________________________ linux-arm-kernel mailing list email@example.com http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-06-21 17:01 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <AS8PR04MB850004639EE6CE9432BBF13E880F9@AS8PR04MB8500.eurprd04.prod.outlook.com> [not found] ` <CAHrpEqRsp2_bt=p5JgS5F-2F_LCwgT+VX7mSENzpEYTQiW1tjg@mail.gmail.com> 2021-06-17 9:27 ` Catalin Marinas 2021-06-17 17:25 ` Will Deacon 2021-06-17 17:41 ` Will Deacon 2021-06-17 20:11 ` [EXT] " Frank Li 2021-06-17 21:40 ` Will Deacon 2021-06-17 22:13 ` Frank Li 2021-06-18 14:56 ` Nitin Garg 2021-06-21 16:11 ` Frank Li 2021-06-21 16:26 ` Will Deacon 2021-06-21 16:59 ` Will Deacon [this message] 2021-06-21 17:56 ` Frank Li 2021-06-21 18:13 ` Will Deacon 2021-06-21 21:32 ` Frank Li 2021-06-22 9:11 ` Will Deacon 2021-06-23 15:48 ` Frank Li 2021-07-06 17:11 ` Will Deacon 2021-07-15 15:53 ` Frank Li 2021-07-22 19:14 ` Frank Li 2021-08-09 13:50 ` Will Deacon 2021-08-09 14:46 ` Frank Li 2021-08-09 15:26 ` Will Deacon 2021-08-10 18:50 ` Frank Li
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