* [PATCH v7 0/3] drm/i915: Move system memory to TTM for discrete
@ 2021-06-22 9:34 ` Thomas Hellström
0 siblings, 0 replies; 19+ messages in thread
From: Thomas Hellström @ 2021-06-22 9:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Thomas Hellström, matthew.auld
Early implementation of moving system memory for discrete cards over to
TTM. We first add the notion of objects being migratable under the object
lock to i915 gem, and add some asserts to verify that objects are either
locked or pinned when the placement is checked by the gem code.
Patch 2 deals with updating the i915 gem bookkeeping after a TTM move,
Patch 3 moves system over from shmem to TTM for discrete
Note that the mock device doesn't consider itself discrete so the TTM
system path is not checked by the mock selftests.
v2:
- Style fixes (reported by Matthew Auld)
- Drop the last patch (migration) It needs selftests and some additional work.
- Unconditionally add VM_IO at mmap time.
v3:
- More style fixes (reported by Matthew Auld)
- Don't overfill the busy placement vector (reported by Matthew Auld)
v4:
- Remove confusion around shrinkable objects (reported by Matthew Auld)
v5:
- Remove confusion around shrinkable objects again, but this time in the
correct patch. (reported by Matthew Auld)
v6:
- One patch already committed.
- Introduce a __i915_gem_object_is_lmem() to be used in situations where we
know that a fence that can't currently signal keeps the object from being
migrated or evicted.
- Rebase on accelerated TTM moves
- Fix TODO:s for supporting system memory with TTM.
- Update the object GEM region after a TTM move if compatible.
- Move a couple of warnings for shmem on DGFX.
v7:
- Just updated a commit message with version history under dashes.
Thomas Hellström (3):
drm/i915: Update object placement flags to be mutable
drm/i915/ttm: Adjust gem flags and caching settings after a move
drm/i915/ttm: Use TTM for system memory
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 22 ++
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 2 +
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 12 +-
drivers/gpu/drm/i915/gem/i915_gem_object.c | 38 ++++
drivers/gpu/drm/i915/gem/i915_gem_object.h | 14 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 20 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 10 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 194 +++++++++++++-----
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 4 +-
.../drm/i915/gem/selftests/huge_gem_object.c | 4 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 5 +-
.../drm/i915/gem/selftests/i915_gem_mman.c | 4 +-
.../drm/i915/gem/selftests/i915_gem_phys.c | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 3 -
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/intel_memory_region.c | 7 +-
drivers/gpu/drm/i915/intel_memory_region.h | 8 +
20 files changed, 265 insertions(+), 95 deletions(-)
--
2.31.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v7 0/3] drm/i915: Move system memory to TTM for discrete
@ 2021-06-22 9:34 ` Thomas Hellström
0 siblings, 0 replies; 19+ messages in thread
From: Thomas Hellström @ 2021-06-22 9:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Thomas Hellström, matthew.auld
Early implementation of moving system memory for discrete cards over to
TTM. We first add the notion of objects being migratable under the object
lock to i915 gem, and add some asserts to verify that objects are either
locked or pinned when the placement is checked by the gem code.
Patch 2 deals with updating the i915 gem bookkeeping after a TTM move,
Patch 3 moves system over from shmem to TTM for discrete
Note that the mock device doesn't consider itself discrete so the TTM
system path is not checked by the mock selftests.
v2:
- Style fixes (reported by Matthew Auld)
- Drop the last patch (migration) It needs selftests and some additional work.
- Unconditionally add VM_IO at mmap time.
v3:
- More style fixes (reported by Matthew Auld)
- Don't overfill the busy placement vector (reported by Matthew Auld)
v4:
- Remove confusion around shrinkable objects (reported by Matthew Auld)
v5:
- Remove confusion around shrinkable objects again, but this time in the
correct patch. (reported by Matthew Auld)
v6:
- One patch already committed.
- Introduce a __i915_gem_object_is_lmem() to be used in situations where we
know that a fence that can't currently signal keeps the object from being
migrated or evicted.
- Rebase on accelerated TTM moves
- Fix TODO:s for supporting system memory with TTM.
- Update the object GEM region after a TTM move if compatible.
- Move a couple of warnings for shmem on DGFX.
v7:
- Just updated a commit message with version history under dashes.
Thomas Hellström (3):
drm/i915: Update object placement flags to be mutable
drm/i915/ttm: Adjust gem flags and caching settings after a move
drm/i915/ttm: Use TTM for system memory
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 22 ++
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 2 +
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 12 +-
drivers/gpu/drm/i915/gem/i915_gem_object.c | 38 ++++
drivers/gpu/drm/i915/gem/i915_gem_object.h | 14 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 20 +-
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 10 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 194 +++++++++++++-----
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 4 +-
.../drm/i915/gem/selftests/huge_gem_object.c | 4 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 5 +-
.../drm/i915/gem/selftests/i915_gem_mman.c | 4 +-
.../drm/i915/gem/selftests/i915_gem_phys.c | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 3 -
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/intel_memory_region.c | 7 +-
drivers/gpu/drm/i915/intel_memory_region.h | 8 +
20 files changed, 265 insertions(+), 95 deletions(-)
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v7 1/3] drm/i915: Update object placement flags to be mutable
2021-06-22 9:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-22 9:34 ` Thomas Hellström
-1 siblings, 0 replies; 19+ messages in thread
From: Thomas Hellström @ 2021-06-22 9:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Thomas Hellström, matthew.auld
The object ops i915_GEM_OBJECT_HAS_IOMEM and the object
I915_BO_ALLOC_STRUCT_PAGE flags are considered immutable by
much of our code. Introduce a new mem_flags member to hold these
and make sure checks for these flags being set are either done
under the object lock or with pages properly pinned. The flags
will change during migration under the object lock.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
v2:
- Unconditionally set VM_IO on our VMAs in line with the rest core gem
and TTM. Since the bo might be migrated while the VMA is still alive,
there is no sense, whether or not it maps iomem might change.
v6:
- Introduce a __i915_gem_object_is_lmem() to be used in situations where we
know that a fence that can't currently signal keeps the object from being
migrated or evicted.
- Move a couple of shmem warnings for DGFX to a later patch where we
actually move system memory to TTM.
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 22 +++++++++++
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 2 +
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 12 +++---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 38 +++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_object.h | 14 ++-----
.../gpu/drm/i915/gem/i915_gem_object_types.h | 20 +++++-----
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 7 ++--
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 4 +-
.../drm/i915/gem/selftests/huge_gem_object.c | 4 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 5 +--
.../drm/i915/gem/selftests/i915_gem_mman.c | 4 +-
.../drm/i915/gem/selftests/i915_gem_phys.c | 3 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
17 files changed, 101 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index ce6b664b10aa..13b217f75055 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -177,8 +177,8 @@ i915_gem_object_create_internal(struct drm_i915_private *i915,
return ERR_PTR(-ENOMEM);
drm_gem_private_object_init(&i915->drm, &obj->base, size);
- i915_gem_object_init(obj, &i915_gem_object_internal_ops, &lock_class,
- I915_BO_ALLOC_STRUCT_PAGE);
+ i915_gem_object_init(obj, &i915_gem_object_internal_ops, &lock_class, 0);
+ obj->mem_flags |= I915_BO_FLAG_STRUCT_PAGE;
/*
* Mark the object as volatile, such that the pages are marked as
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index d539dffa1554..41d5182cd367 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -71,6 +71,28 @@ bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
mr->type == INTEL_MEMORY_STOLEN_LOCAL);
}
+/**
+ * __i915_gem_object_is_lmem - Whether the object is resident in
+ * lmem while in the fence signaling critical path.
+ * @obj: The object to check.
+ *
+ * This function is intended to be called from within the fence signaling
+ * path where the fence keeps the object from being migrated. For example
+ * during gpu reset or similar.
+ *
+ * Return: Whether the object is resident in lmem.
+ */
+bool __i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *mr = READ_ONCE(obj->mm.region);
+
+#ifdef CONFIG_LOCKDEP
+ GEM_WARN_ON(dma_resv_test_signaled(obj->base.resv, true));
+#endif
+ return mr && (mr->type == INTEL_MEMORY_LOCAL ||
+ mr->type == INTEL_MEMORY_STOLEN_LOCAL);
+}
+
struct drm_i915_gem_object *
i915_gem_object_create_lmem(struct drm_i915_private *i915,
resource_size_t size,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index ea76fd11ccb0..27a611deba47 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -21,6 +21,8 @@ i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
+bool __i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
+
struct drm_i915_gem_object *
i915_gem_object_create_lmem(struct drm_i915_private *i915,
resource_size_t size,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 2fd155742bd2..6497a2dbdab9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -684,7 +684,7 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
if (mmap_type != I915_MMAP_TYPE_GTT &&
!i915_gem_object_has_struct_page(obj) &&
- !i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_IOMEM))
+ !i915_gem_object_has_iomem(obj))
return -ENODEV;
mmo = mmap_offset_attach(obj, mmap_type, file);
@@ -708,7 +708,12 @@ __assign_mmap_offset_handle(struct drm_file *file,
if (!obj)
return -ENOENT;
+ err = i915_gem_object_lock_interruptible(obj, NULL);
+ if (err)
+ goto out_put;
err = __assign_mmap_offset(obj, mmap_type, offset, file);
+ i915_gem_object_unlock(obj);
+out_put:
i915_gem_object_put(obj);
return err;
}
@@ -932,10 +937,7 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
return PTR_ERR(anon);
}
- vma->vm_flags |= VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP;
-
- if (i915_gem_object_has_iomem(obj))
- vma->vm_flags |= VM_IO;
+ vma->vm_flags |= VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | VM_IO;
/*
* We keep the ref on mmo->obj, not vm_file, but we require
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index cf18c430d51f..07e8ff9a8aae 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -475,6 +475,44 @@ bool i915_gem_object_migratable(struct drm_i915_gem_object *obj)
return obj->mm.n_placements > 1;
}
+/**
+ * i915_gem_object_has_struct_page - Whether the object is page-backed
+ * @obj: The object to query.
+ *
+ * This function should only be called while the object is locked or pinned,
+ * otherwise the page backing may change under the caller.
+ *
+ * Return: True if page-backed, false otherwise.
+ */
+bool i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
+{
+#ifdef CONFIG_LOCKDEP
+ if (IS_DGFX(to_i915(obj->base.dev)) &&
+ i915_gem_object_evictable((void __force *)obj))
+ assert_object_held_shared(obj);
+#endif
+ return obj->mem_flags & I915_BO_FLAG_STRUCT_PAGE;
+}
+
+/**
+ * i915_gem_object_has_iomem - Whether the object is iomem-backed
+ * @obj: The object to query.
+ *
+ * This function should only be called while the object is locked or pinned,
+ * otherwise the iomem backing may change under the caller.
+ *
+ * Return: True if iomem-backed, false otherwise.
+ */
+bool i915_gem_object_has_iomem(const struct drm_i915_gem_object *obj)
+{
+#ifdef CONFIG_LOCKDEP
+ if (IS_DGFX(to_i915(obj->base.dev)) &&
+ i915_gem_object_evictable((void __force *)obj))
+ assert_object_held_shared(obj);
+#endif
+ return obj->mem_flags & I915_BO_FLAG_IOMEM;
+}
+
void i915_gem_init__objects(struct drm_i915_private *i915)
{
INIT_WORK(&i915->mm.free_work, __i915_gem_free_work);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 7bf4dd46d8d2..ea3224a480c4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -148,7 +148,7 @@ i915_gem_object_put(struct drm_i915_gem_object *obj)
/*
* If more than one potential simultaneous locker, assert held.
*/
-static inline void assert_object_held_shared(struct drm_i915_gem_object *obj)
+static inline void assert_object_held_shared(const struct drm_i915_gem_object *obj)
{
/*
* Note mm list lookup is protected by
@@ -266,17 +266,9 @@ i915_gem_object_type_has(const struct drm_i915_gem_object *obj,
return obj->ops->flags & flags;
}
-static inline bool
-i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
-{
- return obj->flags & I915_BO_ALLOC_STRUCT_PAGE;
-}
+bool i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj);
-static inline bool
-i915_gem_object_has_iomem(const struct drm_i915_gem_object *obj)
-{
- return i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_IOMEM);
-}
+bool i915_gem_object_has_iomem(const struct drm_i915_gem_object *obj);
static inline bool
i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3a2d9ecf8e03..28dec0787b3d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -33,10 +33,9 @@ struct i915_lut_handle {
struct drm_i915_gem_object_ops {
unsigned int flags;
-#define I915_GEM_OBJECT_HAS_IOMEM BIT(1)
-#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(2)
-#define I915_GEM_OBJECT_IS_PROXY BIT(3)
-#define I915_GEM_OBJECT_NO_MMAP BIT(4)
+#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
+#define I915_GEM_OBJECT_IS_PROXY BIT(2)
+#define I915_GEM_OBJECT_NO_MMAP BIT(3)
/* Interface between the GEM object and its backing storage.
* get_pages() is called once prior to the use of the associated set
@@ -201,17 +200,18 @@ struct drm_i915_gem_object {
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
#define I915_BO_ALLOC_VOLATILE BIT(1)
-#define I915_BO_ALLOC_STRUCT_PAGE BIT(2)
-#define I915_BO_ALLOC_CPU_CLEAR BIT(3)
-#define I915_BO_ALLOC_USER BIT(4)
+#define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+#define I915_BO_ALLOC_USER BIT(3)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
- I915_BO_ALLOC_STRUCT_PAGE | \
I915_BO_ALLOC_CPU_CLEAR | \
I915_BO_ALLOC_USER)
-#define I915_BO_READONLY BIT(5)
-#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
+#define I915_BO_READONLY BIT(4)
+#define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
+ unsigned int mem_flags:2;
+#define I915_BO_FLAG_STRUCT_PAGE BIT(0)
+#define I915_BO_FLAG_IOMEM BIT(1)
/*
* Is the object to be mapped as read-only to the GPU
* Only honoured if hardware has relevant pte bit
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 086005c1c7ea..f2f850e31b8e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -351,7 +351,7 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
int err;
if (!i915_gem_object_has_struct_page(obj) &&
- !i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_IOMEM))
+ !i915_gem_object_has_iomem(obj))
return ERR_PTR(-ENXIO);
assert_object_held(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index be72ad0634ba..7986612f48fa 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -76,7 +76,7 @@ static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
/* We're no longer struct page backed */
- obj->flags &= ~I915_BO_ALLOC_STRUCT_PAGE;
+ obj->mem_flags &= ~I915_BO_FLAG_STRUCT_PAGE;
__i915_gem_object_set_pages(obj, st, sg->length);
return 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 5d16c4462fda..7aa1c95c7b7d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -444,7 +444,7 @@ shmem_pread(struct drm_i915_gem_object *obj,
static void shmem_release(struct drm_i915_gem_object *obj)
{
- if (obj->flags & I915_BO_ALLOC_STRUCT_PAGE)
+ if (i915_gem_object_has_struct_page(obj))
i915_gem_object_release_memory_region(obj);
fput(obj->base.filp);
@@ -513,9 +513,8 @@ static int shmem_object_init(struct intel_memory_region *mem,
mapping_set_gfp_mask(mapping, mask);
GEM_BUG_ON(!(mapping_gfp_mask(mapping) & __GFP_RECLAIM));
- i915_gem_object_init(obj, &i915_gem_shmem_ops, &lock_class,
- I915_BO_ALLOC_STRUCT_PAGE);
-
+ i915_gem_object_init(obj, &i915_gem_shmem_ops, &lock_class, 0);
+ obj->mem_flags |= I915_BO_FLAG_STRUCT_PAGE;
obj->write_domain = I915_GEM_DOMAIN_CPU;
obj->read_domains = I915_GEM_DOMAIN_CPU;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index c5deb8b7227c..b5dd3b7037f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -732,7 +732,6 @@ static u64 i915_ttm_mmap_offset(struct drm_i915_gem_object *obj)
const struct drm_i915_gem_object_ops i915_gem_ttm_obj_ops = {
.name = "i915_gem_object_ttm",
- .flags = I915_GEM_OBJECT_HAS_IOMEM,
.get_pages = i915_ttm_get_pages,
.put_pages = i915_ttm_put_pages,
@@ -777,6 +776,7 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
i915_gem_object_init_memory_region(obj, mem);
i915_gem_object_make_unshrinkable(obj);
obj->read_domains = I915_GEM_DOMAIN_WC | I915_GEM_DOMAIN_GTT;
+ obj->mem_flags |= I915_BO_FLAG_IOMEM;
i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
INIT_RADIX_TREE(&obj->ttm.get_io_page.radix, GFP_KERNEL | __GFP_NOWARN);
mutex_init(&obj->ttm.get_io_page.lock);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 4b0acc7eaa27..56edfeff8c02 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -510,8 +510,8 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
return -ENOMEM;
drm_gem_private_object_init(dev, &obj->base, args->user_size);
- i915_gem_object_init(obj, &i915_gem_userptr_ops, &lock_class,
- I915_BO_ALLOC_STRUCT_PAGE);
+ i915_gem_object_init(obj, &i915_gem_userptr_ops, &lock_class, 0);
+ obj->mem_flags = I915_BO_FLAG_STRUCT_PAGE;
obj->read_domains = I915_GEM_DOMAIN_CPU;
obj->write_domain = I915_GEM_DOMAIN_CPU;
i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c b/drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c
index 0c8ecfdf5405..f963b8e1e37b 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c
@@ -114,8 +114,8 @@ huge_gem_object(struct drm_i915_private *i915,
return ERR_PTR(-ENOMEM);
drm_gem_private_object_init(&i915->drm, &obj->base, dma_size);
- i915_gem_object_init(obj, &huge_ops, &lock_class,
- I915_BO_ALLOC_STRUCT_PAGE);
+ i915_gem_object_init(obj, &huge_ops, &lock_class, 0);
+ obj->mem_flags |= I915_BO_FLAG_STRUCT_PAGE;
obj->read_domains = I915_GEM_DOMAIN_CPU;
obj->write_domain = I915_GEM_DOMAIN_CPU;
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index dadd485bc52f..ccc67ed1a84b 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -167,9 +167,8 @@ huge_pages_object(struct drm_i915_private *i915,
return ERR_PTR(-ENOMEM);
drm_gem_private_object_init(&i915->drm, &obj->base, size);
- i915_gem_object_init(obj, &huge_page_ops, &lock_class,
- I915_BO_ALLOC_STRUCT_PAGE);
-
+ i915_gem_object_init(obj, &huge_page_ops, &lock_class, 0);
+ obj->mem_flags |= I915_BO_FLAG_STRUCT_PAGE;
i915_gem_object_set_volatile(obj);
obj->write_domain = I915_GEM_DOMAIN_CPU;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 44b5de06ce64..fcea0ddabcc5 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -837,7 +837,7 @@ static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
if (type != I915_MMAP_TYPE_GTT &&
!i915_gem_object_has_struct_page(obj) &&
- !i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_IOMEM))
+ !i915_gem_object_has_iomem(obj))
return false;
return true;
@@ -991,7 +991,7 @@ static const char *repr_mmap_type(enum i915_mmap_type type)
static bool can_access(const struct drm_i915_gem_object *obj)
{
return i915_gem_object_has_struct_page(obj) ||
- i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_IOMEM);
+ i915_gem_object_has_iomem(obj);
}
static int __igt_mmap_access(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
index 3a6ce87f8b52..d43d8dae0f69 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
@@ -25,13 +25,14 @@ static int mock_phys_object(void *arg)
goto out;
}
+ i915_gem_object_lock(obj, NULL);
if (!i915_gem_object_has_struct_page(obj)) {
+ i915_gem_object_unlock(obj);
err = -EINVAL;
pr_err("shmem has no struct page\n");
goto out_obj;
}
- i915_gem_object_lock(obj, NULL);
err = i915_gem_object_attach_phys(obj, PAGE_SIZE);
i915_gem_object_unlock(obj);
if (err) {
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index cb182c6d265a..a2c58b54a592 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1039,7 +1039,7 @@ i915_vma_coredump_create(const struct intel_gt *gt,
if (ret)
break;
}
- } else if (i915_gem_object_is_lmem(vma->obj)) {
+ } else if (__i915_gem_object_is_lmem(vma->obj)) {
struct intel_memory_region *mem = vma->obj->mm.region;
dma_addr_t dma;
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v7 1/3] drm/i915: Update object placement flags to be mutable
@ 2021-06-22 9:34 ` Thomas Hellström
0 siblings, 0 replies; 19+ messages in thread
From: Thomas Hellström @ 2021-06-22 9:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Thomas Hellström, matthew.auld
The object ops i915_GEM_OBJECT_HAS_IOMEM and the object
I915_BO_ALLOC_STRUCT_PAGE flags are considered immutable by
much of our code. Introduce a new mem_flags member to hold these
and make sure checks for these flags being set are either done
under the object lock or with pages properly pinned. The flags
will change during migration under the object lock.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
v2:
- Unconditionally set VM_IO on our VMAs in line with the rest core gem
and TTM. Since the bo might be migrated while the VMA is still alive,
there is no sense, whether or not it maps iomem might change.
v6:
- Introduce a __i915_gem_object_is_lmem() to be used in situations where we
know that a fence that can't currently signal keeps the object from being
migrated or evicted.
- Move a couple of shmem warnings for DGFX to a later patch where we
actually move system memory to TTM.
---
drivers/gpu/drm/i915/gem/i915_gem_internal.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 22 +++++++++++
drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 2 +
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 12 +++---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 38 +++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_object.h | 14 ++-----
.../gpu/drm/i915/gem/i915_gem_object_types.h | 20 +++++-----
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 7 ++--
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 4 +-
.../drm/i915/gem/selftests/huge_gem_object.c | 4 +-
.../gpu/drm/i915/gem/selftests/huge_pages.c | 5 +--
.../drm/i915/gem/selftests/i915_gem_mman.c | 4 +-
.../drm/i915/gem/selftests/i915_gem_phys.c | 3 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
17 files changed, 101 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_internal.c b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
index ce6b664b10aa..13b217f75055 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_internal.c
@@ -177,8 +177,8 @@ i915_gem_object_create_internal(struct drm_i915_private *i915,
return ERR_PTR(-ENOMEM);
drm_gem_private_object_init(&i915->drm, &obj->base, size);
- i915_gem_object_init(obj, &i915_gem_object_internal_ops, &lock_class,
- I915_BO_ALLOC_STRUCT_PAGE);
+ i915_gem_object_init(obj, &i915_gem_object_internal_ops, &lock_class, 0);
+ obj->mem_flags |= I915_BO_FLAG_STRUCT_PAGE;
/*
* Mark the object as volatile, such that the pages are marked as
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index d539dffa1554..41d5182cd367 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -71,6 +71,28 @@ bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
mr->type == INTEL_MEMORY_STOLEN_LOCAL);
}
+/**
+ * __i915_gem_object_is_lmem - Whether the object is resident in
+ * lmem while in the fence signaling critical path.
+ * @obj: The object to check.
+ *
+ * This function is intended to be called from within the fence signaling
+ * path where the fence keeps the object from being migrated. For example
+ * during gpu reset or similar.
+ *
+ * Return: Whether the object is resident in lmem.
+ */
+bool __i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *mr = READ_ONCE(obj->mm.region);
+
+#ifdef CONFIG_LOCKDEP
+ GEM_WARN_ON(dma_resv_test_signaled(obj->base.resv, true));
+#endif
+ return mr && (mr->type == INTEL_MEMORY_LOCAL ||
+ mr->type == INTEL_MEMORY_STOLEN_LOCAL);
+}
+
struct drm_i915_gem_object *
i915_gem_object_create_lmem(struct drm_i915_private *i915,
resource_size_t size,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
index ea76fd11ccb0..27a611deba47 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h
@@ -21,6 +21,8 @@ i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj,
bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
+bool __i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
+
struct drm_i915_gem_object *
i915_gem_object_create_lmem(struct drm_i915_private *i915,
resource_size_t size,
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 2fd155742bd2..6497a2dbdab9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -684,7 +684,7 @@ __assign_mmap_offset(struct drm_i915_gem_object *obj,
if (mmap_type != I915_MMAP_TYPE_GTT &&
!i915_gem_object_has_struct_page(obj) &&
- !i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_IOMEM))
+ !i915_gem_object_has_iomem(obj))
return -ENODEV;
mmo = mmap_offset_attach(obj, mmap_type, file);
@@ -708,7 +708,12 @@ __assign_mmap_offset_handle(struct drm_file *file,
if (!obj)
return -ENOENT;
+ err = i915_gem_object_lock_interruptible(obj, NULL);
+ if (err)
+ goto out_put;
err = __assign_mmap_offset(obj, mmap_type, offset, file);
+ i915_gem_object_unlock(obj);
+out_put:
i915_gem_object_put(obj);
return err;
}
@@ -932,10 +937,7 @@ int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma)
return PTR_ERR(anon);
}
- vma->vm_flags |= VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP;
-
- if (i915_gem_object_has_iomem(obj))
- vma->vm_flags |= VM_IO;
+ vma->vm_flags |= VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | VM_IO;
/*
* We keep the ref on mmo->obj, not vm_file, but we require
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index cf18c430d51f..07e8ff9a8aae 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -475,6 +475,44 @@ bool i915_gem_object_migratable(struct drm_i915_gem_object *obj)
return obj->mm.n_placements > 1;
}
+/**
+ * i915_gem_object_has_struct_page - Whether the object is page-backed
+ * @obj: The object to query.
+ *
+ * This function should only be called while the object is locked or pinned,
+ * otherwise the page backing may change under the caller.
+ *
+ * Return: True if page-backed, false otherwise.
+ */
+bool i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
+{
+#ifdef CONFIG_LOCKDEP
+ if (IS_DGFX(to_i915(obj->base.dev)) &&
+ i915_gem_object_evictable((void __force *)obj))
+ assert_object_held_shared(obj);
+#endif
+ return obj->mem_flags & I915_BO_FLAG_STRUCT_PAGE;
+}
+
+/**
+ * i915_gem_object_has_iomem - Whether the object is iomem-backed
+ * @obj: The object to query.
+ *
+ * This function should only be called while the object is locked or pinned,
+ * otherwise the iomem backing may change under the caller.
+ *
+ * Return: True if iomem-backed, false otherwise.
+ */
+bool i915_gem_object_has_iomem(const struct drm_i915_gem_object *obj)
+{
+#ifdef CONFIG_LOCKDEP
+ if (IS_DGFX(to_i915(obj->base.dev)) &&
+ i915_gem_object_evictable((void __force *)obj))
+ assert_object_held_shared(obj);
+#endif
+ return obj->mem_flags & I915_BO_FLAG_IOMEM;
+}
+
void i915_gem_init__objects(struct drm_i915_private *i915)
{
INIT_WORK(&i915->mm.free_work, __i915_gem_free_work);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 7bf4dd46d8d2..ea3224a480c4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -148,7 +148,7 @@ i915_gem_object_put(struct drm_i915_gem_object *obj)
/*
* If more than one potential simultaneous locker, assert held.
*/
-static inline void assert_object_held_shared(struct drm_i915_gem_object *obj)
+static inline void assert_object_held_shared(const struct drm_i915_gem_object *obj)
{
/*
* Note mm list lookup is protected by
@@ -266,17 +266,9 @@ i915_gem_object_type_has(const struct drm_i915_gem_object *obj,
return obj->ops->flags & flags;
}
-static inline bool
-i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
-{
- return obj->flags & I915_BO_ALLOC_STRUCT_PAGE;
-}
+bool i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj);
-static inline bool
-i915_gem_object_has_iomem(const struct drm_i915_gem_object *obj)
-{
- return i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_IOMEM);
-}
+bool i915_gem_object_has_iomem(const struct drm_i915_gem_object *obj);
static inline bool
i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 3a2d9ecf8e03..28dec0787b3d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -33,10 +33,9 @@ struct i915_lut_handle {
struct drm_i915_gem_object_ops {
unsigned int flags;
-#define I915_GEM_OBJECT_HAS_IOMEM BIT(1)
-#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(2)
-#define I915_GEM_OBJECT_IS_PROXY BIT(3)
-#define I915_GEM_OBJECT_NO_MMAP BIT(4)
+#define I915_GEM_OBJECT_IS_SHRINKABLE BIT(1)
+#define I915_GEM_OBJECT_IS_PROXY BIT(2)
+#define I915_GEM_OBJECT_NO_MMAP BIT(3)
/* Interface between the GEM object and its backing storage.
* get_pages() is called once prior to the use of the associated set
@@ -201,17 +200,18 @@ struct drm_i915_gem_object {
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
#define I915_BO_ALLOC_VOLATILE BIT(1)
-#define I915_BO_ALLOC_STRUCT_PAGE BIT(2)
-#define I915_BO_ALLOC_CPU_CLEAR BIT(3)
-#define I915_BO_ALLOC_USER BIT(4)
+#define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+#define I915_BO_ALLOC_USER BIT(3)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
- I915_BO_ALLOC_STRUCT_PAGE | \
I915_BO_ALLOC_CPU_CLEAR | \
I915_BO_ALLOC_USER)
-#define I915_BO_READONLY BIT(5)
-#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
+#define I915_BO_READONLY BIT(4)
+#define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
+ unsigned int mem_flags:2;
+#define I915_BO_FLAG_STRUCT_PAGE BIT(0)
+#define I915_BO_FLAG_IOMEM BIT(1)
/*
* Is the object to be mapped as read-only to the GPU
* Only honoured if hardware has relevant pte bit
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 086005c1c7ea..f2f850e31b8e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -351,7 +351,7 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
int err;
if (!i915_gem_object_has_struct_page(obj) &&
- !i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_IOMEM))
+ !i915_gem_object_has_iomem(obj))
return ERR_PTR(-ENXIO);
assert_object_held(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
index be72ad0634ba..7986612f48fa 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_phys.c
@@ -76,7 +76,7 @@ static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
/* We're no longer struct page backed */
- obj->flags &= ~I915_BO_ALLOC_STRUCT_PAGE;
+ obj->mem_flags &= ~I915_BO_FLAG_STRUCT_PAGE;
__i915_gem_object_set_pages(obj, st, sg->length);
return 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 5d16c4462fda..7aa1c95c7b7d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -444,7 +444,7 @@ shmem_pread(struct drm_i915_gem_object *obj,
static void shmem_release(struct drm_i915_gem_object *obj)
{
- if (obj->flags & I915_BO_ALLOC_STRUCT_PAGE)
+ if (i915_gem_object_has_struct_page(obj))
i915_gem_object_release_memory_region(obj);
fput(obj->base.filp);
@@ -513,9 +513,8 @@ static int shmem_object_init(struct intel_memory_region *mem,
mapping_set_gfp_mask(mapping, mask);
GEM_BUG_ON(!(mapping_gfp_mask(mapping) & __GFP_RECLAIM));
- i915_gem_object_init(obj, &i915_gem_shmem_ops, &lock_class,
- I915_BO_ALLOC_STRUCT_PAGE);
-
+ i915_gem_object_init(obj, &i915_gem_shmem_ops, &lock_class, 0);
+ obj->mem_flags |= I915_BO_FLAG_STRUCT_PAGE;
obj->write_domain = I915_GEM_DOMAIN_CPU;
obj->read_domains = I915_GEM_DOMAIN_CPU;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index c5deb8b7227c..b5dd3b7037f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -732,7 +732,6 @@ static u64 i915_ttm_mmap_offset(struct drm_i915_gem_object *obj)
const struct drm_i915_gem_object_ops i915_gem_ttm_obj_ops = {
.name = "i915_gem_object_ttm",
- .flags = I915_GEM_OBJECT_HAS_IOMEM,
.get_pages = i915_ttm_get_pages,
.put_pages = i915_ttm_put_pages,
@@ -777,6 +776,7 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
i915_gem_object_init_memory_region(obj, mem);
i915_gem_object_make_unshrinkable(obj);
obj->read_domains = I915_GEM_DOMAIN_WC | I915_GEM_DOMAIN_GTT;
+ obj->mem_flags |= I915_BO_FLAG_IOMEM;
i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
INIT_RADIX_TREE(&obj->ttm.get_io_page.radix, GFP_KERNEL | __GFP_NOWARN);
mutex_init(&obj->ttm.get_io_page.lock);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
index 4b0acc7eaa27..56edfeff8c02 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
@@ -510,8 +510,8 @@ i915_gem_userptr_ioctl(struct drm_device *dev,
return -ENOMEM;
drm_gem_private_object_init(dev, &obj->base, args->user_size);
- i915_gem_object_init(obj, &i915_gem_userptr_ops, &lock_class,
- I915_BO_ALLOC_STRUCT_PAGE);
+ i915_gem_object_init(obj, &i915_gem_userptr_ops, &lock_class, 0);
+ obj->mem_flags = I915_BO_FLAG_STRUCT_PAGE;
obj->read_domains = I915_GEM_DOMAIN_CPU;
obj->write_domain = I915_GEM_DOMAIN_CPU;
i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c b/drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c
index 0c8ecfdf5405..f963b8e1e37b 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_gem_object.c
@@ -114,8 +114,8 @@ huge_gem_object(struct drm_i915_private *i915,
return ERR_PTR(-ENOMEM);
drm_gem_private_object_init(&i915->drm, &obj->base, dma_size);
- i915_gem_object_init(obj, &huge_ops, &lock_class,
- I915_BO_ALLOC_STRUCT_PAGE);
+ i915_gem_object_init(obj, &huge_ops, &lock_class, 0);
+ obj->mem_flags |= I915_BO_FLAG_STRUCT_PAGE;
obj->read_domains = I915_GEM_DOMAIN_CPU;
obj->write_domain = I915_GEM_DOMAIN_CPU;
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index dadd485bc52f..ccc67ed1a84b 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -167,9 +167,8 @@ huge_pages_object(struct drm_i915_private *i915,
return ERR_PTR(-ENOMEM);
drm_gem_private_object_init(&i915->drm, &obj->base, size);
- i915_gem_object_init(obj, &huge_page_ops, &lock_class,
- I915_BO_ALLOC_STRUCT_PAGE);
-
+ i915_gem_object_init(obj, &huge_page_ops, &lock_class, 0);
+ obj->mem_flags |= I915_BO_FLAG_STRUCT_PAGE;
i915_gem_object_set_volatile(obj);
obj->write_domain = I915_GEM_DOMAIN_CPU;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 44b5de06ce64..fcea0ddabcc5 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -837,7 +837,7 @@ static bool can_mmap(struct drm_i915_gem_object *obj, enum i915_mmap_type type)
if (type != I915_MMAP_TYPE_GTT &&
!i915_gem_object_has_struct_page(obj) &&
- !i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_IOMEM))
+ !i915_gem_object_has_iomem(obj))
return false;
return true;
@@ -991,7 +991,7 @@ static const char *repr_mmap_type(enum i915_mmap_type type)
static bool can_access(const struct drm_i915_gem_object *obj)
{
return i915_gem_object_has_struct_page(obj) ||
- i915_gem_object_type_has(obj, I915_GEM_OBJECT_HAS_IOMEM);
+ i915_gem_object_has_iomem(obj);
}
static int __igt_mmap_access(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
index 3a6ce87f8b52..d43d8dae0f69 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c
@@ -25,13 +25,14 @@ static int mock_phys_object(void *arg)
goto out;
}
+ i915_gem_object_lock(obj, NULL);
if (!i915_gem_object_has_struct_page(obj)) {
+ i915_gem_object_unlock(obj);
err = -EINVAL;
pr_err("shmem has no struct page\n");
goto out_obj;
}
- i915_gem_object_lock(obj, NULL);
err = i915_gem_object_attach_phys(obj, PAGE_SIZE);
i915_gem_object_unlock(obj);
if (err) {
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index cb182c6d265a..a2c58b54a592 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1039,7 +1039,7 @@ i915_vma_coredump_create(const struct intel_gt *gt,
if (ret)
break;
}
- } else if (i915_gem_object_is_lmem(vma->obj)) {
+ } else if (__i915_gem_object_is_lmem(vma->obj)) {
struct intel_memory_region *mem = vma->obj->mm.region;
dma_addr_t dma;
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 2/3] drm/i915/ttm: Adjust gem flags and caching settings after a move
2021-06-22 9:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-22 9:34 ` Thomas Hellström
-1 siblings, 0 replies; 19+ messages in thread
From: Thomas Hellström @ 2021-06-22 9:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Thomas Hellström, matthew.auld
After a TTM move or object init we need to update the i915 gem flags and
caching settings to reflect the new placement. Currently caching settings
are not changed during the lifetime of an object, although that might
change moving forward if we run into performance issues or issues with
WC system page allocations.
Also introduce gpu_binds_iomem() and cpu_maps_iomem() to clean up the
various ways we previously used to detect this.
Finally, initialize the TTM object reserved to be able to update
flags and caching before anyone else gets hold of the object.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
v6:
- Rebase on accelerated ttm moves.
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 143 ++++++++++++++++++------
1 file changed, 107 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index b5dd3b7037f4..966b292d07da 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -91,6 +91,26 @@ static int i915_ttm_err_to_gem(int err)
return err;
}
+static bool gpu_binds_iomem(struct ttm_resource *mem)
+{
+ return mem->mem_type != TTM_PL_SYSTEM;
+}
+
+static bool cpu_maps_iomem(struct ttm_resource *mem)
+{
+ /* Once / if we support GGTT, this is also false for cached ttm_tts */
+ return mem->mem_type != TTM_PL_SYSTEM;
+}
+
+static enum i915_cache_level
+i915_ttm_cache_level(struct drm_i915_private *i915, struct ttm_resource *res,
+ struct ttm_tt *ttm)
+{
+ return ((HAS_LLC(i915) || HAS_SNOOP(i915)) && !gpu_binds_iomem(res) &&
+ ttm->caching == ttm_cached) ? I915_CACHE_LLC :
+ I915_CACHE_NONE;
+}
+
static void i915_ttm_adjust_lru(struct drm_i915_gem_object *obj);
static enum ttm_caching
@@ -248,6 +268,35 @@ static void i915_ttm_free_cached_io_st(struct drm_i915_gem_object *obj)
obj->ttm.cached_io_st = NULL;
}
+static void
+i915_ttm_adjust_domains_after_move(struct drm_i915_gem_object *obj)
+{
+ struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
+
+ if (cpu_maps_iomem(bo->resource) || bo->ttm->caching != ttm_cached) {
+ obj->write_domain = I915_GEM_DOMAIN_WC;
+ obj->read_domains = I915_GEM_DOMAIN_WC;
+ } else {
+ obj->write_domain = I915_GEM_DOMAIN_CPU;
+ obj->read_domains = I915_GEM_DOMAIN_CPU;
+ }
+}
+
+static void i915_ttm_adjust_gem_after_move(struct drm_i915_gem_object *obj)
+{
+ struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
+ unsigned int cache_level;
+
+ obj->mem_flags &= ~(I915_BO_FLAG_STRUCT_PAGE | I915_BO_FLAG_IOMEM);
+
+ obj->mem_flags |= cpu_maps_iomem(bo->resource) ? I915_BO_FLAG_IOMEM :
+ I915_BO_FLAG_STRUCT_PAGE;
+
+ cache_level = i915_ttm_cache_level(to_i915(bo->base.dev), bo->resource,
+ bo->ttm);
+ i915_gem_object_set_cache_coherency(obj, cache_level);
+}
+
static void i915_ttm_purge(struct drm_i915_gem_object *obj)
{
struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
@@ -263,8 +312,10 @@ static void i915_ttm_purge(struct drm_i915_gem_object *obj)
/* TTM's purge interface. Note that we might be reentering. */
ret = ttm_bo_validate(bo, &place, &ctx);
-
if (!ret) {
+ obj->write_domain = 0;
+ obj->read_domains = 0;
+ i915_ttm_adjust_gem_after_move(obj);
i915_ttm_free_cached_io_st(obj);
obj->mm.madv = __I915_MADV_PURGED;
}
@@ -347,12 +398,15 @@ i915_ttm_resource_get_st(struct drm_i915_gem_object *obj,
struct ttm_resource *res)
{
struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
- struct ttm_resource_manager *man =
- ttm_manager_type(bo->bdev, res->mem_type);
- if (man->use_tt)
+ if (!gpu_binds_iomem(res))
return i915_ttm_tt_get_st(bo->ttm);
+ /*
+ * If CPU mapping differs, we need to add the ttm_tt pages to
+ * the resulting st. Might make sense for GGTT.
+ */
+ GEM_WARN_ON(!cpu_maps_iomem(res));
return intel_region_ttm_resource_to_st(obj->mm.region, res);
}
@@ -367,23 +421,25 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
struct sg_table *src_st;
struct i915_request *rq;
+ struct ttm_tt *ttm = bo->ttm;
+ enum i915_cache_level src_level, dst_level;
int ret;
if (!i915->gt.migrate.context)
return -EINVAL;
- if (!bo->ttm || !ttm_tt_is_populated(bo->ttm)) {
+ dst_level = i915_ttm_cache_level(i915, dst_mem, ttm);
+ if (!ttm || !ttm_tt_is_populated(ttm)) {
if (bo->type == ttm_bo_type_kernel)
return -EINVAL;
- if (bo->ttm &&
- !(bo->ttm->page_flags & TTM_PAGE_FLAG_ZERO_ALLOC))
+ if (ttm && !(ttm->page_flags & TTM_PAGE_FLAG_ZERO_ALLOC))
return 0;
intel_engine_pm_get(i915->gt.migrate.context->engine);
ret = intel_context_migrate_clear(i915->gt.migrate.context, NULL,
- dst_st->sgl, I915_CACHE_NONE,
- dst_mem->mem_type >= I915_PL_LMEM0,
+ dst_st->sgl, dst_level,
+ gpu_binds_iomem(dst_mem),
0, &rq);
if (!ret && rq) {
@@ -392,15 +448,16 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
}
intel_engine_pm_put(i915->gt.migrate.context->engine);
} else {
- src_st = src_man->use_tt ? i915_ttm_tt_get_st(bo->ttm) :
- obj->ttm.cached_io_st;
+ src_st = src_man->use_tt ? i915_ttm_tt_get_st(ttm) :
+ obj->ttm.cached_io_st;
+ src_level = i915_ttm_cache_level(i915, bo->resource, ttm);
intel_engine_pm_get(i915->gt.migrate.context->engine);
ret = intel_context_migrate_copy(i915->gt.migrate.context,
- NULL, src_st->sgl, I915_CACHE_NONE,
- bo->resource->mem_type >= I915_PL_LMEM0,
- dst_st->sgl, I915_CACHE_NONE,
- dst_mem->mem_type >= I915_PL_LMEM0,
+ NULL, src_st->sgl, src_level,
+ gpu_binds_iomem(bo->resource),
+ dst_st->sgl, dst_level,
+ gpu_binds_iomem(dst_mem),
&rq);
if (!ret && rq) {
i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
@@ -420,8 +477,6 @@ static int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
struct ttm_resource_manager *dst_man =
ttm_manager_type(bo->bdev, dst_mem->mem_type);
- struct ttm_resource_manager *src_man =
- ttm_manager_type(bo->bdev, bo->resource->mem_type);
struct intel_memory_region *dst_reg, *src_reg;
union {
struct ttm_kmap_iter_tt tt;
@@ -465,12 +520,12 @@ static int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
ret = i915_ttm_accel_move(bo, dst_mem, dst_st);
if (ret) {
/* If we start mapping GGTT, we can no longer use man::use_tt here. */
- dst_iter = dst_man->use_tt ?
+ dst_iter = !cpu_maps_iomem(dst_mem) ?
ttm_kmap_iter_tt_init(&_dst_iter.tt, bo->ttm) :
ttm_kmap_iter_iomap_init(&_dst_iter.io, &dst_reg->iomap,
dst_st, dst_reg->region.start);
- src_iter = src_man->use_tt ?
+ src_iter = !cpu_maps_iomem(bo->resource) ?
ttm_kmap_iter_tt_init(&_src_iter.tt, bo->ttm) :
ttm_kmap_iter_iomap_init(&_src_iter.io, &src_reg->iomap,
obj->ttm.cached_io_st,
@@ -478,21 +533,24 @@ static int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
ttm_move_memcpy(bo, dst_mem->num_pages, dst_iter, src_iter);
}
+ /* Below dst_mem becomes bo->resource. */
ttm_bo_move_sync_cleanup(bo, dst_mem);
+ i915_ttm_adjust_domains_after_move(obj);
i915_ttm_free_cached_io_st(obj);
- if (!dst_man->use_tt) {
+ if (gpu_binds_iomem(dst_mem) || cpu_maps_iomem(dst_mem)) {
obj->ttm.cached_io_st = dst_st;
obj->ttm.get_io_page.sg_pos = dst_st->sgl;
obj->ttm.get_io_page.sg_idx = 0;
}
+ i915_ttm_adjust_gem_after_move(obj);
return 0;
}
static int i915_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *mem)
{
- if (mem->mem_type < I915_PL_LMEM0)
+ if (!cpu_maps_iomem(mem))
return 0;
mem->bus.caching = ttm_write_combined;
@@ -590,6 +648,16 @@ static int i915_ttm_get_pages(struct drm_i915_gem_object *obj)
return i915_ttm_err_to_gem(ret);
}
+ i915_ttm_adjust_lru(obj);
+ if (bo->ttm && !ttm_tt_is_populated(bo->ttm)) {
+ ret = ttm_tt_populate(bo->bdev, bo->ttm, &ctx);
+ if (ret)
+ return ret;
+
+ i915_ttm_adjust_domains_after_move(obj);
+ i915_ttm_adjust_gem_after_move(obj);
+ }
+
/* Object either has a page vector or is an iomem object */
st = bo->ttm ? i915_ttm_tt_get_st(bo->ttm) : obj->ttm.cached_io_st;
if (IS_ERR(st))
@@ -597,8 +665,6 @@ static int i915_ttm_get_pages(struct drm_i915_gem_object *obj)
__i915_gem_object_set_pages(obj, st, i915_sg_dma_sizes(st->sgl));
- i915_ttm_adjust_lru(obj);
-
return ret;
}
@@ -768,6 +834,10 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
{
static struct lock_class_key lock_class;
struct drm_i915_private *i915 = mem->i915;
+ struct ttm_operation_ctx ctx = {
+ .interruptible = true,
+ .no_wait_gpu = false,
+ };
enum ttm_bo_type bo_type;
int ret;
@@ -775,14 +845,13 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
i915_gem_object_init(obj, &i915_gem_ttm_obj_ops, &lock_class, flags);
i915_gem_object_init_memory_region(obj, mem);
i915_gem_object_make_unshrinkable(obj);
- obj->read_domains = I915_GEM_DOMAIN_WC | I915_GEM_DOMAIN_GTT;
- obj->mem_flags |= I915_BO_FLAG_IOMEM;
- i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
INIT_RADIX_TREE(&obj->ttm.get_io_page.radix, GFP_KERNEL | __GFP_NOWARN);
mutex_init(&obj->ttm.get_io_page.lock);
bo_type = (obj->flags & I915_BO_ALLOC_USER) ? ttm_bo_type_device :
ttm_bo_type_kernel;
+ obj->base.vma_node.driver_private = i915_gem_to_ttm(obj);
+
/*
* If this function fails, it will call the destructor, but
* our caller still owns the object. So no freeing in the
@@ -790,14 +859,16 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
* Similarly, in delayed_destroy, we can't call ttm_bo_put()
* until successful initialization.
*/
- obj->base.vma_node.driver_private = i915_gem_to_ttm(obj);
- ret = ttm_bo_init(&i915->bdev, i915_gem_to_ttm(obj), size,
- bo_type, &i915_sys_placement,
- mem->min_page_size >> PAGE_SHIFT,
- true, NULL, NULL, i915_ttm_bo_destroy);
- if (!ret)
- obj->ttm.created = true;
-
- /* i915 wants -ENXIO when out of memory region space. */
- return i915_ttm_err_to_gem(ret);
+ ret = ttm_bo_init_reserved(&i915->bdev, i915_gem_to_ttm(obj), size,
+ bo_type, &i915_sys_placement, 1,
+ &ctx, NULL, NULL, i915_ttm_bo_destroy);
+ if (ret)
+ return i915_ttm_err_to_gem(ret);
+
+ obj->ttm.created = true;
+ i915_ttm_adjust_domains_after_move(obj);
+ i915_ttm_adjust_gem_after_move(obj);
+ i915_gem_object_unlock(obj);
+
+ return 0;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v7 2/3] drm/i915/ttm: Adjust gem flags and caching settings after a move
@ 2021-06-22 9:34 ` Thomas Hellström
0 siblings, 0 replies; 19+ messages in thread
From: Thomas Hellström @ 2021-06-22 9:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Thomas Hellström, matthew.auld
After a TTM move or object init we need to update the i915 gem flags and
caching settings to reflect the new placement. Currently caching settings
are not changed during the lifetime of an object, although that might
change moving forward if we run into performance issues or issues with
WC system page allocations.
Also introduce gpu_binds_iomem() and cpu_maps_iomem() to clean up the
various ways we previously used to detect this.
Finally, initialize the TTM object reserved to be able to update
flags and caching before anyone else gets hold of the object.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
v6:
- Rebase on accelerated ttm moves.
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 143 ++++++++++++++++++------
1 file changed, 107 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index b5dd3b7037f4..966b292d07da 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -91,6 +91,26 @@ static int i915_ttm_err_to_gem(int err)
return err;
}
+static bool gpu_binds_iomem(struct ttm_resource *mem)
+{
+ return mem->mem_type != TTM_PL_SYSTEM;
+}
+
+static bool cpu_maps_iomem(struct ttm_resource *mem)
+{
+ /* Once / if we support GGTT, this is also false for cached ttm_tts */
+ return mem->mem_type != TTM_PL_SYSTEM;
+}
+
+static enum i915_cache_level
+i915_ttm_cache_level(struct drm_i915_private *i915, struct ttm_resource *res,
+ struct ttm_tt *ttm)
+{
+ return ((HAS_LLC(i915) || HAS_SNOOP(i915)) && !gpu_binds_iomem(res) &&
+ ttm->caching == ttm_cached) ? I915_CACHE_LLC :
+ I915_CACHE_NONE;
+}
+
static void i915_ttm_adjust_lru(struct drm_i915_gem_object *obj);
static enum ttm_caching
@@ -248,6 +268,35 @@ static void i915_ttm_free_cached_io_st(struct drm_i915_gem_object *obj)
obj->ttm.cached_io_st = NULL;
}
+static void
+i915_ttm_adjust_domains_after_move(struct drm_i915_gem_object *obj)
+{
+ struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
+
+ if (cpu_maps_iomem(bo->resource) || bo->ttm->caching != ttm_cached) {
+ obj->write_domain = I915_GEM_DOMAIN_WC;
+ obj->read_domains = I915_GEM_DOMAIN_WC;
+ } else {
+ obj->write_domain = I915_GEM_DOMAIN_CPU;
+ obj->read_domains = I915_GEM_DOMAIN_CPU;
+ }
+}
+
+static void i915_ttm_adjust_gem_after_move(struct drm_i915_gem_object *obj)
+{
+ struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
+ unsigned int cache_level;
+
+ obj->mem_flags &= ~(I915_BO_FLAG_STRUCT_PAGE | I915_BO_FLAG_IOMEM);
+
+ obj->mem_flags |= cpu_maps_iomem(bo->resource) ? I915_BO_FLAG_IOMEM :
+ I915_BO_FLAG_STRUCT_PAGE;
+
+ cache_level = i915_ttm_cache_level(to_i915(bo->base.dev), bo->resource,
+ bo->ttm);
+ i915_gem_object_set_cache_coherency(obj, cache_level);
+}
+
static void i915_ttm_purge(struct drm_i915_gem_object *obj)
{
struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
@@ -263,8 +312,10 @@ static void i915_ttm_purge(struct drm_i915_gem_object *obj)
/* TTM's purge interface. Note that we might be reentering. */
ret = ttm_bo_validate(bo, &place, &ctx);
-
if (!ret) {
+ obj->write_domain = 0;
+ obj->read_domains = 0;
+ i915_ttm_adjust_gem_after_move(obj);
i915_ttm_free_cached_io_st(obj);
obj->mm.madv = __I915_MADV_PURGED;
}
@@ -347,12 +398,15 @@ i915_ttm_resource_get_st(struct drm_i915_gem_object *obj,
struct ttm_resource *res)
{
struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
- struct ttm_resource_manager *man =
- ttm_manager_type(bo->bdev, res->mem_type);
- if (man->use_tt)
+ if (!gpu_binds_iomem(res))
return i915_ttm_tt_get_st(bo->ttm);
+ /*
+ * If CPU mapping differs, we need to add the ttm_tt pages to
+ * the resulting st. Might make sense for GGTT.
+ */
+ GEM_WARN_ON(!cpu_maps_iomem(res));
return intel_region_ttm_resource_to_st(obj->mm.region, res);
}
@@ -367,23 +421,25 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
struct sg_table *src_st;
struct i915_request *rq;
+ struct ttm_tt *ttm = bo->ttm;
+ enum i915_cache_level src_level, dst_level;
int ret;
if (!i915->gt.migrate.context)
return -EINVAL;
- if (!bo->ttm || !ttm_tt_is_populated(bo->ttm)) {
+ dst_level = i915_ttm_cache_level(i915, dst_mem, ttm);
+ if (!ttm || !ttm_tt_is_populated(ttm)) {
if (bo->type == ttm_bo_type_kernel)
return -EINVAL;
- if (bo->ttm &&
- !(bo->ttm->page_flags & TTM_PAGE_FLAG_ZERO_ALLOC))
+ if (ttm && !(ttm->page_flags & TTM_PAGE_FLAG_ZERO_ALLOC))
return 0;
intel_engine_pm_get(i915->gt.migrate.context->engine);
ret = intel_context_migrate_clear(i915->gt.migrate.context, NULL,
- dst_st->sgl, I915_CACHE_NONE,
- dst_mem->mem_type >= I915_PL_LMEM0,
+ dst_st->sgl, dst_level,
+ gpu_binds_iomem(dst_mem),
0, &rq);
if (!ret && rq) {
@@ -392,15 +448,16 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
}
intel_engine_pm_put(i915->gt.migrate.context->engine);
} else {
- src_st = src_man->use_tt ? i915_ttm_tt_get_st(bo->ttm) :
- obj->ttm.cached_io_st;
+ src_st = src_man->use_tt ? i915_ttm_tt_get_st(ttm) :
+ obj->ttm.cached_io_st;
+ src_level = i915_ttm_cache_level(i915, bo->resource, ttm);
intel_engine_pm_get(i915->gt.migrate.context->engine);
ret = intel_context_migrate_copy(i915->gt.migrate.context,
- NULL, src_st->sgl, I915_CACHE_NONE,
- bo->resource->mem_type >= I915_PL_LMEM0,
- dst_st->sgl, I915_CACHE_NONE,
- dst_mem->mem_type >= I915_PL_LMEM0,
+ NULL, src_st->sgl, src_level,
+ gpu_binds_iomem(bo->resource),
+ dst_st->sgl, dst_level,
+ gpu_binds_iomem(dst_mem),
&rq);
if (!ret && rq) {
i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
@@ -420,8 +477,6 @@ static int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
struct ttm_resource_manager *dst_man =
ttm_manager_type(bo->bdev, dst_mem->mem_type);
- struct ttm_resource_manager *src_man =
- ttm_manager_type(bo->bdev, bo->resource->mem_type);
struct intel_memory_region *dst_reg, *src_reg;
union {
struct ttm_kmap_iter_tt tt;
@@ -465,12 +520,12 @@ static int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
ret = i915_ttm_accel_move(bo, dst_mem, dst_st);
if (ret) {
/* If we start mapping GGTT, we can no longer use man::use_tt here. */
- dst_iter = dst_man->use_tt ?
+ dst_iter = !cpu_maps_iomem(dst_mem) ?
ttm_kmap_iter_tt_init(&_dst_iter.tt, bo->ttm) :
ttm_kmap_iter_iomap_init(&_dst_iter.io, &dst_reg->iomap,
dst_st, dst_reg->region.start);
- src_iter = src_man->use_tt ?
+ src_iter = !cpu_maps_iomem(bo->resource) ?
ttm_kmap_iter_tt_init(&_src_iter.tt, bo->ttm) :
ttm_kmap_iter_iomap_init(&_src_iter.io, &src_reg->iomap,
obj->ttm.cached_io_st,
@@ -478,21 +533,24 @@ static int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
ttm_move_memcpy(bo, dst_mem->num_pages, dst_iter, src_iter);
}
+ /* Below dst_mem becomes bo->resource. */
ttm_bo_move_sync_cleanup(bo, dst_mem);
+ i915_ttm_adjust_domains_after_move(obj);
i915_ttm_free_cached_io_st(obj);
- if (!dst_man->use_tt) {
+ if (gpu_binds_iomem(dst_mem) || cpu_maps_iomem(dst_mem)) {
obj->ttm.cached_io_st = dst_st;
obj->ttm.get_io_page.sg_pos = dst_st->sgl;
obj->ttm.get_io_page.sg_idx = 0;
}
+ i915_ttm_adjust_gem_after_move(obj);
return 0;
}
static int i915_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *mem)
{
- if (mem->mem_type < I915_PL_LMEM0)
+ if (!cpu_maps_iomem(mem))
return 0;
mem->bus.caching = ttm_write_combined;
@@ -590,6 +648,16 @@ static int i915_ttm_get_pages(struct drm_i915_gem_object *obj)
return i915_ttm_err_to_gem(ret);
}
+ i915_ttm_adjust_lru(obj);
+ if (bo->ttm && !ttm_tt_is_populated(bo->ttm)) {
+ ret = ttm_tt_populate(bo->bdev, bo->ttm, &ctx);
+ if (ret)
+ return ret;
+
+ i915_ttm_adjust_domains_after_move(obj);
+ i915_ttm_adjust_gem_after_move(obj);
+ }
+
/* Object either has a page vector or is an iomem object */
st = bo->ttm ? i915_ttm_tt_get_st(bo->ttm) : obj->ttm.cached_io_st;
if (IS_ERR(st))
@@ -597,8 +665,6 @@ static int i915_ttm_get_pages(struct drm_i915_gem_object *obj)
__i915_gem_object_set_pages(obj, st, i915_sg_dma_sizes(st->sgl));
- i915_ttm_adjust_lru(obj);
-
return ret;
}
@@ -768,6 +834,10 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
{
static struct lock_class_key lock_class;
struct drm_i915_private *i915 = mem->i915;
+ struct ttm_operation_ctx ctx = {
+ .interruptible = true,
+ .no_wait_gpu = false,
+ };
enum ttm_bo_type bo_type;
int ret;
@@ -775,14 +845,13 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
i915_gem_object_init(obj, &i915_gem_ttm_obj_ops, &lock_class, flags);
i915_gem_object_init_memory_region(obj, mem);
i915_gem_object_make_unshrinkable(obj);
- obj->read_domains = I915_GEM_DOMAIN_WC | I915_GEM_DOMAIN_GTT;
- obj->mem_flags |= I915_BO_FLAG_IOMEM;
- i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
INIT_RADIX_TREE(&obj->ttm.get_io_page.radix, GFP_KERNEL | __GFP_NOWARN);
mutex_init(&obj->ttm.get_io_page.lock);
bo_type = (obj->flags & I915_BO_ALLOC_USER) ? ttm_bo_type_device :
ttm_bo_type_kernel;
+ obj->base.vma_node.driver_private = i915_gem_to_ttm(obj);
+
/*
* If this function fails, it will call the destructor, but
* our caller still owns the object. So no freeing in the
@@ -790,14 +859,16 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
* Similarly, in delayed_destroy, we can't call ttm_bo_put()
* until successful initialization.
*/
- obj->base.vma_node.driver_private = i915_gem_to_ttm(obj);
- ret = ttm_bo_init(&i915->bdev, i915_gem_to_ttm(obj), size,
- bo_type, &i915_sys_placement,
- mem->min_page_size >> PAGE_SHIFT,
- true, NULL, NULL, i915_ttm_bo_destroy);
- if (!ret)
- obj->ttm.created = true;
-
- /* i915 wants -ENXIO when out of memory region space. */
- return i915_ttm_err_to_gem(ret);
+ ret = ttm_bo_init_reserved(&i915->bdev, i915_gem_to_ttm(obj), size,
+ bo_type, &i915_sys_placement, 1,
+ &ctx, NULL, NULL, i915_ttm_bo_destroy);
+ if (ret)
+ return i915_ttm_err_to_gem(ret);
+
+ obj->ttm.created = true;
+ i915_ttm_adjust_domains_after_move(obj);
+ i915_ttm_adjust_gem_after_move(obj);
+ i915_gem_object_unlock(obj);
+
+ return 0;
}
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v7 3/3] drm/i915/ttm: Use TTM for system memory
2021-06-22 9:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-22 9:34 ` Thomas Hellström
-1 siblings, 0 replies; 19+ messages in thread
From: Thomas Hellström @ 2021-06-22 9:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Thomas Hellström, matthew.auld
For discrete, use TTM for both cached and WC system memory. That means
we currently rely on the TTM memory accounting / shrinker. For cached
system memory we should consider remaining shmem-backed, which can be
implemented from our ttm_tt_populate callback. We can then also reuse our
own very elaborate shrinker for that memory.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
v2:
- Fix IS_ERR_OR_NULL() check to IS_ERR() (Reported by Matthew Auld)
v3:
- Commit message typo fix
v6:
- Fix TODO:s for supporting system memory with TTM.
- Update the object GEM region after a TTM move if compatible.
- Add a couple of warnings for shmem on DGFX.
---
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 3 ++
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 51 +++++++++++++++++-----
drivers/gpu/drm/i915/i915_drv.h | 3 --
drivers/gpu/drm/i915/intel_memory_region.c | 7 ++-
drivers/gpu/drm/i915/intel_memory_region.h | 8 ++++
5 files changed, 58 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 7aa1c95c7b7d..3648ae1d6628 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -284,6 +284,7 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
bool needs_clflush)
{
GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
+ GEM_WARN_ON(IS_DGFX(to_i915(obj->base.dev)));
if (obj->mm.madv == I915_MADV_DONTNEED)
obj->mm.dirty = false;
@@ -302,6 +303,7 @@ void i915_gem_object_put_pages_shmem(struct drm_i915_gem_object *obj, struct sg_
struct pagevec pvec;
struct page *page;
+ GEM_WARN_ON(IS_DGFX(to_i915(obj->base.dev)));
__i915_gem_object_release_shmem(obj, pages, true);
i915_gem_gtt_finish_pages(obj, pages);
@@ -560,6 +562,7 @@ i915_gem_object_create_shmem_from_data(struct drm_i915_private *dev_priv,
resource_size_t offset;
int err;
+ GEM_WARN_ON(IS_DGFX(dev_priv));
obj = i915_gem_object_create_shmem(dev_priv, round_up(size, PAGE_SIZE));
if (IS_ERR(obj))
return obj;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 966b292d07da..07097f150065 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -286,6 +286,25 @@ static void i915_ttm_adjust_gem_after_move(struct drm_i915_gem_object *obj)
{
struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
unsigned int cache_level;
+ unsigned int i;
+
+ /*
+ * If object was moved to an allowable region, update the object
+ * region to consider it migrated. Note that if it's currently not
+ * in an allowable region, it's evicted and we don't update the
+ * object region.
+ */
+ if (intel_region_to_ttm_type(obj->mm.region) != bo->resource->mem_type) {
+ for (i = 0; i < obj->mm.n_placements; ++i) {
+ struct intel_memory_region *mr = obj->mm.placements[i];
+
+ if (intel_region_to_ttm_type(mr) == bo->resource->mem_type &&
+ mr != obj->mm.region) {
+ intel_memory_region_put(obj->mm.region);
+ obj->mm.region = intel_memory_region_get(mr);
+ }
+ }
+ }
obj->mem_flags &= ~(I915_BO_FLAG_STRUCT_PAGE | I915_BO_FLAG_IOMEM);
@@ -615,13 +634,6 @@ static int i915_ttm_get_pages(struct drm_i915_gem_object *obj)
/* Move to the requested placement. */
i915_ttm_placement_from_obj(obj, &requested, busy, &placement);
- /*
- * For now we support LMEM only with TTM.
- * TODO: Remove with system support
- */
- GEM_BUG_ON(requested.mem_type < I915_PL_LMEM0 ||
- busy[0].mem_type < I915_PL_LMEM0);
-
/* First try only the requested placement. No eviction. */
real_num_busy = fetch_and_zero(&placement.num_busy_placement);
ret = ttm_bo_validate(bo, &placement, &ctx);
@@ -635,9 +647,6 @@ static int i915_ttm_get_pages(struct drm_i915_gem_object *obj)
ret == -EAGAIN)
return ret;
- /* TODO: Remove this when we support system as TTM. */
- real_num_busy = 1;
-
/*
* If the initial attempt fails, allow all accepted placements,
* evicting if necessary.
@@ -872,3 +881,25 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
return 0;
}
+
+static const struct intel_memory_region_ops ttm_system_region_ops = {
+ .init_object = __i915_gem_ttm_object_init,
+};
+
+struct intel_memory_region *
+i915_gem_ttm_system_setup(struct drm_i915_private *i915,
+ u16 type, u16 instance)
+{
+ struct intel_memory_region *mr;
+
+ mr = intel_memory_region_create(i915, 0,
+ totalram_pages() << PAGE_SHIFT,
+ PAGE_SIZE, 0,
+ type, instance,
+ &ttm_system_region_ops);
+ if (IS_ERR(mr))
+ return mr;
+
+ intel_memory_region_set_name(mr, "system-ttm");
+ return mr;
+}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 01e11fe38642..bfbfbae57573 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1751,9 +1751,6 @@ void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
void i915_gem_init_early(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
-struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915,
- u16 type, u16 instance);
-
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
/*
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index df59f884d37c..779eb2fa90b6 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -173,7 +173,12 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
instance = intel_region_map[i].instance;
switch (type) {
case INTEL_MEMORY_SYSTEM:
- mem = i915_gem_shmem_setup(i915, type, instance);
+ if (IS_DGFX(i915))
+ mem = i915_gem_ttm_system_setup(i915, type,
+ instance);
+ else
+ mem = i915_gem_shmem_setup(i915, type,
+ instance);
break;
case INTEL_MEMORY_STOLEN_LOCAL:
mem = i915_gem_stolen_lmem_setup(i915, type, instance);
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index 2be8433d373a..b1b9e461d53b 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -125,4 +125,12 @@ intel_memory_region_set_name(struct intel_memory_region *mem,
int intel_memory_region_reserve(struct intel_memory_region *mem,
resource_size_t offset,
resource_size_t size);
+
+struct intel_memory_region *
+i915_gem_ttm_system_setup(struct drm_i915_private *i915,
+ u16 type, u16 instance);
+struct intel_memory_region *
+i915_gem_shmem_setup(struct drm_i915_private *i915,
+ u16 type, u16 instance);
+
#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v7 3/3] drm/i915/ttm: Use TTM for system memory
@ 2021-06-22 9:34 ` Thomas Hellström
0 siblings, 0 replies; 19+ messages in thread
From: Thomas Hellström @ 2021-06-22 9:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Thomas Hellström, matthew.auld
For discrete, use TTM for both cached and WC system memory. That means
we currently rely on the TTM memory accounting / shrinker. For cached
system memory we should consider remaining shmem-backed, which can be
implemented from our ttm_tt_populate callback. We can then also reuse our
own very elaborate shrinker for that memory.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
v2:
- Fix IS_ERR_OR_NULL() check to IS_ERR() (Reported by Matthew Auld)
v3:
- Commit message typo fix
v6:
- Fix TODO:s for supporting system memory with TTM.
- Update the object GEM region after a TTM move if compatible.
- Add a couple of warnings for shmem on DGFX.
---
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 3 ++
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 51 +++++++++++++++++-----
drivers/gpu/drm/i915/i915_drv.h | 3 --
drivers/gpu/drm/i915/intel_memory_region.c | 7 ++-
drivers/gpu/drm/i915/intel_memory_region.h | 8 ++++
5 files changed, 58 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 7aa1c95c7b7d..3648ae1d6628 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -284,6 +284,7 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
bool needs_clflush)
{
GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
+ GEM_WARN_ON(IS_DGFX(to_i915(obj->base.dev)));
if (obj->mm.madv == I915_MADV_DONTNEED)
obj->mm.dirty = false;
@@ -302,6 +303,7 @@ void i915_gem_object_put_pages_shmem(struct drm_i915_gem_object *obj, struct sg_
struct pagevec pvec;
struct page *page;
+ GEM_WARN_ON(IS_DGFX(to_i915(obj->base.dev)));
__i915_gem_object_release_shmem(obj, pages, true);
i915_gem_gtt_finish_pages(obj, pages);
@@ -560,6 +562,7 @@ i915_gem_object_create_shmem_from_data(struct drm_i915_private *dev_priv,
resource_size_t offset;
int err;
+ GEM_WARN_ON(IS_DGFX(dev_priv));
obj = i915_gem_object_create_shmem(dev_priv, round_up(size, PAGE_SIZE));
if (IS_ERR(obj))
return obj;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 966b292d07da..07097f150065 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -286,6 +286,25 @@ static void i915_ttm_adjust_gem_after_move(struct drm_i915_gem_object *obj)
{
struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
unsigned int cache_level;
+ unsigned int i;
+
+ /*
+ * If object was moved to an allowable region, update the object
+ * region to consider it migrated. Note that if it's currently not
+ * in an allowable region, it's evicted and we don't update the
+ * object region.
+ */
+ if (intel_region_to_ttm_type(obj->mm.region) != bo->resource->mem_type) {
+ for (i = 0; i < obj->mm.n_placements; ++i) {
+ struct intel_memory_region *mr = obj->mm.placements[i];
+
+ if (intel_region_to_ttm_type(mr) == bo->resource->mem_type &&
+ mr != obj->mm.region) {
+ intel_memory_region_put(obj->mm.region);
+ obj->mm.region = intel_memory_region_get(mr);
+ }
+ }
+ }
obj->mem_flags &= ~(I915_BO_FLAG_STRUCT_PAGE | I915_BO_FLAG_IOMEM);
@@ -615,13 +634,6 @@ static int i915_ttm_get_pages(struct drm_i915_gem_object *obj)
/* Move to the requested placement. */
i915_ttm_placement_from_obj(obj, &requested, busy, &placement);
- /*
- * For now we support LMEM only with TTM.
- * TODO: Remove with system support
- */
- GEM_BUG_ON(requested.mem_type < I915_PL_LMEM0 ||
- busy[0].mem_type < I915_PL_LMEM0);
-
/* First try only the requested placement. No eviction. */
real_num_busy = fetch_and_zero(&placement.num_busy_placement);
ret = ttm_bo_validate(bo, &placement, &ctx);
@@ -635,9 +647,6 @@ static int i915_ttm_get_pages(struct drm_i915_gem_object *obj)
ret == -EAGAIN)
return ret;
- /* TODO: Remove this when we support system as TTM. */
- real_num_busy = 1;
-
/*
* If the initial attempt fails, allow all accepted placements,
* evicting if necessary.
@@ -872,3 +881,25 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
return 0;
}
+
+static const struct intel_memory_region_ops ttm_system_region_ops = {
+ .init_object = __i915_gem_ttm_object_init,
+};
+
+struct intel_memory_region *
+i915_gem_ttm_system_setup(struct drm_i915_private *i915,
+ u16 type, u16 instance)
+{
+ struct intel_memory_region *mr;
+
+ mr = intel_memory_region_create(i915, 0,
+ totalram_pages() << PAGE_SHIFT,
+ PAGE_SIZE, 0,
+ type, instance,
+ &ttm_system_region_ops);
+ if (IS_ERR(mr))
+ return mr;
+
+ intel_memory_region_set_name(mr, "system-ttm");
+ return mr;
+}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 01e11fe38642..bfbfbae57573 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1751,9 +1751,6 @@ void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
void i915_gem_init_early(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
-struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915,
- u16 type, u16 instance);
-
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
/*
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index df59f884d37c..779eb2fa90b6 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -173,7 +173,12 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
instance = intel_region_map[i].instance;
switch (type) {
case INTEL_MEMORY_SYSTEM:
- mem = i915_gem_shmem_setup(i915, type, instance);
+ if (IS_DGFX(i915))
+ mem = i915_gem_ttm_system_setup(i915, type,
+ instance);
+ else
+ mem = i915_gem_shmem_setup(i915, type,
+ instance);
break;
case INTEL_MEMORY_STOLEN_LOCAL:
mem = i915_gem_stolen_lmem_setup(i915, type, instance);
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index 2be8433d373a..b1b9e461d53b 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -125,4 +125,12 @@ intel_memory_region_set_name(struct intel_memory_region *mem,
int intel_memory_region_reserve(struct intel_memory_region *mem,
resource_size_t offset,
resource_size_t size);
+
+struct intel_memory_region *
+i915_gem_ttm_system_setup(struct drm_i915_private *i915,
+ u16 type, u16 instance);
+struct intel_memory_region *
+i915_gem_shmem_setup(struct drm_i915_private *i915,
+ u16 type, u16 instance);
+
#endif
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v7 2/3] drm/i915/ttm: Adjust gem flags and caching settings after a move
2021-06-22 9:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-22 9:44 ` Matthew Auld
-1 siblings, 0 replies; 19+ messages in thread
From: Matthew Auld @ 2021-06-22 9:44 UTC (permalink / raw)
To: Thomas Hellström
Cc: Intel Graphics Development, Matthew Auld, ML dri-devel
On Tue, 22 Jun 2021 at 10:34, Thomas Hellström
<thomas.hellstrom@linux.intel.com> wrote:
>
> After a TTM move or object init we need to update the i915 gem flags and
> caching settings to reflect the new placement. Currently caching settings
> are not changed during the lifetime of an object, although that might
> change moving forward if we run into performance issues or issues with
> WC system page allocations.
> Also introduce gpu_binds_iomem() and cpu_maps_iomem() to clean up the
> various ways we previously used to detect this.
> Finally, initialize the TTM object reserved to be able to update
> flags and caching before anyone else gets hold of the object.
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> ---
> v6:
> - Rebase on accelerated ttm moves.
> ---
<snip>
> @@ -775,14 +845,13 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
> i915_gem_object_init(obj, &i915_gem_ttm_obj_ops, &lock_class, flags);
> i915_gem_object_init_memory_region(obj, mem);
> i915_gem_object_make_unshrinkable(obj);
> - obj->read_domains = I915_GEM_DOMAIN_WC | I915_GEM_DOMAIN_GTT;
> - obj->mem_flags |= I915_BO_FLAG_IOMEM;
> - i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
> INIT_RADIX_TREE(&obj->ttm.get_io_page.radix, GFP_KERNEL | __GFP_NOWARN);
> mutex_init(&obj->ttm.get_io_page.lock);
> bo_type = (obj->flags & I915_BO_ALLOC_USER) ? ttm_bo_type_device :
> ttm_bo_type_kernel;
>
> + obj->base.vma_node.driver_private = i915_gem_to_ttm(obj);
> +
> /*
> * If this function fails, it will call the destructor, but
> * our caller still owns the object. So no freeing in the
> @@ -790,14 +859,16 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
> * Similarly, in delayed_destroy, we can't call ttm_bo_put()
> * until successful initialization.
> */
> - obj->base.vma_node.driver_private = i915_gem_to_ttm(obj);
> - ret = ttm_bo_init(&i915->bdev, i915_gem_to_ttm(obj), size,
> - bo_type, &i915_sys_placement,
> - mem->min_page_size >> PAGE_SHIFT,
> - true, NULL, NULL, i915_ttm_bo_destroy);
> - if (!ret)
> - obj->ttm.created = true;
> -
> - /* i915 wants -ENXIO when out of memory region space. */
> - return i915_ttm_err_to_gem(ret);
> + ret = ttm_bo_init_reserved(&i915->bdev, i915_gem_to_ttm(obj), size,
> + bo_type, &i915_sys_placement, 1,
mem->min_page_size >> PAGE_SHIFT? Although just realised that looks
iffy since it only considers the current region, when it should
consider all future placements. I wonder if it makes sense to make
page_alignment part of ttm_place? Anyway, it doesn't matter for this
series.
> + &ctx, NULL, NULL, i915_ttm_bo_destroy);
> + if (ret)
> + return i915_ttm_err_to_gem(ret);
> +
> + obj->ttm.created = true;
> + i915_ttm_adjust_domains_after_move(obj);
> + i915_ttm_adjust_gem_after_move(obj);
> + i915_gem_object_unlock(obj);
> +
> + return 0;
> }
> --
> 2.31.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v7 2/3] drm/i915/ttm: Adjust gem flags and caching settings after a move
@ 2021-06-22 9:44 ` Matthew Auld
0 siblings, 0 replies; 19+ messages in thread
From: Matthew Auld @ 2021-06-22 9:44 UTC (permalink / raw)
To: Thomas Hellström
Cc: Intel Graphics Development, Matthew Auld, ML dri-devel
On Tue, 22 Jun 2021 at 10:34, Thomas Hellström
<thomas.hellstrom@linux.intel.com> wrote:
>
> After a TTM move or object init we need to update the i915 gem flags and
> caching settings to reflect the new placement. Currently caching settings
> are not changed during the lifetime of an object, although that might
> change moving forward if we run into performance issues or issues with
> WC system page allocations.
> Also introduce gpu_binds_iomem() and cpu_maps_iomem() to clean up the
> various ways we previously used to detect this.
> Finally, initialize the TTM object reserved to be able to update
> flags and caching before anyone else gets hold of the object.
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> ---
> v6:
> - Rebase on accelerated ttm moves.
> ---
<snip>
> @@ -775,14 +845,13 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
> i915_gem_object_init(obj, &i915_gem_ttm_obj_ops, &lock_class, flags);
> i915_gem_object_init_memory_region(obj, mem);
> i915_gem_object_make_unshrinkable(obj);
> - obj->read_domains = I915_GEM_DOMAIN_WC | I915_GEM_DOMAIN_GTT;
> - obj->mem_flags |= I915_BO_FLAG_IOMEM;
> - i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
> INIT_RADIX_TREE(&obj->ttm.get_io_page.radix, GFP_KERNEL | __GFP_NOWARN);
> mutex_init(&obj->ttm.get_io_page.lock);
> bo_type = (obj->flags & I915_BO_ALLOC_USER) ? ttm_bo_type_device :
> ttm_bo_type_kernel;
>
> + obj->base.vma_node.driver_private = i915_gem_to_ttm(obj);
> +
> /*
> * If this function fails, it will call the destructor, but
> * our caller still owns the object. So no freeing in the
> @@ -790,14 +859,16 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
> * Similarly, in delayed_destroy, we can't call ttm_bo_put()
> * until successful initialization.
> */
> - obj->base.vma_node.driver_private = i915_gem_to_ttm(obj);
> - ret = ttm_bo_init(&i915->bdev, i915_gem_to_ttm(obj), size,
> - bo_type, &i915_sys_placement,
> - mem->min_page_size >> PAGE_SHIFT,
> - true, NULL, NULL, i915_ttm_bo_destroy);
> - if (!ret)
> - obj->ttm.created = true;
> -
> - /* i915 wants -ENXIO when out of memory region space. */
> - return i915_ttm_err_to_gem(ret);
> + ret = ttm_bo_init_reserved(&i915->bdev, i915_gem_to_ttm(obj), size,
> + bo_type, &i915_sys_placement, 1,
mem->min_page_size >> PAGE_SHIFT? Although just realised that looks
iffy since it only considers the current region, when it should
consider all future placements. I wonder if it makes sense to make
page_alignment part of ttm_place? Anyway, it doesn't matter for this
series.
> + &ctx, NULL, NULL, i915_ttm_bo_destroy);
> + if (ret)
> + return i915_ttm_err_to_gem(ret);
> +
> + obj->ttm.created = true;
> + i915_ttm_adjust_domains_after_move(obj);
> + i915_ttm_adjust_gem_after_move(obj);
> + i915_gem_object_unlock(obj);
> +
> + return 0;
> }
> --
> 2.31.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v7 2/3] drm/i915/ttm: Adjust gem flags and caching settings after a move
2021-06-22 9:44 ` Matthew Auld
@ 2021-06-22 10:07 ` Thomas Hellström
-1 siblings, 0 replies; 19+ messages in thread
From: Thomas Hellström @ 2021-06-22 10:07 UTC (permalink / raw)
To: Matthew Auld; +Cc: Intel Graphics Development, Matthew Auld, ML dri-devel
On 6/22/21 11:44 AM, Matthew Auld wrote:
> On Tue, 22 Jun 2021 at 10:34, Thomas Hellström
> <thomas.hellstrom@linux.intel.com> wrote:
>> After a TTM move or object init we need to update the i915 gem flags and
>> caching settings to reflect the new placement. Currently caching settings
>> are not changed during the lifetime of an object, although that might
>> change moving forward if we run into performance issues or issues with
>> WC system page allocations.
>> Also introduce gpu_binds_iomem() and cpu_maps_iomem() to clean up the
>> various ways we previously used to detect this.
>> Finally, initialize the TTM object reserved to be able to update
>> flags and caching before anyone else gets hold of the object.
>>
>> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>> ---
>> v6:
>> - Rebase on accelerated ttm moves.
>> ---
> <snip>
>
>> @@ -775,14 +845,13 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
>> i915_gem_object_init(obj, &i915_gem_ttm_obj_ops, &lock_class, flags);
>> i915_gem_object_init_memory_region(obj, mem);
>> i915_gem_object_make_unshrinkable(obj);
>> - obj->read_domains = I915_GEM_DOMAIN_WC | I915_GEM_DOMAIN_GTT;
>> - obj->mem_flags |= I915_BO_FLAG_IOMEM;
>> - i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
>> INIT_RADIX_TREE(&obj->ttm.get_io_page.radix, GFP_KERNEL | __GFP_NOWARN);
>> mutex_init(&obj->ttm.get_io_page.lock);
>> bo_type = (obj->flags & I915_BO_ALLOC_USER) ? ttm_bo_type_device :
>> ttm_bo_type_kernel;
>>
>> + obj->base.vma_node.driver_private = i915_gem_to_ttm(obj);
>> +
>> /*
>> * If this function fails, it will call the destructor, but
>> * our caller still owns the object. So no freeing in the
>> @@ -790,14 +859,16 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
>> * Similarly, in delayed_destroy, we can't call ttm_bo_put()
>> * until successful initialization.
>> */
>> - obj->base.vma_node.driver_private = i915_gem_to_ttm(obj);
>> - ret = ttm_bo_init(&i915->bdev, i915_gem_to_ttm(obj), size,
>> - bo_type, &i915_sys_placement,
>> - mem->min_page_size >> PAGE_SHIFT,
>> - true, NULL, NULL, i915_ttm_bo_destroy);
>> - if (!ret)
>> - obj->ttm.created = true;
>> -
>> - /* i915 wants -ENXIO when out of memory region space. */
>> - return i915_ttm_err_to_gem(ret);
>> + ret = ttm_bo_init_reserved(&i915->bdev, i915_gem_to_ttm(obj), size,
>> + bo_type, &i915_sys_placement, 1,
> mem->min_page_size >> PAGE_SHIFT? Although just realised that looks
> iffy since it only considers the current region, when it should
> consider all future placements. I wonder if it makes sense to make
> page_alignment part of ttm_place? Anyway, it doesn't matter for this
> series.
Good catch. Yes completely agree it should be part of ttm_place. But
extending ttm_place and audit all drivers to always clear unused parts
of ttm_place is a big task.
But it's also the case that the region manager is allowed to enforce an
alignment, unknown to us here, so we might want to take that approach to
begin with?
/Thomas
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v7 2/3] drm/i915/ttm: Adjust gem flags and caching settings after a move
@ 2021-06-22 10:07 ` Thomas Hellström
0 siblings, 0 replies; 19+ messages in thread
From: Thomas Hellström @ 2021-06-22 10:07 UTC (permalink / raw)
To: Matthew Auld; +Cc: Intel Graphics Development, Matthew Auld, ML dri-devel
On 6/22/21 11:44 AM, Matthew Auld wrote:
> On Tue, 22 Jun 2021 at 10:34, Thomas Hellström
> <thomas.hellstrom@linux.intel.com> wrote:
>> After a TTM move or object init we need to update the i915 gem flags and
>> caching settings to reflect the new placement. Currently caching settings
>> are not changed during the lifetime of an object, although that might
>> change moving forward if we run into performance issues or issues with
>> WC system page allocations.
>> Also introduce gpu_binds_iomem() and cpu_maps_iomem() to clean up the
>> various ways we previously used to detect this.
>> Finally, initialize the TTM object reserved to be able to update
>> flags and caching before anyone else gets hold of the object.
>>
>> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>> ---
>> v6:
>> - Rebase on accelerated ttm moves.
>> ---
> <snip>
>
>> @@ -775,14 +845,13 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
>> i915_gem_object_init(obj, &i915_gem_ttm_obj_ops, &lock_class, flags);
>> i915_gem_object_init_memory_region(obj, mem);
>> i915_gem_object_make_unshrinkable(obj);
>> - obj->read_domains = I915_GEM_DOMAIN_WC | I915_GEM_DOMAIN_GTT;
>> - obj->mem_flags |= I915_BO_FLAG_IOMEM;
>> - i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
>> INIT_RADIX_TREE(&obj->ttm.get_io_page.radix, GFP_KERNEL | __GFP_NOWARN);
>> mutex_init(&obj->ttm.get_io_page.lock);
>> bo_type = (obj->flags & I915_BO_ALLOC_USER) ? ttm_bo_type_device :
>> ttm_bo_type_kernel;
>>
>> + obj->base.vma_node.driver_private = i915_gem_to_ttm(obj);
>> +
>> /*
>> * If this function fails, it will call the destructor, but
>> * our caller still owns the object. So no freeing in the
>> @@ -790,14 +859,16 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
>> * Similarly, in delayed_destroy, we can't call ttm_bo_put()
>> * until successful initialization.
>> */
>> - obj->base.vma_node.driver_private = i915_gem_to_ttm(obj);
>> - ret = ttm_bo_init(&i915->bdev, i915_gem_to_ttm(obj), size,
>> - bo_type, &i915_sys_placement,
>> - mem->min_page_size >> PAGE_SHIFT,
>> - true, NULL, NULL, i915_ttm_bo_destroy);
>> - if (!ret)
>> - obj->ttm.created = true;
>> -
>> - /* i915 wants -ENXIO when out of memory region space. */
>> - return i915_ttm_err_to_gem(ret);
>> + ret = ttm_bo_init_reserved(&i915->bdev, i915_gem_to_ttm(obj), size,
>> + bo_type, &i915_sys_placement, 1,
> mem->min_page_size >> PAGE_SHIFT? Although just realised that looks
> iffy since it only considers the current region, when it should
> consider all future placements. I wonder if it makes sense to make
> page_alignment part of ttm_place? Anyway, it doesn't matter for this
> series.
Good catch. Yes completely agree it should be part of ttm_place. But
extending ttm_place and audit all drivers to always clear unused parts
of ttm_place is a big task.
But it's also the case that the region manager is allowed to enforce an
alignment, unknown to us here, so we might want to take that approach to
begin with?
/Thomas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v7 3/3] drm/i915/ttm: Use TTM for system memory
2021-06-22 9:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-22 10:55 ` Matthew Auld
-1 siblings, 0 replies; 19+ messages in thread
From: Matthew Auld @ 2021-06-22 10:55 UTC (permalink / raw)
To: Thomas Hellström
Cc: Intel Graphics Development, Matthew Auld, ML dri-devel
On Tue, 22 Jun 2021 at 10:34, Thomas Hellström
<thomas.hellstrom@linux.intel.com> wrote:
>
> For discrete, use TTM for both cached and WC system memory. That means
> we currently rely on the TTM memory accounting / shrinker. For cached
> system memory we should consider remaining shmem-backed, which can be
> implemented from our ttm_tt_populate callback. We can then also reuse our
> own very elaborate shrinker for that memory.
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> ---
> v2:
> - Fix IS_ERR_OR_NULL() check to IS_ERR() (Reported by Matthew Auld)
> v3:
> - Commit message typo fix
> v6:
> - Fix TODO:s for supporting system memory with TTM.
> - Update the object GEM region after a TTM move if compatible.
> - Add a couple of warnings for shmem on DGFX.
> ---
> drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 3 ++
> drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 51 +++++++++++++++++-----
> drivers/gpu/drm/i915/i915_drv.h | 3 --
> drivers/gpu/drm/i915/intel_memory_region.c | 7 ++-
> drivers/gpu/drm/i915/intel_memory_region.h | 8 ++++
> 5 files changed, 58 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> index 7aa1c95c7b7d..3648ae1d6628 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> @@ -284,6 +284,7 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
> bool needs_clflush)
> {
> GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
> + GEM_WARN_ON(IS_DGFX(to_i915(obj->base.dev)));
>
> if (obj->mm.madv == I915_MADV_DONTNEED)
> obj->mm.dirty = false;
> @@ -302,6 +303,7 @@ void i915_gem_object_put_pages_shmem(struct drm_i915_gem_object *obj, struct sg_
> struct pagevec pvec;
> struct page *page;
>
> + GEM_WARN_ON(IS_DGFX(to_i915(obj->base.dev)));
> __i915_gem_object_release_shmem(obj, pages, true);
>
> i915_gem_gtt_finish_pages(obj, pages);
> @@ -560,6 +562,7 @@ i915_gem_object_create_shmem_from_data(struct drm_i915_private *dev_priv,
> resource_size_t offset;
> int err;
>
> + GEM_WARN_ON(IS_DGFX(dev_priv));
> obj = i915_gem_object_create_shmem(dev_priv, round_up(size, PAGE_SIZE));
> if (IS_ERR(obj))
> return obj;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> index 966b292d07da..07097f150065 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> @@ -286,6 +286,25 @@ static void i915_ttm_adjust_gem_after_move(struct drm_i915_gem_object *obj)
> {
> struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
> unsigned int cache_level;
> + unsigned int i;
> +
> + /*
> + * If object was moved to an allowable region, update the object
> + * region to consider it migrated. Note that if it's currently not
> + * in an allowable region, it's evicted and we don't update the
> + * object region.
> + */
> + if (intel_region_to_ttm_type(obj->mm.region) != bo->resource->mem_type) {
> + for (i = 0; i < obj->mm.n_placements; ++i) {
> + struct intel_memory_region *mr = obj->mm.placements[i];
> +
> + if (intel_region_to_ttm_type(mr) == bo->resource->mem_type &&
> + mr != obj->mm.region) {
> + intel_memory_region_put(obj->mm.region);
> + obj->mm.region = intel_memory_region_get(mr);
break;?
i915_gem_object_{init, release}_memory_region?
There is also the region_link stuff, but I guess we can nuke that?
> + }
> + }
> + }
>
> obj->mem_flags &= ~(I915_BO_FLAG_STRUCT_PAGE | I915_BO_FLAG_IOMEM);
>
> @@ -615,13 +634,6 @@ static int i915_ttm_get_pages(struct drm_i915_gem_object *obj)
> /* Move to the requested placement. */
> i915_ttm_placement_from_obj(obj, &requested, busy, &placement);
>
> - /*
> - * For now we support LMEM only with TTM.
> - * TODO: Remove with system support
> - */
> - GEM_BUG_ON(requested.mem_type < I915_PL_LMEM0 ||
> - busy[0].mem_type < I915_PL_LMEM0);
> -
> /* First try only the requested placement. No eviction. */
> real_num_busy = fetch_and_zero(&placement.num_busy_placement);
> ret = ttm_bo_validate(bo, &placement, &ctx);
> @@ -635,9 +647,6 @@ static int i915_ttm_get_pages(struct drm_i915_gem_object *obj)
> ret == -EAGAIN)
> return ret;
>
> - /* TODO: Remove this when we support system as TTM. */
> - real_num_busy = 1;
> -
> /*
> * If the initial attempt fails, allow all accepted placements,
> * evicting if necessary.
> @@ -872,3 +881,25 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
>
> return 0;
> }
> +
> +static const struct intel_memory_region_ops ttm_system_region_ops = {
> + .init_object = __i915_gem_ttm_object_init,
> +};
> +
> +struct intel_memory_region *
> +i915_gem_ttm_system_setup(struct drm_i915_private *i915,
> + u16 type, u16 instance)
> +{
> + struct intel_memory_region *mr;
> +
> + mr = intel_memory_region_create(i915, 0,
> + totalram_pages() << PAGE_SHIFT,
> + PAGE_SIZE, 0,
> + type, instance,
> + &ttm_system_region_ops);
> + if (IS_ERR(mr))
> + return mr;
> +
> + intel_memory_region_set_name(mr, "system-ttm");
> + return mr;
> +}
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 01e11fe38642..bfbfbae57573 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1751,9 +1751,6 @@ void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
> void i915_gem_init_early(struct drm_i915_private *dev_priv);
> void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
>
> -struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915,
> - u16 type, u16 instance);
> -
> static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
> {
> /*
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
> index df59f884d37c..779eb2fa90b6 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.c
> +++ b/drivers/gpu/drm/i915/intel_memory_region.c
> @@ -173,7 +173,12 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
> instance = intel_region_map[i].instance;
> switch (type) {
> case INTEL_MEMORY_SYSTEM:
> - mem = i915_gem_shmem_setup(i915, type, instance);
> + if (IS_DGFX(i915))
> + mem = i915_gem_ttm_system_setup(i915, type,
> + instance);
> + else
> + mem = i915_gem_shmem_setup(i915, type,
> + instance);
> break;
> case INTEL_MEMORY_STOLEN_LOCAL:
> mem = i915_gem_stolen_lmem_setup(i915, type, instance);
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
> index 2be8433d373a..b1b9e461d53b 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.h
> +++ b/drivers/gpu/drm/i915/intel_memory_region.h
> @@ -125,4 +125,12 @@ intel_memory_region_set_name(struct intel_memory_region *mem,
> int intel_memory_region_reserve(struct intel_memory_region *mem,
> resource_size_t offset,
> resource_size_t size);
> +
> +struct intel_memory_region *
> +i915_gem_ttm_system_setup(struct drm_i915_private *i915,
> + u16 type, u16 instance);
> +struct intel_memory_region *
> +i915_gem_shmem_setup(struct drm_i915_private *i915,
> + u16 type, u16 instance);
> +
> #endif
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v7 3/3] drm/i915/ttm: Use TTM for system memory
@ 2021-06-22 10:55 ` Matthew Auld
0 siblings, 0 replies; 19+ messages in thread
From: Matthew Auld @ 2021-06-22 10:55 UTC (permalink / raw)
To: Thomas Hellström
Cc: Intel Graphics Development, Matthew Auld, ML dri-devel
On Tue, 22 Jun 2021 at 10:34, Thomas Hellström
<thomas.hellstrom@linux.intel.com> wrote:
>
> For discrete, use TTM for both cached and WC system memory. That means
> we currently rely on the TTM memory accounting / shrinker. For cached
> system memory we should consider remaining shmem-backed, which can be
> implemented from our ttm_tt_populate callback. We can then also reuse our
> own very elaborate shrinker for that memory.
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> ---
> v2:
> - Fix IS_ERR_OR_NULL() check to IS_ERR() (Reported by Matthew Auld)
> v3:
> - Commit message typo fix
> v6:
> - Fix TODO:s for supporting system memory with TTM.
> - Update the object GEM region after a TTM move if compatible.
> - Add a couple of warnings for shmem on DGFX.
> ---
> drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 3 ++
> drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 51 +++++++++++++++++-----
> drivers/gpu/drm/i915/i915_drv.h | 3 --
> drivers/gpu/drm/i915/intel_memory_region.c | 7 ++-
> drivers/gpu/drm/i915/intel_memory_region.h | 8 ++++
> 5 files changed, 58 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> index 7aa1c95c7b7d..3648ae1d6628 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> @@ -284,6 +284,7 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
> bool needs_clflush)
> {
> GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
> + GEM_WARN_ON(IS_DGFX(to_i915(obj->base.dev)));
>
> if (obj->mm.madv == I915_MADV_DONTNEED)
> obj->mm.dirty = false;
> @@ -302,6 +303,7 @@ void i915_gem_object_put_pages_shmem(struct drm_i915_gem_object *obj, struct sg_
> struct pagevec pvec;
> struct page *page;
>
> + GEM_WARN_ON(IS_DGFX(to_i915(obj->base.dev)));
> __i915_gem_object_release_shmem(obj, pages, true);
>
> i915_gem_gtt_finish_pages(obj, pages);
> @@ -560,6 +562,7 @@ i915_gem_object_create_shmem_from_data(struct drm_i915_private *dev_priv,
> resource_size_t offset;
> int err;
>
> + GEM_WARN_ON(IS_DGFX(dev_priv));
> obj = i915_gem_object_create_shmem(dev_priv, round_up(size, PAGE_SIZE));
> if (IS_ERR(obj))
> return obj;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> index 966b292d07da..07097f150065 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> @@ -286,6 +286,25 @@ static void i915_ttm_adjust_gem_after_move(struct drm_i915_gem_object *obj)
> {
> struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
> unsigned int cache_level;
> + unsigned int i;
> +
> + /*
> + * If object was moved to an allowable region, update the object
> + * region to consider it migrated. Note that if it's currently not
> + * in an allowable region, it's evicted and we don't update the
> + * object region.
> + */
> + if (intel_region_to_ttm_type(obj->mm.region) != bo->resource->mem_type) {
> + for (i = 0; i < obj->mm.n_placements; ++i) {
> + struct intel_memory_region *mr = obj->mm.placements[i];
> +
> + if (intel_region_to_ttm_type(mr) == bo->resource->mem_type &&
> + mr != obj->mm.region) {
> + intel_memory_region_put(obj->mm.region);
> + obj->mm.region = intel_memory_region_get(mr);
break;?
i915_gem_object_{init, release}_memory_region?
There is also the region_link stuff, but I guess we can nuke that?
> + }
> + }
> + }
>
> obj->mem_flags &= ~(I915_BO_FLAG_STRUCT_PAGE | I915_BO_FLAG_IOMEM);
>
> @@ -615,13 +634,6 @@ static int i915_ttm_get_pages(struct drm_i915_gem_object *obj)
> /* Move to the requested placement. */
> i915_ttm_placement_from_obj(obj, &requested, busy, &placement);
>
> - /*
> - * For now we support LMEM only with TTM.
> - * TODO: Remove with system support
> - */
> - GEM_BUG_ON(requested.mem_type < I915_PL_LMEM0 ||
> - busy[0].mem_type < I915_PL_LMEM0);
> -
> /* First try only the requested placement. No eviction. */
> real_num_busy = fetch_and_zero(&placement.num_busy_placement);
> ret = ttm_bo_validate(bo, &placement, &ctx);
> @@ -635,9 +647,6 @@ static int i915_ttm_get_pages(struct drm_i915_gem_object *obj)
> ret == -EAGAIN)
> return ret;
>
> - /* TODO: Remove this when we support system as TTM. */
> - real_num_busy = 1;
> -
> /*
> * If the initial attempt fails, allow all accepted placements,
> * evicting if necessary.
> @@ -872,3 +881,25 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
>
> return 0;
> }
> +
> +static const struct intel_memory_region_ops ttm_system_region_ops = {
> + .init_object = __i915_gem_ttm_object_init,
> +};
> +
> +struct intel_memory_region *
> +i915_gem_ttm_system_setup(struct drm_i915_private *i915,
> + u16 type, u16 instance)
> +{
> + struct intel_memory_region *mr;
> +
> + mr = intel_memory_region_create(i915, 0,
> + totalram_pages() << PAGE_SHIFT,
> + PAGE_SIZE, 0,
> + type, instance,
> + &ttm_system_region_ops);
> + if (IS_ERR(mr))
> + return mr;
> +
> + intel_memory_region_set_name(mr, "system-ttm");
> + return mr;
> +}
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 01e11fe38642..bfbfbae57573 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1751,9 +1751,6 @@ void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
> void i915_gem_init_early(struct drm_i915_private *dev_priv);
> void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
>
> -struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915,
> - u16 type, u16 instance);
> -
> static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
> {
> /*
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
> index df59f884d37c..779eb2fa90b6 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.c
> +++ b/drivers/gpu/drm/i915/intel_memory_region.c
> @@ -173,7 +173,12 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
> instance = intel_region_map[i].instance;
> switch (type) {
> case INTEL_MEMORY_SYSTEM:
> - mem = i915_gem_shmem_setup(i915, type, instance);
> + if (IS_DGFX(i915))
> + mem = i915_gem_ttm_system_setup(i915, type,
> + instance);
> + else
> + mem = i915_gem_shmem_setup(i915, type,
> + instance);
> break;
> case INTEL_MEMORY_STOLEN_LOCAL:
> mem = i915_gem_stolen_lmem_setup(i915, type, instance);
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
> index 2be8433d373a..b1b9e461d53b 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.h
> +++ b/drivers/gpu/drm/i915/intel_memory_region.h
> @@ -125,4 +125,12 @@ intel_memory_region_set_name(struct intel_memory_region *mem,
> int intel_memory_region_reserve(struct intel_memory_region *mem,
> resource_size_t offset,
> resource_size_t size);
> +
> +struct intel_memory_region *
> +i915_gem_ttm_system_setup(struct drm_i915_private *i915,
> + u16 type, u16 instance);
> +struct intel_memory_region *
> +i915_gem_shmem_setup(struct drm_i915_private *i915,
> + u16 type, u16 instance);
> +
> #endif
> --
> 2.31.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v7 3/3] drm/i915/ttm: Use TTM for system memory
2021-06-22 10:55 ` [Intel-gfx] " Matthew Auld
@ 2021-06-22 11:00 ` Thomas Hellström
-1 siblings, 0 replies; 19+ messages in thread
From: Thomas Hellström @ 2021-06-22 11:00 UTC (permalink / raw)
To: Matthew Auld; +Cc: Intel Graphics Development, Matthew Auld, ML dri-devel
On 6/22/21 12:55 PM, Matthew Auld wrote:
> On Tue, 22 Jun 2021 at 10:34, Thomas Hellström
> <thomas.hellstrom@linux.intel.com> wrote:
>> For discrete, use TTM for both cached and WC system memory. That means
>> we currently rely on the TTM memory accounting / shrinker. For cached
>> system memory we should consider remaining shmem-backed, which can be
>> implemented from our ttm_tt_populate callback. We can then also reuse our
>> own very elaborate shrinker for that memory.
>>
>> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>> ---
>> v2:
>> - Fix IS_ERR_OR_NULL() check to IS_ERR() (Reported by Matthew Auld)
>> v3:
>> - Commit message typo fix
>> v6:
>> - Fix TODO:s for supporting system memory with TTM.
>> - Update the object GEM region after a TTM move if compatible.
>> - Add a couple of warnings for shmem on DGFX.
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 3 ++
>> drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 51 +++++++++++++++++-----
>> drivers/gpu/drm/i915/i915_drv.h | 3 --
>> drivers/gpu/drm/i915/intel_memory_region.c | 7 ++-
>> drivers/gpu/drm/i915/intel_memory_region.h | 8 ++++
>> 5 files changed, 58 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
>> index 7aa1c95c7b7d..3648ae1d6628 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
>> @@ -284,6 +284,7 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
>> bool needs_clflush)
>> {
>> GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
>> + GEM_WARN_ON(IS_DGFX(to_i915(obj->base.dev)));
>>
>> if (obj->mm.madv == I915_MADV_DONTNEED)
>> obj->mm.dirty = false;
>> @@ -302,6 +303,7 @@ void i915_gem_object_put_pages_shmem(struct drm_i915_gem_object *obj, struct sg_
>> struct pagevec pvec;
>> struct page *page;
>>
>> + GEM_WARN_ON(IS_DGFX(to_i915(obj->base.dev)));
>> __i915_gem_object_release_shmem(obj, pages, true);
>>
>> i915_gem_gtt_finish_pages(obj, pages);
>> @@ -560,6 +562,7 @@ i915_gem_object_create_shmem_from_data(struct drm_i915_private *dev_priv,
>> resource_size_t offset;
>> int err;
>>
>> + GEM_WARN_ON(IS_DGFX(dev_priv));
>> obj = i915_gem_object_create_shmem(dev_priv, round_up(size, PAGE_SIZE));
>> if (IS_ERR(obj))
>> return obj;
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>> index 966b292d07da..07097f150065 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>> @@ -286,6 +286,25 @@ static void i915_ttm_adjust_gem_after_move(struct drm_i915_gem_object *obj)
>> {
>> struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
>> unsigned int cache_level;
>> + unsigned int i;
>> +
>> + /*
>> + * If object was moved to an allowable region, update the object
>> + * region to consider it migrated. Note that if it's currently not
>> + * in an allowable region, it's evicted and we don't update the
>> + * object region.
>> + */
>> + if (intel_region_to_ttm_type(obj->mm.region) != bo->resource->mem_type) {
>> + for (i = 0; i < obj->mm.n_placements; ++i) {
>> + struct intel_memory_region *mr = obj->mm.placements[i];
>> +
>> + if (intel_region_to_ttm_type(mr) == bo->resource->mem_type &&
>> + mr != obj->mm.region) {
>> + intel_memory_region_put(obj->mm.region);
>> + obj->mm.region = intel_memory_region_get(mr);
> break;?
>
> i915_gem_object_{init, release}_memory_region?
>
> There is also the region_link stuff, but I guess we can nuke that?
Ah, yes, I'll fix that up. I think we will actually need that for
suspend/resume, as the TTM LRU lists aren't sufficient...
Thanks for reviewing!
/Thomas
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v7 3/3] drm/i915/ttm: Use TTM for system memory
@ 2021-06-22 11:00 ` Thomas Hellström
0 siblings, 0 replies; 19+ messages in thread
From: Thomas Hellström @ 2021-06-22 11:00 UTC (permalink / raw)
To: Matthew Auld; +Cc: Intel Graphics Development, Matthew Auld, ML dri-devel
On 6/22/21 12:55 PM, Matthew Auld wrote:
> On Tue, 22 Jun 2021 at 10:34, Thomas Hellström
> <thomas.hellstrom@linux.intel.com> wrote:
>> For discrete, use TTM for both cached and WC system memory. That means
>> we currently rely on the TTM memory accounting / shrinker. For cached
>> system memory we should consider remaining shmem-backed, which can be
>> implemented from our ttm_tt_populate callback. We can then also reuse our
>> own very elaborate shrinker for that memory.
>>
>> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>> ---
>> v2:
>> - Fix IS_ERR_OR_NULL() check to IS_ERR() (Reported by Matthew Auld)
>> v3:
>> - Commit message typo fix
>> v6:
>> - Fix TODO:s for supporting system memory with TTM.
>> - Update the object GEM region after a TTM move if compatible.
>> - Add a couple of warnings for shmem on DGFX.
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 3 ++
>> drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 51 +++++++++++++++++-----
>> drivers/gpu/drm/i915/i915_drv.h | 3 --
>> drivers/gpu/drm/i915/intel_memory_region.c | 7 ++-
>> drivers/gpu/drm/i915/intel_memory_region.h | 8 ++++
>> 5 files changed, 58 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
>> index 7aa1c95c7b7d..3648ae1d6628 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
>> @@ -284,6 +284,7 @@ __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj,
>> bool needs_clflush)
>> {
>> GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
>> + GEM_WARN_ON(IS_DGFX(to_i915(obj->base.dev)));
>>
>> if (obj->mm.madv == I915_MADV_DONTNEED)
>> obj->mm.dirty = false;
>> @@ -302,6 +303,7 @@ void i915_gem_object_put_pages_shmem(struct drm_i915_gem_object *obj, struct sg_
>> struct pagevec pvec;
>> struct page *page;
>>
>> + GEM_WARN_ON(IS_DGFX(to_i915(obj->base.dev)));
>> __i915_gem_object_release_shmem(obj, pages, true);
>>
>> i915_gem_gtt_finish_pages(obj, pages);
>> @@ -560,6 +562,7 @@ i915_gem_object_create_shmem_from_data(struct drm_i915_private *dev_priv,
>> resource_size_t offset;
>> int err;
>>
>> + GEM_WARN_ON(IS_DGFX(dev_priv));
>> obj = i915_gem_object_create_shmem(dev_priv, round_up(size, PAGE_SIZE));
>> if (IS_ERR(obj))
>> return obj;
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>> index 966b292d07da..07097f150065 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
>> @@ -286,6 +286,25 @@ static void i915_ttm_adjust_gem_after_move(struct drm_i915_gem_object *obj)
>> {
>> struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
>> unsigned int cache_level;
>> + unsigned int i;
>> +
>> + /*
>> + * If object was moved to an allowable region, update the object
>> + * region to consider it migrated. Note that if it's currently not
>> + * in an allowable region, it's evicted and we don't update the
>> + * object region.
>> + */
>> + if (intel_region_to_ttm_type(obj->mm.region) != bo->resource->mem_type) {
>> + for (i = 0; i < obj->mm.n_placements; ++i) {
>> + struct intel_memory_region *mr = obj->mm.placements[i];
>> +
>> + if (intel_region_to_ttm_type(mr) == bo->resource->mem_type &&
>> + mr != obj->mm.region) {
>> + intel_memory_region_put(obj->mm.region);
>> + obj->mm.region = intel_memory_region_get(mr);
> break;?
>
> i915_gem_object_{init, release}_memory_region?
>
> There is also the region_link stuff, but I guess we can nuke that?
Ah, yes, I'll fix that up. I think we will actually need that for
suspend/resume, as the TTM LRU lists aren't sufficient...
Thanks for reviewing!
/Thomas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move system memory to TTM for discrete (rev7)
2021-06-22 9:34 ` [Intel-gfx] " Thomas Hellström
` (3 preceding siblings ...)
(?)
@ 2021-06-22 11:07 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2021-06-22 11:07 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Move system memory to TTM for discrete (rev7)
URL : https://patchwork.freedesktop.org/series/90898/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/gem/i915_gem_ttm.c:808:38: warning: symbol 'i915_gem_ttm_obj_ops' was not declared. Should it be static?
-O:drivers/gpu/drm/i915/gem/i915_gem_ttm.c:733:38: warning: symbol 'i915_gem_ttm_obj_ops' was not declared. Should it be static?
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Move system memory to TTM for discrete (rev7)
2021-06-22 9:34 ` [Intel-gfx] " Thomas Hellström
` (4 preceding siblings ...)
(?)
@ 2021-06-22 11:36 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2021-06-22 11:36 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4084 bytes --]
== Series Details ==
Series: drm/i915: Move system memory to TTM for discrete (rev7)
URL : https://patchwork.freedesktop.org/series/90898/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10261 -> Patchwork_20426
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20426:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_parallel@engines@userptr:
- {fi-dg1-1}: [FAIL][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/fi-dg1-1/igt@gem_exec_parallel@engines@userptr.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/fi-dg1-1/igt@gem_exec_parallel@engines@userptr.html
* igt@i915_selftest@live@gt_pm:
- {fi-jsl-1}: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
* igt@runner@aborted:
- {fi-dg1-1}: NOTRUN -> [FAIL][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/fi-dg1-1/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_20426 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-skl-6700k2: NOTRUN -> [SKIP][6] ([fdo#109271]) +24 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/fi-skl-6700k2/igt@amdgpu/amd_basic@cs-gfx.html
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271]) +4 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/fi-kbl-soraka/igt@amdgpu/amd_basic@cs-gfx.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6700k2: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/fi-skl-6700k2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
#### Possible fixes ####
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-skl-6700k2: [INCOMPLETE][9] ([i915#146] / [i915#2405]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/fi-skl-6700k2/igt@kms_chamelium@common-hpd-after-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/fi-skl-6700k2/igt@kms_chamelium@common-hpd-after-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Participating hosts (44 -> 38)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-n3050 fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10261 -> Patchwork_20426
CI-20190529: 20190529
CI_DRM_10261: 132b189b72a94328f17fd70321bfe63e5b4208e9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6117: 3ba0a02404f243d6d8f232c6215163cc4b0fd699 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20426: 324152868ec7f72345a32b8729031558529929fe @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
324152868ec7 drm/i915/ttm: Use TTM for system memory
4e479fc2ee7c drm/i915/ttm: Adjust gem flags and caching settings after a move
181ccb1c4076 drm/i915: Update object placement flags to be mutable
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/index.html
[-- Attachment #1.2: Type: text/html, Size: 5012 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Move system memory to TTM for discrete (rev7)
2021-06-22 9:34 ` [Intel-gfx] " Thomas Hellström
` (5 preceding siblings ...)
(?)
@ 2021-06-22 13:34 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2021-06-22 13:34 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30278 bytes --]
== Series Details ==
Series: drm/i915: Move system memory to TTM for discrete (rev7)
URL : https://patchwork.freedesktop.org/series/90898/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10261_full -> Patchwork_20426_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_20426_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-kbl: NOTRUN -> [DMESG-WARN][1] ([i915#180])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +5 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-snb6/igt@gem_ctx_persistence@legacy-engines-queued.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#3063]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-tglb6/igt@gem_eio@in-flight-contexts-10ms.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-tglb1/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-glk4/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-kbl1/igt@gem_exec_fair@basic-none@vecs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl3/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_mmap_gtt@cpuset-big-copy:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#307])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb1/igt@gem_mmap_gtt@cpuset-big-copy.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][13] ([i915#2658])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-apl8/igt@gem_pread@exhaustion.html
- shard-snb: NOTRUN -> [WARN][14] ([i915#2658])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-snb2/igt@gem_pread@exhaustion.html
- shard-kbl: NOTRUN -> [WARN][15] ([i915#2658])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl6/igt@gem_pread@exhaustion.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3323])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-apl2/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][17] ([i915#3318])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl4/igt@gem_userptr_blits@vma-merge.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: NOTRUN -> [WARN][18] ([i915#1804] / [i915#2684])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271]) +210 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-apl1/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_selftest@mock@requests:
- shard-skl: NOTRUN -> [INCOMPLETE][20] ([i915#198])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl9/igt@i915_selftest@mock@requests.html
* igt@kms_big_fb@linear-32bpp-rotate-180:
- shard-glk: [PASS][21] -> [DMESG-WARN][22] ([i915#118] / [i915#95])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-glk5/igt@kms_big_fb@linear-32bpp-rotate-180.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-glk1/igt@kms_big_fb@linear-32bpp-rotate-180.html
* igt@kms_chamelium@dp-crc-fast:
- shard-iclb: NOTRUN -> [SKIP][23] ([fdo#109284] / [fdo#111827]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb6/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][24] ([fdo#109271] / [fdo#111827]) +25 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-apl3/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-skl: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827]) +5 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl3/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][26] ([fdo#109271] / [fdo#111827]) +7 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl2/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color@pipe-a-ctm-0-5:
- shard-skl: NOTRUN -> [DMESG-WARN][27] ([i915#1982])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl4/igt@kms_color@pipe-a-ctm-0-5.html
* igt@kms_color@pipe-a-ctm-negative:
- shard-skl: [PASS][28] -> [DMESG-WARN][29] ([i915#1982]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-skl2/igt@kms_color@pipe-a-ctm-negative.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl1/igt@kms_color@pipe-a-ctm-negative.html
* igt@kms_color_chamelium@pipe-d-ctm-0-5:
- shard-snb: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +14 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-snb2/igt@kms_color_chamelium@pipe-d-ctm-0-5.html
* igt@kms_content_protection@atomic-dpms:
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#109300] / [fdo#111066])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@srm:
- shard-apl: NOTRUN -> [TIMEOUT][32] ([i915#1319])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-apl1/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-b-cursor-512x170-sliding:
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#109278] / [fdo#109279])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb6/igt@kms_cursor_crc@pipe-b-cursor-512x170-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-kbl: NOTRUN -> [SKIP][34] ([fdo#109271]) +89 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl2/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109274] / [fdo#109278]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][36] -> [FAIL][37] ([i915#2346] / [i915#533])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-kbl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#533]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl2/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1:
- shard-glk: [PASS][39] -> [FAIL][40] ([i915#79])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#79])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][43] -> [DMESG-WARN][44] ([i915#180]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][45] -> [DMESG-WARN][46] ([i915#180])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][47] -> [FAIL][48] ([i915#2122]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff:
- shard-skl: NOTRUN -> [SKIP][49] ([fdo#109271]) +63 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl9/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][50] ([fdo#109280]) +5 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_invalid_dotclock:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109310])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb6/igt@kms_invalid_dotclock.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#533]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-apl3/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][53] ([fdo#108145] / [i915#265]) +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl6/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265]) +4 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][55] -> [FAIL][56] ([fdo#108145] / [i915#265])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][57] ([fdo#108145] / [i915#265]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-d-coverage-vs-premult-vs-constant:
- shard-iclb: NOTRUN -> [SKIP][58] ([fdo#109278]) +3 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb6/igt@kms_plane_alpha_blend@pipe-d-coverage-vs-premult-vs-constant.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#658]) +3 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-skl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#658]) +3 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#658]) +4 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-apl1/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][62] -> [SKIP][63] ([fdo#109642] / [fdo#111068] / [i915#658])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-iclb2/igt@kms_psr2_su@page_flip.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb7/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [PASS][64] -> [SKIP][65] ([fdo#109441])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb3/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_vblank@pipe-d-query-forked-hang:
- shard-snb: NOTRUN -> [SKIP][66] ([fdo#109271]) +263 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-snb6/igt@kms_vblank@pipe-d-query-forked-hang.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#2437]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-apl2/igt@kms_writeback@writeback-fb-id.html
* igt@perf@polling-parameterized:
- shard-tglb: [PASS][68] -> [FAIL][69] ([i915#1542])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-tglb2/igt@perf@polling-parameterized.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-tglb5/igt@perf@polling-parameterized.html
* igt@sysfs_heartbeat_interval@mixed@bcs0:
- shard-skl: NOTRUN -> [FAIL][70] ([i915#1731])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl3/igt@sysfs_heartbeat_interval@mixed@bcs0.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][71] ([i915#658]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-iclb6/igt@feature_discovery@psr2.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-kbl: [INCOMPLETE][73] ([i915#794]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-kbl2/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [FAIL][75] ([i915#2410]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-tglb2/igt@gem_ctx_persistence@many-contexts.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-tglb7/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [FAIL][77] ([i915#2842]) -> [PASS][78] +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-tglb1/igt@gem_exec_fair@basic-pace@bcs0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-tglb8/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [FAIL][79] ([i915#2521]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl2/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-0:
- shard-glk: [DMESG-WARN][81] ([i915#118] / [i915#95]) -> [PASS][82] +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-glk4/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-glk6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][83] ([i915#79]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:
- shard-skl: [INCOMPLETE][85] ([i915#198]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-skl6/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl4/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
* igt@kms_flip@plain-flip-ts-check@a-hdmi-a2:
- shard-glk: [FAIL][87] ([i915#2122]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-glk5/igt@kms_flip@plain-flip-ts-check@a-hdmi-a2.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-glk1/igt@kms_flip@plain-flip-ts-check@a-hdmi-a2.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [INCOMPLETE][89] ([i915#123]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-skl4/igt@kms_frontbuffer_tracking@psr-suspend.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl3/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-kbl: [DMESG-WARN][91] ([i915#180]) -> [PASS][92] +2 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][93] ([fdo#108145] / [i915#265]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][95] ([fdo#109441]) -> [PASS][96] +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-iclb5/igt@kms_psr@psr2_no_drrs.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-skl: [INCOMPLETE][97] ([i915#198] / [i915#2828]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-skl4/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl9/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][99] ([i915#180]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-apl3/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-apl8/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
* igt@perf@polling-small-buf:
- shard-skl: [FAIL][101] ([i915#1722]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-skl10/igt@perf@polling-small-buf.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-skl10/igt@perf@polling-small-buf.html
#### Warnings ####
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][103] ([i915#2842]) -> [FAIL][104] ([i915#2852])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-iclb3/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [FAIL][105] ([i915#2842]) -> [SKIP][106] ([fdo#109271])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][107] ([i915#2684]) -> [WARN][108] ([i915#1804] / [i915#2684])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2:
- shard-iclb: [SKIP][109] ([i915#658]) -> [SKIP][110] ([i915#2920]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-iclb5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][111] ([i915#2920]) -> [SKIP][112] ([i915#658]) +3 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124]) ([i915#1436] / [i915#180] / [i915#3002] / [i915#3363])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-kbl7/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-kbl7/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-kbl7/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-kbl4/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-kbl2/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-kbl3/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl7/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl3/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl7/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl7/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl3/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-kbl2/igt@runner@aborted.html
- shard-iclb: ([FAIL][125], [FAIL][126], [FAIL][127]) ([i915#1814] / [i915#3002]) -> ([FAIL][128], [FAIL][129]) ([i915#3002])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-iclb6/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-iclb4/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-iclb1/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb1/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-iclb2/igt@runner@aborted.html
- shard-apl: ([FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][134], [FAIL][135], [FAIL][136]) ([i915#180] / [i915#3002] / [i915#3363])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-apl8/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-apl8/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-apl6/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10261/shard-apl3/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-apl2/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-apl6/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/shard-apl8/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109310]: https://bugs.freedesktop.org/show_bug.cgi?id=109310
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2828]: https://gitlab.freedesktop.org/drm/intel/issues/2828
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#307]: https://gitlab.freedesktop.org/drm/intel/issues/307
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#658]: https://gitlab.freedeskto
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20426/index.html
[-- Attachment #1.2: Type: text/html, Size: 37804 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2021-06-22 13:34 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-22 9:34 [PATCH v7 0/3] drm/i915: Move system memory to TTM for discrete Thomas Hellström
2021-06-22 9:34 ` [Intel-gfx] " Thomas Hellström
2021-06-22 9:34 ` [PATCH v7 1/3] drm/i915: Update object placement flags to be mutable Thomas Hellström
2021-06-22 9:34 ` [Intel-gfx] " Thomas Hellström
2021-06-22 9:34 ` [PATCH v7 2/3] drm/i915/ttm: Adjust gem flags and caching settings after a move Thomas Hellström
2021-06-22 9:34 ` [Intel-gfx] " Thomas Hellström
2021-06-22 9:44 ` Matthew Auld
2021-06-22 9:44 ` Matthew Auld
2021-06-22 10:07 ` Thomas Hellström
2021-06-22 10:07 ` Thomas Hellström
2021-06-22 9:34 ` [PATCH v7 3/3] drm/i915/ttm: Use TTM for system memory Thomas Hellström
2021-06-22 9:34 ` [Intel-gfx] " Thomas Hellström
2021-06-22 10:55 ` Matthew Auld
2021-06-22 10:55 ` [Intel-gfx] " Matthew Auld
2021-06-22 11:00 ` Thomas Hellström
2021-06-22 11:00 ` [Intel-gfx] " Thomas Hellström
2021-06-22 11:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Move system memory to TTM for discrete (rev7) Patchwork
2021-06-22 11:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-22 13:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.