* [PATCH v5 0/4] fpga: reorganize to subdirs
@ 2021-06-22 20:05 ` trix
0 siblings, 0 replies; 15+ messages in thread
From: trix @ 2021-06-22 20:05 UTC (permalink / raw)
To: hao.wu, mdf, corbet, michal.simek, gregkh, nava.manne, dinguyen,
krzysztof.kozlowski, yilun.xu, davidgow, fpacheco,
russell.h.weight, richard.gong, luca
Cc: linux-fpga, linux-doc, linux-kernel, linux-arm-kernel, Tom Rix
From: Tom Rix <trix@redhat.com>
The incoming xrt patchset has a toplevel subdir xrt/
The current fpga/ uses a single dir with filename prefixes to subdivide owners
For consistency, there should be only one way to organize the fpga/ dir.
Because the subdir model scales better, refactor to use it.
The discussion wrt xrt is here:
https://lore.kernel.org/linux-fpga/68e85a4f-4a10-1ff9-0443-aa565878c855@redhat.com/
Follow drivers/net/ethernet/ which has control configs
NET_VENDOR_BLA that map to drivers/net/ethernet/bla
Since fpgas do not have many vendors, drop the 'VENDOR' and use
FPGA_BLA.
There are several new subdirs
altera/
dfl/
lattice/
xilinx/
Each subdir has a Kconfig that has a new/reused
if FPGA_BLA
... existing configs ...
endif FPGA_BLA
Which is sourced into the main fpga/Kconfig
Each subdir has a Makefile whose transversal is controlled in the
fpga/Makefile by
obj-$(CONFIG_FPGA_BLA) += bla/
Some cleanup to arrange thing alphabetically and make fpga/Makefile's
whitespace look more like net/'s
Changes from
v1
Drop renaming files
Cleanup makefiles
v2
Expand commit messages
Add SPDX to Kconfig
Expand new Kconfig variable help messages
v3
Update Documentation/fpga/dfl.rst for fpga/dfl/
v4
Restore HAS_IOMEM depends in dfl/Kconfig
Fix vendor names in Kconfig's
Tom Rix (4):
fpga: dfl: reorganize to subdir layout
fpga: xilinx: reorganize to subdir layout
fpga: altera: reorganize to subdir layout
fpga: lattice: reorganize to subdir layout
Documentation/fpga/dfl.rst | 4 +-
MAINTAINERS | 2 +-
drivers/fpga/Kconfig | 204 +-----------------
drivers/fpga/Makefile | 47 +---
drivers/fpga/altera/Kconfig | 85 ++++++++
drivers/fpga/altera/Makefile | 12 ++
drivers/fpga/{ => altera}/altera-cvp.c | 0
drivers/fpga/{ => altera}/altera-fpga2sdram.c | 0
.../fpga/{ => altera}/altera-freeze-bridge.c | 0
drivers/fpga/{ => altera}/altera-hps2fpga.c | 0
.../{ => altera}/altera-pr-ip-core-plat.c | 0
drivers/fpga/{ => altera}/altera-pr-ip-core.c | 0
drivers/fpga/{ => altera}/altera-ps-spi.c | 0
drivers/fpga/{ => altera}/socfpga-a10.c | 0
drivers/fpga/{ => altera}/socfpga.c | 0
drivers/fpga/{ => altera}/stratix10-soc.c | 0
drivers/fpga/{ => altera}/ts73xx-fpga.c | 0
drivers/fpga/dfl/Kconfig | 83 +++++++
drivers/fpga/dfl/Makefile | 16 ++
drivers/fpga/{ => dfl}/dfl-afu-dma-region.c | 0
drivers/fpga/{ => dfl}/dfl-afu-error.c | 0
drivers/fpga/{ => dfl}/dfl-afu-main.c | 0
drivers/fpga/{ => dfl}/dfl-afu-region.c | 0
drivers/fpga/{ => dfl}/dfl-afu.h | 0
drivers/fpga/{ => dfl}/dfl-fme-br.c | 0
drivers/fpga/{ => dfl}/dfl-fme-error.c | 0
drivers/fpga/{ => dfl}/dfl-fme-main.c | 0
drivers/fpga/{ => dfl}/dfl-fme-mgr.c | 0
drivers/fpga/{ => dfl}/dfl-fme-perf.c | 0
drivers/fpga/{ => dfl}/dfl-fme-pr.c | 0
drivers/fpga/{ => dfl}/dfl-fme-pr.h | 0
drivers/fpga/{ => dfl}/dfl-fme-region.c | 0
drivers/fpga/{ => dfl}/dfl-fme.h | 0
drivers/fpga/{ => dfl}/dfl-n3000-nios.c | 0
drivers/fpga/{ => dfl}/dfl-pci.c | 0
drivers/fpga/{ => dfl}/dfl.c | 0
drivers/fpga/{ => dfl}/dfl.h | 0
drivers/fpga/lattice/Kconfig | 29 +++
drivers/fpga/lattice/Makefile | 4 +
drivers/fpga/{ => lattice}/ice40-spi.c | 0
drivers/fpga/{ => lattice}/machxo2-spi.c | 0
drivers/fpga/xilinx/Kconfig | 55 +++++
drivers/fpga/xilinx/Makefile | 6 +
.../fpga/{ => xilinx}/xilinx-pr-decoupler.c | 0
drivers/fpga/{ => xilinx}/xilinx-spi.c | 0
drivers/fpga/{ => xilinx}/zynq-fpga.c | 0
drivers/fpga/{ => xilinx}/zynqmp-fpga.c | 0
47 files changed, 305 insertions(+), 242 deletions(-)
create mode 100644 drivers/fpga/altera/Kconfig
create mode 100644 drivers/fpga/altera/Makefile
rename drivers/fpga/{ => altera}/altera-cvp.c (100%)
rename drivers/fpga/{ => altera}/altera-fpga2sdram.c (100%)
rename drivers/fpga/{ => altera}/altera-freeze-bridge.c (100%)
rename drivers/fpga/{ => altera}/altera-hps2fpga.c (100%)
rename drivers/fpga/{ => altera}/altera-pr-ip-core-plat.c (100%)
rename drivers/fpga/{ => altera}/altera-pr-ip-core.c (100%)
rename drivers/fpga/{ => altera}/altera-ps-spi.c (100%)
rename drivers/fpga/{ => altera}/socfpga-a10.c (100%)
rename drivers/fpga/{ => altera}/socfpga.c (100%)
rename drivers/fpga/{ => altera}/stratix10-soc.c (100%)
rename drivers/fpga/{ => altera}/ts73xx-fpga.c (100%)
create mode 100644 drivers/fpga/dfl/Kconfig
create mode 100644 drivers/fpga/dfl/Makefile
rename drivers/fpga/{ => dfl}/dfl-afu-dma-region.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu-error.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu-main.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu-region.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu.h (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-br.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-error.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-main.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-mgr.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-perf.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-pr.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-pr.h (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-region.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme.h (100%)
rename drivers/fpga/{ => dfl}/dfl-n3000-nios.c (100%)
rename drivers/fpga/{ => dfl}/dfl-pci.c (100%)
rename drivers/fpga/{ => dfl}/dfl.c (100%)
rename drivers/fpga/{ => dfl}/dfl.h (100%)
create mode 100644 drivers/fpga/lattice/Kconfig
create mode 100644 drivers/fpga/lattice/Makefile
rename drivers/fpga/{ => lattice}/ice40-spi.c (100%)
rename drivers/fpga/{ => lattice}/machxo2-spi.c (100%)
create mode 100644 drivers/fpga/xilinx/Kconfig
create mode 100644 drivers/fpga/xilinx/Makefile
rename drivers/fpga/{ => xilinx}/xilinx-pr-decoupler.c (100%)
rename drivers/fpga/{ => xilinx}/xilinx-spi.c (100%)
rename drivers/fpga/{ => xilinx}/zynq-fpga.c (100%)
rename drivers/fpga/{ => xilinx}/zynqmp-fpga.c (100%)
--
2.26.3
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v5 0/4] fpga: reorganize to subdirs
@ 2021-06-22 20:05 ` trix
0 siblings, 0 replies; 15+ messages in thread
From: trix @ 2021-06-22 20:05 UTC (permalink / raw)
To: hao.wu, mdf, corbet, michal.simek, gregkh, nava.manne, dinguyen,
krzysztof.kozlowski, yilun.xu, davidgow, fpacheco,
russell.h.weight, richard.gong, luca
Cc: linux-fpga, linux-doc, linux-kernel, linux-arm-kernel, Tom Rix
From: Tom Rix <trix@redhat.com>
The incoming xrt patchset has a toplevel subdir xrt/
The current fpga/ uses a single dir with filename prefixes to subdivide owners
For consistency, there should be only one way to organize the fpga/ dir.
Because the subdir model scales better, refactor to use it.
The discussion wrt xrt is here:
https://lore.kernel.org/linux-fpga/68e85a4f-4a10-1ff9-0443-aa565878c855@redhat.com/
Follow drivers/net/ethernet/ which has control configs
NET_VENDOR_BLA that map to drivers/net/ethernet/bla
Since fpgas do not have many vendors, drop the 'VENDOR' and use
FPGA_BLA.
There are several new subdirs
altera/
dfl/
lattice/
xilinx/
Each subdir has a Kconfig that has a new/reused
if FPGA_BLA
... existing configs ...
endif FPGA_BLA
Which is sourced into the main fpga/Kconfig
Each subdir has a Makefile whose transversal is controlled in the
fpga/Makefile by
obj-$(CONFIG_FPGA_BLA) += bla/
Some cleanup to arrange thing alphabetically and make fpga/Makefile's
whitespace look more like net/'s
Changes from
v1
Drop renaming files
Cleanup makefiles
v2
Expand commit messages
Add SPDX to Kconfig
Expand new Kconfig variable help messages
v3
Update Documentation/fpga/dfl.rst for fpga/dfl/
v4
Restore HAS_IOMEM depends in dfl/Kconfig
Fix vendor names in Kconfig's
Tom Rix (4):
fpga: dfl: reorganize to subdir layout
fpga: xilinx: reorganize to subdir layout
fpga: altera: reorganize to subdir layout
fpga: lattice: reorganize to subdir layout
Documentation/fpga/dfl.rst | 4 +-
MAINTAINERS | 2 +-
drivers/fpga/Kconfig | 204 +-----------------
drivers/fpga/Makefile | 47 +---
drivers/fpga/altera/Kconfig | 85 ++++++++
drivers/fpga/altera/Makefile | 12 ++
drivers/fpga/{ => altera}/altera-cvp.c | 0
drivers/fpga/{ => altera}/altera-fpga2sdram.c | 0
.../fpga/{ => altera}/altera-freeze-bridge.c | 0
drivers/fpga/{ => altera}/altera-hps2fpga.c | 0
.../{ => altera}/altera-pr-ip-core-plat.c | 0
drivers/fpga/{ => altera}/altera-pr-ip-core.c | 0
drivers/fpga/{ => altera}/altera-ps-spi.c | 0
drivers/fpga/{ => altera}/socfpga-a10.c | 0
drivers/fpga/{ => altera}/socfpga.c | 0
drivers/fpga/{ => altera}/stratix10-soc.c | 0
drivers/fpga/{ => altera}/ts73xx-fpga.c | 0
drivers/fpga/dfl/Kconfig | 83 +++++++
drivers/fpga/dfl/Makefile | 16 ++
drivers/fpga/{ => dfl}/dfl-afu-dma-region.c | 0
drivers/fpga/{ => dfl}/dfl-afu-error.c | 0
drivers/fpga/{ => dfl}/dfl-afu-main.c | 0
drivers/fpga/{ => dfl}/dfl-afu-region.c | 0
drivers/fpga/{ => dfl}/dfl-afu.h | 0
drivers/fpga/{ => dfl}/dfl-fme-br.c | 0
drivers/fpga/{ => dfl}/dfl-fme-error.c | 0
drivers/fpga/{ => dfl}/dfl-fme-main.c | 0
drivers/fpga/{ => dfl}/dfl-fme-mgr.c | 0
drivers/fpga/{ => dfl}/dfl-fme-perf.c | 0
drivers/fpga/{ => dfl}/dfl-fme-pr.c | 0
drivers/fpga/{ => dfl}/dfl-fme-pr.h | 0
drivers/fpga/{ => dfl}/dfl-fme-region.c | 0
drivers/fpga/{ => dfl}/dfl-fme.h | 0
drivers/fpga/{ => dfl}/dfl-n3000-nios.c | 0
drivers/fpga/{ => dfl}/dfl-pci.c | 0
drivers/fpga/{ => dfl}/dfl.c | 0
drivers/fpga/{ => dfl}/dfl.h | 0
drivers/fpga/lattice/Kconfig | 29 +++
drivers/fpga/lattice/Makefile | 4 +
drivers/fpga/{ => lattice}/ice40-spi.c | 0
drivers/fpga/{ => lattice}/machxo2-spi.c | 0
drivers/fpga/xilinx/Kconfig | 55 +++++
drivers/fpga/xilinx/Makefile | 6 +
.../fpga/{ => xilinx}/xilinx-pr-decoupler.c | 0
drivers/fpga/{ => xilinx}/xilinx-spi.c | 0
drivers/fpga/{ => xilinx}/zynq-fpga.c | 0
drivers/fpga/{ => xilinx}/zynqmp-fpga.c | 0
47 files changed, 305 insertions(+), 242 deletions(-)
create mode 100644 drivers/fpga/altera/Kconfig
create mode 100644 drivers/fpga/altera/Makefile
rename drivers/fpga/{ => altera}/altera-cvp.c (100%)
rename drivers/fpga/{ => altera}/altera-fpga2sdram.c (100%)
rename drivers/fpga/{ => altera}/altera-freeze-bridge.c (100%)
rename drivers/fpga/{ => altera}/altera-hps2fpga.c (100%)
rename drivers/fpga/{ => altera}/altera-pr-ip-core-plat.c (100%)
rename drivers/fpga/{ => altera}/altera-pr-ip-core.c (100%)
rename drivers/fpga/{ => altera}/altera-ps-spi.c (100%)
rename drivers/fpga/{ => altera}/socfpga-a10.c (100%)
rename drivers/fpga/{ => altera}/socfpga.c (100%)
rename drivers/fpga/{ => altera}/stratix10-soc.c (100%)
rename drivers/fpga/{ => altera}/ts73xx-fpga.c (100%)
create mode 100644 drivers/fpga/dfl/Kconfig
create mode 100644 drivers/fpga/dfl/Makefile
rename drivers/fpga/{ => dfl}/dfl-afu-dma-region.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu-error.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu-main.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu-region.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu.h (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-br.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-error.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-main.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-mgr.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-perf.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-pr.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-pr.h (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-region.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme.h (100%)
rename drivers/fpga/{ => dfl}/dfl-n3000-nios.c (100%)
rename drivers/fpga/{ => dfl}/dfl-pci.c (100%)
rename drivers/fpga/{ => dfl}/dfl.c (100%)
rename drivers/fpga/{ => dfl}/dfl.h (100%)
create mode 100644 drivers/fpga/lattice/Kconfig
create mode 100644 drivers/fpga/lattice/Makefile
rename drivers/fpga/{ => lattice}/ice40-spi.c (100%)
rename drivers/fpga/{ => lattice}/machxo2-spi.c (100%)
create mode 100644 drivers/fpga/xilinx/Kconfig
create mode 100644 drivers/fpga/xilinx/Makefile
rename drivers/fpga/{ => xilinx}/xilinx-pr-decoupler.c (100%)
rename drivers/fpga/{ => xilinx}/xilinx-spi.c (100%)
rename drivers/fpga/{ => xilinx}/zynq-fpga.c (100%)
rename drivers/fpga/{ => xilinx}/zynqmp-fpga.c (100%)
--
2.26.3
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v5 1/4] fpga: dfl: reorganize to subdir layout
2021-06-22 20:05 ` trix
@ 2021-06-22 20:05 ` trix
-1 siblings, 0 replies; 15+ messages in thread
From: trix @ 2021-06-22 20:05 UTC (permalink / raw)
To: hao.wu, mdf, corbet, michal.simek, gregkh, nava.manne, dinguyen,
krzysztof.kozlowski, yilun.xu, davidgow, fpacheco,
russell.h.weight, richard.gong, luca
Cc: linux-fpga, linux-doc, linux-kernel, linux-arm-kernel, Tom Rix
From: Tom Rix <trix@redhat.com>
Follow drivers/net/ethernet/ which has control configs
NET_VENDOR_BLA that map to drivers/net/ethernet/bla
Since fpgas do not have many vendors, drop the 'VENDOR' and use
FPGA_BLA.
There are several new subdirs
altera/
dfl/
lattice/
xilinx/
Each subdir has a Kconfig that has a new/reused
if FPGA_BLA
... existing configs ...
endif FPGA_BLA
Which is sourced into the main fpga/Kconfig
Each subdir has a Makefile whose transversal is controlled in the
fpga/Makefile by
obj-$(CONFIG_FPGA_BLA) += bla/
This is the dfl/ subdir part.
Create a dfl/ subdir
Move dfl-* files to it.
Add a Kconfig and Makefile
Because FPGA_DFL is now used in dfl/Kconfig in a if/endif
block, all the other configs in dfl/Kconfig implicitly depend
on FPGA_DFL.
Signed-off-by: Tom Rix <trix@redhat.com>
---
Documentation/fpga/dfl.rst | 4 +-
MAINTAINERS | 2 +-
drivers/fpga/Kconfig | 80 +-------------------
drivers/fpga/Makefile | 18 +----
drivers/fpga/dfl/Kconfig | 83 +++++++++++++++++++++
drivers/fpga/dfl/Makefile | 16 ++++
drivers/fpga/{ => dfl}/dfl-afu-dma-region.c | 0
drivers/fpga/{ => dfl}/dfl-afu-error.c | 0
drivers/fpga/{ => dfl}/dfl-afu-main.c | 0
drivers/fpga/{ => dfl}/dfl-afu-region.c | 0
drivers/fpga/{ => dfl}/dfl-afu.h | 0
drivers/fpga/{ => dfl}/dfl-fme-br.c | 0
drivers/fpga/{ => dfl}/dfl-fme-error.c | 0
drivers/fpga/{ => dfl}/dfl-fme-main.c | 0
drivers/fpga/{ => dfl}/dfl-fme-mgr.c | 0
drivers/fpga/{ => dfl}/dfl-fme-perf.c | 0
drivers/fpga/{ => dfl}/dfl-fme-pr.c | 0
drivers/fpga/{ => dfl}/dfl-fme-pr.h | 0
drivers/fpga/{ => dfl}/dfl-fme-region.c | 0
drivers/fpga/{ => dfl}/dfl-fme.h | 0
drivers/fpga/{ => dfl}/dfl-n3000-nios.c | 0
drivers/fpga/{ => dfl}/dfl-pci.c | 0
drivers/fpga/{ => dfl}/dfl.c | 0
drivers/fpga/{ => dfl}/dfl.h | 0
24 files changed, 104 insertions(+), 99 deletions(-)
create mode 100644 drivers/fpga/dfl/Kconfig
create mode 100644 drivers/fpga/dfl/Makefile
rename drivers/fpga/{ => dfl}/dfl-afu-dma-region.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu-error.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu-main.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu-region.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu.h (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-br.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-error.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-main.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-mgr.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-perf.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-pr.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-pr.h (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-region.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme.h (100%)
rename drivers/fpga/{ => dfl}/dfl-n3000-nios.c (100%)
rename drivers/fpga/{ => dfl}/dfl-pci.c (100%)
rename drivers/fpga/{ => dfl}/dfl.c (100%)
rename drivers/fpga/{ => dfl}/dfl.h (100%)
diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
index ef9eec71f6f3a..532fdc2e7d623 100644
--- a/Documentation/fpga/dfl.rst
+++ b/Documentation/fpga/dfl.rst
@@ -210,7 +210,7 @@ device and etc. Its driver module is always loaded first once the device is
created by the system. This driver plays an infrastructural role in the
driver architecture. It locates the DFLs in the device memory, handles them
and related resources to common interfaces from DFL framework for enumeration.
-(Please refer to drivers/fpga/dfl.c for detailed enumeration APIs).
+(Please refer to drivers/fpga/dfl/dfl.c for detailed enumeration APIs).
The FPGA Management Engine (FME) driver is a platform driver which is loaded
automatically after FME platform device creation from the DFL device module. It
@@ -499,7 +499,7 @@ In some cases, we may need to add some new private features to existing FIUs
framework, as each private feature will be parsed automatically and related
mmio resources can be found under FIU platform device created by DFL framework.
Developer only needs to provide a sub feature driver with matched feature id.
-FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
+FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl/dfl-fme-pr.c)
could be a reference.
Location of DFLs on a PCI Device
diff --git a/MAINTAINERS b/MAINTAINERS
index 9ae47618c857d..853997f755083 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7244,7 +7244,7 @@ L: linux-fpga@vger.kernel.org
S: Maintained
F: Documentation/ABI/testing/sysfs-bus-dfl*
F: Documentation/fpga/dfl.rst
-F: drivers/fpga/dfl*
+F: drivers/fpga/dfl/
F: drivers/uio/uio_dfl.c
F: include/linux/dfl.h
F: include/uapi/linux/fpga-dfl.h
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 8cd454ee20c0c..7a290b2234576 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -145,85 +145,7 @@ config OF_FPGA_REGION
Support for loading FPGA images by applying a Device Tree
overlay.
-config FPGA_DFL
- tristate "FPGA Device Feature List (DFL) support"
- select FPGA_BRIDGE
- select FPGA_REGION
- depends on HAS_IOMEM
- help
- Device Feature List (DFL) defines a feature list structure that
- creates a linked list of feature headers within the MMIO space
- to provide an extensible way of adding features for FPGA.
- Driver can walk through the feature headers to enumerate feature
- devices (e.g. FPGA Management Engine, Port and Accelerator
- Function Unit) and their private features for target FPGA devices.
-
- Select this option to enable common support for Field-Programmable
- Gate Array (FPGA) solutions which implement Device Feature List.
- It provides enumeration APIs and feature device infrastructure.
-
-config FPGA_DFL_FME
- tristate "FPGA DFL FME Driver"
- depends on FPGA_DFL && HWMON && PERF_EVENTS
- help
- The FPGA Management Engine (FME) is a feature device implemented
- under Device Feature List (DFL) framework. Select this option to
- enable the platform device driver for FME which implements all
- FPGA platform level management features. There shall be one FME
- per DFL based FPGA device.
-
-config FPGA_DFL_FME_MGR
- tristate "FPGA DFL FME Manager Driver"
- depends on FPGA_DFL_FME && HAS_IOMEM
- help
- Say Y to enable FPGA Manager driver for FPGA Management Engine.
-
-config FPGA_DFL_FME_BRIDGE
- tristate "FPGA DFL FME Bridge Driver"
- depends on FPGA_DFL_FME && HAS_IOMEM
- help
- Say Y to enable FPGA Bridge driver for FPGA Management Engine.
-
-config FPGA_DFL_FME_REGION
- tristate "FPGA DFL FME Region Driver"
- depends on FPGA_DFL_FME && HAS_IOMEM
- help
- Say Y to enable FPGA Region driver for FPGA Management Engine.
-
-config FPGA_DFL_AFU
- tristate "FPGA DFL AFU Driver"
- depends on FPGA_DFL
- help
- This is the driver for FPGA Accelerated Function Unit (AFU) which
- implements AFU and Port management features. A User AFU connects
- to the FPGA infrastructure via a Port. There may be more than one
- Port/AFU per DFL based FPGA device.
-
-config FPGA_DFL_NIOS_INTEL_PAC_N3000
- tristate "FPGA DFL NIOS Driver for Intel PAC N3000"
- depends on FPGA_DFL
- select REGMAP
- help
- This is the driver for the N3000 Nios private feature on Intel
- PAC (Programmable Acceleration Card) N3000. It communicates
- with the embedded Nios processor to configure the retimers on
- the card. It also instantiates the SPI master (spi-altera) for
- the card's BMC (Board Management Controller).
-
-config FPGA_DFL_PCI
- tristate "FPGA DFL PCIe Device Driver"
- depends on PCI && FPGA_DFL
- help
- Select this option to enable PCIe driver for PCIe-based
- Field-Programmable Gate Array (FPGA) solutions which implement
- the Device Feature List (DFL). This driver provides interfaces
- for userspace applications to configure, enumerate, open and access
- FPGA accelerators on the FPGA DFL devices, enables system level
- management functions such as FPGA partial reconfiguration, power
- management and virtualization with DFL framework and DFL feature
- device drivers.
-
- To compile this as a module, choose M here.
+source "drivers/fpga/dfl/Kconfig"
config FPGA_MGR_ZYNQMP_FPGA
tristate "Xilinx ZynqMP FPGA"
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 18dc9885883a2..bda74e54ce390 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -31,20 +31,4 @@ obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
obj-$(CONFIG_FPGA_REGION) += fpga-region.o
obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
-# FPGA Device Feature List Support
-obj-$(CONFIG_FPGA_DFL) += dfl.o
-obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o
-obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o
-obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o
-obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o
-obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o
-
-dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o
-dfl-fme-objs += dfl-fme-perf.o
-dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o
-dfl-afu-objs += dfl-afu-error.o
-
-obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o
-
-# Drivers for FPGAs which implement DFL
-obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
+obj-$(CONFIG_FPGA_DFL) += dfl/
diff --git a/drivers/fpga/dfl/Kconfig b/drivers/fpga/dfl/Kconfig
new file mode 100644
index 0000000000000..4c95e9072db46
--- /dev/null
+++ b/drivers/fpga/dfl/Kconfig
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config FPGA_DFL
+ tristate "FPGA Device Feature List (DFL) support"
+ select FPGA_BRIDGE
+ select FPGA_REGION
+ depends on HAS_IOMEM
+ help
+ Device Feature List (DFL) defines a feature list structure that
+ creates a linked list of feature headers within the MMIO space
+ to provide an extensible way of adding features for FPGA.
+ Driver can walk through the feature headers to enumerate feature
+ devices (e.g. FPGA Management Engine, Port and Accelerator
+ Function Unit) and their private features for target FPGA devices.
+
+ Select this option to enable common support for Field-Programmable
+ Gate Array (FPGA) solutions which implement Device Feature List.
+ It provides enumeration APIs and feature device infrastructure.
+
+if FPGA_DFL
+
+config FPGA_DFL_FME
+ tristate "FPGA DFL FME Driver"
+ depends on HWMON && PERF_EVENTS
+ help
+ The FPGA Management Engine (FME) is a feature device implemented
+ under Device Feature List (DFL) framework. Select this option to
+ enable the platform device driver for FME which implements all
+ FPGA platform level management features. There shall be one FME
+ per DFL based FPGA device.
+
+config FPGA_DFL_FME_MGR
+ tristate "FPGA DFL FME Manager Driver"
+ depends on FPGA_DFL_FME && HAS_IOMEM
+ help
+ Say Y to enable FPGA Manager driver for FPGA Management Engine.
+
+config FPGA_DFL_FME_BRIDGE
+ tristate "FPGA DFL FME Bridge Driver"
+ depends on FPGA_DFL_FME && HAS_IOMEM
+ help
+ Say Y to enable FPGA Bridge driver for FPGA Management Engine.
+
+config FPGA_DFL_FME_REGION
+ tristate "FPGA DFL FME Region Driver"
+ depends on FPGA_DFL_FME && HAS_IOMEM
+ help
+ Say Y to enable FPGA Region driver for FPGA Management Engine.
+
+config FPGA_DFL_AFU
+ tristate "FPGA DFL AFU Driver"
+ help
+ This is the driver for FPGA Accelerated Function Unit (AFU) which
+ implements AFU and Port management features. A User AFU connects
+ to the FPGA infrastructure via a Port. There may be more than one
+ Port/AFU per DFL based FPGA device.
+
+config FPGA_DFL_NIOS_INTEL_PAC_N3000
+ tristate "FPGA DFL NIOS Driver for Intel PAC N3000"
+ select REGMAP
+ help
+ This is the driver for the N3000 Nios private feature on Intel
+ PAC (Programmable Acceleration Card) N3000. It communicates
+ with the embedded Nios processor to configure the retimers on
+ the card. It also instantiates the SPI master (spi-altera) for
+ the card's BMC (Board Management Controller).
+
+config FPGA_DFL_PCI
+ tristate "FPGA DFL PCIe Device Driver"
+ depends on PCI
+ help
+ Select this option to enable PCIe driver for PCIe-based
+ Field-Programmable Gate Array (FPGA) solutions which implement
+ the Device Feature List (DFL). This driver provides interfaces
+ for userspace applications to configure, enumerate, open and access
+ FPGA accelerators on the FPGA DFL devices, enables system level
+ management functions such as FPGA partial reconfiguration, power
+ management and virtualization with DFL framework and DFL feature
+ device drivers.
+
+ To compile this as a module, choose M here.
+
+endif #FPGA_DFL
diff --git a/drivers/fpga/dfl/Makefile b/drivers/fpga/dfl/Makefile
new file mode 100644
index 0000000000000..1c22507c60aa0
--- /dev/null
+++ b/drivers/fpga/dfl/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# FPGA Device Feature List (DFL) Support
+obj-$(CONFIG_FPGA_DFL) += dfl.o
+obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o
+obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o
+obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o
+obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o
+obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o
+obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o
+obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
+
+dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o \
+ dfl-fme-perf.o
+dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o \
+ dfl-afu-error.o
diff --git a/drivers/fpga/dfl-afu-dma-region.c b/drivers/fpga/dfl/dfl-afu-dma-region.c
similarity index 100%
rename from drivers/fpga/dfl-afu-dma-region.c
rename to drivers/fpga/dfl/dfl-afu-dma-region.c
diff --git a/drivers/fpga/dfl-afu-error.c b/drivers/fpga/dfl/dfl-afu-error.c
similarity index 100%
rename from drivers/fpga/dfl-afu-error.c
rename to drivers/fpga/dfl/dfl-afu-error.c
diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl/dfl-afu-main.c
similarity index 100%
rename from drivers/fpga/dfl-afu-main.c
rename to drivers/fpga/dfl/dfl-afu-main.c
diff --git a/drivers/fpga/dfl-afu-region.c b/drivers/fpga/dfl/dfl-afu-region.c
similarity index 100%
rename from drivers/fpga/dfl-afu-region.c
rename to drivers/fpga/dfl/dfl-afu-region.c
diff --git a/drivers/fpga/dfl-afu.h b/drivers/fpga/dfl/dfl-afu.h
similarity index 100%
rename from drivers/fpga/dfl-afu.h
rename to drivers/fpga/dfl/dfl-afu.h
diff --git a/drivers/fpga/dfl-fme-br.c b/drivers/fpga/dfl/dfl-fme-br.c
similarity index 100%
rename from drivers/fpga/dfl-fme-br.c
rename to drivers/fpga/dfl/dfl-fme-br.c
diff --git a/drivers/fpga/dfl-fme-error.c b/drivers/fpga/dfl/dfl-fme-error.c
similarity index 100%
rename from drivers/fpga/dfl-fme-error.c
rename to drivers/fpga/dfl/dfl-fme-error.c
diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl/dfl-fme-main.c
similarity index 100%
rename from drivers/fpga/dfl-fme-main.c
rename to drivers/fpga/dfl/dfl-fme-main.c
diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl/dfl-fme-mgr.c
similarity index 100%
rename from drivers/fpga/dfl-fme-mgr.c
rename to drivers/fpga/dfl/dfl-fme-mgr.c
diff --git a/drivers/fpga/dfl-fme-perf.c b/drivers/fpga/dfl/dfl-fme-perf.c
similarity index 100%
rename from drivers/fpga/dfl-fme-perf.c
rename to drivers/fpga/dfl/dfl-fme-perf.c
diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl/dfl-fme-pr.c
similarity index 100%
rename from drivers/fpga/dfl-fme-pr.c
rename to drivers/fpga/dfl/dfl-fme-pr.c
diff --git a/drivers/fpga/dfl-fme-pr.h b/drivers/fpga/dfl/dfl-fme-pr.h
similarity index 100%
rename from drivers/fpga/dfl-fme-pr.h
rename to drivers/fpga/dfl/dfl-fme-pr.h
diff --git a/drivers/fpga/dfl-fme-region.c b/drivers/fpga/dfl/dfl-fme-region.c
similarity index 100%
rename from drivers/fpga/dfl-fme-region.c
rename to drivers/fpga/dfl/dfl-fme-region.c
diff --git a/drivers/fpga/dfl-fme.h b/drivers/fpga/dfl/dfl-fme.h
similarity index 100%
rename from drivers/fpga/dfl-fme.h
rename to drivers/fpga/dfl/dfl-fme.h
diff --git a/drivers/fpga/dfl-n3000-nios.c b/drivers/fpga/dfl/dfl-n3000-nios.c
similarity index 100%
rename from drivers/fpga/dfl-n3000-nios.c
rename to drivers/fpga/dfl/dfl-n3000-nios.c
diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl/dfl-pci.c
similarity index 100%
rename from drivers/fpga/dfl-pci.c
rename to drivers/fpga/dfl/dfl-pci.c
diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl/dfl.c
similarity index 100%
rename from drivers/fpga/dfl.c
rename to drivers/fpga/dfl/dfl.c
diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl/dfl.h
similarity index 100%
rename from drivers/fpga/dfl.h
rename to drivers/fpga/dfl/dfl.h
--
2.26.3
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v5 1/4] fpga: dfl: reorganize to subdir layout
@ 2021-06-22 20:05 ` trix
0 siblings, 0 replies; 15+ messages in thread
From: trix @ 2021-06-22 20:05 UTC (permalink / raw)
To: hao.wu, mdf, corbet, michal.simek, gregkh, nava.manne, dinguyen,
krzysztof.kozlowski, yilun.xu, davidgow, fpacheco,
russell.h.weight, richard.gong, luca
Cc: linux-fpga, linux-doc, linux-kernel, linux-arm-kernel, Tom Rix
From: Tom Rix <trix@redhat.com>
Follow drivers/net/ethernet/ which has control configs
NET_VENDOR_BLA that map to drivers/net/ethernet/bla
Since fpgas do not have many vendors, drop the 'VENDOR' and use
FPGA_BLA.
There are several new subdirs
altera/
dfl/
lattice/
xilinx/
Each subdir has a Kconfig that has a new/reused
if FPGA_BLA
... existing configs ...
endif FPGA_BLA
Which is sourced into the main fpga/Kconfig
Each subdir has a Makefile whose transversal is controlled in the
fpga/Makefile by
obj-$(CONFIG_FPGA_BLA) += bla/
This is the dfl/ subdir part.
Create a dfl/ subdir
Move dfl-* files to it.
Add a Kconfig and Makefile
Because FPGA_DFL is now used in dfl/Kconfig in a if/endif
block, all the other configs in dfl/Kconfig implicitly depend
on FPGA_DFL.
Signed-off-by: Tom Rix <trix@redhat.com>
---
Documentation/fpga/dfl.rst | 4 +-
MAINTAINERS | 2 +-
drivers/fpga/Kconfig | 80 +-------------------
drivers/fpga/Makefile | 18 +----
drivers/fpga/dfl/Kconfig | 83 +++++++++++++++++++++
drivers/fpga/dfl/Makefile | 16 ++++
drivers/fpga/{ => dfl}/dfl-afu-dma-region.c | 0
drivers/fpga/{ => dfl}/dfl-afu-error.c | 0
drivers/fpga/{ => dfl}/dfl-afu-main.c | 0
drivers/fpga/{ => dfl}/dfl-afu-region.c | 0
drivers/fpga/{ => dfl}/dfl-afu.h | 0
drivers/fpga/{ => dfl}/dfl-fme-br.c | 0
drivers/fpga/{ => dfl}/dfl-fme-error.c | 0
drivers/fpga/{ => dfl}/dfl-fme-main.c | 0
drivers/fpga/{ => dfl}/dfl-fme-mgr.c | 0
drivers/fpga/{ => dfl}/dfl-fme-perf.c | 0
drivers/fpga/{ => dfl}/dfl-fme-pr.c | 0
drivers/fpga/{ => dfl}/dfl-fme-pr.h | 0
drivers/fpga/{ => dfl}/dfl-fme-region.c | 0
drivers/fpga/{ => dfl}/dfl-fme.h | 0
drivers/fpga/{ => dfl}/dfl-n3000-nios.c | 0
drivers/fpga/{ => dfl}/dfl-pci.c | 0
drivers/fpga/{ => dfl}/dfl.c | 0
drivers/fpga/{ => dfl}/dfl.h | 0
24 files changed, 104 insertions(+), 99 deletions(-)
create mode 100644 drivers/fpga/dfl/Kconfig
create mode 100644 drivers/fpga/dfl/Makefile
rename drivers/fpga/{ => dfl}/dfl-afu-dma-region.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu-error.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu-main.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu-region.c (100%)
rename drivers/fpga/{ => dfl}/dfl-afu.h (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-br.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-error.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-main.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-mgr.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-perf.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-pr.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-pr.h (100%)
rename drivers/fpga/{ => dfl}/dfl-fme-region.c (100%)
rename drivers/fpga/{ => dfl}/dfl-fme.h (100%)
rename drivers/fpga/{ => dfl}/dfl-n3000-nios.c (100%)
rename drivers/fpga/{ => dfl}/dfl-pci.c (100%)
rename drivers/fpga/{ => dfl}/dfl.c (100%)
rename drivers/fpga/{ => dfl}/dfl.h (100%)
diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
index ef9eec71f6f3a..532fdc2e7d623 100644
--- a/Documentation/fpga/dfl.rst
+++ b/Documentation/fpga/dfl.rst
@@ -210,7 +210,7 @@ device and etc. Its driver module is always loaded first once the device is
created by the system. This driver plays an infrastructural role in the
driver architecture. It locates the DFLs in the device memory, handles them
and related resources to common interfaces from DFL framework for enumeration.
-(Please refer to drivers/fpga/dfl.c for detailed enumeration APIs).
+(Please refer to drivers/fpga/dfl/dfl.c for detailed enumeration APIs).
The FPGA Management Engine (FME) driver is a platform driver which is loaded
automatically after FME platform device creation from the DFL device module. It
@@ -499,7 +499,7 @@ In some cases, we may need to add some new private features to existing FIUs
framework, as each private feature will be parsed automatically and related
mmio resources can be found under FIU platform device created by DFL framework.
Developer only needs to provide a sub feature driver with matched feature id.
-FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
+FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl/dfl-fme-pr.c)
could be a reference.
Location of DFLs on a PCI Device
diff --git a/MAINTAINERS b/MAINTAINERS
index 9ae47618c857d..853997f755083 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7244,7 +7244,7 @@ L: linux-fpga@vger.kernel.org
S: Maintained
F: Documentation/ABI/testing/sysfs-bus-dfl*
F: Documentation/fpga/dfl.rst
-F: drivers/fpga/dfl*
+F: drivers/fpga/dfl/
F: drivers/uio/uio_dfl.c
F: include/linux/dfl.h
F: include/uapi/linux/fpga-dfl.h
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 8cd454ee20c0c..7a290b2234576 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -145,85 +145,7 @@ config OF_FPGA_REGION
Support for loading FPGA images by applying a Device Tree
overlay.
-config FPGA_DFL
- tristate "FPGA Device Feature List (DFL) support"
- select FPGA_BRIDGE
- select FPGA_REGION
- depends on HAS_IOMEM
- help
- Device Feature List (DFL) defines a feature list structure that
- creates a linked list of feature headers within the MMIO space
- to provide an extensible way of adding features for FPGA.
- Driver can walk through the feature headers to enumerate feature
- devices (e.g. FPGA Management Engine, Port and Accelerator
- Function Unit) and their private features for target FPGA devices.
-
- Select this option to enable common support for Field-Programmable
- Gate Array (FPGA) solutions which implement Device Feature List.
- It provides enumeration APIs and feature device infrastructure.
-
-config FPGA_DFL_FME
- tristate "FPGA DFL FME Driver"
- depends on FPGA_DFL && HWMON && PERF_EVENTS
- help
- The FPGA Management Engine (FME) is a feature device implemented
- under Device Feature List (DFL) framework. Select this option to
- enable the platform device driver for FME which implements all
- FPGA platform level management features. There shall be one FME
- per DFL based FPGA device.
-
-config FPGA_DFL_FME_MGR
- tristate "FPGA DFL FME Manager Driver"
- depends on FPGA_DFL_FME && HAS_IOMEM
- help
- Say Y to enable FPGA Manager driver for FPGA Management Engine.
-
-config FPGA_DFL_FME_BRIDGE
- tristate "FPGA DFL FME Bridge Driver"
- depends on FPGA_DFL_FME && HAS_IOMEM
- help
- Say Y to enable FPGA Bridge driver for FPGA Management Engine.
-
-config FPGA_DFL_FME_REGION
- tristate "FPGA DFL FME Region Driver"
- depends on FPGA_DFL_FME && HAS_IOMEM
- help
- Say Y to enable FPGA Region driver for FPGA Management Engine.
-
-config FPGA_DFL_AFU
- tristate "FPGA DFL AFU Driver"
- depends on FPGA_DFL
- help
- This is the driver for FPGA Accelerated Function Unit (AFU) which
- implements AFU and Port management features. A User AFU connects
- to the FPGA infrastructure via a Port. There may be more than one
- Port/AFU per DFL based FPGA device.
-
-config FPGA_DFL_NIOS_INTEL_PAC_N3000
- tristate "FPGA DFL NIOS Driver for Intel PAC N3000"
- depends on FPGA_DFL
- select REGMAP
- help
- This is the driver for the N3000 Nios private feature on Intel
- PAC (Programmable Acceleration Card) N3000. It communicates
- with the embedded Nios processor to configure the retimers on
- the card. It also instantiates the SPI master (spi-altera) for
- the card's BMC (Board Management Controller).
-
-config FPGA_DFL_PCI
- tristate "FPGA DFL PCIe Device Driver"
- depends on PCI && FPGA_DFL
- help
- Select this option to enable PCIe driver for PCIe-based
- Field-Programmable Gate Array (FPGA) solutions which implement
- the Device Feature List (DFL). This driver provides interfaces
- for userspace applications to configure, enumerate, open and access
- FPGA accelerators on the FPGA DFL devices, enables system level
- management functions such as FPGA partial reconfiguration, power
- management and virtualization with DFL framework and DFL feature
- device drivers.
-
- To compile this as a module, choose M here.
+source "drivers/fpga/dfl/Kconfig"
config FPGA_MGR_ZYNQMP_FPGA
tristate "Xilinx ZynqMP FPGA"
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 18dc9885883a2..bda74e54ce390 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -31,20 +31,4 @@ obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
obj-$(CONFIG_FPGA_REGION) += fpga-region.o
obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
-# FPGA Device Feature List Support
-obj-$(CONFIG_FPGA_DFL) += dfl.o
-obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o
-obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o
-obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o
-obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o
-obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o
-
-dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o
-dfl-fme-objs += dfl-fme-perf.o
-dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o
-dfl-afu-objs += dfl-afu-error.o
-
-obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o
-
-# Drivers for FPGAs which implement DFL
-obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
+obj-$(CONFIG_FPGA_DFL) += dfl/
diff --git a/drivers/fpga/dfl/Kconfig b/drivers/fpga/dfl/Kconfig
new file mode 100644
index 0000000000000..4c95e9072db46
--- /dev/null
+++ b/drivers/fpga/dfl/Kconfig
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config FPGA_DFL
+ tristate "FPGA Device Feature List (DFL) support"
+ select FPGA_BRIDGE
+ select FPGA_REGION
+ depends on HAS_IOMEM
+ help
+ Device Feature List (DFL) defines a feature list structure that
+ creates a linked list of feature headers within the MMIO space
+ to provide an extensible way of adding features for FPGA.
+ Driver can walk through the feature headers to enumerate feature
+ devices (e.g. FPGA Management Engine, Port and Accelerator
+ Function Unit) and their private features for target FPGA devices.
+
+ Select this option to enable common support for Field-Programmable
+ Gate Array (FPGA) solutions which implement Device Feature List.
+ It provides enumeration APIs and feature device infrastructure.
+
+if FPGA_DFL
+
+config FPGA_DFL_FME
+ tristate "FPGA DFL FME Driver"
+ depends on HWMON && PERF_EVENTS
+ help
+ The FPGA Management Engine (FME) is a feature device implemented
+ under Device Feature List (DFL) framework. Select this option to
+ enable the platform device driver for FME which implements all
+ FPGA platform level management features. There shall be one FME
+ per DFL based FPGA device.
+
+config FPGA_DFL_FME_MGR
+ tristate "FPGA DFL FME Manager Driver"
+ depends on FPGA_DFL_FME && HAS_IOMEM
+ help
+ Say Y to enable FPGA Manager driver for FPGA Management Engine.
+
+config FPGA_DFL_FME_BRIDGE
+ tristate "FPGA DFL FME Bridge Driver"
+ depends on FPGA_DFL_FME && HAS_IOMEM
+ help
+ Say Y to enable FPGA Bridge driver for FPGA Management Engine.
+
+config FPGA_DFL_FME_REGION
+ tristate "FPGA DFL FME Region Driver"
+ depends on FPGA_DFL_FME && HAS_IOMEM
+ help
+ Say Y to enable FPGA Region driver for FPGA Management Engine.
+
+config FPGA_DFL_AFU
+ tristate "FPGA DFL AFU Driver"
+ help
+ This is the driver for FPGA Accelerated Function Unit (AFU) which
+ implements AFU and Port management features. A User AFU connects
+ to the FPGA infrastructure via a Port. There may be more than one
+ Port/AFU per DFL based FPGA device.
+
+config FPGA_DFL_NIOS_INTEL_PAC_N3000
+ tristate "FPGA DFL NIOS Driver for Intel PAC N3000"
+ select REGMAP
+ help
+ This is the driver for the N3000 Nios private feature on Intel
+ PAC (Programmable Acceleration Card) N3000. It communicates
+ with the embedded Nios processor to configure the retimers on
+ the card. It also instantiates the SPI master (spi-altera) for
+ the card's BMC (Board Management Controller).
+
+config FPGA_DFL_PCI
+ tristate "FPGA DFL PCIe Device Driver"
+ depends on PCI
+ help
+ Select this option to enable PCIe driver for PCIe-based
+ Field-Programmable Gate Array (FPGA) solutions which implement
+ the Device Feature List (DFL). This driver provides interfaces
+ for userspace applications to configure, enumerate, open and access
+ FPGA accelerators on the FPGA DFL devices, enables system level
+ management functions such as FPGA partial reconfiguration, power
+ management and virtualization with DFL framework and DFL feature
+ device drivers.
+
+ To compile this as a module, choose M here.
+
+endif #FPGA_DFL
diff --git a/drivers/fpga/dfl/Makefile b/drivers/fpga/dfl/Makefile
new file mode 100644
index 0000000000000..1c22507c60aa0
--- /dev/null
+++ b/drivers/fpga/dfl/Makefile
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# FPGA Device Feature List (DFL) Support
+obj-$(CONFIG_FPGA_DFL) += dfl.o
+obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o
+obj-$(CONFIG_FPGA_DFL_FME) += dfl-fme.o
+obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o
+obj-$(CONFIG_FPGA_DFL_FME_MGR) += dfl-fme-mgr.o
+obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o
+obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o
+obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
+
+dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o \
+ dfl-fme-perf.o
+dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o \
+ dfl-afu-error.o
diff --git a/drivers/fpga/dfl-afu-dma-region.c b/drivers/fpga/dfl/dfl-afu-dma-region.c
similarity index 100%
rename from drivers/fpga/dfl-afu-dma-region.c
rename to drivers/fpga/dfl/dfl-afu-dma-region.c
diff --git a/drivers/fpga/dfl-afu-error.c b/drivers/fpga/dfl/dfl-afu-error.c
similarity index 100%
rename from drivers/fpga/dfl-afu-error.c
rename to drivers/fpga/dfl/dfl-afu-error.c
diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl/dfl-afu-main.c
similarity index 100%
rename from drivers/fpga/dfl-afu-main.c
rename to drivers/fpga/dfl/dfl-afu-main.c
diff --git a/drivers/fpga/dfl-afu-region.c b/drivers/fpga/dfl/dfl-afu-region.c
similarity index 100%
rename from drivers/fpga/dfl-afu-region.c
rename to drivers/fpga/dfl/dfl-afu-region.c
diff --git a/drivers/fpga/dfl-afu.h b/drivers/fpga/dfl/dfl-afu.h
similarity index 100%
rename from drivers/fpga/dfl-afu.h
rename to drivers/fpga/dfl/dfl-afu.h
diff --git a/drivers/fpga/dfl-fme-br.c b/drivers/fpga/dfl/dfl-fme-br.c
similarity index 100%
rename from drivers/fpga/dfl-fme-br.c
rename to drivers/fpga/dfl/dfl-fme-br.c
diff --git a/drivers/fpga/dfl-fme-error.c b/drivers/fpga/dfl/dfl-fme-error.c
similarity index 100%
rename from drivers/fpga/dfl-fme-error.c
rename to drivers/fpga/dfl/dfl-fme-error.c
diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl/dfl-fme-main.c
similarity index 100%
rename from drivers/fpga/dfl-fme-main.c
rename to drivers/fpga/dfl/dfl-fme-main.c
diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl/dfl-fme-mgr.c
similarity index 100%
rename from drivers/fpga/dfl-fme-mgr.c
rename to drivers/fpga/dfl/dfl-fme-mgr.c
diff --git a/drivers/fpga/dfl-fme-perf.c b/drivers/fpga/dfl/dfl-fme-perf.c
similarity index 100%
rename from drivers/fpga/dfl-fme-perf.c
rename to drivers/fpga/dfl/dfl-fme-perf.c
diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl/dfl-fme-pr.c
similarity index 100%
rename from drivers/fpga/dfl-fme-pr.c
rename to drivers/fpga/dfl/dfl-fme-pr.c
diff --git a/drivers/fpga/dfl-fme-pr.h b/drivers/fpga/dfl/dfl-fme-pr.h
similarity index 100%
rename from drivers/fpga/dfl-fme-pr.h
rename to drivers/fpga/dfl/dfl-fme-pr.h
diff --git a/drivers/fpga/dfl-fme-region.c b/drivers/fpga/dfl/dfl-fme-region.c
similarity index 100%
rename from drivers/fpga/dfl-fme-region.c
rename to drivers/fpga/dfl/dfl-fme-region.c
diff --git a/drivers/fpga/dfl-fme.h b/drivers/fpga/dfl/dfl-fme.h
similarity index 100%
rename from drivers/fpga/dfl-fme.h
rename to drivers/fpga/dfl/dfl-fme.h
diff --git a/drivers/fpga/dfl-n3000-nios.c b/drivers/fpga/dfl/dfl-n3000-nios.c
similarity index 100%
rename from drivers/fpga/dfl-n3000-nios.c
rename to drivers/fpga/dfl/dfl-n3000-nios.c
diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl/dfl-pci.c
similarity index 100%
rename from drivers/fpga/dfl-pci.c
rename to drivers/fpga/dfl/dfl-pci.c
diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl/dfl.c
similarity index 100%
rename from drivers/fpga/dfl.c
rename to drivers/fpga/dfl/dfl.c
diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl/dfl.h
similarity index 100%
rename from drivers/fpga/dfl.h
rename to drivers/fpga/dfl/dfl.h
--
2.26.3
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v5 2/4] fpga: xilinx: reorganize to subdir layout
2021-06-22 20:05 ` trix
@ 2021-06-22 20:05 ` trix
-1 siblings, 0 replies; 15+ messages in thread
From: trix @ 2021-06-22 20:05 UTC (permalink / raw)
To: hao.wu, mdf, corbet, michal.simek, gregkh, nava.manne, dinguyen,
krzysztof.kozlowski, yilun.xu, davidgow, fpacheco,
russell.h.weight, richard.gong, luca
Cc: linux-fpga, linux-doc, linux-kernel, linux-arm-kernel, Tom Rix
From: Tom Rix <trix@redhat.com>
Follow drivers/net/ethernet/ which has control configs
NET_VENDOR_BLA that map to drivers/net/ethernet/bla
Since fpgas do not have many vendors, drop the 'VENDOR' and use
FPGA_BLA.
There are several new subdirs
altera/
dfl/
lattice/
xilinx/
Each subdir has a Kconfig that has a new/reused
if FPGA_BLA
... existing configs ...
endif FPGA_BLA
Which is sourced into the main fpga/Kconfig
Each subdir has a Makefile whose transversal is controlled in the
fpga/Makefile by
obj-$(CONFIG_FPGA_BLA) += bla/
This is the xilinx/ subdir part
Create a xilinx/ subdir
Move xilinx-* and zynq* files to it.
Add a Kconfig and Makefile
Signed-off-by: Tom Rix <trix@redhat.com>
---
drivers/fpga/Kconfig | 40 +-------------
drivers/fpga/Makefile | 5 +-
drivers/fpga/xilinx/Kconfig | 55 +++++++++++++++++++
drivers/fpga/xilinx/Makefile | 6 ++
.../fpga/{ => xilinx}/xilinx-pr-decoupler.c | 0
drivers/fpga/{ => xilinx}/xilinx-spi.c | 0
drivers/fpga/{ => xilinx}/zynq-fpga.c | 0
drivers/fpga/{ => xilinx}/zynqmp-fpga.c | 0
8 files changed, 63 insertions(+), 43 deletions(-)
create mode 100644 drivers/fpga/xilinx/Kconfig
create mode 100644 drivers/fpga/xilinx/Makefile
rename drivers/fpga/{ => xilinx}/xilinx-pr-decoupler.c (100%)
rename drivers/fpga/{ => xilinx}/xilinx-spi.c (100%)
rename drivers/fpga/{ => xilinx}/zynq-fpga.c (100%)
rename drivers/fpga/{ => xilinx}/zynqmp-fpga.c (100%)
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 7a290b2234576..28c261807b428 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -52,25 +52,12 @@ config FPGA_MGR_ALTERA_CVP
FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
-config FPGA_MGR_ZYNQ_FPGA
- tristate "Xilinx Zynq FPGA"
- depends on ARCH_ZYNQ || COMPILE_TEST
- help
- FPGA manager driver support for Xilinx Zynq FPGAs.
-
config FPGA_MGR_STRATIX10_SOC
tristate "Intel Stratix10 SoC FPGA Manager"
depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE)
help
FPGA manager driver support for the Intel Stratix10 SoC.
-config FPGA_MGR_XILINX_SPI
- tristate "Xilinx Configuration over Slave Serial (SPI)"
- depends on SPI
- help
- FPGA manager driver support for Xilinx FPGA configuration
- over slave serial interface.
-
config FPGA_MGR_ICE40_SPI
tristate "Lattice iCE40 SPI"
depends on OF && SPI
@@ -113,23 +100,6 @@ config ALTERA_FREEZE_BRIDGE
isolate one region of the FPGA from the busses while that
region is being reprogrammed.
-config XILINX_PR_DECOUPLER
- tristate "Xilinx LogiCORE PR Decoupler"
- depends on FPGA_BRIDGE
- depends on HAS_IOMEM
- help
- Say Y to enable drivers for Xilinx LogiCORE PR Decoupler
- or Xilinx Dynamic Function eXchnage AIX Shutdown Manager.
- The PR Decoupler exists in the FPGA fabric to isolate one
- region of the FPGA from the busses while that region is
- being reprogrammed during partial reconfig.
- The Dynamic Function eXchange AXI shutdown manager prevents
- AXI traffic from passing through the bridge. The controller
- safely handles AXI4MM and AXI4-Lite interfaces on a
- Reconfigurable Partition when it is undergoing dynamic
- reconfiguration, preventing the system deadlock that can
- occur if AXI transactions are interrupted by DFX.
-
config FPGA_REGION
tristate "FPGA Region"
depends on FPGA_BRIDGE
@@ -146,14 +116,6 @@ config OF_FPGA_REGION
overlay.
source "drivers/fpga/dfl/Kconfig"
-
-config FPGA_MGR_ZYNQMP_FPGA
- tristate "Xilinx ZynqMP FPGA"
- depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
- help
- FPGA manager driver support for Xilinx ZynqMP FPGAs.
- This driver uses the processor configuration port(PCAP)
- to configure the programmable logic(PL) through PS
- on ZynqMP SoC.
+source "drivers/fpga/xilinx/Kconfig"
endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index bda74e54ce390..0868c7c4264d8 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -15,9 +15,6 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o
obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
-obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
-obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
-obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
@@ -25,10 +22,10 @@ obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
-obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
# High Level Interfaces
obj-$(CONFIG_FPGA_REGION) += fpga-region.o
obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
obj-$(CONFIG_FPGA_DFL) += dfl/
+obj-$(CONFIG_FPGA_XILINX) += xilinx/
diff --git a/drivers/fpga/xilinx/Kconfig b/drivers/fpga/xilinx/Kconfig
new file mode 100644
index 0000000000000..b907f9793195c
--- /dev/null
+++ b/drivers/fpga/xilinx/Kconfig
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config FPGA_XILINX
+ bool "Xilinx FPGAs"
+ default y
+ help
+ If you have a Xilinx FPGA, say Y.
+
+ Note that the answer to this question doesn't directly affect the
+ kernel: saying N will just cause the configurator to skip all
+ the questions about Xilinx FPGAs. If you say Y, you will be asked
+ for your specific device in the following questions.
+
+if FPGA_XILINX
+
+config FPGA_MGR_ZYNQ_FPGA
+ tristate "Xilinx Zynq FPGA"
+ depends on ARCH_ZYNQ || COMPILE_TEST
+ help
+ FPGA manager driver support for Xilinx Zynq FPGAs.
+
+config FPGA_MGR_ZYNQMP_FPGA
+ tristate "Xilinx ZynqMP FPGA"
+ depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
+ help
+ FPGA manager driver support for Xilinx ZynqMP FPGAs.
+ This driver uses the processor configuration port(PCAP)
+ to configure the programmable logic(PL) through PS
+ on ZynqMP SoC.
+
+config XILINX_PR_DECOUPLER
+ tristate "Xilinx LogiCORE PR Decoupler"
+ depends on FPGA_BRIDGE
+ depends on HAS_IOMEM
+ help
+ Say Y to enable drivers for Xilinx LogiCORE PR Decoupler
+ or Xilinx Dynamic Function eXchnage AIX Shutdown Manager.
+ The PR Decoupler exists in the FPGA fabric to isolate one
+ region of the FPGA from the busses while that region is
+ being reprogrammed during partial reconfig.
+ The Dynamic Function eXchange AXI shutdown manager prevents
+ AXI traffic from passing through the bridge. The controller
+ safely handles AXI4MM and AXI4-Lite interfaces on a
+ Reconfigurable Partition when it is undergoing dynamic
+ reconfiguration, preventing the system deadlock that can
+ occur if AXI transactions are interrupted by DFX.
+
+config FPGA_MGR_XILINX_SPI
+ tristate "Xilinx Configuration over Slave Serial (SPI)"
+ depends on SPI
+ help
+ FPGA manager driver support for Xilinx FPGA configuration
+ over slave serial interface.
+
+endif #FPGA_XILINX
diff --git a/drivers/fpga/xilinx/Makefile b/drivers/fpga/xilinx/Makefile
new file mode 100644
index 0000000000000..2361aa14eb549
--- /dev/null
+++ b/drivers/fpga/xilinx/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
+obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
+obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
+obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
diff --git a/drivers/fpga/xilinx-pr-decoupler.c b/drivers/fpga/xilinx/xilinx-pr-decoupler.c
similarity index 100%
rename from drivers/fpga/xilinx-pr-decoupler.c
rename to drivers/fpga/xilinx/xilinx-pr-decoupler.c
diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx/xilinx-spi.c
similarity index 100%
rename from drivers/fpga/xilinx-spi.c
rename to drivers/fpga/xilinx/xilinx-spi.c
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/xilinx/zynq-fpga.c
similarity index 100%
rename from drivers/fpga/zynq-fpga.c
rename to drivers/fpga/xilinx/zynq-fpga.c
diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/xilinx/zynqmp-fpga.c
similarity index 100%
rename from drivers/fpga/zynqmp-fpga.c
rename to drivers/fpga/xilinx/zynqmp-fpga.c
--
2.26.3
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v5 2/4] fpga: xilinx: reorganize to subdir layout
@ 2021-06-22 20:05 ` trix
0 siblings, 0 replies; 15+ messages in thread
From: trix @ 2021-06-22 20:05 UTC (permalink / raw)
To: hao.wu, mdf, corbet, michal.simek, gregkh, nava.manne, dinguyen,
krzysztof.kozlowski, yilun.xu, davidgow, fpacheco,
russell.h.weight, richard.gong, luca
Cc: linux-fpga, linux-doc, linux-kernel, linux-arm-kernel, Tom Rix
From: Tom Rix <trix@redhat.com>
Follow drivers/net/ethernet/ which has control configs
NET_VENDOR_BLA that map to drivers/net/ethernet/bla
Since fpgas do not have many vendors, drop the 'VENDOR' and use
FPGA_BLA.
There are several new subdirs
altera/
dfl/
lattice/
xilinx/
Each subdir has a Kconfig that has a new/reused
if FPGA_BLA
... existing configs ...
endif FPGA_BLA
Which is sourced into the main fpga/Kconfig
Each subdir has a Makefile whose transversal is controlled in the
fpga/Makefile by
obj-$(CONFIG_FPGA_BLA) += bla/
This is the xilinx/ subdir part
Create a xilinx/ subdir
Move xilinx-* and zynq* files to it.
Add a Kconfig and Makefile
Signed-off-by: Tom Rix <trix@redhat.com>
---
drivers/fpga/Kconfig | 40 +-------------
drivers/fpga/Makefile | 5 +-
drivers/fpga/xilinx/Kconfig | 55 +++++++++++++++++++
drivers/fpga/xilinx/Makefile | 6 ++
.../fpga/{ => xilinx}/xilinx-pr-decoupler.c | 0
drivers/fpga/{ => xilinx}/xilinx-spi.c | 0
drivers/fpga/{ => xilinx}/zynq-fpga.c | 0
drivers/fpga/{ => xilinx}/zynqmp-fpga.c | 0
8 files changed, 63 insertions(+), 43 deletions(-)
create mode 100644 drivers/fpga/xilinx/Kconfig
create mode 100644 drivers/fpga/xilinx/Makefile
rename drivers/fpga/{ => xilinx}/xilinx-pr-decoupler.c (100%)
rename drivers/fpga/{ => xilinx}/xilinx-spi.c (100%)
rename drivers/fpga/{ => xilinx}/zynq-fpga.c (100%)
rename drivers/fpga/{ => xilinx}/zynqmp-fpga.c (100%)
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 7a290b2234576..28c261807b428 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -52,25 +52,12 @@ config FPGA_MGR_ALTERA_CVP
FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
-config FPGA_MGR_ZYNQ_FPGA
- tristate "Xilinx Zynq FPGA"
- depends on ARCH_ZYNQ || COMPILE_TEST
- help
- FPGA manager driver support for Xilinx Zynq FPGAs.
-
config FPGA_MGR_STRATIX10_SOC
tristate "Intel Stratix10 SoC FPGA Manager"
depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE)
help
FPGA manager driver support for the Intel Stratix10 SoC.
-config FPGA_MGR_XILINX_SPI
- tristate "Xilinx Configuration over Slave Serial (SPI)"
- depends on SPI
- help
- FPGA manager driver support for Xilinx FPGA configuration
- over slave serial interface.
-
config FPGA_MGR_ICE40_SPI
tristate "Lattice iCE40 SPI"
depends on OF && SPI
@@ -113,23 +100,6 @@ config ALTERA_FREEZE_BRIDGE
isolate one region of the FPGA from the busses while that
region is being reprogrammed.
-config XILINX_PR_DECOUPLER
- tristate "Xilinx LogiCORE PR Decoupler"
- depends on FPGA_BRIDGE
- depends on HAS_IOMEM
- help
- Say Y to enable drivers for Xilinx LogiCORE PR Decoupler
- or Xilinx Dynamic Function eXchnage AIX Shutdown Manager.
- The PR Decoupler exists in the FPGA fabric to isolate one
- region of the FPGA from the busses while that region is
- being reprogrammed during partial reconfig.
- The Dynamic Function eXchange AXI shutdown manager prevents
- AXI traffic from passing through the bridge. The controller
- safely handles AXI4MM and AXI4-Lite interfaces on a
- Reconfigurable Partition when it is undergoing dynamic
- reconfiguration, preventing the system deadlock that can
- occur if AXI transactions are interrupted by DFX.
-
config FPGA_REGION
tristate "FPGA Region"
depends on FPGA_BRIDGE
@@ -146,14 +116,6 @@ config OF_FPGA_REGION
overlay.
source "drivers/fpga/dfl/Kconfig"
-
-config FPGA_MGR_ZYNQMP_FPGA
- tristate "Xilinx ZynqMP FPGA"
- depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
- help
- FPGA manager driver support for Xilinx ZynqMP FPGAs.
- This driver uses the processor configuration port(PCAP)
- to configure the programmable logic(PL) through PS
- on ZynqMP SoC.
+source "drivers/fpga/xilinx/Kconfig"
endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index bda74e54ce390..0868c7c4264d8 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -15,9 +15,6 @@ obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o
obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
-obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
-obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
-obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
@@ -25,10 +22,10 @@ obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
-obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
# High Level Interfaces
obj-$(CONFIG_FPGA_REGION) += fpga-region.o
obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
obj-$(CONFIG_FPGA_DFL) += dfl/
+obj-$(CONFIG_FPGA_XILINX) += xilinx/
diff --git a/drivers/fpga/xilinx/Kconfig b/drivers/fpga/xilinx/Kconfig
new file mode 100644
index 0000000000000..b907f9793195c
--- /dev/null
+++ b/drivers/fpga/xilinx/Kconfig
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config FPGA_XILINX
+ bool "Xilinx FPGAs"
+ default y
+ help
+ If you have a Xilinx FPGA, say Y.
+
+ Note that the answer to this question doesn't directly affect the
+ kernel: saying N will just cause the configurator to skip all
+ the questions about Xilinx FPGAs. If you say Y, you will be asked
+ for your specific device in the following questions.
+
+if FPGA_XILINX
+
+config FPGA_MGR_ZYNQ_FPGA
+ tristate "Xilinx Zynq FPGA"
+ depends on ARCH_ZYNQ || COMPILE_TEST
+ help
+ FPGA manager driver support for Xilinx Zynq FPGAs.
+
+config FPGA_MGR_ZYNQMP_FPGA
+ tristate "Xilinx ZynqMP FPGA"
+ depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
+ help
+ FPGA manager driver support for Xilinx ZynqMP FPGAs.
+ This driver uses the processor configuration port(PCAP)
+ to configure the programmable logic(PL) through PS
+ on ZynqMP SoC.
+
+config XILINX_PR_DECOUPLER
+ tristate "Xilinx LogiCORE PR Decoupler"
+ depends on FPGA_BRIDGE
+ depends on HAS_IOMEM
+ help
+ Say Y to enable drivers for Xilinx LogiCORE PR Decoupler
+ or Xilinx Dynamic Function eXchnage AIX Shutdown Manager.
+ The PR Decoupler exists in the FPGA fabric to isolate one
+ region of the FPGA from the busses while that region is
+ being reprogrammed during partial reconfig.
+ The Dynamic Function eXchange AXI shutdown manager prevents
+ AXI traffic from passing through the bridge. The controller
+ safely handles AXI4MM and AXI4-Lite interfaces on a
+ Reconfigurable Partition when it is undergoing dynamic
+ reconfiguration, preventing the system deadlock that can
+ occur if AXI transactions are interrupted by DFX.
+
+config FPGA_MGR_XILINX_SPI
+ tristate "Xilinx Configuration over Slave Serial (SPI)"
+ depends on SPI
+ help
+ FPGA manager driver support for Xilinx FPGA configuration
+ over slave serial interface.
+
+endif #FPGA_XILINX
diff --git a/drivers/fpga/xilinx/Makefile b/drivers/fpga/xilinx/Makefile
new file mode 100644
index 0000000000000..2361aa14eb549
--- /dev/null
+++ b/drivers/fpga/xilinx/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
+obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
+obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
+obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
diff --git a/drivers/fpga/xilinx-pr-decoupler.c b/drivers/fpga/xilinx/xilinx-pr-decoupler.c
similarity index 100%
rename from drivers/fpga/xilinx-pr-decoupler.c
rename to drivers/fpga/xilinx/xilinx-pr-decoupler.c
diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx/xilinx-spi.c
similarity index 100%
rename from drivers/fpga/xilinx-spi.c
rename to drivers/fpga/xilinx/xilinx-spi.c
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/xilinx/zynq-fpga.c
similarity index 100%
rename from drivers/fpga/zynq-fpga.c
rename to drivers/fpga/xilinx/zynq-fpga.c
diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/xilinx/zynqmp-fpga.c
similarity index 100%
rename from drivers/fpga/zynqmp-fpga.c
rename to drivers/fpga/xilinx/zynqmp-fpga.c
--
2.26.3
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v5 3/4] fpga: altera: reorganize to subdir layout
2021-06-22 20:05 ` trix
@ 2021-06-22 20:05 ` trix
-1 siblings, 0 replies; 15+ messages in thread
From: trix @ 2021-06-22 20:05 UTC (permalink / raw)
To: hao.wu, mdf, corbet, michal.simek, gregkh, nava.manne, dinguyen,
krzysztof.kozlowski, yilun.xu, davidgow, fpacheco,
russell.h.weight, richard.gong, luca
Cc: linux-fpga, linux-doc, linux-kernel, linux-arm-kernel, Tom Rix
From: Tom Rix <trix@redhat.com>
Follow drivers/net/ethernet/ which has control configs
NET_VENDOR_BLA that map to drivers/net/ethernet/bla
Since fpgas do not have many vendors, drop the 'VENDOR' and use
FPGA_BLA.
There are several new subdirs
altera/
dfl/
lattice/
xilinx/
Each subdir has a Kconfig that has a new/reused
if FPGA_BLA
... existing configs ...
endif FPGA_BLA
Which is sourced into the main fpga/Kconfig
Each subdir has a Makefile whose transversal is controlled in the
fpga/Makefile by
obj-$(CONFIG_FPGA_BLA) += bla/
This is the altera/ subdir part.
Create a altera/ subdir
Move altera-* and soc* ts73xx* files to it.
Add a Kconfig and Makefile
Signed-off-by: Tom Rix <trix@redhat.com>
---
drivers/fpga/Kconfig | 70 +--------------
drivers/fpga/Makefile | 11 +--
drivers/fpga/altera/Kconfig | 85 +++++++++++++++++++
drivers/fpga/altera/Makefile | 12 +++
drivers/fpga/{ => altera}/altera-cvp.c | 0
drivers/fpga/{ => altera}/altera-fpga2sdram.c | 0
.../fpga/{ => altera}/altera-freeze-bridge.c | 0
drivers/fpga/{ => altera}/altera-hps2fpga.c | 0
.../{ => altera}/altera-pr-ip-core-plat.c | 0
drivers/fpga/{ => altera}/altera-pr-ip-core.c | 0
drivers/fpga/{ => altera}/altera-ps-spi.c | 0
drivers/fpga/{ => altera}/socfpga-a10.c | 0
drivers/fpga/{ => altera}/socfpga.c | 0
drivers/fpga/{ => altera}/stratix10-soc.c | 0
drivers/fpga/{ => altera}/ts73xx-fpga.c | 0
15 files changed, 99 insertions(+), 79 deletions(-)
create mode 100644 drivers/fpga/altera/Kconfig
create mode 100644 drivers/fpga/altera/Makefile
rename drivers/fpga/{ => altera}/altera-cvp.c (100%)
rename drivers/fpga/{ => altera}/altera-fpga2sdram.c (100%)
rename drivers/fpga/{ => altera}/altera-freeze-bridge.c (100%)
rename drivers/fpga/{ => altera}/altera-hps2fpga.c (100%)
rename drivers/fpga/{ => altera}/altera-pr-ip-core-plat.c (100%)
rename drivers/fpga/{ => altera}/altera-pr-ip-core.c (100%)
rename drivers/fpga/{ => altera}/altera-ps-spi.c (100%)
rename drivers/fpga/{ => altera}/socfpga-a10.c (100%)
rename drivers/fpga/{ => altera}/socfpga.c (100%)
rename drivers/fpga/{ => altera}/stratix10-soc.c (100%)
rename drivers/fpga/{ => altera}/ts73xx-fpga.c (100%)
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 28c261807b428..2c829b1105925 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -12,52 +12,6 @@ menuconfig FPGA
if FPGA
-config FPGA_MGR_SOCFPGA
- tristate "Altera SOCFPGA FPGA Manager"
- depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
- help
- FPGA manager driver support for Altera SOCFPGA.
-
-config FPGA_MGR_SOCFPGA_A10
- tristate "Altera SoCFPGA Arria10"
- depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
- select REGMAP_MMIO
- help
- FPGA manager driver support for Altera Arria10 SoCFPGA.
-
-config ALTERA_PR_IP_CORE
- tristate "Altera Partial Reconfiguration IP Core"
- help
- Core driver support for Altera Partial Reconfiguration IP component
-
-config ALTERA_PR_IP_CORE_PLAT
- tristate "Platform support of Altera Partial Reconfiguration IP Core"
- depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
- help
- Platform driver support for Altera Partial Reconfiguration IP
- component
-
-config FPGA_MGR_ALTERA_PS_SPI
- tristate "Altera FPGA Passive Serial over SPI"
- depends on SPI
- select BITREVERSE
- help
- FPGA manager driver support for Altera Arria/Cyclone/Stratix
- using the passive serial interface over SPI.
-
-config FPGA_MGR_ALTERA_CVP
- tristate "Altera CvP FPGA Manager"
- depends on PCI
- help
- FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
- Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
-
-config FPGA_MGR_STRATIX10_SOC
- tristate "Intel Stratix10 SoC FPGA Manager"
- depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE)
- help
- FPGA manager driver support for the Intel Stratix10 SoC.
-
config FPGA_MGR_ICE40_SPI
tristate "Lattice iCE40 SPI"
depends on OF && SPI
@@ -71,35 +25,12 @@ config FPGA_MGR_MACHXO2_SPI
FPGA manager driver support for Lattice MachXO2 configuration
over slave SPI interface.
-config FPGA_MGR_TS73XX
- tristate "Technologic Systems TS-73xx SBC FPGA Manager"
- depends on ARCH_EP93XX && MACH_TS72XX
- help
- FPGA manager driver support for the Altera Cyclone II FPGA
- present on the TS-73xx SBC boards.
-
config FPGA_BRIDGE
tristate "FPGA Bridge Framework"
help
Say Y here if you want to support bridges connected between host
processors and FPGAs or between FPGAs.
-config SOCFPGA_FPGA_BRIDGE
- tristate "Altera SoCFPGA FPGA Bridges"
- depends on ARCH_INTEL_SOCFPGA && FPGA_BRIDGE
- help
- Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
- devices.
-
-config ALTERA_FREEZE_BRIDGE
- tristate "Altera FPGA Freeze Bridge"
- depends on FPGA_BRIDGE && HAS_IOMEM
- help
- Say Y to enable drivers for Altera FPGA Freeze bridges. A
- freeze bridge is a bridge that exists in the FPGA fabric to
- isolate one region of the FPGA from the busses while that
- region is being reprogrammed.
-
config FPGA_REGION
tristate "FPGA Region"
depends on FPGA_BRIDGE
@@ -115,6 +46,7 @@ config OF_FPGA_REGION
Support for loading FPGA images by applying a Device Tree
overlay.
+source "drivers/fpga/altera/Kconfig"
source "drivers/fpga/dfl/Kconfig"
source "drivers/fpga/xilinx/Kconfig"
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 0868c7c4264d8..db83aeb997f24 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -7,25 +7,16 @@
obj-$(CONFIG_FPGA) += fpga-mgr.o
# FPGA Manager Drivers
-obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
-obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
-obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
-obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
-obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o
-obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
-obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
-obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
# FPGA Bridge Drivers
obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
-obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
-obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
# High Level Interfaces
obj-$(CONFIG_FPGA_REGION) += fpga-region.o
obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
+obj-$(CONFIG_FPGA_ALTERA) += altera/
obj-$(CONFIG_FPGA_DFL) += dfl/
obj-$(CONFIG_FPGA_XILINX) += xilinx/
diff --git a/drivers/fpga/altera/Kconfig b/drivers/fpga/altera/Kconfig
new file mode 100644
index 0000000000000..7075c6dc48e44
--- /dev/null
+++ b/drivers/fpga/altera/Kconfig
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config FPGA_ALTERA
+ bool "Altera FPGAs"
+ default y
+ help
+ If you have an Altera FPGA, say Y.
+
+ Note that the answer to this question doesn't directly affect the
+ kernel: saying N will just cause the configurator to skip all
+ the questions about Altera FPGAs. If you say Y, you will be asked
+ for your specific device in the following questions.
+
+if FPGA_ALTERA
+
+config FPGA_MGR_SOCFPGA
+ tristate "Altera SOCFPGA FPGA Manager"
+ depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
+ help
+ FPGA manager driver support for Altera SOCFPGA.
+
+config FPGA_MGR_SOCFPGA_A10
+ tristate "Altera SoCFPGA Arria10"
+ depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
+ select REGMAP_MMIO
+ help
+ FPGA manager driver support for Altera Arria10 SoCFPGA.
+
+config ALTERA_PR_IP_CORE
+ tristate "Altera Partial Reconfiguration IP Core"
+ help
+ Core driver support for Altera Partial Reconfiguration IP component
+
+config ALTERA_PR_IP_CORE_PLAT
+ tristate "Platform support of Altera Partial Reconfiguration IP Core"
+ depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
+ help
+ Platform driver support for Altera Partial Reconfiguration IP
+ component
+
+config FPGA_MGR_ALTERA_PS_SPI
+ tristate "Altera FPGA Passive Serial over SPI"
+ depends on SPI
+ select BITREVERSE
+ help
+ FPGA manager driver support for Altera Arria/Cyclone/Stratix
+ using the passive serial interface over SPI.
+
+config FPGA_MGR_ALTERA_CVP
+ tristate "Altera CvP FPGA Manager"
+ depends on PCI
+ help
+ FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
+ Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
+
+config FPGA_MGR_STRATIX10_SOC
+ tristate "Intel Stratix10 SoC FPGA Manager"
+ depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE)
+ help
+ FPGA manager driver support for the Intel Stratix10 SoC.
+
+config FPGA_MGR_TS73XX
+ tristate "Technologic Systems TS-73xx SBC FPGA Manager"
+ depends on ARCH_EP93XX && MACH_TS72XX
+ help
+ FPGA manager driver support for the Altera Cyclone II FPGA
+ present on the TS-73xx SBC boards.
+
+config ALTERA_FREEZE_BRIDGE
+ tristate "Altera FPGA Freeze Bridge"
+ depends on FPGA_BRIDGE && HAS_IOMEM
+ help
+ Say Y to enable drivers for Altera FPGA Freeze bridges. A
+ freeze bridge is a bridge that exists in the FPGA fabric to
+ isolate one region of the FPGA from the busses while that
+ region is being reprogrammed.
+
+config SOCFPGA_FPGA_BRIDGE
+ tristate "Altera SoCFPGA FPGA Bridges"
+ depends on ARCH_INTEL_SOCFPGA && FPGA_BRIDGE
+ help
+ Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
+ devices.
+
+endif #FPGA_ALTERA
diff --git a/drivers/fpga/altera/Makefile b/drivers/fpga/altera/Makefile
new file mode 100644
index 0000000000000..9c86057cff110
--- /dev/null
+++ b/drivers/fpga/altera/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
+obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
+obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
+obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
+obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
+obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
+obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
+obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o
+obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
+obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera/altera-cvp.c
similarity index 100%
rename from drivers/fpga/altera-cvp.c
rename to drivers/fpga/altera/altera-cvp.c
diff --git a/drivers/fpga/altera-fpga2sdram.c b/drivers/fpga/altera/altera-fpga2sdram.c
similarity index 100%
rename from drivers/fpga/altera-fpga2sdram.c
rename to drivers/fpga/altera/altera-fpga2sdram.c
diff --git a/drivers/fpga/altera-freeze-bridge.c b/drivers/fpga/altera/altera-freeze-bridge.c
similarity index 100%
rename from drivers/fpga/altera-freeze-bridge.c
rename to drivers/fpga/altera/altera-freeze-bridge.c
diff --git a/drivers/fpga/altera-hps2fpga.c b/drivers/fpga/altera/altera-hps2fpga.c
similarity index 100%
rename from drivers/fpga/altera-hps2fpga.c
rename to drivers/fpga/altera/altera-hps2fpga.c
diff --git a/drivers/fpga/altera-pr-ip-core-plat.c b/drivers/fpga/altera/altera-pr-ip-core-plat.c
similarity index 100%
rename from drivers/fpga/altera-pr-ip-core-plat.c
rename to drivers/fpga/altera/altera-pr-ip-core-plat.c
diff --git a/drivers/fpga/altera-pr-ip-core.c b/drivers/fpga/altera/altera-pr-ip-core.c
similarity index 100%
rename from drivers/fpga/altera-pr-ip-core.c
rename to drivers/fpga/altera/altera-pr-ip-core.c
diff --git a/drivers/fpga/altera-ps-spi.c b/drivers/fpga/altera/altera-ps-spi.c
similarity index 100%
rename from drivers/fpga/altera-ps-spi.c
rename to drivers/fpga/altera/altera-ps-spi.c
diff --git a/drivers/fpga/socfpga-a10.c b/drivers/fpga/altera/socfpga-a10.c
similarity index 100%
rename from drivers/fpga/socfpga-a10.c
rename to drivers/fpga/altera/socfpga-a10.c
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/altera/socfpga.c
similarity index 100%
rename from drivers/fpga/socfpga.c
rename to drivers/fpga/altera/socfpga.c
diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/altera/stratix10-soc.c
similarity index 100%
rename from drivers/fpga/stratix10-soc.c
rename to drivers/fpga/altera/stratix10-soc.c
diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/altera/ts73xx-fpga.c
similarity index 100%
rename from drivers/fpga/ts73xx-fpga.c
rename to drivers/fpga/altera/ts73xx-fpga.c
--
2.26.3
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v5 3/4] fpga: altera: reorganize to subdir layout
@ 2021-06-22 20:05 ` trix
0 siblings, 0 replies; 15+ messages in thread
From: trix @ 2021-06-22 20:05 UTC (permalink / raw)
To: hao.wu, mdf, corbet, michal.simek, gregkh, nava.manne, dinguyen,
krzysztof.kozlowski, yilun.xu, davidgow, fpacheco,
russell.h.weight, richard.gong, luca
Cc: linux-fpga, linux-doc, linux-kernel, linux-arm-kernel, Tom Rix
From: Tom Rix <trix@redhat.com>
Follow drivers/net/ethernet/ which has control configs
NET_VENDOR_BLA that map to drivers/net/ethernet/bla
Since fpgas do not have many vendors, drop the 'VENDOR' and use
FPGA_BLA.
There are several new subdirs
altera/
dfl/
lattice/
xilinx/
Each subdir has a Kconfig that has a new/reused
if FPGA_BLA
... existing configs ...
endif FPGA_BLA
Which is sourced into the main fpga/Kconfig
Each subdir has a Makefile whose transversal is controlled in the
fpga/Makefile by
obj-$(CONFIG_FPGA_BLA) += bla/
This is the altera/ subdir part.
Create a altera/ subdir
Move altera-* and soc* ts73xx* files to it.
Add a Kconfig and Makefile
Signed-off-by: Tom Rix <trix@redhat.com>
---
drivers/fpga/Kconfig | 70 +--------------
drivers/fpga/Makefile | 11 +--
drivers/fpga/altera/Kconfig | 85 +++++++++++++++++++
drivers/fpga/altera/Makefile | 12 +++
drivers/fpga/{ => altera}/altera-cvp.c | 0
drivers/fpga/{ => altera}/altera-fpga2sdram.c | 0
.../fpga/{ => altera}/altera-freeze-bridge.c | 0
drivers/fpga/{ => altera}/altera-hps2fpga.c | 0
.../{ => altera}/altera-pr-ip-core-plat.c | 0
drivers/fpga/{ => altera}/altera-pr-ip-core.c | 0
drivers/fpga/{ => altera}/altera-ps-spi.c | 0
drivers/fpga/{ => altera}/socfpga-a10.c | 0
drivers/fpga/{ => altera}/socfpga.c | 0
drivers/fpga/{ => altera}/stratix10-soc.c | 0
drivers/fpga/{ => altera}/ts73xx-fpga.c | 0
15 files changed, 99 insertions(+), 79 deletions(-)
create mode 100644 drivers/fpga/altera/Kconfig
create mode 100644 drivers/fpga/altera/Makefile
rename drivers/fpga/{ => altera}/altera-cvp.c (100%)
rename drivers/fpga/{ => altera}/altera-fpga2sdram.c (100%)
rename drivers/fpga/{ => altera}/altera-freeze-bridge.c (100%)
rename drivers/fpga/{ => altera}/altera-hps2fpga.c (100%)
rename drivers/fpga/{ => altera}/altera-pr-ip-core-plat.c (100%)
rename drivers/fpga/{ => altera}/altera-pr-ip-core.c (100%)
rename drivers/fpga/{ => altera}/altera-ps-spi.c (100%)
rename drivers/fpga/{ => altera}/socfpga-a10.c (100%)
rename drivers/fpga/{ => altera}/socfpga.c (100%)
rename drivers/fpga/{ => altera}/stratix10-soc.c (100%)
rename drivers/fpga/{ => altera}/ts73xx-fpga.c (100%)
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 28c261807b428..2c829b1105925 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -12,52 +12,6 @@ menuconfig FPGA
if FPGA
-config FPGA_MGR_SOCFPGA
- tristate "Altera SOCFPGA FPGA Manager"
- depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
- help
- FPGA manager driver support for Altera SOCFPGA.
-
-config FPGA_MGR_SOCFPGA_A10
- tristate "Altera SoCFPGA Arria10"
- depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
- select REGMAP_MMIO
- help
- FPGA manager driver support for Altera Arria10 SoCFPGA.
-
-config ALTERA_PR_IP_CORE
- tristate "Altera Partial Reconfiguration IP Core"
- help
- Core driver support for Altera Partial Reconfiguration IP component
-
-config ALTERA_PR_IP_CORE_PLAT
- tristate "Platform support of Altera Partial Reconfiguration IP Core"
- depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
- help
- Platform driver support for Altera Partial Reconfiguration IP
- component
-
-config FPGA_MGR_ALTERA_PS_SPI
- tristate "Altera FPGA Passive Serial over SPI"
- depends on SPI
- select BITREVERSE
- help
- FPGA manager driver support for Altera Arria/Cyclone/Stratix
- using the passive serial interface over SPI.
-
-config FPGA_MGR_ALTERA_CVP
- tristate "Altera CvP FPGA Manager"
- depends on PCI
- help
- FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
- Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
-
-config FPGA_MGR_STRATIX10_SOC
- tristate "Intel Stratix10 SoC FPGA Manager"
- depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE)
- help
- FPGA manager driver support for the Intel Stratix10 SoC.
-
config FPGA_MGR_ICE40_SPI
tristate "Lattice iCE40 SPI"
depends on OF && SPI
@@ -71,35 +25,12 @@ config FPGA_MGR_MACHXO2_SPI
FPGA manager driver support for Lattice MachXO2 configuration
over slave SPI interface.
-config FPGA_MGR_TS73XX
- tristate "Technologic Systems TS-73xx SBC FPGA Manager"
- depends on ARCH_EP93XX && MACH_TS72XX
- help
- FPGA manager driver support for the Altera Cyclone II FPGA
- present on the TS-73xx SBC boards.
-
config FPGA_BRIDGE
tristate "FPGA Bridge Framework"
help
Say Y here if you want to support bridges connected between host
processors and FPGAs or between FPGAs.
-config SOCFPGA_FPGA_BRIDGE
- tristate "Altera SoCFPGA FPGA Bridges"
- depends on ARCH_INTEL_SOCFPGA && FPGA_BRIDGE
- help
- Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
- devices.
-
-config ALTERA_FREEZE_BRIDGE
- tristate "Altera FPGA Freeze Bridge"
- depends on FPGA_BRIDGE && HAS_IOMEM
- help
- Say Y to enable drivers for Altera FPGA Freeze bridges. A
- freeze bridge is a bridge that exists in the FPGA fabric to
- isolate one region of the FPGA from the busses while that
- region is being reprogrammed.
-
config FPGA_REGION
tristate "FPGA Region"
depends on FPGA_BRIDGE
@@ -115,6 +46,7 @@ config OF_FPGA_REGION
Support for loading FPGA images by applying a Device Tree
overlay.
+source "drivers/fpga/altera/Kconfig"
source "drivers/fpga/dfl/Kconfig"
source "drivers/fpga/xilinx/Kconfig"
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 0868c7c4264d8..db83aeb997f24 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -7,25 +7,16 @@
obj-$(CONFIG_FPGA) += fpga-mgr.o
# FPGA Manager Drivers
-obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
-obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
-obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
-obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
-obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o
-obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
-obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
-obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
# FPGA Bridge Drivers
obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
-obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
-obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
# High Level Interfaces
obj-$(CONFIG_FPGA_REGION) += fpga-region.o
obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
+obj-$(CONFIG_FPGA_ALTERA) += altera/
obj-$(CONFIG_FPGA_DFL) += dfl/
obj-$(CONFIG_FPGA_XILINX) += xilinx/
diff --git a/drivers/fpga/altera/Kconfig b/drivers/fpga/altera/Kconfig
new file mode 100644
index 0000000000000..7075c6dc48e44
--- /dev/null
+++ b/drivers/fpga/altera/Kconfig
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config FPGA_ALTERA
+ bool "Altera FPGAs"
+ default y
+ help
+ If you have an Altera FPGA, say Y.
+
+ Note that the answer to this question doesn't directly affect the
+ kernel: saying N will just cause the configurator to skip all
+ the questions about Altera FPGAs. If you say Y, you will be asked
+ for your specific device in the following questions.
+
+if FPGA_ALTERA
+
+config FPGA_MGR_SOCFPGA
+ tristate "Altera SOCFPGA FPGA Manager"
+ depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
+ help
+ FPGA manager driver support for Altera SOCFPGA.
+
+config FPGA_MGR_SOCFPGA_A10
+ tristate "Altera SoCFPGA Arria10"
+ depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
+ select REGMAP_MMIO
+ help
+ FPGA manager driver support for Altera Arria10 SoCFPGA.
+
+config ALTERA_PR_IP_CORE
+ tristate "Altera Partial Reconfiguration IP Core"
+ help
+ Core driver support for Altera Partial Reconfiguration IP component
+
+config ALTERA_PR_IP_CORE_PLAT
+ tristate "Platform support of Altera Partial Reconfiguration IP Core"
+ depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
+ help
+ Platform driver support for Altera Partial Reconfiguration IP
+ component
+
+config FPGA_MGR_ALTERA_PS_SPI
+ tristate "Altera FPGA Passive Serial over SPI"
+ depends on SPI
+ select BITREVERSE
+ help
+ FPGA manager driver support for Altera Arria/Cyclone/Stratix
+ using the passive serial interface over SPI.
+
+config FPGA_MGR_ALTERA_CVP
+ tristate "Altera CvP FPGA Manager"
+ depends on PCI
+ help
+ FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
+ Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
+
+config FPGA_MGR_STRATIX10_SOC
+ tristate "Intel Stratix10 SoC FPGA Manager"
+ depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE)
+ help
+ FPGA manager driver support for the Intel Stratix10 SoC.
+
+config FPGA_MGR_TS73XX
+ tristate "Technologic Systems TS-73xx SBC FPGA Manager"
+ depends on ARCH_EP93XX && MACH_TS72XX
+ help
+ FPGA manager driver support for the Altera Cyclone II FPGA
+ present on the TS-73xx SBC boards.
+
+config ALTERA_FREEZE_BRIDGE
+ tristate "Altera FPGA Freeze Bridge"
+ depends on FPGA_BRIDGE && HAS_IOMEM
+ help
+ Say Y to enable drivers for Altera FPGA Freeze bridges. A
+ freeze bridge is a bridge that exists in the FPGA fabric to
+ isolate one region of the FPGA from the busses while that
+ region is being reprogrammed.
+
+config SOCFPGA_FPGA_BRIDGE
+ tristate "Altera SoCFPGA FPGA Bridges"
+ depends on ARCH_INTEL_SOCFPGA && FPGA_BRIDGE
+ help
+ Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
+ devices.
+
+endif #FPGA_ALTERA
diff --git a/drivers/fpga/altera/Makefile b/drivers/fpga/altera/Makefile
new file mode 100644
index 0000000000000..9c86057cff110
--- /dev/null
+++ b/drivers/fpga/altera/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
+obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
+obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
+obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o
+obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o
+obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
+obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
+obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o
+obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
+obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera/altera-cvp.c
similarity index 100%
rename from drivers/fpga/altera-cvp.c
rename to drivers/fpga/altera/altera-cvp.c
diff --git a/drivers/fpga/altera-fpga2sdram.c b/drivers/fpga/altera/altera-fpga2sdram.c
similarity index 100%
rename from drivers/fpga/altera-fpga2sdram.c
rename to drivers/fpga/altera/altera-fpga2sdram.c
diff --git a/drivers/fpga/altera-freeze-bridge.c b/drivers/fpga/altera/altera-freeze-bridge.c
similarity index 100%
rename from drivers/fpga/altera-freeze-bridge.c
rename to drivers/fpga/altera/altera-freeze-bridge.c
diff --git a/drivers/fpga/altera-hps2fpga.c b/drivers/fpga/altera/altera-hps2fpga.c
similarity index 100%
rename from drivers/fpga/altera-hps2fpga.c
rename to drivers/fpga/altera/altera-hps2fpga.c
diff --git a/drivers/fpga/altera-pr-ip-core-plat.c b/drivers/fpga/altera/altera-pr-ip-core-plat.c
similarity index 100%
rename from drivers/fpga/altera-pr-ip-core-plat.c
rename to drivers/fpga/altera/altera-pr-ip-core-plat.c
diff --git a/drivers/fpga/altera-pr-ip-core.c b/drivers/fpga/altera/altera-pr-ip-core.c
similarity index 100%
rename from drivers/fpga/altera-pr-ip-core.c
rename to drivers/fpga/altera/altera-pr-ip-core.c
diff --git a/drivers/fpga/altera-ps-spi.c b/drivers/fpga/altera/altera-ps-spi.c
similarity index 100%
rename from drivers/fpga/altera-ps-spi.c
rename to drivers/fpga/altera/altera-ps-spi.c
diff --git a/drivers/fpga/socfpga-a10.c b/drivers/fpga/altera/socfpga-a10.c
similarity index 100%
rename from drivers/fpga/socfpga-a10.c
rename to drivers/fpga/altera/socfpga-a10.c
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/altera/socfpga.c
similarity index 100%
rename from drivers/fpga/socfpga.c
rename to drivers/fpga/altera/socfpga.c
diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/altera/stratix10-soc.c
similarity index 100%
rename from drivers/fpga/stratix10-soc.c
rename to drivers/fpga/altera/stratix10-soc.c
diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/altera/ts73xx-fpga.c
similarity index 100%
rename from drivers/fpga/ts73xx-fpga.c
rename to drivers/fpga/altera/ts73xx-fpga.c
--
2.26.3
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v5 4/4] fpga: lattice: reorganize to subdir layout
2021-06-22 20:05 ` trix
@ 2021-06-22 20:05 ` trix
-1 siblings, 0 replies; 15+ messages in thread
From: trix @ 2021-06-22 20:05 UTC (permalink / raw)
To: hao.wu, mdf, corbet, michal.simek, gregkh, nava.manne, dinguyen,
krzysztof.kozlowski, yilun.xu, davidgow, fpacheco,
russell.h.weight, richard.gong, luca
Cc: linux-fpga, linux-doc, linux-kernel, linux-arm-kernel, Tom Rix
From: Tom Rix <trix@redhat.com>
Follow drivers/net/ethernet/ which has control configs
NET_VENDOR_BLA that map to drivers/net/ethernet/bla
Since fpgas do not have many vendors, drop the 'VENDOR' and use
FPGA_BLA.
There are several new subdirs
altera/
dfl/
lattice/
xilinx/
Each subdir has a Kconfig that has a new/reused
if FPGA_BLA
... existing configs ...
endif FPGA_BLA
Which is sourced into the main fpga/Kconfig
Each subdir has a Makefile whose transversal is controlled in the
fpga/Makefile by
obj-$(CONFIG_FPGA_BLA) += bla/
This is the lattice/ subdir part.
Create a lattice/ subdir
Move ice40* and machxo2* files to it.
Add a Kconfig and Makefile
Signed-off-by: Tom Rix <trix@redhat.com>
---
drivers/fpga/Kconfig | 14 +-----------
drivers/fpga/Makefile | 13 ++++-------
drivers/fpga/lattice/Kconfig | 29 ++++++++++++++++++++++++
drivers/fpga/lattice/Makefile | 4 ++++
drivers/fpga/{ => lattice}/ice40-spi.c | 0
drivers/fpga/{ => lattice}/machxo2-spi.c | 0
6 files changed, 39 insertions(+), 21 deletions(-)
create mode 100644 drivers/fpga/lattice/Kconfig
create mode 100644 drivers/fpga/lattice/Makefile
rename drivers/fpga/{ => lattice}/ice40-spi.c (100%)
rename drivers/fpga/{ => lattice}/machxo2-spi.c (100%)
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 2c829b1105925..955b155da3575 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -12,19 +12,6 @@ menuconfig FPGA
if FPGA
-config FPGA_MGR_ICE40_SPI
- tristate "Lattice iCE40 SPI"
- depends on OF && SPI
- help
- FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
-
-config FPGA_MGR_MACHXO2_SPI
- tristate "Lattice MachXO2 SPI"
- depends on SPI
- help
- FPGA manager driver support for Lattice MachXO2 configuration
- over slave SPI interface.
-
config FPGA_BRIDGE
tristate "FPGA Bridge Framework"
help
@@ -48,6 +35,7 @@ config OF_FPGA_REGION
source "drivers/fpga/altera/Kconfig"
source "drivers/fpga/dfl/Kconfig"
+source "drivers/fpga/lattice/Kconfig"
source "drivers/fpga/xilinx/Kconfig"
endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index db83aeb997f24..9197698201e3a 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -4,19 +4,16 @@
#
# Core FPGA Manager Framework
-obj-$(CONFIG_FPGA) += fpga-mgr.o
-
-# FPGA Manager Drivers
-obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
-obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
+obj-$(CONFIG_FPGA) += fpga-mgr.o
# FPGA Bridge Drivers
-obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
+obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
# High Level Interfaces
-obj-$(CONFIG_FPGA_REGION) += fpga-region.o
-obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
+obj-$(CONFIG_FPGA_REGION) += fpga-region.o
+obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
obj-$(CONFIG_FPGA_ALTERA) += altera/
obj-$(CONFIG_FPGA_DFL) += dfl/
+obj-$(CONFIG_FPGA_LATTICE) += lattice/
obj-$(CONFIG_FPGA_XILINX) += xilinx/
diff --git a/drivers/fpga/lattice/Kconfig b/drivers/fpga/lattice/Kconfig
new file mode 100644
index 0000000000000..47f5a0c62aa4e
--- /dev/null
+++ b/drivers/fpga/lattice/Kconfig
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config FPGA_LATTICE
+ bool "Lattice FPGAs"
+ default y
+ help
+ If you have a Lattice FPGA, say Y.
+
+ Note that the answer to this question doesn't directly affect the
+ kernel: saying N will just cause the configurator to skip all
+ the questions about Lattice FPGAs. If you say Y, you will be asked
+ for your specific device in the following questions.
+
+if FPGA_LATTICE
+
+config FPGA_MGR_ICE40_SPI
+ tristate "Lattice iCE40 SPI"
+ depends on OF && SPI
+ help
+ FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
+
+config FPGA_MGR_MACHXO2_SPI
+ tristate "Lattice MachXO2 SPI"
+ depends on SPI
+ help
+ FPGA manager driver support for Lattice MachXO2 configuration
+ over slave SPI interface.
+
+endif #FPGA_LATTICE
diff --git a/drivers/fpga/lattice/Makefile b/drivers/fpga/lattice/Makefile
new file mode 100644
index 0000000000000..f542c96a73d40
--- /dev/null
+++ b/drivers/fpga/lattice/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
+obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
diff --git a/drivers/fpga/ice40-spi.c b/drivers/fpga/lattice/ice40-spi.c
similarity index 100%
rename from drivers/fpga/ice40-spi.c
rename to drivers/fpga/lattice/ice40-spi.c
diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/lattice/machxo2-spi.c
similarity index 100%
rename from drivers/fpga/machxo2-spi.c
rename to drivers/fpga/lattice/machxo2-spi.c
--
2.26.3
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v5 4/4] fpga: lattice: reorganize to subdir layout
@ 2021-06-22 20:05 ` trix
0 siblings, 0 replies; 15+ messages in thread
From: trix @ 2021-06-22 20:05 UTC (permalink / raw)
To: hao.wu, mdf, corbet, michal.simek, gregkh, nava.manne, dinguyen,
krzysztof.kozlowski, yilun.xu, davidgow, fpacheco,
russell.h.weight, richard.gong, luca
Cc: linux-fpga, linux-doc, linux-kernel, linux-arm-kernel, Tom Rix
From: Tom Rix <trix@redhat.com>
Follow drivers/net/ethernet/ which has control configs
NET_VENDOR_BLA that map to drivers/net/ethernet/bla
Since fpgas do not have many vendors, drop the 'VENDOR' and use
FPGA_BLA.
There are several new subdirs
altera/
dfl/
lattice/
xilinx/
Each subdir has a Kconfig that has a new/reused
if FPGA_BLA
... existing configs ...
endif FPGA_BLA
Which is sourced into the main fpga/Kconfig
Each subdir has a Makefile whose transversal is controlled in the
fpga/Makefile by
obj-$(CONFIG_FPGA_BLA) += bla/
This is the lattice/ subdir part.
Create a lattice/ subdir
Move ice40* and machxo2* files to it.
Add a Kconfig and Makefile
Signed-off-by: Tom Rix <trix@redhat.com>
---
drivers/fpga/Kconfig | 14 +-----------
drivers/fpga/Makefile | 13 ++++-------
drivers/fpga/lattice/Kconfig | 29 ++++++++++++++++++++++++
drivers/fpga/lattice/Makefile | 4 ++++
drivers/fpga/{ => lattice}/ice40-spi.c | 0
drivers/fpga/{ => lattice}/machxo2-spi.c | 0
6 files changed, 39 insertions(+), 21 deletions(-)
create mode 100644 drivers/fpga/lattice/Kconfig
create mode 100644 drivers/fpga/lattice/Makefile
rename drivers/fpga/{ => lattice}/ice40-spi.c (100%)
rename drivers/fpga/{ => lattice}/machxo2-spi.c (100%)
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 2c829b1105925..955b155da3575 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -12,19 +12,6 @@ menuconfig FPGA
if FPGA
-config FPGA_MGR_ICE40_SPI
- tristate "Lattice iCE40 SPI"
- depends on OF && SPI
- help
- FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
-
-config FPGA_MGR_MACHXO2_SPI
- tristate "Lattice MachXO2 SPI"
- depends on SPI
- help
- FPGA manager driver support for Lattice MachXO2 configuration
- over slave SPI interface.
-
config FPGA_BRIDGE
tristate "FPGA Bridge Framework"
help
@@ -48,6 +35,7 @@ config OF_FPGA_REGION
source "drivers/fpga/altera/Kconfig"
source "drivers/fpga/dfl/Kconfig"
+source "drivers/fpga/lattice/Kconfig"
source "drivers/fpga/xilinx/Kconfig"
endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index db83aeb997f24..9197698201e3a 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -4,19 +4,16 @@
#
# Core FPGA Manager Framework
-obj-$(CONFIG_FPGA) += fpga-mgr.o
-
-# FPGA Manager Drivers
-obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
-obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
+obj-$(CONFIG_FPGA) += fpga-mgr.o
# FPGA Bridge Drivers
-obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
+obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
# High Level Interfaces
-obj-$(CONFIG_FPGA_REGION) += fpga-region.o
-obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
+obj-$(CONFIG_FPGA_REGION) += fpga-region.o
+obj-$(CONFIG_OF_FPGA_REGION) += of-fpga-region.o
obj-$(CONFIG_FPGA_ALTERA) += altera/
obj-$(CONFIG_FPGA_DFL) += dfl/
+obj-$(CONFIG_FPGA_LATTICE) += lattice/
obj-$(CONFIG_FPGA_XILINX) += xilinx/
diff --git a/drivers/fpga/lattice/Kconfig b/drivers/fpga/lattice/Kconfig
new file mode 100644
index 0000000000000..47f5a0c62aa4e
--- /dev/null
+++ b/drivers/fpga/lattice/Kconfig
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config FPGA_LATTICE
+ bool "Lattice FPGAs"
+ default y
+ help
+ If you have a Lattice FPGA, say Y.
+
+ Note that the answer to this question doesn't directly affect the
+ kernel: saying N will just cause the configurator to skip all
+ the questions about Lattice FPGAs. If you say Y, you will be asked
+ for your specific device in the following questions.
+
+if FPGA_LATTICE
+
+config FPGA_MGR_ICE40_SPI
+ tristate "Lattice iCE40 SPI"
+ depends on OF && SPI
+ help
+ FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
+
+config FPGA_MGR_MACHXO2_SPI
+ tristate "Lattice MachXO2 SPI"
+ depends on SPI
+ help
+ FPGA manager driver support for Lattice MachXO2 configuration
+ over slave SPI interface.
+
+endif #FPGA_LATTICE
diff --git a/drivers/fpga/lattice/Makefile b/drivers/fpga/lattice/Makefile
new file mode 100644
index 0000000000000..f542c96a73d40
--- /dev/null
+++ b/drivers/fpga/lattice/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o
+obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o
diff --git a/drivers/fpga/ice40-spi.c b/drivers/fpga/lattice/ice40-spi.c
similarity index 100%
rename from drivers/fpga/ice40-spi.c
rename to drivers/fpga/lattice/ice40-spi.c
diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/lattice/machxo2-spi.c
similarity index 100%
rename from drivers/fpga/machxo2-spi.c
rename to drivers/fpga/lattice/machxo2-spi.c
--
2.26.3
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v5 2/4] fpga: xilinx: reorganize to subdir layout
2021-06-22 20:05 ` trix
@ 2021-06-28 8:46 ` Dan Carpenter
-1 siblings, 0 replies; 15+ messages in thread
From: kernel test robot @ 2021-06-26 3:49 UTC (permalink / raw)
To: kbuild
[-- Attachment #1: Type: text/plain, Size: 9379 bytes --]
CC: kbuild-all(a)lists.01.org
In-Reply-To: <20210622200511.3739914-4-trix@redhat.com>
References: <20210622200511.3739914-4-trix@redhat.com>
TO: trix(a)redhat.com
TO: hao.wu(a)intel.com
TO: mdf(a)kernel.org
TO: corbet(a)lwn.net
TO: michal.simek(a)xilinx.com
TO: gregkh(a)linuxfoundation.org
TO: nava.manne(a)xilinx.com
TO: dinguyen(a)kernel.org
TO: krzysztof.kozlowski(a)canonical.com
TO: yilun.xu(a)intel.com
TO: davidgow(a)google.com
Hi,
I love your patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.13-rc7 next-20210625]
[cannot apply to xlnx/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/trix-redhat-com/fpga-reorganize-to-subdirs/20210623-040811
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 0c18f29aae7ce3dadd26d8ee3505d07cc982df75
:::::: branch date: 3 days ago
:::::: commit date: 3 days ago
config: i386-randconfig-m031-20210625 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
smatch warnings:
drivers/fpga/xilinx/zynq-fpga.c:626 zynq_fpga_probe() warn: 'priv->clk' not released on lines: 615.
vim +626 drivers/fpga/xilinx/zynq-fpga.c
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 552
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 553 static int zynq_fpga_probe(struct platform_device *pdev)
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 554 {
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 555 struct device *dev = &pdev->dev;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 556 struct zynq_fpga_priv *priv;
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 557 struct fpga_manager *mgr;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 558 struct resource *res;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 559 int err;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 560
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 561 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 562 if (!priv)
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 563 return -ENOMEM;
425902f5c8e303 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2017-02-01 564 spin_lock_init(&priv->dma_lock);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 565
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 566 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 567 priv->io_base = devm_ioremap_resource(dev, res);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 568 if (IS_ERR(priv->io_base))
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 569 return PTR_ERR(priv->io_base);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 570
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 571 priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node,
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 572 "syscon");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 573 if (IS_ERR(priv->slcr)) {
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 574 dev_err(dev, "unable to get zynq-slcr regmap\n");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 575 return PTR_ERR(priv->slcr);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 576 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 577
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 578 init_completion(&priv->dma_done);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 579
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 580 priv->irq = platform_get_irq(pdev, 0);
d20c0da8b2020a drivers/fpga/zynq-fpga.c Stephen Boyd 2019-07-30 581 if (priv->irq < 0)
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 582 return priv->irq;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 583
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 584 priv->clk = devm_clk_get(dev, "ref_clk");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 585 if (IS_ERR(priv->clk)) {
daec0f4a594d48 drivers/fpga/zynq-fpga.c Shubhrajyoti Datta 2020-02-12 586 if (PTR_ERR(priv->clk) != -EPROBE_DEFER)
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 587 dev_err(dev, "input clock not found\n");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 588 return PTR_ERR(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 589 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 590
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 591 err = clk_prepare_enable(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 592 if (err) {
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 593 dev_err(dev, "unable to enable clock\n");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 594 return err;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 595 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 596
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 597 /* unlock the device */
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 598 zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 599
6b45e0f24c7b53 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2017-02-01 600 zynq_fpga_set_irq(priv, 0);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 601 zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 602 err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, dev_name(dev),
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 603 priv);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 604 if (err) {
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 605 dev_err(dev, "unable to request IRQ\n");
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 606 clk_disable_unprepare(priv->clk);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 607 return err;
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 608 }
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 609
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 610 clk_disable(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 611
084181fe8cc747 drivers/fpga/zynq-fpga.c Alan Tull 2018-10-15 612 mgr = devm_fpga_mgr_create(dev, "Xilinx Zynq FPGA Manager",
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 613 &zynq_fpga_ops, priv);
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 614 if (!mgr)
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 615 return -ENOMEM;
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 616
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 617 platform_set_drvdata(pdev, mgr);
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 618
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 619 err = fpga_mgr_register(mgr);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 620 if (err) {
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 621 dev_err(dev, "unable to register FPGA manager\n");
6376931babd833 drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-19 622 clk_unprepare(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 623 return err;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 624 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 625
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 @626 return 0;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 627 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 628
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 37643 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 2/4] fpga: xilinx: reorganize to subdir layout
@ 2021-06-28 8:46 ` Dan Carpenter
0 siblings, 0 replies; 15+ messages in thread
From: Dan Carpenter @ 2021-06-28 8:46 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 8367 bytes --]
Hi,
url: https://github.com/0day-ci/linux/commits/trix-redhat-com/fpga-reorganize-to-subdirs/20210623-040811
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 0c18f29aae7ce3dadd26d8ee3505d07cc982df75
config: i386-randconfig-m031-20210625 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
smatch warnings:
drivers/fpga/xilinx/zynq-fpga.c:626 zynq_fpga_probe() warn: 'priv->clk' not released on lines: 615.
vim +626 drivers/fpga/xilinx/zynq-fpga.c
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 553 static int zynq_fpga_probe(struct platform_device *pdev)
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 554 {
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 555 struct device *dev = &pdev->dev;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 556 struct zynq_fpga_priv *priv;
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 557 struct fpga_manager *mgr;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 558 struct resource *res;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 559 int err;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 560
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 561 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 562 if (!priv)
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 563 return -ENOMEM;
425902f5c8e303 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2017-02-01 564 spin_lock_init(&priv->dma_lock);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 565
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 566 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 567 priv->io_base = devm_ioremap_resource(dev, res);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 568 if (IS_ERR(priv->io_base))
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 569 return PTR_ERR(priv->io_base);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 570
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 571 priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node,
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 572 "syscon");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 573 if (IS_ERR(priv->slcr)) {
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 574 dev_err(dev, "unable to get zynq-slcr regmap\n");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 575 return PTR_ERR(priv->slcr);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 576 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 577
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 578 init_completion(&priv->dma_done);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 579
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 580 priv->irq = platform_get_irq(pdev, 0);
d20c0da8b2020a drivers/fpga/zynq-fpga.c Stephen Boyd 2019-07-30 581 if (priv->irq < 0)
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 582 return priv->irq;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 583
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 584 priv->clk = devm_clk_get(dev, "ref_clk");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 585 if (IS_ERR(priv->clk)) {
daec0f4a594d48 drivers/fpga/zynq-fpga.c Shubhrajyoti Datta 2020-02-12 586 if (PTR_ERR(priv->clk) != -EPROBE_DEFER)
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 587 dev_err(dev, "input clock not found\n");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 588 return PTR_ERR(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 589 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 590
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 591 err = clk_prepare_enable(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 592 if (err) {
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 593 dev_err(dev, "unable to enable clock\n");
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 594 return err;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 595 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 596
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 597 /* unlock the device */
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 598 zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 599
6b45e0f24c7b53 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2017-02-01 600 zynq_fpga_set_irq(priv, 0);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 601 zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 602 err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, dev_name(dev),
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 603 priv);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 604 if (err) {
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 605 dev_err(dev, "unable to request IRQ\n");
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 606 clk_disable_unprepare(priv->clk);
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 607 return err;
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 608 }
340c0c53ea3073 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 609
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 610 clk_disable(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 611
084181fe8cc747 drivers/fpga/zynq-fpga.c Alan Tull 2018-10-15 612 mgr = devm_fpga_mgr_create(dev, "Xilinx Zynq FPGA Manager",
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 613 &zynq_fpga_ops, priv);
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 614 if (!mgr)
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 615 return -ENOMEM;
clk_unprepare(priv->clk);
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 616
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 617 platform_set_drvdata(pdev, mgr);
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 618
7085e2a94f7df5 drivers/fpga/zynq-fpga.c Alan Tull 2018-05-16 619 err = fpga_mgr_register(mgr);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 620 if (err) {
1930c2865108d5 drivers/fpga/zynq-fpga.c Jason Gunthorpe 2016-11-21 621 dev_err(dev, "unable to register FPGA manager\n");
6376931babd833 drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-19 622 clk_unprepare(priv->clk);
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 623 return err;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 624 }
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 625
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 @626 return 0;
37784706bf9e3b drivers/fpga/zynq-fpga.c Moritz Fischer 2015-10-16 627 }
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 3/4] fpga: altera: reorganize to subdir layout
2021-06-22 20:05 ` trix
(?)
@ 2021-07-02 1:56 ` kernel test robot
2021-07-02 2:43 ` Moritz Fischer
-1 siblings, 1 reply; 15+ messages in thread
From: kernel test robot @ 2021-07-02 1:56 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 2896 bytes --]
Hi,
I love your patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.13 next-20210701]
[cannot apply to xlnx/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/trix-redhat-com/fpga-reorganize-to-subdirs/20210623-040811
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 0c18f29aae7ce3dadd26d8ee3505d07cc982df75
config: x86_64-randconfig-r031-20210702 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 9eb613b2de3163686b1a4bd1160f15ac56a4b083)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
# https://github.com/0day-ci/linux/commit/5e515251fd2c4a922934399c3c2007271dcf1398
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review trix-redhat-com/fpga-reorganize-to-subdirs/20210623-040811
git checkout 5e515251fd2c4a922934399c3c2007271dcf1398
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/fpga/altera/altera-freeze-bridge.c:201:34: warning: unused variable 'altera_freeze_br_of_match' [-Wunused-const-variable]
static const struct of_device_id altera_freeze_br_of_match[] = {
^
1 warning generated.
vim +/altera_freeze_br_of_match +201 drivers/fpga/altera/altera-freeze-bridge.c
ca24a648f535a0 drivers/fpga/altera-freeze-bridge.c Alan Tull 2016-11-01 200
ca24a648f535a0 drivers/fpga/altera-freeze-bridge.c Alan Tull 2016-11-01 @201 static const struct of_device_id altera_freeze_br_of_match[] = {
ca24a648f535a0 drivers/fpga/altera-freeze-bridge.c Alan Tull 2016-11-01 202 { .compatible = "altr,freeze-bridge-controller", },
ca24a648f535a0 drivers/fpga/altera-freeze-bridge.c Alan Tull 2016-11-01 203 {},
ca24a648f535a0 drivers/fpga/altera-freeze-bridge.c Alan Tull 2016-11-01 204 };
ca24a648f535a0 drivers/fpga/altera-freeze-bridge.c Alan Tull 2016-11-01 205 MODULE_DEVICE_TABLE(of, altera_freeze_br_of_match);
ca24a648f535a0 drivers/fpga/altera-freeze-bridge.c Alan Tull 2016-11-01 206
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 39286 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 3/4] fpga: altera: reorganize to subdir layout
2021-07-02 1:56 ` kernel test robot
@ 2021-07-02 2:43 ` Moritz Fischer
0 siblings, 0 replies; 15+ messages in thread
From: Moritz Fischer @ 2021-07-02 2:43 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 3157 bytes --]
On Fri, Jul 02, 2021 at 09:56:18AM +0800, kernel test robot wrote:
> Hi,
>
> I love your patch! Perhaps something to improve:
>
> [auto build test WARNING on linus/master]
> [also build test WARNING on v5.13 next-20210701]
> [cannot apply to xlnx/master]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url: https://github.com/0day-ci/linux/commits/trix-redhat-com/fpga-reorganize-to-subdirs/20210623-040811
> base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 0c18f29aae7ce3dadd26d8ee3505d07cc982df75
> config: x86_64-randconfig-r031-20210702 (attached as .config)
> compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 9eb613b2de3163686b1a4bd1160f15ac56a4b083)
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # install x86_64 cross compiling tool for clang build
> # apt-get install binutils-x86-64-linux-gnu
> # https://github.com/0day-ci/linux/commit/5e515251fd2c4a922934399c3c2007271dcf1398
> git remote add linux-review https://github.com/0day-ci/linux
> git fetch --no-tags linux-review trix-redhat-com/fpga-reorganize-to-subdirs/20210623-040811
> git checkout 5e515251fd2c4a922934399c3c2007271dcf1398
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All warnings (new ones prefixed by >>):
>
> >> drivers/fpga/altera/altera-freeze-bridge.c:201:34: warning: unused variable 'altera_freeze_br_of_match' [-Wunused-const-variable]
> static const struct of_device_id altera_freeze_br_of_match[] = {
> ^
> 1 warning generated.
>
>
> vim +/altera_freeze_br_of_match +201 drivers/fpga/altera/altera-freeze-bridge.c
>
> ca24a648f535a0 drivers/fpga/altera-freeze-bridge.c Alan Tull 2016-11-01 200
> ca24a648f535a0 drivers/fpga/altera-freeze-bridge.c Alan Tull 2016-11-01 @201 static const struct of_device_id altera_freeze_br_of_match[] = {
> ca24a648f535a0 drivers/fpga/altera-freeze-bridge.c Alan Tull 2016-11-01 202 { .compatible = "altr,freeze-bridge-controller", },
> ca24a648f535a0 drivers/fpga/altera-freeze-bridge.c Alan Tull 2016-11-01 203 {},
> ca24a648f535a0 drivers/fpga/altera-freeze-bridge.c Alan Tull 2016-11-01 204 };
> ca24a648f535a0 drivers/fpga/altera-freeze-bridge.c Alan Tull 2016-11-01 205 MODULE_DEVICE_TABLE(of, altera_freeze_br_of_match);
> ca24a648f535a0 drivers/fpga/altera-freeze-bridge.c Alan Tull 2016-11-01 206
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
I have a series to clean all of those up, I'll send it out tomorrow
morning.
- Moritz
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 2/4] fpga: xilinx: reorganize to subdir layout
2021-06-22 20:05 ` trix
(?)
@ 2021-07-05 14:48 ` kernel test robot
-1 siblings, 0 replies; 15+ messages in thread
From: kernel test robot @ 2021-07-05 14:48 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 2821 bytes --]
Hi,
I love your patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.13 next-20210701]
[cannot apply to xlnx/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/trix-redhat-com/fpga-reorganize-to-subdirs/20210623-040811
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 0c18f29aae7ce3dadd26d8ee3505d07cc982df75
config: x86_64-randconfig-a016-20210705 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project 3f9bf9f42a9043e20c6d2a74dd4f47a90a7e2b41)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
# https://github.com/0day-ci/linux/commit/d9e57cd01c49381771481c50a7705262d4980335
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review trix-redhat-com/fpga-reorganize-to-subdirs/20210623-040811
git checkout d9e57cd01c49381771481c50a7705262d4980335
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/fpga/xilinx/xilinx-spi.c:259:34: warning: unused variable 'xlnx_spi_of_match' [-Wunused-const-variable]
static const struct of_device_id xlnx_spi_of_match[] = {
^
1 warning generated.
vim +/xlnx_spi_of_match +259 drivers/fpga/xilinx/xilinx-spi.c
061c97d13f1a69 drivers/fpga/xilinx-spi.c Anatolij Gustschin 2017-03-23 258
061c97d13f1a69 drivers/fpga/xilinx-spi.c Anatolij Gustschin 2017-03-23 @259 static const struct of_device_id xlnx_spi_of_match[] = {
061c97d13f1a69 drivers/fpga/xilinx-spi.c Anatolij Gustschin 2017-03-23 260 { .compatible = "xlnx,fpga-slave-serial", },
061c97d13f1a69 drivers/fpga/xilinx-spi.c Anatolij Gustschin 2017-03-23 261 {}
061c97d13f1a69 drivers/fpga/xilinx-spi.c Anatolij Gustschin 2017-03-23 262 };
061c97d13f1a69 drivers/fpga/xilinx-spi.c Anatolij Gustschin 2017-03-23 263 MODULE_DEVICE_TABLE(of, xlnx_spi_of_match);
061c97d13f1a69 drivers/fpga/xilinx-spi.c Anatolij Gustschin 2017-03-23 264
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 42304 bytes --]
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2021-07-05 14:48 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-22 20:05 [PATCH v5 0/4] fpga: reorganize to subdirs trix
2021-06-22 20:05 ` trix
2021-06-22 20:05 ` [PATCH v5 1/4] fpga: dfl: reorganize to subdir layout trix
2021-06-22 20:05 ` trix
2021-06-22 20:05 ` [PATCH v5 2/4] fpga: xilinx: " trix
2021-06-22 20:05 ` trix
2021-07-05 14:48 ` kernel test robot
2021-06-22 20:05 ` [PATCH v5 3/4] fpga: altera: " trix
2021-06-22 20:05 ` trix
2021-07-02 1:56 ` kernel test robot
2021-07-02 2:43 ` Moritz Fischer
2021-06-22 20:05 ` [PATCH v5 4/4] fpga: lattice: " trix
2021-06-22 20:05 ` trix
2021-06-26 3:49 [PATCH v5 2/4] fpga: xilinx: " kernel test robot
2021-06-28 8:46 ` Dan Carpenter
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