* [PATCH] hw/sd: sdhci: Enable 64-bit system bus capability in the default SD/MMC host controller
@ 2021-06-23 18:59 Joanne Koong
2021-07-02 22:08 ` Philippe Mathieu-Daudé
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Joanne Koong @ 2021-06-23 18:59 UTC (permalink / raw)
To: qemu-devel, joannekoong; +Cc: qemu-block
The default SD/MMC host controller uses SD spec v2.00. 64-bit system bus capability
was added in v2.
In this change, we arrive at 0x157834b4 by computing (0x057834b4 | (1ul << 28))
where 28 represents the BUS64BIT SDHC_CAPAB field.
Signed-off-by: Joanne Koong <joannekoong@gmail.com>
---
hw/sd/sdhci-internal.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index e8c753d6d1..a76fc704e5 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -316,16 +316,16 @@ extern const VMStateDescription sdhci_vmstate;
* - 3.3v and 1.8v voltages
* - SDMA/ADMA1/ADMA2
* - high-speed
+ * - 64-bit system bus
* max host controller R/W buffers size: 512B
* max clock frequency for SDclock: 52 MHz
* timeout clock frequency: 52 MHz
*
* does not support:
* - 3.0v voltage
- * - 64-bit system bus
* - suspend/resume
*/
-#define SDHC_CAPAB_REG_DEFAULT 0x057834b4
+#define SDHC_CAPAB_REG_DEFAULT 0x157834b4
#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \
--
2.20.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] hw/sd: sdhci: Enable 64-bit system bus capability in the default SD/MMC host controller
2021-06-23 18:59 [PATCH] hw/sd: sdhci: Enable 64-bit system bus capability in the default SD/MMC host controller Joanne Koong
@ 2021-07-02 22:08 ` Philippe Mathieu-Daudé
2021-07-05 8:01 ` Bin Meng
2021-07-05 9:54 ` Philippe Mathieu-Daudé
2 siblings, 0 replies; 5+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-02 22:08 UTC (permalink / raw)
To: Joanne Koong, qemu-devel; +Cc: Bin Meng, qemu-block
Hi Joanne,
Next time I recommend you to Cc the maintainers, otherwise they
might miss your patch. See:
https://wiki.qemu.org/Contribute/SubmitAPatch#CC_the_relevant_maintainer
$ ./scripts/get_maintainer.pl -f hw/sd/sdhci-internal.h
"Philippe Mathieu-Daudé" <f4bug@amsat.org> (odd fixer:SD (Secure Card))
Bin Meng <bin.meng@windriver.com> (odd fixer:SD (Secure Card))
qemu-block@nongnu.org (open list:SD (Secure Card))
qemu-devel@nongnu.org (open list:All patches CC here)
On 6/23/21 8:59 PM, Joanne Koong wrote:
> The default SD/MMC host controller uses SD spec v2.00. 64-bit system bus capability
> was added in v2.
>
> In this change, we arrive at 0x157834b4 by computing (0x057834b4 | (1ul << 28))
> where 28 represents the BUS64BIT SDHC_CAPAB field.
>
> Signed-off-by: Joanne Koong <joannekoong@gmail.com>
> ---
> hw/sd/sdhci-internal.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
> index e8c753d6d1..a76fc704e5 100644
> --- a/hw/sd/sdhci-internal.h
> +++ b/hw/sd/sdhci-internal.h
> @@ -316,16 +316,16 @@ extern const VMStateDescription sdhci_vmstate;
> * - 3.3v and 1.8v voltages
> * - SDMA/ADMA1/ADMA2
> * - high-speed
> + * - 64-bit system bus
> * max host controller R/W buffers size: 512B
> * max clock frequency for SDclock: 52 MHz
> * timeout clock frequency: 52 MHz
> *
> * does not support:
> * - 3.0v voltage
> - * - 64-bit system bus
> * - suspend/resume
> */
> -#define SDHC_CAPAB_REG_DEFAULT 0x057834b4
> +#define SDHC_CAPAB_REG_DEFAULT 0x157834b4
>
> #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
> DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \
>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] hw/sd: sdhci: Enable 64-bit system bus capability in the default SD/MMC host controller
2021-06-23 18:59 [PATCH] hw/sd: sdhci: Enable 64-bit system bus capability in the default SD/MMC host controller Joanne Koong
2021-07-02 22:08 ` Philippe Mathieu-Daudé
@ 2021-07-05 8:01 ` Bin Meng
2021-07-05 9:54 ` Philippe Mathieu-Daudé
2 siblings, 0 replies; 5+ messages in thread
From: Bin Meng @ 2021-07-05 8:01 UTC (permalink / raw)
To: Joanne Koong; +Cc: qemu-devel@nongnu.org Developers, Qemu-block
On Thu, Jun 24, 2021 at 3:01 AM Joanne Koong <joannekoong@gmail.com> wrote:
>
> The default SD/MMC host controller uses SD spec v2.00. 64-bit system bus capability
> was added in v2.
>
> In this change, we arrive at 0x157834b4 by computing (0x057834b4 | (1ul << 28))
> where 28 represents the BUS64BIT SDHC_CAPAB field.
>
> Signed-off-by: Joanne Koong <joannekoong@gmail.com>
> ---
> hw/sd/sdhci-internal.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] hw/sd: sdhci: Enable 64-bit system bus capability in the default SD/MMC host controller
2021-06-23 18:59 [PATCH] hw/sd: sdhci: Enable 64-bit system bus capability in the default SD/MMC host controller Joanne Koong
2021-07-02 22:08 ` Philippe Mathieu-Daudé
2021-07-05 8:01 ` Bin Meng
@ 2021-07-05 9:54 ` Philippe Mathieu-Daudé
2021-07-06 19:00 ` Joanne Koong
2 siblings, 1 reply; 5+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-05 9:54 UTC (permalink / raw)
To: Joanne Koong, qemu-devel; +Cc: qemu-block
On 6/23/21 8:59 PM, Joanne Koong wrote:
> The default SD/MMC host controller uses SD spec v2.00. 64-bit system bus capability
> was added in v2.
>
> In this change, we arrive at 0x157834b4 by computing (0x057834b4 | (1ul << 28))
> where 28 represents the BUS64BIT SDHC_CAPAB field.
>
> Signed-off-by: Joanne Koong <joannekoong@gmail.com>
> ---
> hw/sd/sdhci-internal.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Thanks, series applied to sdmmc-next tree.
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] hw/sd: sdhci: Enable 64-bit system bus capability in the default SD/MMC host controller
2021-07-05 9:54 ` Philippe Mathieu-Daudé
@ 2021-07-06 19:00 ` Joanne Koong
0 siblings, 0 replies; 5+ messages in thread
From: Joanne Koong @ 2021-07-06 19:00 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-devel, qemu-block
[-- Attachment #1: Type: text/plain, Size: 646 bytes --]
Awesome! Thank you, Philippe and Bin!
On Mon, Jul 5, 2021 at 2:54 AM Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> On 6/23/21 8:59 PM, Joanne Koong wrote:
> > The default SD/MMC host controller uses SD spec v2.00. 64-bit system bus
> capability
> > was added in v2.
> >
> > In this change, we arrive at 0x157834b4 by computing (0x057834b4 | (1ul
> << 28))
> > where 28 represents the BUS64BIT SDHC_CAPAB field.
> >
> > Signed-off-by: Joanne Koong <joannekoong@gmail.com>
> > ---
> > hw/sd/sdhci-internal.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
>
> Thanks, series applied to sdmmc-next tree.
>
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2021-06-23 18:59 [PATCH] hw/sd: sdhci: Enable 64-bit system bus capability in the default SD/MMC host controller Joanne Koong
2021-07-02 22:08 ` Philippe Mathieu-Daudé
2021-07-05 8:01 ` Bin Meng
2021-07-05 9:54 ` Philippe Mathieu-Daudé
2021-07-06 19:00 ` Joanne Koong
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