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From: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
To: <u-boot@lists.denx.de>
Cc: <joe.hershberger@ni.com>, <rfried.dev@gmail.com>,
	<monstr@monstr.eu>, <git@xilinx.com>, <somaashokreddy@gmail.com>,
	Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Subject: [PATCH 1/2] net: xilinx: axi_emac: Cleanup of of_to_plat()
Date: Thu, 24 Jun 2021 00:34:40 -0600	[thread overview]
Message-ID: <20210624063441.24072-2-ashok.reddy.soma@xilinx.com> (raw)
In-Reply-To: <20210624063441.24072-1-ashok.reddy.soma@xilinx.com>

There are lot of accesses to priv data in of_to_plat(), which is incorrect.
Create a platform data structure and use it in of_to_plat(), then copy all
platform data to priv data in probe.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
---

 drivers/net/xilinx_axi_emac.c | 47 ++++++++++++++++++++++++-----------
 1 file changed, 32 insertions(+), 15 deletions(-)

diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 2ce6271afe..cfc6082475 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -87,6 +87,16 @@ struct axidma_reg {
 	u32 tail_hi; /* TAILDESC high 32 bit */
 };
 
+/* Platform data structures */
+struct axidma_plat {
+	struct eth_pdata eth_pdata;
+	struct axidma_reg *dmatx;
+	struct axidma_reg *dmarx;
+	int phyaddr;
+	u8 eth_hasnobuf;
+	int phy_of_handle;
+};
+
 /* Private driver structures */
 struct axidma_priv {
 	struct axidma_reg *dmatx;
@@ -690,9 +700,20 @@ static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
 
 static int axi_emac_probe(struct udevice *dev)
 {
+	struct axidma_plat *plat = dev_get_plat(dev);
+	struct eth_pdata *pdata = &plat->eth_pdata;
 	struct axidma_priv *priv = dev_get_priv(dev);
 	int ret;
 
+	priv->iobase = (struct axi_regs *)pdata->iobase;
+	priv->dmatx = plat->dmatx;
+	/* RX channel offset is 0x30 */
+	priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
+	priv->eth_hasnobuf = plat->eth_hasnobuf;
+	priv->phyaddr = plat->phyaddr;
+	priv->phy_of_handle = plat->phy_of_handle;
+	priv->interface = pdata->phy_interface;
+
 	priv->bus = mdio_alloc();
 	priv->bus->read = axiemac_miiphy_read;
 	priv->bus->write = axiemac_miiphy_write;
@@ -729,14 +750,13 @@ static const struct eth_ops axi_emac_ops = {
 
 static int axi_emac_of_to_plat(struct udevice *dev)
 {
-	struct eth_pdata *pdata = dev_get_plat(dev);
-	struct axidma_priv *priv = dev_get_priv(dev);
+	struct axidma_plat *plat = dev_get_plat(dev);
+	struct eth_pdata *pdata = &plat->eth_pdata;
 	int node = dev_of_offset(dev);
 	int offset = 0;
 	const char *phy_mode;
 
 	pdata->iobase = dev_read_addr(dev);
-	priv->iobase = (struct axi_regs *)pdata->iobase;
 
 	offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
 				       "axistream-connected");
@@ -744,21 +764,19 @@ static int axi_emac_of_to_plat(struct udevice *dev)
 		printf("%s: axistream is not found\n", __func__);
 		return -EINVAL;
 	}
-	priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
+	plat->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
 							  offset, "reg");
-	if (!priv->dmatx) {
+	if (!plat->dmatx) {
 		printf("%s: axi_dma register space not found\n", __func__);
 		return -EINVAL;
 	}
-	/* RX channel offset is 0x30 */
-	priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
 
-	priv->phyaddr = -1;
+	plat->phyaddr = -1;
 
 	offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
 	if (offset > 0) {
-		priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
-		priv->phy_of_handle = offset;
+		plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
+		plat->phy_of_handle = offset;
 	}
 
 	phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
@@ -768,13 +786,12 @@ static int axi_emac_of_to_plat(struct udevice *dev)
 		printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 		return -EINVAL;
 	}
-	priv->interface = pdata->phy_interface;
 
-	priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
+	plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
 					     "xlnx,eth-hasnobuf");
 
-	printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
-	       priv->phyaddr, phy_string_for_interface(priv->interface));
+	printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase,
+	       plat->phyaddr, phy_string_for_interface(pdata->phy_interface));
 
 	return 0;
 }
@@ -793,5 +810,5 @@ U_BOOT_DRIVER(axi_emac) = {
 	.remove	= axi_emac_remove,
 	.ops	= &axi_emac_ops,
 	.priv_auto	= sizeof(struct axidma_priv),
-	.plat_auto	= sizeof(struct eth_pdata),
+	.plat_auto	= sizeof(struct axidma_plat),
 };
-- 
2.17.1


  reply	other threads:[~2021-06-24  6:35 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-24  6:34 [PATCH 0/2] Add support for 10G/25G to AXI emac driver Ashok Reddy Soma
2021-06-24  6:34 ` Ashok Reddy Soma [this message]
2021-06-27 20:00   ` [PATCH 1/2] net: xilinx: axi_emac: Cleanup of of_to_plat() Ramon Fried
2021-06-24  6:34 ` [PATCH 2/2] net: xilinx: axi_emac: Add support for 10G/25G AXI ethernet Ashok Reddy Soma
2021-06-27 20:01   ` Ramon Fried
2021-06-28  7:07 ` [PATCH 0/2] Add support for 10G/25G to AXI emac driver Michal Simek
2021-06-28 17:13   ` Ramon Fried
2021-06-29  4:30     ` Ashok Reddy Soma
2021-06-29  5:17       ` Ramon Fried

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