From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>
Subject: [Intel-gfx] [PATCH 2/2] drm/i915/dg1: Double memory bandwidth available
Date: Thu, 24 Jun 2021 09:31:13 +0100 [thread overview]
Message-ID: <20210624083113.365039-2-matthew.auld@intel.com> (raw)
In-Reply-To: <20210624083113.365039-1-matthew.auld@intel.com>
From: Clint Taylor <clinton.a.taylor@intel.com>
Use MCHBAR Gear_type information to compute memory bandwidth available
during MCHBAR calculations.
Tested-by: Swati Sharma <swati2.sharma@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Swati Sharma <swati2.sharma@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 62a70f364f2b..603bc3669e3d 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -41,6 +41,9 @@ struct intel_qgv_info {
#define DG1_DRAM_T_RP_MASK (0x7F << 0)
#define DG1_DRAM_T_RP_SHIFT 0
+#define ICL_GEAR_TYPE_MASK (0x01 << 16)
+#define ICL_GEAR_TYPE_SHIFT 16
+
static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
struct intel_qgv_point *sp,
int point)
@@ -55,6 +58,11 @@ static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
else
dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
sp->dclk = dclk_ratio * dclk_reference;
+
+ val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
+ if ((val & ICL_GEAR_TYPE_MASK) >> ICL_GEAR_TYPE_SHIFT)
+ sp->dclk *= 2;
+
if (sp->dclk == 0)
return -EINVAL;
--
2.26.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-06-24 8:31 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-24 8:31 [Intel-gfx] [PATCH 1/2] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR Matthew Auld
2021-06-24 8:31 ` Matthew Auld [this message]
2021-06-24 11:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2021-06-24 14:50 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2021-06-18 16:13 [Intel-gfx] [PATCH 1/2] " Matthew Auld
2021-06-18 16:13 ` [Intel-gfx] [PATCH 2/2] drm/i915/dg1: Double memory bandwidth available Matthew Auld
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210624083113.365039-2-matthew.auld@intel.com \
--to=matthew.auld@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
--cc=lucas.demarchi@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.