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24 Jun 2021 04:40:50 -0700 IronPort-SDR: goeMpz0zUBJ8YeLo6lIYJW3GOklly4nRtgi/U8wgQ+dcCjq8IeAjKN1hB0ewfWfaLYtlJuBw9T vfx6qNgANzGq7DTM7e0duPKu0qmlPERMhfBdH0tGQUvg/Qiy8tzTL4e9STf632JtasaOaZNcYR L13UBOH80nGFTh5XLpqhU5459B+12B5K6D4s393Flc3BWL2JboXXLFZhtLEsY5W7vIFR0p1kjf muYxAJmTAVIWq3cw2aM5m8ZhNOl/MceD/pjHaGGB9u01V/W+vjqiI6l+2j0bx0E8EjARjimQFT QPs= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.248]) by uls-op-cesaip02.wdc.com with ESMTP; 24 Jun 2021 05:02:16 -0700 From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL 7/7] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer Date: Thu, 24 Jun 2021 05:02:11 -0700 Message-Id: <20210624120211.85499-8-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210624120211.85499-1-alistair.francis@wdc.com> References: <20210624120211.85499-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=802348aeb=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Connect the Ibex timer to the OpenTitan machine. The timer can trigger the RISC-V MIE interrupt as well as a custom device interrupt. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 5e7f4e9b4537f863bcb8db1264b840b56ef2a929.1624001156.git.alistair.francis@wdc.com --- include/hw/riscv/opentitan.h | 5 ++++- hw/riscv/opentitan.c | 14 +++++++++++--- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index aab9bc9245..86cceef698 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -22,6 +22,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/intc/ibex_plic.h" #include "hw/char/ibex_uart.h" +#include "hw/timer/ibex_timer.h" #include "qom/object.h" #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" @@ -35,6 +36,7 @@ struct LowRISCIbexSoCState { RISCVHartArrayState cpus; IbexPlicState plic; IbexUartState uart; + IbexTimerState timer; MemoryRegion flash_mem; MemoryRegion rom; @@ -57,7 +59,7 @@ enum { IBEX_DEV_SPI, IBEX_DEV_I2C, IBEX_DEV_PATTGEN, - IBEX_DEV_RV_TIMER, + IBEX_DEV_TIMER, IBEX_DEV_SENSOR_CTRL, IBEX_DEV_OTP_CTRL, IBEX_DEV_PWRMGR, @@ -82,6 +84,7 @@ enum { }; enum { + IBEX_TIMER_TIMEREXPIRED0_0 = 125, IBEX_UART0_RX_PARITY_ERR_IRQ = 8, IBEX_UART0_RX_TIMEOUT_IRQ = 7, IBEX_UART0_RX_BREAK_ERR_IRQ = 6, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 7545dcda9c..c5a7e3bacb 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -36,7 +36,7 @@ static const MemMapEntry ibex_memmap[] = { [IBEX_DEV_SPI] = { 0x40050000, 0x1000 }, [IBEX_DEV_I2C] = { 0x40080000, 0x1000 }, [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 }, - [IBEX_DEV_RV_TIMER] = { 0x40100000, 0x1000 }, + [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 }, [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 }, [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 }, [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 }, @@ -106,6 +106,8 @@ static void lowrisc_ibex_soc_init(Object *obj) object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC); object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); + + object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER); } static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) @@ -159,6 +161,14 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 3, qdev_get_gpio_in(DEVICE(&s->plic), IBEX_UART0_RX_OVERFLOW_IRQ)); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), + 0, qdev_get_gpio_in(DEVICE(&s->plic), + IBEX_TIMER_TIMEREXPIRED0_0)); + create_unimplemented_device("riscv.lowrisc.ibex.gpio", memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); create_unimplemented_device("riscv.lowrisc.ibex.spi", @@ -167,8 +177,6 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); create_unimplemented_device("riscv.lowrisc.ibex.pattgen", memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size); - create_unimplemented_device("riscv.lowrisc.ibex.rv_timer", - memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size); create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl", memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size); create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl", -- 2.31.1