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Thu, 24 Jun 2021 08:05:42 -0400 (EDT) Date: Thu, 24 Jun 2021 14:05:40 +0200 From: Maxime Ripard To: Miquel Raynal Cc: u-boot@lists.denx.de, Andre Przywara Subject: Re: [U-Boot] [PATCH v3 13/20] spl: nand: sunxi: use PIO instead of DMA Message-ID: <20210624120540.7oyhdmerjndsylbq@gilmour> References: <20180228195202.8183-1-miquel.raynal@bootlin.com> <20180228195202.8183-14-miquel.raynal@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20180228195202.8183-14-miquel.raynal@bootlin.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi Miquel, On Wed, Feb 28, 2018 at 08:51:55PM +0100, Miquel Raynal wrote: > SPL support was first written to support only the earlier generations of > Allwinner SoCs, and was only really enabled on the A13 / GR8. However, > those old SoCs had a DMA engine that has been replaced since the A31 by > another DMA controller that is no longer compatible. >=20 > Since the code directly uses that DMA controller, it cannot operate > properly on the later SoCs, while the NAND controller has not changed. >=20 > There's two paths forward, the first one would have been to add support > for that DMA controller too, the second to just remove the DMA usage > entirely and rely on PIO. >=20 > The later has been chosen because CPU overload at this stage is not an > issue and it makes the driver more generic, and easier to understand. >=20 > Signed-off-by: Miquel Raynal > Acked-by: Boris Brezillon I'm a bit late to the party, but this bricks the CHIP Pro too. While U-Boot proper seems to be flashed properly (re-reading it from the NAND after flashing brings up the same CRC than the original image), the SPL will only read 0s. The transfer does complete though, so maybe it's just the copy from the SRAM to the main memory that doesn't work? The offset looks correct though, so I'm not sure. Maxime