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From: "Martin Hundebøll" <martin@geanix.com>
To: Wu Hao <hao.wu@intel.com>, Tom Rix <trix@redhat.com>,
	Moritz Fischer <mdf@kernel.org>, Xu Yilun <yilun.xu@intel.com>,
	Jean Delvare <jdelvare@suse.com>,
	Guenter Roeck <linux@roeck-us.net>,
	Lee Jones <lee.jones@linaro.org>, Mark Brown <broonie@kernel.org>
Cc: "Martin Hundebøll" <mhu@silicom.dk>,
	linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-hwmon@vger.kernel.org, linux-spi@vger.kernel.org
Subject: [PATCH v2 1/5] fpga: dfl: pci: add device IDs for Silicom N501x PAC cards
Date: Fri, 25 Jun 2021 09:42:09 +0200	[thread overview]
Message-ID: <20210625074213.654274-2-martin@geanix.com> (raw)
In-Reply-To: <20210625074213.654274-1-martin@geanix.com>

From: Martin Hundebøll <mhu@silicom.dk>

This adds the approved PCI Express Device IDs for the Silicom PAC N5010
and N5011 cards (aka. Silicom Lightning Creek cards).

The N5010 features an FPGA that manages/interfaces four QSFP ports, and
allows on-board custom packet processing/filtering/routing, based on
logic loaded with user-provided FPGA bitstreams.

The N5011 cards adds a PCIe switch that exposes, in addition to the FPGA
itself, two Intel E810 (aka Columbiaville) ethernet controllers. With
this, packets can be forwarded from the FPGA to the host for further
processing.

Signed-off-by: Martin Hundebøll <mhu@silicom.dk>
Acked-by: Wu Hao <hao.wu@intel.com>
---

Changes since v1:
 * Commit message is updated with card description
 * Added Hao's Acked-by

 drivers/fpga/dfl-pci.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
index b44523ea8c91..4d68719e608f 100644
--- a/drivers/fpga/dfl-pci.c
+++ b/drivers/fpga/dfl-pci.c
@@ -74,6 +74,9 @@ static void cci_pci_free_irq(struct pci_dev *pcidev)
 #define PCIE_DEVICE_ID_PF_DSC_1_X		0x09C4
 #define PCIE_DEVICE_ID_INTEL_PAC_N3000		0x0B30
 #define PCIE_DEVICE_ID_INTEL_PAC_D5005		0x0B2B
+#define PCIE_DEVICE_ID_SILICOM_PAC_N5010	0x1000
+#define PCIE_DEVICE_ID_SILICOM_PAC_N5011	0x1001
+
 /* VF Device */
 #define PCIE_DEVICE_ID_VF_INT_5_X		0xBCBF
 #define PCIE_DEVICE_ID_VF_INT_6_X		0xBCC1
@@ -90,6 +93,8 @@ static struct pci_device_id cci_pcie_id_tbl[] = {
 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),},
 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),},
 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),},
+	{PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5010),},
+	{PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5011),},
 	{0,}
 };
 MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
-- 
2.31.0


  reply	other threads:[~2021-06-25  7:42 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-25  7:42 [PATCH v2 0/5] fpga/mfd/hwmon: Initial support for Silicom N5010 PAC Martin Hundebøll
2021-06-25  7:42 ` Martin Hundebøll [this message]
2021-06-25 18:43   ` [PATCH v2 1/5] fpga: dfl: pci: add device IDs for Silicom N501x PAC cards Moritz Fischer
2021-06-25  7:42 ` [PATCH v2 2/5] fpga: dfl: expose feature revision from struct dfl_device Martin Hundebøll
2021-06-25 19:26   ` Moritz Fischer
2021-06-28  3:38     ` Wu, Hao
2021-06-25  7:42 ` [PATCH v2 3/5] spi: spi-altera-dfl: support n5010 feature revision Martin Hundebøll
2021-06-28  5:58   ` Xu Yilun
2021-06-28 17:39   ` Moritz Fischer
2021-06-29 11:35     ` Mark Brown
2021-06-29 11:49     ` Martin Hundebøll
2021-06-29 14:37       ` Wu, Hao
2021-06-29 22:30         ` matthew.gerlach
2021-06-25  7:42 ` [PATCH v2 4/5] mfd: intel-m10-bmc: add n5010 variant Martin Hundebøll
2021-06-25 18:45   ` Moritz Fischer
2021-06-29  1:39     ` Xu Yilun
2021-06-28  5:59   ` Xu Yilun
2021-06-28 10:33     ` Lee Jones
2021-06-30 10:57   ` Lee Jones
2021-06-25  7:42 ` [PATCH v2 5/5] hwmon: intel-m10-bmc-hwmon: add n5010 sensors Martin Hundebøll
2021-06-28  6:00   ` Xu Yilun
2021-06-28 14:11     ` Guenter Roeck
2021-06-28 16:35   ` Guenter Roeck
2021-06-28 17:28     ` Moritz Fischer
2021-06-29  1:40       ` Xu Yilun

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