From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0BCDC11F64 for ; Mon, 28 Jun 2021 17:42:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A7E9761C65 for ; Mon, 28 Jun 2021 17:42:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A7E9761C65 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 27C716E4FF; Mon, 28 Jun 2021 17:42:24 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id E44586E4FF for ; Mon, 28 Jun 2021 17:42:22 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10029"; a="195298467" X-IronPort-AV: E=Sophos;i="5.83,306,1616482800"; d="scan'208";a="195298467" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2021 10:42:22 -0700 X-IronPort-AV: E=Sophos;i="5.83,306,1616482800"; d="scan'208";a="407830838" Received: from ideak-desk.fi.intel.com ([10.237.68.141]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2021 10:42:20 -0700 Date: Mon, 28 Jun 2021 20:42:16 +0300 From: Imre Deak To: Anshuman Gupta Message-ID: <20210628174216.GD2494908@ideak-desk.fi.intel.com> References: <20210601100228.6064-1-anshuman.gupta@intel.com> <20210601100228.6064-2-anshuman.gupta@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210601100228.6064-2-anshuman.gupta@intel.com> Subject: Re: [Intel-gfx] [RFC v3 1/2] drm/i915/dg1: Adjust the AUDIO power domain X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Jun 01, 2021 at 03:32:27PM +0530, Anshuman Gupta wrote: > DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power > well. Adjusting the power domain accordingly to > POWER_DOMAIN_AUDIO_VERBS for audio detection and POWER_DOMAIN_AUDIO > for audio playback. > = > Cc: Ville Syrj=E4l=E4 > Cc: Kai Vehmanen > Cc: Uma Shankar > Cc: Imre Deak > Signed-off-by: Anshuman Gupta > --- > .../drm/i915/display/intel_display_power.c | 382 +++++++++++++++++- > .../drm/i915/display/intel_display_power.h | 1 + > 2 files changed, 382 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers= /gpu/drm/i915/display/intel_display_power.c > index 2f7d1664c473..da5894138e8b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -106,6 +106,8 @@ intel_display_power_domain_str(enum intel_display_pow= er_domain domain) > return "PORT_OTHER"; > case POWER_DOMAIN_VGA: > return "VGA"; > + case POWER_DOMAIN_AUDIO_VERBS: > + return "AUDIO_VERBS"; Maybe better named AUDIO_MMIO, as VERBS are a subset of that imo. > case POWER_DOMAIN_AUDIO: > return "AUDIO"; Let's also rename this to AUDIO_PLAYBACK for clarity. > case POWER_DOMAIN_AUX_A: > @@ -2499,6 +2501,7 @@ intel_display_power_put_mask_in_set(struct drm_i915= _private *i915, > BIT_ULL(POWER_DOMAIN_PORT_DSI) | \ > BIT_ULL(POWER_DOMAIN_PORT_CRT) | \ > BIT_ULL(POWER_DOMAIN_VGA) | \ > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > BIT_ULL(POWER_DOMAIN_AUX_C) | \ > @@ -2549,6 +2552,7 @@ intel_display_power_put_mask_in_set(struct drm_i915= _private *i915, > BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ > BIT_ULL(POWER_DOMAIN_PORT_DSI) | \ > BIT_ULL(POWER_DOMAIN_VGA) | \ > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > BIT_ULL(POWER_DOMAIN_AUX_C) | \ > @@ -2582,6 +2586,7 @@ intel_display_power_put_mask_in_set(struct drm_i915= _private *i915, > BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ > BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ > BIT_ULL(POWER_DOMAIN_VGA) | \ > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > BIT_ULL(POWER_DOMAIN_INIT)) > = > @@ -2598,6 +2603,7 @@ intel_display_power_put_mask_in_set(struct drm_i915= _private *i915, > BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \ > BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ > BIT_ULL(POWER_DOMAIN_VGA) | \ > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > BIT_ULL(POWER_DOMAIN_INIT)) > = > @@ -2616,6 +2622,7 @@ intel_display_power_put_mask_in_set(struct drm_i915= _private *i915, > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > BIT_ULL(POWER_DOMAIN_AUX_C) | \ > BIT_ULL(POWER_DOMAIN_AUX_D) | \ > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > BIT_ULL(POWER_DOMAIN_VGA) | \ > BIT_ULL(POWER_DOMAIN_INIT)) > @@ -2651,6 +2658,7 @@ intel_display_power_put_mask_in_set(struct drm_i915= _private *i915, > BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > BIT_ULL(POWER_DOMAIN_AUX_C) | \ > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > BIT_ULL(POWER_DOMAIN_VGA) | \ > BIT_ULL(POWER_DOMAIN_INIT)) > @@ -2684,6 +2692,7 @@ intel_display_power_put_mask_in_set(struct drm_i915= _private *i915, > BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > BIT_ULL(POWER_DOMAIN_AUX_C) | \ > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > BIT_ULL(POWER_DOMAIN_VGA) | \ > BIT_ULL(POWER_DOMAIN_INIT)) > @@ -2739,6 +2748,7 @@ intel_display_power_put_mask_in_set(struct drm_i915= _private *i915, > BIT_ULL(POWER_DOMAIN_AUX_C) | \ > BIT_ULL(POWER_DOMAIN_AUX_D) | \ > BIT_ULL(POWER_DOMAIN_AUX_F) | \ > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > BIT_ULL(POWER_DOMAIN_VGA) | \ > BIT_ULL(POWER_DOMAIN_INIT)) > @@ -2821,6 +2831,7 @@ intel_display_power_put_mask_in_set(struct drm_i915= _private *i915, > BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \ > BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \ > BIT_ULL(POWER_DOMAIN_VGA) | \ > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > BIT_ULL(POWER_DOMAIN_INIT)) > /* > @@ -2913,6 +2924,7 @@ intel_display_power_put_mask_in_set(struct drm_i915= _private *i915, > BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \ > BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \ > BIT_ULL(POWER_DOMAIN_VGA) | \ > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > BIT_ULL(POWER_DOMAIN_INIT)) > = > @@ -2983,6 +2995,7 @@ intel_display_power_put_mask_in_set(struct drm_i915= _private *i915, > RKL_PW_4_POWER_DOMAINS | \ > BIT_ULL(POWER_DOMAIN_PIPE_B) | \ > BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ > + BIT_ULL(POWER_DOMAIN_AUDIO_VERBS) | \ > BIT_ULL(POWER_DOMAIN_AUDIO) | \ > BIT_ULL(POWER_DOMAIN_VGA) | \ > BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ > @@ -3020,6 +3033,42 @@ intel_display_power_put_mask_in_set(struct drm_i91= 5_private *i915, > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > BIT_ULL(POWER_DOMAIN_INIT)) > = > +/* > + * DG1 Audio MMIO/VERBS lies in PG0 power well. > + */ > + > +#define DG1_PW_2_POWER_DOMAINS ( \ > + DG1_PW_3_POWER_DOMAINS | \ > + BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \ > + BIT_ULL(POWER_DOMAIN_INIT)) Let's keep the order for other platforms and move DG1_PW_2 after the DG1_PW_3 definition. > + > +#define DG1_PW_3_POWER_DOMAINS ( \ > + TGL_PW_4_POWER_DOMAINS | \ > + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ > + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \ > + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \ > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \ > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \ > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \ > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \ > + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \ DG1 has only TC1/2 DDIs. > + BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \ > + BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \ > + BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \ > + BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \ > + BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \ > + BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \ Only AUX_USBC1/2. > + BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \ > + BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \ > + BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \ > + BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \ > + BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \ > + BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \ No TBT on DG1. > + BIT_ULL(POWER_DOMAIN_VGA) | \ > + BIT_ULL(POWER_DOMAIN_AUDIO) | \ > + BIT_ULL(POWER_DOMAIN_INIT)) > + What about DC3co? I read about this change on HSD 1407435623: "DC3 clock off mode is not possible with this mode since cdclk cannot be tu= rned off." Will DMC take care of this? Could you please open a ticket to clarify the "Audio codec idle and disabled." DC3co requirement text wrt. this change on the BSpec/49196 page? > /* > * XE_LPD Power Domains > * What about the D13 platform? Looks like it has the same split between the MMIO and playback audio functionality. > @@ -4497,6 +4546,335 @@ static const struct i915_power_well_desc tgl_powe= r_wells[] =3D { > }, > }; > = > +static const struct i915_power_well_desc dg1_power_wells[] =3D { Let's follow the order of platform definitions and move this after the rkl power well list. > + { > + .name =3D "always-on", > + .always_on =3D true, > + .domains =3D POWER_DOMAIN_MASK, > + .ops =3D &i9xx_always_on_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + }, > + { > + .name =3D "power well 1", > + /* Handled by the DMC firmware */ > + .always_on =3D true, > + .domains =3D 0, > + .ops =3D &hsw_power_well_ops, > + .id =3D SKL_DISP_PW_1, > + { > + .hsw.regs =3D &hsw_power_well_regs, > + .hsw.idx =3D ICL_PW_CTL_IDX_PW_1, > + .hsw.has_fuses =3D true, > + }, > + }, > + { > + .name =3D "DC off", > + .domains =3D TGL_DISPLAY_DC_OFF_POWER_DOMAINS, > + .ops =3D &gen9_dc_off_power_well_ops, > + .id =3D SKL_DISP_DC_OFF, > + }, > + { > + .name =3D "power well 2", > + .domains =3D DG1_PW_2_POWER_DOMAINS, > + .ops =3D &hsw_power_well_ops, > + .id =3D SKL_DISP_PW_2, > + { > + .hsw.regs =3D &hsw_power_well_regs, > + .hsw.idx =3D ICL_PW_CTL_IDX_PW_2, > + .hsw.has_fuses =3D true, > + }, > + }, > + { > + .name =3D "power well 3", > + .domains =3D DG1_PW_3_POWER_DOMAINS, > + .ops =3D &hsw_power_well_ops, > + .id =3D ICL_DISP_PW_3, > + { > + .hsw.regs =3D &hsw_power_well_regs, > + .hsw.idx =3D ICL_PW_CTL_IDX_PW_3, > + .hsw.irq_pipe_mask =3D BIT(PIPE_B), > + .hsw.has_vga =3D true, > + .hsw.has_fuses =3D true, > + }, > + }, > + { > + .name =3D "DDI A IO", > + .domains =3D ICL_DDI_IO_A_POWER_DOMAINS, > + .ops =3D &hsw_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_ddi_power_well_regs, > + .hsw.idx =3D ICL_PW_CTL_IDX_DDI_A, > + } > + }, > + { > + .name =3D "DDI B IO", > + .domains =3D ICL_DDI_IO_B_POWER_DOMAINS, > + .ops =3D &hsw_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_ddi_power_well_regs, > + .hsw.idx =3D ICL_PW_CTL_IDX_DDI_B, > + } > + }, > + { > + .name =3D "DDI C IO", > + .domains =3D ICL_DDI_IO_C_POWER_DOMAINS, > + .ops =3D &hsw_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_ddi_power_well_regs, > + .hsw.idx =3D ICL_PW_CTL_IDX_DDI_C, > + } > + }, No DDI C on DG1. > + { > + .name =3D "DDI IO TC1", > + .domains =3D TGL_DDI_IO_TC1_POWER_DOMAINS, > + .ops =3D &hsw_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_ddi_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_DDI_TC1, > + }, > + }, > + { > + .name =3D "DDI IO TC2", > + .domains =3D TGL_DDI_IO_TC2_POWER_DOMAINS, > + .ops =3D &hsw_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_ddi_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_DDI_TC2, > + }, > + }, > + { > + .name =3D "DDI IO TC3", > + .domains =3D TGL_DDI_IO_TC3_POWER_DOMAINS, > + .ops =3D &hsw_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_ddi_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_DDI_TC3, > + }, > + }, > + { > + .name =3D "DDI IO TC4", > + .domains =3D TGL_DDI_IO_TC4_POWER_DOMAINS, > + .ops =3D &hsw_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_ddi_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_DDI_TC4, > + }, > + }, > + { > + .name =3D "DDI IO TC5", > + .domains =3D TGL_DDI_IO_TC5_POWER_DOMAINS, > + .ops =3D &hsw_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_ddi_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_DDI_TC5, > + }, > + }, > + { > + .name =3D "DDI IO TC6", > + .domains =3D TGL_DDI_IO_TC6_POWER_DOMAINS, > + .ops =3D &hsw_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_ddi_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_DDI_TC6, > + }, > + }, Only DDI TC1/2 on DG1. > + { > + .name =3D "AUX A", > + .domains =3D TGL_AUX_A_IO_POWER_DOMAINS, > + .ops =3D &icl_aux_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_aux_power_well_regs, > + .hsw.idx =3D ICL_PW_CTL_IDX_AUX_A, > + }, > + }, > + { > + .name =3D "AUX B", > + .domains =3D TGL_AUX_B_IO_POWER_DOMAINS, > + .ops =3D &icl_aux_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_aux_power_well_regs, > + .hsw.idx =3D ICL_PW_CTL_IDX_AUX_B, > + }, > + }, > + { > + .name =3D "AUX C", > + .domains =3D TGL_AUX_C_IO_POWER_DOMAINS, > + .ops =3D &icl_aux_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_aux_power_well_regs, > + .hsw.idx =3D ICL_PW_CTL_IDX_AUX_C, > + }, > + }, No AUX C on DG1. > + { > + .name =3D "AUX USBC1", > + .domains =3D TGL_AUX_IO_USBC1_POWER_DOMAINS, > + .ops =3D &icl_aux_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_aux_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_AUX_TC1, > + .hsw.is_tc_tbt =3D false, > + }, > + }, > + { > + .name =3D "AUX USBC2", > + .domains =3D TGL_AUX_IO_USBC2_POWER_DOMAINS, > + .ops =3D &icl_aux_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_aux_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_AUX_TC2, > + .hsw.is_tc_tbt =3D false, > + }, > + }, > + { > + .name =3D "AUX USBC3", > + .domains =3D TGL_AUX_IO_USBC3_POWER_DOMAINS, > + .ops =3D &icl_aux_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_aux_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_AUX_TC3, > + .hsw.is_tc_tbt =3D false, > + }, > + }, > + { > + .name =3D "AUX USBC4", > + .domains =3D TGL_AUX_IO_USBC4_POWER_DOMAINS, > + .ops =3D &icl_aux_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_aux_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_AUX_TC4, > + .hsw.is_tc_tbt =3D false, > + }, > + }, > + { > + .name =3D "AUX USBC5", > + .domains =3D TGL_AUX_IO_USBC5_POWER_DOMAINS, > + .ops =3D &icl_aux_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_aux_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_AUX_TC5, > + .hsw.is_tc_tbt =3D false, > + }, > + }, > + { > + .name =3D "AUX USBC6", > + .domains =3D TGL_AUX_IO_USBC6_POWER_DOMAINS, > + .ops =3D &icl_aux_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_aux_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_AUX_TC6, > + .hsw.is_tc_tbt =3D false, > + }, > + }, Only AUX USBC1/2 on DG1. > + { > + .name =3D "AUX TBT1", > + .domains =3D TGL_AUX_IO_TBT1_POWER_DOMAINS, > + .ops =3D &icl_aux_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_aux_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_AUX_TBT1, > + .hsw.is_tc_tbt =3D true, > + }, > + }, > + { > + .name =3D "AUX TBT2", > + .domains =3D TGL_AUX_IO_TBT2_POWER_DOMAINS, > + .ops =3D &icl_aux_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_aux_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_AUX_TBT2, > + .hsw.is_tc_tbt =3D true, > + }, > + }, > + { > + .name =3D "AUX TBT3", > + .domains =3D TGL_AUX_IO_TBT3_POWER_DOMAINS, > + .ops =3D &icl_aux_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_aux_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_AUX_TBT3, > + .hsw.is_tc_tbt =3D true, > + }, > + }, > + { > + .name =3D "AUX TBT4", > + .domains =3D TGL_AUX_IO_TBT4_POWER_DOMAINS, > + .ops =3D &icl_aux_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_aux_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_AUX_TBT4, > + .hsw.is_tc_tbt =3D true, > + }, > + }, > + { > + .name =3D "AUX TBT5", > + .domains =3D TGL_AUX_IO_TBT5_POWER_DOMAINS, > + .ops =3D &icl_aux_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_aux_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_AUX_TBT5, > + .hsw.is_tc_tbt =3D true, > + }, > + }, > + { > + .name =3D "AUX TBT6", > + .domains =3D TGL_AUX_IO_TBT6_POWER_DOMAINS, > + .ops =3D &icl_aux_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &icl_aux_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_AUX_TBT6, > + .hsw.is_tc_tbt =3D true, > + }, > + }, No TBT on DG1. > + { > + .name =3D "power well 4", > + .domains =3D TGL_PW_4_POWER_DOMAINS, > + .ops =3D &hsw_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &hsw_power_well_regs, > + .hsw.idx =3D ICL_PW_CTL_IDX_PW_4, > + .hsw.has_fuses =3D true, > + .hsw.irq_pipe_mask =3D BIT(PIPE_C), > + } > + }, > + { > + .name =3D "power well 5", > + .domains =3D TGL_PW_5_POWER_DOMAINS, > + .ops =3D &hsw_power_well_ops, > + .id =3D DISP_PW_ID_NONE, > + { > + .hsw.regs =3D &hsw_power_well_regs, > + .hsw.idx =3D TGL_PW_CTL_IDX_PW_5, > + .hsw.has_fuses =3D true, > + .hsw.irq_pipe_mask =3D BIT(PIPE_D), > + }, > + }, > +}; > + > static const struct i915_power_well_desc rkl_power_wells[] =3D { > { > .name =3D "always-on", > @@ -5110,9 +5488,11 @@ int intel_power_domains_init(struct drm_i915_priva= te *dev_priv) > err =3D 0; > } else if (DISPLAY_VER(dev_priv) >=3D 13) { > err =3D set_power_wells(power_domains, xelpd_power_wells); > - } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { > + } else if (IS_ALDERLAKE_S(dev_priv)) { > err =3D set_power_wells_mask(power_domains, tgl_power_wells, > BIT_ULL(TGL_DISP_PW_TC_COLD_OFF)); > + } else if (IS_DG1(dev_priv)) { > + err =3D set_power_wells(power_domains, dg1_power_wells); Let's move this after the D13 case. > } else if (IS_ROCKETLAKE(dev_priv)) { > err =3D set_power_wells(power_domains, rkl_power_wells); > } else if (DISPLAY_VER(dev_priv) =3D=3D 12) { > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers= /gpu/drm/i915/display/intel_display_power.h > index 4f0917df4375..d9c824264ac9 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.h > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h > @@ -76,6 +76,7 @@ enum intel_display_power_domain { > POWER_DOMAIN_PORT_CRT, > POWER_DOMAIN_PORT_OTHER, > POWER_DOMAIN_VGA, > + POWER_DOMAIN_AUDIO_VERBS, > POWER_DOMAIN_AUDIO, > POWER_DOMAIN_AUX_A, > POWER_DOMAIN_AUX_B, > -- = > 2.26.2 > = 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