From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3525CC11F68 for ; Fri, 2 Jul 2021 17:38:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E6844613E9 for ; Fri, 2 Jul 2021 17:38:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E6844613E9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZdjXX6rQe+Ulf6tOQNK2KQR5yAHzimxx5qdU5U74fHg=; b=KtuWGxd8LiwRD4 E3CQYm6drBD/9y3YPVwa7V4OhpB1wGYz8z+TvcqN3r5pu3YkMfQi0a8Q6vc74um6RcFiDBpBCC952 9F0ure+OOqdurUyAyzffVZFQnONMf1/WRisHQPRgBUnsKzk69G3x8/4k44RE6YGJnVprT02LMDize UZSYiPW1kyIaYp9aZECLbs0s32K4H9Zs8kUqc+m/vyPuEbUTgebmA9ncizUUC9iMFAnWhEK6JvJQk IotO2HsGztp8TxJnMsOfqn3yjewIbCo7CHxHlPkusEht9ankBLiwX2/D7Dhl7Iza0A7X6HAlZbR9s VE9/5uj+FNpPl0o451YQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lzN6S-003dUP-Uf; Fri, 02 Jul 2021 17:37:25 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lzN6P-003dTz-Jh for linux-arm-kernel@lists.infradead.org; Fri, 02 Jul 2021 17:37:23 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 3204E611CB; Fri, 2 Jul 2021 17:37:20 +0000 (UTC) Date: Fri, 2 Jul 2021 18:37:17 +0100 From: Catalin Marinas To: Peter Collingbourne Cc: Vincenzo Frascino , Will Deacon , Evgenii Stepanov , Linux ARM Subject: Re: [PATCH] arm64: mte: avoid TFSR related operations unless in async mode Message-ID: <20210702173717.GB685@arm.com> References: <20210701031448.2173-1-pcc@google.com> <20210701173738.GI12484@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210702_103721_711469_6333A82E X-CRM114-Status: GOOD ( 26.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jul 01, 2021 at 11:11:34AM -0700, Peter Collingbourne wrote: > On Thu, Jul 1, 2021 at 10:37 AM Catalin Marinas wrote: > > On Wed, Jun 30, 2021 at 08:14:48PM -0700, Peter Collingbourne wrote: > > > /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */ > > > @@ -151,11 +157,14 @@ alternative_else_nop_endif > > > .endm > > > > > > /* Clear the MTE asynchronous tag check faults */ > > > - .macro clear_mte_async_tcf > > > + .macro clear_mte_async_tcf thread_sctlr > > > #ifdef CONFIG_ARM64_MTE > > > alternative_if ARM64_MTE > > > + /* See comment in check_mte_async_tcf above. */ > > > + tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f > > > dsb ish > > > msr_s SYS_TFSRE0_EL1, xzr > > > +1: > > > > Here, maybe, as we have a DSB. > > Yes, disabling clear_mte_async_tcf offered an order of magnitude > larger speedup than disabing check_mte_async_tcf, presumably due to > the DSB. I would reckon though that if we're going to make some of the > code conditional on TCF we might as well make all of it conditional in > order to get the maximum possible benefit. I'd like to avoid a TBZ on sctlr_user if it's not necessary. I reckon the big CPUs would prefer async mode anyway. > Nevertheless, isn't it the case that disabling check_mte_async_tcf for > non-ASYNC tasks is necessary for correctness if we want to disable > clear_mte_async_tcf? Imagine that we just disable clear_mte_async_tcf, > and then we get a tag check failing uaccess in a TCF=ASYNC task which > then gets preempted by a TCF=NONE task which will skip clear on kernel > exit. If we don't disable check on kernel entry then I believe that we > will get a false positive tag check fault in the TCF=NONE task the > next time it enters the kernel. You are right, only doing one side would cause potential issues. The uaccess routines honour the SCTLR_EL1.TCF0 setting (it's been corrected in the architecture pseudocode some months ago). If we zero TFSRE0_EL1 in mte_tread_switch(), it should cover your case. This shouldn't be expensive since we already have a DSB on that path. I'm not sure it's better than your proposal but not allowing the TFSRE0_EL1 state to span multiple threads makes reasoning about it a bit easier. If the above context switch zeroing doesn't work, we could go ahead with your patch. But since TFSRE0_EL1 != 0 is a rare event and we expect to run in async mode on some CPUs, we could move the TBZ on sctlr_user in check_mte_async_tcf after the tbz for the actual TFSRE0_EL1. IOW, only check it prior to setting the TIF flag. BTW, I think currently on entry we can avoid zeroing TFSRE0_EL1 since we clear it on return anyway, so one less instruction (irrespective of your patch). -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel