From: Catalin Marinas <catalin.marinas@arm.com>
To: Peter Collingbourne <pcc@google.com>
Cc: Vincenzo Frascino <vincenzo.frascino@arm.com>,
Will Deacon <will@kernel.org>,
Andrey Konovalov <andreyknvl@gmail.com>,
Evgenii Stepanov <eugenis@google.com>,
Szabolcs Nagy <szabolcs.nagy@arm.com>,
Tejas Belagod <Tejas.Belagod@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm64: mte: switch GCR_EL1 on task switch rather than entry/exit
Date: Fri, 2 Jul 2021 18:44:50 +0100 [thread overview]
Message-ID: <20210702174450.GC685@arm.com> (raw)
In-Reply-To: <20210702031922.1291398-1-pcc@google.com>
On Thu, Jul 01, 2021 at 08:19:22PM -0700, Peter Collingbourne wrote:
> Accessing GCR_EL1 and issuing an ISB can be expensive on some
> microarchitectures. To avoid taking this performance hit on every
> kernel entry/exit, switch GCR_EL1 on task switch rather than
> entry/exit.
Is it the ISB that's causing issues or the MRS/MSR as well? I think we
can avoid the ISB when PtrAuth is enabled by shuffling the entry code a
bit. We can also simplify the mte_set_gcr macro to avoid an MRS.
--
Catalin
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next prev parent reply other threads:[~2021-07-02 17:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-02 3:19 [PATCH] arm64: mte: switch GCR_EL1 on task switch rather than entry/exit Peter Collingbourne
2021-07-02 17:44 ` Catalin Marinas [this message]
2021-07-02 18:39 ` Peter Collingbourne
2021-07-05 14:17 ` Catalin Marinas
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