* [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations
@ 2021-07-02 20:45 Ville Syrjala
2021-07-02 20:45 ` [Intel-gfx] [PATCH 1/8] drm/i915/fbc: Rewrite the FBC tiling check a bit Ville Syrjala
` (13 more replies)
0 siblings, 14 replies; 22+ messages in thread
From: Ville Syrjala @ 2021-07-02 20:45 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The way we calculate the CFB stride/size is kind of a mess, and
I'm not sure if we're even allocating enough stolen memory always.
Let's make it all more straightforward, and add some new related
workarounds as well.
Ville Syrjälä (8):
drm/i915/fbc: Rewrite the FBC tiling check a bit
drm/i915/fbc: Extract intel_fbc_update()
drm/i915/fbc: Move the "recompress on activate" to a central place
drm/i915/fbc: Polish the skl+ FBC stride override handling
drm/i915/fbc: Rework cfb stride/size calculations
drm/i915/fbc: Align FBC segments to 512B on glk+
drm/i915/fbc: Implement Wa_16011863758 for icl+
drm/i915/fbc: Allow higher compression limits on FBC1
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 242 ++++++++++++-------
drivers/gpu/drm/i915/display/intel_fbc.h | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/i915_reg.h | 9 +-
5 files changed, 168 insertions(+), 96 deletions(-)
--
2.31.1
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 1/8] drm/i915/fbc: Rewrite the FBC tiling check a bit
2021-07-02 20:45 [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
@ 2021-07-02 20:45 ` Ville Syrjala
2021-07-02 20:45 ` [Intel-gfx] [PATCH 2/8] drm/i915/fbc: Extract intel_fbc_update() Ville Syrjala
` (12 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2021-07-02 20:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Write the tiling check in a nicer form. No functional
changes due to Y-tile scanout being a gen9+ feature.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 82effb64a3b9..85cfb0da8576 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -675,11 +675,9 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
{
switch (modifier) {
case DRM_FORMAT_MOD_LINEAR:
- if (DISPLAY_VER(dev_priv) >= 9)
- return true;
- return false;
- case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
+ return DISPLAY_VER(dev_priv) >= 9;
+ case I915_FORMAT_MOD_X_TILED:
return true;
default:
return false;
--
2.31.1
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^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 2/8] drm/i915/fbc: Extract intel_fbc_update()
2021-07-02 20:45 [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
2021-07-02 20:45 ` [Intel-gfx] [PATCH 1/8] drm/i915/fbc: Rewrite the FBC tiling check a bit Ville Syrjala
@ 2021-07-02 20:45 ` Ville Syrjala
2021-07-02 20:45 ` [Intel-gfx] [PATCH 3/8] drm/i915/fbc: Move the "recompress on activate" to a central place Ville Syrjala
` (11 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2021-07-02 20:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pull the fbc enable vs. disable stuff into a small helper so
we don't have to have it pollute the higher level modeset code.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +---
drivers/gpu/drm/i915/display/intel_fbc.c | 26 ++++++++++++++++++--
drivers/gpu/drm/i915/display/intel_fbc.h | 2 +-
3 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 026c28c612f0..ab395d61963c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10252,10 +10252,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
intel_encoders_update_pipe(state, crtc);
}
- if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
- intel_fbc_disable(crtc);
- else
- intel_fbc_enable(state, crtc);
+ intel_fbc_update(state, crtc);
/* Perform vblank evasion around commit operation */
intel_pipe_update_start(new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 85cfb0da8576..8b721c8cdd6c 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1244,8 +1244,8 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
* intel_fbc_enable multiple times for the same pipe without an
* intel_fbc_disable in the middle, as long as it is deactivated.
*/
-void intel_fbc_enable(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+static void intel_fbc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_plane *plane = to_intel_plane(crtc->base.primary);
@@ -1320,6 +1320,28 @@ void intel_fbc_disable(struct intel_crtc *crtc)
mutex_unlock(&fbc->lock);
}
+/**
+ * intel_fbc_update: enable/disable FBC on the CRTC
+ * @state: atomic state
+ * @crtc: the CRTC
+ *
+ * This function checks if the given CRTC was chosen for FBC, then enables it if
+ * possible. Notice that it doesn't activate FBC. It is valid to call
+ * intel_fbc_update multiple times for the same pipe without an
+ * intel_fbc_disable in the middle.
+ */
+void intel_fbc_update(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (crtc_state->update_pipe && !crtc_state->enable_fbc)
+ intel_fbc_disable(crtc);
+ else
+ intel_fbc_enable(state, crtc);
+}
+
/**
* intel_fbc_global_disable - globally disable FBC
* @dev_priv: i915 device instance
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 6dc1edefe81b..b97d908738e6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -24,7 +24,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state,
void intel_fbc_post_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_fbc_init(struct drm_i915_private *dev_priv);
-void intel_fbc_enable(struct intel_atomic_state *state,
+void intel_fbc_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void intel_fbc_disable(struct intel_crtc *crtc);
void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
--
2.31.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 3/8] drm/i915/fbc: Move the "recompress on activate" to a central place
2021-07-02 20:45 [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
2021-07-02 20:45 ` [Intel-gfx] [PATCH 1/8] drm/i915/fbc: Rewrite the FBC tiling check a bit Ville Syrjala
2021-07-02 20:45 ` [Intel-gfx] [PATCH 2/8] drm/i915/fbc: Extract intel_fbc_update() Ville Syrjala
@ 2021-07-02 20:45 ` Ville Syrjala
2021-07-02 20:45 ` [Intel-gfx] [PATCH 4/8] drm/i915/fbc: Polish the skl+ FBC stride override handling Ville Syrjala
` (10 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2021-07-02 20:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On ILK+ we current do a nuke right after activating FBC. If my
memory isn't playing tricks on me this is actially required if
FBC didn't stay disabled for a full frame. In that case the
deactivate+reactivate may not invalidate the cfb. I'd have to
double chekc to be sure though.
So let's keep the nuke, and just extend it backwards to cover
all the platforms by doing it a bit higher up.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 8b721c8cdd6c..c9cde96f330b 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -232,16 +232,16 @@ static void i965_fbc_recompress(struct drm_i915_private *dev_priv)
/* This function forces a CFB recompression through the nuke operation. */
static void snb_fbc_recompress(struct drm_i915_private *dev_priv)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
-
- trace_intel_fbc_nuke(fbc->crtc);
-
intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE);
intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
}
static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
{
+ struct intel_fbc *fbc = &dev_priv->fbc;
+
+ trace_intel_fbc_nuke(fbc->crtc);
+
if (DISPLAY_VER(dev_priv) >= 6)
snb_fbc_recompress(dev_priv);
else if (DISPLAY_VER(dev_priv) >= 4)
@@ -280,8 +280,6 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
params->fence_y_offset);
/* enable it... */
intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
-
- intel_fbc_recompress(dev_priv);
}
static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
@@ -339,8 +337,6 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
dpfc_ctl |= FBC_CTL_FALSE_COLOR;
intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
-
- intel_fbc_recompress(dev_priv);
}
static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
@@ -402,6 +398,12 @@ bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
return dev_priv->fbc.active;
}
+static void intel_fbc_activate(struct drm_i915_private *dev_priv)
+{
+ intel_fbc_hw_activate(dev_priv);
+ intel_fbc_recompress(dev_priv);
+}
+
static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
const char *reason)
{
@@ -1088,7 +1090,7 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc)
return;
if (!fbc->busy_bits)
- intel_fbc_hw_activate(dev_priv);
+ intel_fbc_activate(dev_priv);
else
intel_fbc_deactivate(dev_priv, "frontbuffer write");
}
--
2.31.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 4/8] drm/i915/fbc: Polish the skl+ FBC stride override handling
2021-07-02 20:45 [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
` (2 preceding siblings ...)
2021-07-02 20:45 ` [Intel-gfx] [PATCH 3/8] drm/i915/fbc: Move the "recompress on activate" to a central place Ville Syrjala
@ 2021-07-02 20:45 ` Ville Syrjala
2021-07-05 8:02 ` Jani Nikula
2021-07-02 20:46 ` [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb stride/size calculations Ville Syrjala
` (9 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Ville Syrjala @ 2021-07-02 20:45 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Polish the FBC stride override stuff:
- just call it override_cfb_stride since it'll be used on
more gens later
- Use REG_BIT() & co. for the registers and give everything
CHICKEN_ prefix since glk+ will have a different register
for this
- Use intel_de_rmw() for the RMW
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 27 ++++++++++++------------
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
3 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index c9cde96f330b..f5cbbc53837c 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -306,14 +306,15 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
/* Display WA #0529: skl, kbl, bxt. */
if (DISPLAY_VER(dev_priv) == 9) {
- u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4);
+ u32 val = 0;
- val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
+ if (params->override_cfb_stride)
+ val |= CHICKEN_FBC_STRIDE_OVERRIDE |
+ CHICKEN_FBC_STRIDE(params->override_cfb_stride);
- if (params->gen9_wa_cfb_stride)
- val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
-
- intel_de_write(dev_priv, CHICKEN_MISC_4, val);
+ intel_de_rmw(dev_priv, CHICKEN_MISC_4,
+ CHICKEN_FBC_STRIDE_OVERRIDE |
+ CHICKEN_FBC_STRIDE_MASK, val);
}
dpfc_ctl = 0;
@@ -749,7 +750,7 @@ static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
fbc->compressed_fb.size * fbc->limit;
}
-static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
+static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv)
{
struct intel_fbc *fbc = &dev_priv->fbc;
struct intel_fbc_state_cache *cache = &fbc->state_cache;
@@ -761,11 +762,11 @@ static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
return 0;
}
-static bool intel_fbc_gen9_wa_cfb_stride_changed(struct drm_i915_private *dev_priv)
+static bool intel_fbc_override_cfb_stride_changed(struct drm_i915_private *dev_priv)
{
struct intel_fbc *fbc = &dev_priv->fbc;
- return fbc->params.gen9_wa_cfb_stride != intel_fbc_gen9_wa_cfb_stride(dev_priv);
+ return fbc->params.override_cfb_stride != intel_fbc_override_cfb_stride(dev_priv);
}
static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
@@ -950,7 +951,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
- params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride;
+ params->override_cfb_stride = cache->override_cfb_stride;
params->plane_visible = cache->plane.visible;
}
@@ -984,7 +985,7 @@ static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
return false;
- if (params->gen9_wa_cfb_stride != cache->gen9_wa_cfb_stride)
+ if (params->override_cfb_stride != cache->override_cfb_stride)
return false;
return true;
@@ -1266,7 +1267,7 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
if (fbc->crtc) {
if (fbc->crtc != crtc ||
(!intel_fbc_cfb_size_changed(dev_priv) &&
- !intel_fbc_gen9_wa_cfb_stride_changed(dev_priv)))
+ !intel_fbc_override_cfb_stride_changed(dev_priv)))
goto out;
__intel_fbc_disable(dev_priv);
@@ -1288,7 +1289,7 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
goto out;
}
- cache->gen9_wa_cfb_stride = intel_fbc_gen9_wa_cfb_stride(dev_priv);
+ cache->override_cfb_stride = intel_fbc_override_cfb_stride(dev_priv);
drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n",
pipe_name(crtc->pipe));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6dff4ca01241..91a2d2425fd3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -401,7 +401,7 @@ struct intel_fbc {
} fb;
unsigned int fence_y_offset;
- u16 gen9_wa_cfb_stride;
+ u16 override_cfb_stride;
u16 interval;
s8 fence_id;
bool psr2_active;
@@ -428,7 +428,7 @@ struct intel_fbc {
int cfb_size;
unsigned int fence_y_offset;
- u16 gen9_wa_cfb_stride;
+ u16 override_cfb_stride;
u16 interval;
s8 fence_id;
bool plane_visible;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 16a19239d86d..ab2bd4837efd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8131,8 +8131,9 @@ enum {
#define GLK_CL0_PWR_DOWN (1 << 10)
#define CHICKEN_MISC_4 _MMIO(0x4208c)
-#define FBC_STRIDE_OVERRIDE (1 << 13)
-#define FBC_STRIDE_MASK 0x1FFF
+#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
+#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
+#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
#define _CHICKEN_PIPESL_1_A 0x420b0
#define _CHICKEN_PIPESL_1_B 0x420b4
--
2.31.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb stride/size calculations
2021-07-02 20:45 [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
` (3 preceding siblings ...)
2021-07-02 20:45 ` [Intel-gfx] [PATCH 4/8] drm/i915/fbc: Polish the skl+ FBC stride override handling Ville Syrjala
@ 2021-07-02 20:46 ` Ville Syrjala
2021-09-06 5:23 ` Shankar, Uma
2021-07-02 20:46 ` [Intel-gfx] [PATCH 6/8] drm/i915/fbc: Align FBC segments to 512B on glk+ Ville Syrjala
` (8 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Ville Syrjala @ 2021-07-02 20:46 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The code to calculate the cfb stride/size is a bit of mess.
The cfb size is getting calculated based purely on the plane
stride and plane height. That doesn't account for extra
alignment we want for the cfb stride. The gen9 override
stride OTOH is just calculated based on the plane width, and
it does try to make things more aligned but any extra alignment
added there is not considered in the cfb size calculations.
So not at all convinced this is working as intended. Additionally
the compression limit handling is split between the cfb allocation
code and g4x_dpfc_ctl_limit() (for the 16bpp case), which is just
confusing.
Let's streamline the whole thing:
- Start with the plane stride, convert that into cfb stride (cfb is
always 4 bytes per pixel). All the calculations will assume 1:1
compression limit since that will give us the max values, and we
don't yet know how much stolen memory we will be able to allocate
- Align the cfb stride to 512 bytes on modern platforms. This guarantees
the 4 line segment will be 512 byte aligned regardles of the final
compression limit we choose later. The 512 byte alignment for the
segment is required by at least some of the platforms, and just doing
it always seems like the easiest option
- Figure out if we need to use the override stride or not. For X-tiled
it's never needed since the plane stride is already 512 byte aligned,
for Y-tiled it will be needed if the plane stride is not a multiple
of 512 bytes, and for linear it's apparently always needed because the
hardware miscalculates the cfb stride as PLANE_STRIDE*512 instead of
the PLANE_STRIDE*64 that it use with linear.
- The cfb size will be calculated based on the aligned cfb stride to
guarantee we actually reserved enough stolen memory and the FBC hw
won't end up scribbling over whatever else is allocated in stolen
- The compression limit handling we just do fully in the cfb allocation
code to make things less confusing
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 141 ++++++++++++++---------
drivers/gpu/drm/i915/i915_drv.h | 4 +-
2 files changed, 90 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index f5cbbc53837c..2baf58af016c 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -62,19 +62,54 @@ static void intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache *
*height = cache->plane.src_h;
}
-static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
- const struct intel_fbc_state_cache *cache)
+/* plane stride in pixels */
+static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
{
- int lines;
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ unsigned int stride;
+
+ stride = plane_state->view.color_plane[0].stride;
+ if (!drm_rotation_90_or_270(plane_state->hw.rotation))
+ stride /= fb->format->cpp[0];
+
+ return stride;
+}
+
+/* plane stride based cfb stride in bytes, assuming 1:1 compression limit */
+static unsigned int _intel_fbc_cfb_stride(const struct intel_fbc_state_cache *cache)
+{
+ /* FBC always 4 bytes per pixel internally */
+ return cache->fb.stride * 4;
+}
+
+/* properly aligned cfb stride in bytes, assuming 1:1 compression limit */
+static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915,
+ const struct intel_fbc_state_cache *cache)
+{
+ unsigned int stride = _intel_fbc_cfb_stride(cache);
+
+ /*
+ * At least some of the platforms require each 4 line segment to
+ * be 512 byte aligned. Aligning each line to 512 bytes guarantees
+ * that regardless of the compression limit we choose later.
+ */
+ if (DISPLAY_VER(i915) == 9)
+ return ALIGN(stride, 512);
+ else
+ return stride;
+}
+
+static unsigned int intel_fbc_cfb_size(struct drm_i915_private *dev_priv,
+ const struct intel_fbc_state_cache *cache)
+{
+ int lines = cache->plane.src_h;
- intel_fbc_get_plane_source_size(cache, NULL, &lines);
if (DISPLAY_VER(dev_priv) == 7)
lines = min(lines, 2048);
else if (DISPLAY_VER(dev_priv) >= 8)
lines = min(lines, 2560);
- /* Hardware needs the full buffer stride, not just the active area. */
- return lines * cache->fb.stride;
+ return lines * intel_fbc_cfb_stride(dev_priv, cache);
}
static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
@@ -150,15 +185,9 @@ static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915)
{
- const struct intel_fbc_reg_params *params = &i915->fbc.params;
- int limit = i915->fbc.limit;
-
- if (params->fb.format->cpp[0] == 2)
- limit <<= 1;
-
- switch (limit) {
+ switch (i915->fbc.limit) {
default:
- MISSING_CASE(limit);
+ MISSING_CASE(i915->fbc.limit);
fallthrough;
case 1:
return DPFC_CTL_LIMIT_1X;
@@ -301,7 +330,8 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc *fbc = &dev_priv->fbc;
+ const struct intel_fbc_reg_params *params = &fbc->params;
u32 dpfc_ctl;
/* Display WA #0529: skl, kbl, bxt. */
@@ -310,7 +340,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
if (params->override_cfb_stride)
val |= CHICKEN_FBC_STRIDE_OVERRIDE |
- CHICKEN_FBC_STRIDE(params->override_cfb_stride);
+ CHICKEN_FBC_STRIDE(params->override_cfb_stride / fbc->limit);
intel_de_rmw(dev_priv, CHICKEN_MISC_4,
CHICKEN_FBC_STRIDE_OVERRIDE |
@@ -443,7 +473,12 @@ static u64 intel_fbc_stolen_end(struct drm_i915_private *dev_priv)
return min(end, intel_fbc_cfb_base_max(dev_priv));
}
-static int intel_fbc_max_limit(struct drm_i915_private *dev_priv, int fb_cpp)
+static int intel_fbc_min_limit(int fb_cpp)
+{
+ return fb_cpp == 2 ? 2 : 1;
+}
+
+static int intel_fbc_max_limit(struct drm_i915_private *dev_priv)
{
/*
* FIXME: FBC1 can have arbitrary cfb stride,
@@ -457,7 +492,7 @@ static int intel_fbc_max_limit(struct drm_i915_private *dev_priv, int fb_cpp)
return 1;
/* FBC2 can only do 1:1, 1:2, 1:4 */
- return fb_cpp == 2 ? 2 : 4;
+ return 4;
}
static int find_compression_limit(struct drm_i915_private *dev_priv,
@@ -466,7 +501,9 @@ static int find_compression_limit(struct drm_i915_private *dev_priv,
{
struct intel_fbc *fbc = &dev_priv->fbc;
u64 end = intel_fbc_stolen_end(dev_priv);
- int ret, limit = 1;
+ int ret, limit = intel_fbc_min_limit(fb_cpp);
+
+ size /= limit;
/* Try to over-allocate to reduce reallocations and fragmentation. */
ret = i915_gem_stolen_insert_node_in_range(dev_priv, &fbc->compressed_fb,
@@ -474,7 +511,7 @@ static int find_compression_limit(struct drm_i915_private *dev_priv,
if (ret == 0)
return limit;
- for (; limit <= intel_fbc_max_limit(dev_priv, fb_cpp); limit <<= 1) {
+ for (; limit <= intel_fbc_max_limit(dev_priv); limit <<= 1) {
ret = i915_gem_stolen_insert_node_in_range(dev_priv, &fbc->compressed_fb,
size >>= 1, 4096, 0, end);
if (ret == 0)
@@ -505,10 +542,9 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
ret = find_compression_limit(dev_priv, size, fb_cpp);
if (!ret)
goto err_llb;
- else if (ret > 1) {
+ else if (ret > intel_fbc_min_limit(fb_cpp))
drm_info_once(&dev_priv->drm,
"Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
- }
fbc->limit = ret;
@@ -719,11 +755,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
cache->fb.format = fb->format;
cache->fb.modifier = fb->modifier;
-
- /* FIXME is this correct? */
- cache->fb.stride = plane_state->view.color_plane[0].stride;
- if (drm_rotation_90_or_270(plane_state->hw.rotation))
- cache->fb.stride *= fb->format->cpp[0];
+ cache->fb.stride = intel_fbc_plane_stride(plane_state);
/* FBC1 compression interval: arbitrary choice of 1 second */
cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
@@ -746,27 +778,29 @@ static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
{
struct intel_fbc *fbc = &dev_priv->fbc;
- return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
+ return intel_fbc_cfb_size(dev_priv, &fbc->state_cache) >
fbc->compressed_fb.size * fbc->limit;
}
-static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv)
+static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv,
+ const struct intel_fbc_state_cache *cache)
{
- struct intel_fbc *fbc = &dev_priv->fbc;
- struct intel_fbc_state_cache *cache = &fbc->state_cache;
+ unsigned int stride = _intel_fbc_cfb_stride(cache);
+ unsigned int stride_aligned = intel_fbc_cfb_stride(dev_priv, cache);
- if ((DISPLAY_VER(dev_priv) == 9) &&
- cache->fb.modifier != I915_FORMAT_MOD_X_TILED)
- return DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->limit) * 8;
- else
- return 0;
-}
+ /*
+ * Override stride in 64 byte units per 4 line segment.
+ *
+ * Gen9 hw miscalculates cfb stride for linear as
+ * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so
+ * we always need to use the override there.
+ */
+ if (stride != stride_aligned ||
+ (DISPLAY_VER(dev_priv) == 9 &&
+ cache->fb.modifier == DRM_FORMAT_MOD_LINEAR))
+ return stride_aligned * 4 / 64;
-static bool intel_fbc_override_cfb_stride_changed(struct drm_i915_private *dev_priv)
-{
- struct intel_fbc *fbc = &dev_priv->fbc;
-
- return fbc->params.override_cfb_stride != intel_fbc_override_cfb_stride(dev_priv);
+ return 0;
}
static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
@@ -861,7 +895,8 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
return false;
}
- if (!stride_is_valid(dev_priv, cache->fb.modifier, cache->fb.stride)) {
+ if (!stride_is_valid(dev_priv, cache->fb.modifier,
+ cache->fb.stride * cache->fb.format->cpp[0])) {
fbc->no_fbc_reason = "framebuffer stride not supported";
return false;
}
@@ -949,9 +984,9 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
params->fb.modifier = cache->fb.modifier;
params->fb.stride = cache->fb.stride;
- params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
-
- params->override_cfb_stride = cache->override_cfb_stride;
+ params->cfb_stride = intel_fbc_cfb_stride(dev_priv, cache);
+ params->cfb_size = intel_fbc_cfb_size(dev_priv, cache);
+ params->override_cfb_stride = intel_fbc_override_cfb_stride(dev_priv, cache);
params->plane_visible = cache->plane.visible;
}
@@ -982,10 +1017,13 @@ static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
if (params->fb.stride != cache->fb.stride)
return false;
- if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
+ if (params->cfb_stride != intel_fbc_cfb_stride(dev_priv, cache))
return false;
- if (params->override_cfb_stride != cache->override_cfb_stride)
+ if (params->cfb_size != intel_fbc_cfb_size(dev_priv, cache))
+ return false;
+
+ if (params->override_cfb_stride != intel_fbc_override_cfb_stride(dev_priv, cache))
return false;
return true;
@@ -1266,8 +1304,7 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
if (fbc->crtc) {
if (fbc->crtc != crtc ||
- (!intel_fbc_cfb_size_changed(dev_priv) &&
- !intel_fbc_override_cfb_stride_changed(dev_priv)))
+ !intel_fbc_cfb_size_changed(dev_priv))
goto out;
__intel_fbc_disable(dev_priv);
@@ -1282,15 +1319,13 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
goto out;
if (intel_fbc_alloc_cfb(dev_priv,
- intel_fbc_calculate_cfb_size(dev_priv, cache),
+ intel_fbc_cfb_size(dev_priv, cache),
plane_state->hw.fb->format->cpp[0])) {
cache->plane.visible = false;
fbc->no_fbc_reason = "not enough stolen memory";
goto out;
}
- cache->override_cfb_stride = intel_fbc_override_cfb_stride(dev_priv);
-
drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n",
pipe_name(crtc->pipe));
fbc->no_fbc_reason = "FBC enabled but not active yet\n";
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91a2d2425fd3..d124306c0a08 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -401,7 +401,6 @@ struct intel_fbc {
} fb;
unsigned int fence_y_offset;
- u16 override_cfb_stride;
u16 interval;
s8 fence_id;
bool psr2_active;
@@ -426,7 +425,8 @@ struct intel_fbc {
u64 modifier;
} fb;
- int cfb_size;
+ unsigned int cfb_stride;
+ unsigned int cfb_size;
unsigned int fence_y_offset;
u16 override_cfb_stride;
u16 interval;
--
2.31.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 6/8] drm/i915/fbc: Align FBC segments to 512B on glk+
2021-07-02 20:45 [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
` (4 preceding siblings ...)
2021-07-02 20:46 ` [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb stride/size calculations Ville Syrjala
@ 2021-07-02 20:46 ` Ville Syrjala
2021-08-19 10:50 ` Juha-Pekka Heikkila
2021-07-02 20:46 ` [Intel-gfx] [PATCH 7/8] drm/i915/fbc: Implement Wa_16011863758 for icl+ Ville Syrjala
` (7 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Ville Syrjala @ 2021-07-02 20:46 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Apply the same 512 byte FBC segment alignment to glk+ as we use
on skl+. The only real difference is that we now have a dedicated
register for the FBC override stride. Not 100% sure which
platforms really need the 512B alignment, but it's easieest
to just do it on everything.
Also the hardware no longer seems to misclaculate the CFB stride
for linear, so we can omit the use of the override stride for
linear unless the stride is misaligned.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 14 +++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 2baf58af016c..2da5295092e7 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -93,7 +93,7 @@ static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915,
* be 512 byte aligned. Aligning each line to 512 bytes guarantees
* that regardless of the compression limit we choose later.
*/
- if (DISPLAY_VER(i915) == 9)
+ if (DISPLAY_VER(i915) >= 9)
return ALIGN(stride, 512);
else
return stride;
@@ -334,10 +334,18 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
const struct intel_fbc_reg_params *params = &fbc->params;
u32 dpfc_ctl;
- /* Display WA #0529: skl, kbl, bxt. */
- if (DISPLAY_VER(dev_priv) == 9) {
+ if (DISPLAY_VER(dev_priv) >= 10) {
u32 val = 0;
+ if (params->override_cfb_stride)
+ val |= FBC_STRIDE_OVERRIDE |
+ FBC_STRIDE(params->override_cfb_stride / fbc->limit);
+
+ intel_de_write(dev_priv, GLK_FBC_STRIDE, val);
+ } else if (DISPLAY_VER(dev_priv) == 9) {
+ u32 val = 0;
+
+ /* Display WA #0529: skl, kbl, bxt. */
if (params->override_cfb_stride)
val |= CHICKEN_FBC_STRIDE_OVERRIDE |
CHICKEN_FBC_STRIDE(params->override_cfb_stride / fbc->limit);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ab2bd4837efd..7cf318d84d81 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3334,6 +3334,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
#define ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL (1 << 14)
#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23)
+#define GLK_FBC_STRIDE _MMIO(0x43228)
+#define FBC_STRIDE_OVERRIDE REG_BIT(15)
+#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
+#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
#define ILK_FBC_RT_BASE _MMIO(0x2128)
#define ILK_FBC_RT_VALID (1 << 0)
#define SNB_FBC_FRONT_BUFFER (1 << 1)
--
2.31.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 7/8] drm/i915/fbc: Implement Wa_16011863758 for icl+
2021-07-02 20:45 [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
` (5 preceding siblings ...)
2021-07-02 20:46 ` [Intel-gfx] [PATCH 6/8] drm/i915/fbc: Align FBC segments to 512B on glk+ Ville Syrjala
@ 2021-07-02 20:46 ` Ville Syrjala
2021-08-19 10:52 ` Juha-Pekka Heikkila
2021-07-02 20:46 ` [Intel-gfx] [PATCH 8/8] drm/i915/fbc: Allow higher compression limits on FBC1 Ville Syrjala
` (6 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Ville Syrjala @ 2021-07-02 20:46 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
There's some kind of weird corner cases in FBC which requires
FBC segments to be separated by at least one extra cacheline.
Make sure that is present.
TODO: the formula laid out in the spec seem to be semi-nonsense
so this is mostly my interpretation on what it is actually trying
to say. Need to wait for clarification from the hw folks to know
for sure.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 2da5295092e7..daf2191dd3f6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -88,6 +88,16 @@ static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915,
{
unsigned int stride = _intel_fbc_cfb_stride(cache);
+ /*
+ * Wa_16011863758: icl+
+ * CFB segment stride needs at least one extra cacheline.
+ * We make sure each line has an extra cacheline so that
+ * the 4 line segment will have one regarless of the
+ * compression limit we choose later.
+ */
+ if (DISPLAY_VER(i915) >= 11)
+ stride = max(stride, cache->plane.src_w * 4 + 64u);
+
/*
* At least some of the platforms require each 4 line segment to
* be 512 byte aligned. Aligning each line to 512 bytes guarantees
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH 8/8] drm/i915/fbc: Allow higher compression limits on FBC1
2021-07-02 20:45 [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
` (6 preceding siblings ...)
2021-07-02 20:46 ` [Intel-gfx] [PATCH 7/8] drm/i915/fbc: Implement Wa_16011863758 for icl+ Ville Syrjala
@ 2021-07-02 20:46 ` Ville Syrjala
2021-08-23 17:52 ` Juha-Pekka Heikkilä
2021-07-02 22:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations Patchwork
` (5 subsequent siblings)
13 siblings, 1 reply; 22+ messages in thread
From: Ville Syrjala @ 2021-07-02 20:46 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On FBC1 we can specify an arbitrary cfb stride. The hw will
simply throw away any compressed line that would exceed the
specified limit and keep using the uncompressed data instead.
Thus we can allow arbitrary compression limits.
The one thing we have to keep in mind though is that the cfb
stride is specified in units of 32B (gen2) or 64B (gen3+).
Fortunately X-tile is already 128B (gen2) or 512B (gen3+) wide
so as long as we limit outselves to the same 4x compression
limit that FBC2 has we are guaranteed to have a sufficiently
aligned cfb stride.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 20 +++++++-------------
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index daf2191dd3f6..d46ee7b49d68 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -144,15 +144,13 @@ static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
{
- struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
+ struct intel_fbc *fbc = &dev_priv->fbc;
+ const struct intel_fbc_reg_params *params = &fbc->params;
int cfb_pitch;
int i;
u32 fbc_ctl;
- /* Note: fbc.limit == 1 for i8xx */
- cfb_pitch = params->cfb_size / FBC_LL_SIZE;
- if (params->fb.stride < cfb_pitch)
- cfb_pitch = params->fb.stride;
+ cfb_pitch = params->cfb_stride / fbc->limit;
/* FBC_CTL wants 32B or 64B units */
if (DISPLAY_VER(dev_priv) == 2)
@@ -498,18 +496,14 @@ static int intel_fbc_min_limit(int fb_cpp)
static int intel_fbc_max_limit(struct drm_i915_private *dev_priv)
{
- /*
- * FIXME: FBC1 can have arbitrary cfb stride,
- * so we could support different compression ratios.
- */
- if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
- return 1;
-
/* WaFbcOnly1to1Ratio:ctg */
if (IS_G4X(dev_priv))
return 1;
- /* FBC2 can only do 1:1, 1:2, 1:4 */
+ /*
+ * FBC2 can only do 1:1, 1:2, 1:4, we limit
+ * FBC1 to the same out of convenience.
+ */
return 4;
}
--
2.31.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations
2021-07-02 20:45 [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
` (7 preceding siblings ...)
2021-07-02 20:46 ` [Intel-gfx] [PATCH 8/8] drm/i915/fbc: Allow higher compression limits on FBC1 Ville Syrjala
@ 2021-07-02 22:02 ` Patchwork
2021-07-02 22:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (4 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2021-07-02 22:02 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/fbc: Rework CFB stride/size calculations
URL : https://patchwork.freedesktop.org/series/92163/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1896:21: expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1896:21: got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1896:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1210:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: Rework CFB stride/size calculations
2021-07-02 20:45 [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
` (8 preceding siblings ...)
2021-07-02 22:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations Patchwork
@ 2021-07-02 22:29 ` Patchwork
2021-07-03 1:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2021-07-02 22:29 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3312 bytes --]
== Series Details ==
Series: drm/i915/fbc: Rework CFB stride/size calculations
URL : https://patchwork.freedesktop.org/series/92163/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10304 -> Patchwork_20523
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/index.html
Known issues
------------
Here are the changes found in Patchwork_20523 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][2] ([i915#2782]) -> [PASS][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [FAIL][4] ([i915#3449]) -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][6] ([i915#1372]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#3449]: https://gitlab.freedesktop.org/drm/intel/issues/3449
Participating hosts (36 -> 34)
------------------------------
Missing (2): fi-bsw-cyan fi-bsw-n3050
Build changes
-------------
* Linux: CI_DRM_10304 -> Patchwork_20523
CI-20190529: 20190529
CI_DRM_10304: 3d3b5479895dd6dd133571ded4318adf595708ba @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6128: b24e5949af7e51f0af484d2ce4cb4c5a41ac5358 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20523: 1a6338102e7402b04550d6d1ba533ad8f5ad6410 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1a6338102e74 drm/i915/fbc: Allow higher compression limits on FBC1
c43b5d4d5ee5 drm/i915/fbc: Implement Wa_16011863758 for icl+
e7a875531eb4 drm/i915/fbc: Align FBC segments to 512B on glk+
9fce51c1d980 drm/i915/fbc: Rework cfb stride/size calculations
1c684d0e6024 drm/i915/fbc: Polish the skl+ FBC stride override handling
fc475b3b46e9 drm/i915/fbc: Move the "recompress on activate" to a central place
faaa5f8aa77e drm/i915/fbc: Extract intel_fbc_update()
df6e25b7503e drm/i915/fbc: Rewrite the FBC tiling check a bit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/fbc: Rework CFB stride/size calculations
2021-07-02 20:45 [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
` (9 preceding siblings ...)
2021-07-02 22:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-07-03 1:37 ` Patchwork
2021-07-07 15:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations (rev2) Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2021-07-03 1:37 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30272 bytes --]
== Series Details ==
Series: drm/i915/fbc: Rework CFB stride/size calculations
URL : https://patchwork.freedesktop.org/series/92163/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10304_full -> Patchwork_20523_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20523_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20523_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20523_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_eio@in-flight-10ms:
- shard-iclb: [PASS][1] -> [TIMEOUT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-iclb6/igt@gem_eio@in-flight-10ms.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-iclb2/igt@gem_eio@in-flight-10ms.html
* igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled:
- shard-glk: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-glk6/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-glk3/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html
Known issues
------------
Here are the changes found in Patchwork_20523_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-glk2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: NOTRUN -> [FAIL][9] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [PASS][10] -> [SKIP][11] ([fdo#109271])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-kbl2/igt@gem_exec_fair@basic-pace@vcs1.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2849])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl9/igt@gem_huc_copy@huc-copy.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][15] ([i915#2658])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl1/igt@gem_pread@exhaustion.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3323])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl8/igt@gem_userptr_blits@dmabuf-sync.html
* igt@i915_suspend@forcewake:
- shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#636])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-skl10/igt@i915_suspend@forcewake.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl8/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#110725] / [fdo#111614])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-iclb1/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-glk: [PASS][20] -> [DMESG-WARN][21] ([i915#118] / [i915#95])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-glk9/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-glk5/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][22] ([i915#3722])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#95]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-kbl3/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl6/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
- shard-apl: NOTRUN -> [DMESG-WARN][25] ([i915#95])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl3/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- shard-apl: [PASS][26] -> [DMESG-WARN][27] ([i915#95])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-apl1/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl8/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][28] ([fdo#109271]) +37 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-glk4/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_rc_ccs:
- shard-skl: NOTRUN -> [FAIL][29] ([i915#3678]) +3 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl6/igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_rc_ccs.html
* igt@kms_chamelium@dp-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +10 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl9/igt@kms_chamelium@dp-crc-multiple.html
* igt@kms_color@pipe-a-ctm-0-25:
- shard-skl: [PASS][31] -> [DMESG-WARN][32] ([i915#1982])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-skl7/igt@kms_color@pipe-a-ctm-0-25.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl3/igt@kms_color@pipe-a-ctm-0-25.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +28 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl1/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-b-degamma:
- shard-glk: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +2 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-glk4/igt@kms_color_chamelium@pipe-b-degamma.html
* igt@kms_color_chamelium@pipe-c-ctm-max:
- shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +8 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl2/igt@kms_color_chamelium@pipe-c-ctm-max.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][36] ([i915#1319]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl3/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen:
- shard-skl: [PASS][37] -> [FAIL][38] ([i915#3444])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
- shard-skl: NOTRUN -> [SKIP][39] ([fdo#109271]) +161 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][40] -> [DMESG-WARN][41] ([i915#180]) +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: NOTRUN -> [FAIL][42] ([i915#2346])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: NOTRUN -> [FAIL][43] ([i915#2346] / [i915#533])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: NOTRUN -> [FAIL][44] ([i915#79])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
- shard-skl: [PASS][45] -> [INCOMPLETE][46] ([i915#198] / [i915#1982])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-skl10/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl6/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [PASS][47] -> [DMESG-WARN][48] ([i915#180])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-apl8/igt@kms_flip@flip-vs-suspend@a-dp1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl2/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
- shard-skl: [PASS][49] -> [FAIL][50] ([i915#2122])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl7/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#2672]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109280])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][53] -> [FAIL][54] ([i915#1188]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-skl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#533])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl8/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-apl: NOTRUN -> [DMESG-WARN][56] ([i915#180])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][57] ([fdo#108145] / [i915#265]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][58] ([i915#265])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: NOTRUN -> [FAIL][59] ([fdo#108145] / [i915#265]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][60] ([fdo#108145] / [i915#265]) +5 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-x:
- shard-kbl: NOTRUN -> [SKIP][61] ([fdo#109271]) +103 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl7/igt@kms_plane_multiple@atomic-pipe-d-tiling-x.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-skl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#658])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-apl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#658]) +5 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#658])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][65] -> [SKIP][66] ([fdo#109441]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-skl: NOTRUN -> [WARN][67] ([i915#2100])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl6/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][68] ([IGT#2])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl3/igt@kms_sysfs_edid_timing.html
- shard-kbl: NOTRUN -> [FAIL][69] ([IGT#2])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl2/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][70] -> [DMESG-WARN][71] ([i915#180] / [i915#295])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271]) +332 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl3/igt@kms_vblank@pipe-d-ts-continuation-idle.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#533]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl7/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-check-output:
- shard-skl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#2437])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl8/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2437])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl1/igt@kms_writeback@writeback-fb-id.html
* igt@perf@polling-small-buf:
- shard-skl: [PASS][76] -> [FAIL][77] ([i915#1722])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-skl1/igt@perf@polling-small-buf.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl6/igt@perf@polling-small-buf.html
* igt@sysfs_clients@fair-3:
- shard-glk: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2994])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-glk4/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@fair-7:
- shard-apl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2994]) +5 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl1/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@sema-25:
- shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2994]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl6/igt@sysfs_clients@sema-25.html
* igt@sysfs_heartbeat_interval@mixed@vcs0:
- shard-glk: [PASS][81] -> [FAIL][82] ([i915#1731]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-glk3/igt@sysfs_heartbeat_interval@mixed@vcs0.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-glk7/igt@sysfs_heartbeat_interval@mixed@vcs0.html
- shard-skl: [PASS][83] -> [FAIL][84] ([i915#1731])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-skl6/igt@sysfs_heartbeat_interval@mixed@vcs0.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl2/igt@sysfs_heartbeat_interval@mixed@vcs0.html
#### Possible fixes ####
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [FAIL][85] ([i915#2410]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-tglb6/igt@gem_ctx_persistence@many-contexts.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-tglb2/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_eio@in-flight-suspend:
- shard-skl: [INCOMPLETE][87] ([i915#198]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-skl5/igt@gem_eio@in-flight-suspend.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl8/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][89] ([i915#2842]) -> [PASS][90] +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-glk: [FAIL][91] ([i915#2842]) -> [PASS][92] +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-glk8/igt@gem_exec_fair@basic-none-solo@rcs0.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-glk5/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [FAIL][93] ([i915#2842]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][95] ([i915#2842]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][97] ([i915#1436] / [i915#716]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-skl6/igt@gen9_exec_parse@allowed-single.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl9/igt@gen9_exec_parse@allowed-single.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled:
- shard-skl: [FAIL][99] -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-skl1/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-cpu-ytiled.html
* igt@kms_flip@flip-vs-expired-vblank@c-dp1:
- shard-apl: [FAIL][101] ([i915#79]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-apl7/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl3/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1:
- shard-glk: [FAIL][103] ([i915#79]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-glk6/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][105] ([i915#180]) -> [PASS][106] +6 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@plain-flip-ts-check@b-edp1:
- shard-skl: [FAIL][107] ([i915#2122]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-skl7/igt@kms_flip@plain-flip-ts-check@b-edp1.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl9/igt@kms_flip@plain-flip-ts-check@b-edp1.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-apl: [DMESG-WARN][109] ([i915#180]) -> [PASS][110] +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-apl1/igt@kms_hdr@bpc-switch-suspend.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl8/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- shard-skl: [DMESG-WARN][111] ([i915#1982]) -> [PASS][112] +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-skl6/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl9/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][113] ([fdo#108145] / [i915#265]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][115] ([fdo#109441]) -> [PASS][116] +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-iclb6/igt@kms_psr@psr2_no_drrs.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
#### Warnings ####
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: [INCOMPLETE][117] ([i915#198]) -> [FAIL][118] ([i915#454])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-skl8/igt@i915_pm_dc@dc6-dpms.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-skl6/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][119] ([i915#1804] / [i915#2684]) -> [WARN][120] ([i915#2684]) +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][121] ([i915#1226]) -> [SKIP][122] ([fdo#109349])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-iclb1/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-iclb: [SKIP][123] ([i915#2920]) -> [SKIP][124] ([i915#658]) +4 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-iclb1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3:
- shard-iclb: [SKIP][125] ([i915#658]) -> [SKIP][126] ([i915#2920]) +1 similar issue
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132]) ([i915#180] / [i915#3002] / [i915#3363]) -> ([FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-kbl4/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-kbl4/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-kbl4/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-kbl4/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-kbl3/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-kbl1/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl3/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl1/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl3/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl3/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl2/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl4/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-kbl4/igt@runner@aborted.html
- shard-iclb: ([FAIL][140], [FAIL][141], [FAIL][142]) ([i915#1814] / [i915#3002]) -> ([FAIL][143], [FAIL][144]) ([i915#3002])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-iclb7/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-iclb2/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-iclb5/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-iclb1/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-iclb3/igt@runner@aborted.html
- shard-apl: ([FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][150], [FAIL][151], [FAIL][152]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-apl1/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-apl3/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-apl6/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-apl6/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10304/shard-apl8/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl2/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl1/igt@runner@aborted.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/shard-apl6/igt@runner@aborted.html
- shard-skl: ([FAIL][153], [FAIL][154], [FAIL][155]) ([i915#1436] / [i915#3002] / [i915#3363]) -> ([FAIL][156], [FAIL][157]) ([i915#3002] / [i915#3363])
[153]: https://intel-gfx-ci.01.org/tree/drm-ti
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20523/index.html
[-- Attachment #1.2: Type: text/html, Size: 33721 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 4/8] drm/i915/fbc: Polish the skl+ FBC stride override handling
2021-07-02 20:45 ` [Intel-gfx] [PATCH 4/8] drm/i915/fbc: Polish the skl+ FBC stride override handling Ville Syrjala
@ 2021-07-05 8:02 ` Jani Nikula
0 siblings, 0 replies; 22+ messages in thread
From: Jani Nikula @ 2021-07-05 8:02 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 02 Jul 2021, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Polish the FBC stride override stuff:
> - just call it override_cfb_stride since it'll be used on
> more gens later
> - Use REG_BIT() & co. for the registers and give everything
> CHICKEN_ prefix since glk+ will have a different register
> for this
> - Use intel_de_rmw() for the RMW
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 27 ++++++++++++------------
> drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> 3 files changed, 19 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index c9cde96f330b..f5cbbc53837c 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -306,14 +306,15 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
>
> /* Display WA #0529: skl, kbl, bxt. */
> if (DISPLAY_VER(dev_priv) == 9) {
> - u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4);
> + u32 val = 0;
>
> - val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
> + if (params->override_cfb_stride)
> + val |= CHICKEN_FBC_STRIDE_OVERRIDE |
> + CHICKEN_FBC_STRIDE(params->override_cfb_stride);
>
> - if (params->gen9_wa_cfb_stride)
> - val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
> -
> - intel_de_write(dev_priv, CHICKEN_MISC_4, val);
> + intel_de_rmw(dev_priv, CHICKEN_MISC_4,
> + CHICKEN_FBC_STRIDE_OVERRIDE |
> + CHICKEN_FBC_STRIDE_MASK, val);
> }
>
> dpfc_ctl = 0;
> @@ -749,7 +750,7 @@ static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
> fbc->compressed_fb.size * fbc->limit;
> }
>
> -static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
> +static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv)
> {
> struct intel_fbc *fbc = &dev_priv->fbc;
> struct intel_fbc_state_cache *cache = &fbc->state_cache;
> @@ -761,11 +762,11 @@ static u16 intel_fbc_gen9_wa_cfb_stride(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> -static bool intel_fbc_gen9_wa_cfb_stride_changed(struct drm_i915_private *dev_priv)
> +static bool intel_fbc_override_cfb_stride_changed(struct drm_i915_private *dev_priv)
> {
> struct intel_fbc *fbc = &dev_priv->fbc;
>
> - return fbc->params.gen9_wa_cfb_stride != intel_fbc_gen9_wa_cfb_stride(dev_priv);
> + return fbc->params.override_cfb_stride != intel_fbc_override_cfb_stride(dev_priv);
> }
>
> static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
> @@ -950,7 +951,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
>
> params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
>
> - params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride;
> + params->override_cfb_stride = cache->override_cfb_stride;
>
> params->plane_visible = cache->plane.visible;
> }
> @@ -984,7 +985,7 @@ static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
> if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
> return false;
>
> - if (params->gen9_wa_cfb_stride != cache->gen9_wa_cfb_stride)
> + if (params->override_cfb_stride != cache->override_cfb_stride)
> return false;
>
> return true;
> @@ -1266,7 +1267,7 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
> if (fbc->crtc) {
> if (fbc->crtc != crtc ||
> (!intel_fbc_cfb_size_changed(dev_priv) &&
> - !intel_fbc_gen9_wa_cfb_stride_changed(dev_priv)))
> + !intel_fbc_override_cfb_stride_changed(dev_priv)))
> goto out;
>
> __intel_fbc_disable(dev_priv);
> @@ -1288,7 +1289,7 @@ static void intel_fbc_enable(struct intel_atomic_state *state,
> goto out;
> }
>
> - cache->gen9_wa_cfb_stride = intel_fbc_gen9_wa_cfb_stride(dev_priv);
> + cache->override_cfb_stride = intel_fbc_override_cfb_stride(dev_priv);
>
> drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n",
> pipe_name(crtc->pipe));
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6dff4ca01241..91a2d2425fd3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -401,7 +401,7 @@ struct intel_fbc {
> } fb;
>
> unsigned int fence_y_offset;
> - u16 gen9_wa_cfb_stride;
> + u16 override_cfb_stride;
> u16 interval;
> s8 fence_id;
> bool psr2_active;
> @@ -428,7 +428,7 @@ struct intel_fbc {
>
> int cfb_size;
> unsigned int fence_y_offset;
> - u16 gen9_wa_cfb_stride;
> + u16 override_cfb_stride;
> u16 interval;
> s8 fence_id;
> bool plane_visible;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 16a19239d86d..ab2bd4837efd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8131,8 +8131,9 @@ enum {
> #define GLK_CL0_PWR_DOWN (1 << 10)
>
> #define CHICKEN_MISC_4 _MMIO(0x4208c)
> -#define FBC_STRIDE_OVERRIDE (1 << 13)
> -#define FBC_STRIDE_MASK 0x1FFF
> +#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
> +#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
> +#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
>
> #define _CHICKEN_PIPESL_1_A 0x420b0
> #define _CHICKEN_PIPESL_1_B 0x420b4
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations (rev2)
2021-07-02 20:45 [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
` (10 preceding siblings ...)
2021-07-03 1:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-07-07 15:31 ` Patchwork
2021-07-07 15:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-07 20:05 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2021-07-07 15:31 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/fbc: Rework CFB stride/size calculations (rev2)
URL : https://patchwork.freedesktop.org/series/92163/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1896:21: expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1896:21: got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1896:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1210:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: Rework CFB stride/size calculations (rev2)
2021-07-02 20:45 [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
` (11 preceding siblings ...)
2021-07-07 15:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations (rev2) Patchwork
@ 2021-07-07 15:58 ` Patchwork
2021-07-07 20:05 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2021-07-07 15:58 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3168 bytes --]
== Series Details ==
Series: drm/i915/fbc: Rework CFB stride/size calculations (rev2)
URL : https://patchwork.freedesktop.org/series/92163/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10309 -> Patchwork_20545
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/index.html
Known issues
------------
Here are the changes found in Patchwork_20545 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [PASS][1] -> [DMESG-FAIL][2] ([i915#165])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0:
- {fi-tgl-1115g4}: [FAIL][3] ([i915#1888]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][5] ([i915#1372]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
Participating hosts (44 -> 40)
------------------------------
Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-bsw-cyan fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_10309 -> Patchwork_20545
CI-20190529: 20190529
CI_DRM_10309: 6a5db0d08c45a29cebcfd39b53a15be664b9369c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6130: 390edfb703c346f06b0850db71bd3cc1342a3c02 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20545: 0185143ee826d212fa71169f94eb876a7d72b293 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
0185143ee826 drm/i915/fbc: Allow higher compression limits on FBC1
1091564c7004 drm/i915/fbc: Implement Wa_16011863758 for icl+
29df4825d9dd drm/i915/fbc: Align FBC segments to 512B on glk+
69bbbd1d9aae drm/i915/fbc: Rework cfb stride/size calculations
270422b7c7b2 drm/i915/fbc: Polish the skl+ FBC stride override handling
81c9ecdfa371 drm/i915/fbc: Move the "recompress on activate" to a central place
dee78ea53693 drm/i915/fbc: Extract intel_fbc_update()
0b6c118b349e drm/i915/fbc: Rewrite the FBC tiling check a bit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/index.html
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_______________________________________________
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/fbc: Rework CFB stride/size calculations (rev2)
2021-07-02 20:45 [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
` (12 preceding siblings ...)
2021-07-07 15:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-07-07 20:05 ` Patchwork
13 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2021-07-07 20:05 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
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== Series Details ==
Series: drm/i915/fbc: Rework CFB stride/size calculations (rev2)
URL : https://patchwork.freedesktop.org/series/92163/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10309_full -> Patchwork_20545_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20545_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- {shard-rkl}: [SKIP][1] ([i915#3721]) -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs:
- {shard-rkl}: [FAIL][3] ([i915#3678]) -> [SKIP][4] +4 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-1/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html
* igt@kms_flip_tiling@flip-changes-tiling-y:
- {shard-rkl}: NOTRUN -> [SKIP][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-1/igt@kms_flip_tiling@flip-changes-tiling-y.html
Known issues
------------
Here are the changes found in Patchwork_20545_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-3x:
- shard-iclb: NOTRUN -> [SKIP][6] ([i915#1839])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@feature_discovery@display-3x.html
* igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-snb2/igt@gem_ctx_persistence@legacy-engines-mixed.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-tglb2/igt@gem_exec_fair@basic-none-share@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-tglb6/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fence@basic-wait@bcs0:
- shard-kbl: NOTRUN -> [SKIP][12] ([fdo#109271]) +57 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl4/igt@gem_exec_fence@basic-wait@bcs0.html
* igt@gem_exec_params@no-blt:
- shard-iclb: NOTRUN -> [SKIP][13] ([fdo#109283])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@gem_exec_params@no-blt.html
* igt@gem_exec_reloc@basic-wide-active@bcs0:
- shard-apl: NOTRUN -> [FAIL][14] ([i915#3633]) +3 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl1/igt@gem_exec_reloc@basic-wide-active@bcs0.html
* igt@gem_exec_reloc@basic-wide-active@rcs0:
- shard-snb: NOTRUN -> [FAIL][15] ([i915#3633]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-snb2/igt@gem_exec_reloc@basic-wide-active@rcs0.html
* igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][16] ([i915#3633])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb4/igt@gem_exec_reloc@basic-wide-active@vcs1.html
* igt@gem_exec_whisper@basic-contexts-all:
- shard-glk: [PASS][17] -> [DMESG-WARN][18] ([i915#118] / [i915#95])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-glk1/igt@gem_exec_whisper@basic-contexts-all.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-glk3/igt@gem_exec_whisper@basic-contexts-all.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl1/igt@gem_huc_copy@huc-copy.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [WARN][20] ([i915#2658])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl8/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#3297])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][22] -> [DMESG-WARN][23] ([i915#180]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl8/igt@gem_workarounds@suspend-resume-context.html
* igt@gen7_exec_parse@chained-batch:
- shard-iclb: NOTRUN -> [SKIP][24] ([fdo#109289]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@gen7_exec_parse@chained-batch.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: NOTRUN -> [FAIL][25] ([i915#3343])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: NOTRUN -> [WARN][26] ([i915#2684])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][27] -> [INCOMPLETE][28] ([i915#2782])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-snb7/igt@i915_selftest@live@hangcheck.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-snb6/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#110725] / [fdo#111614])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- shard-kbl: [PASS][30] -> [DMESG-WARN][31] ([i915#95])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-kbl2/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl1/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_big_joiner@basic:
- shard-iclb: NOTRUN -> [SKIP][32] ([i915#2705])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271]) +9 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-skl7/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cdclk@plane-scaling:
- shard-iclb: NOTRUN -> [SKIP][34] ([i915#3742])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium@dp-hpd-fast:
- shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +7 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl4/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_color@pipe-b-ctm-0-75:
- shard-skl: [PASS][36] -> [DMESG-WARN][37] ([i915#1982])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-skl8/igt@kms_color@pipe-b-ctm-0-75.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-skl2/igt@kms_color@pipe-b-ctm-0-75.html
* igt@kms_color_chamelium@pipe-a-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109284] / [fdo#111827]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@kms_color_chamelium@pipe-a-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-c-ctm-max:
- shard-apl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +17 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl3/igt@kms_color_chamelium@pipe-c-ctm-max.html
* igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
- shard-snb: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +11 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-snb5/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][41] ([i915#1319])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl8/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-iclb: NOTRUN -> [SKIP][42] ([i915#3116])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109278] / [fdo#109279])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: NOTRUN -> [DMESG-WARN][44] ([i915#180])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-64x21-sliding:
- shard-iclb: NOTRUN -> [SKIP][45] ([fdo#109278]) +10 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@kms_cursor_crc@pipe-d-cursor-64x21-sliding.html
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-skl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#533])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-skl7/igt@kms_cursor_legacy@pipe-d-single-bo.html
* igt@kms_flip@2x-flip-vs-modeset-vs-hang:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109274]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
- shard-skl: [PASS][48] -> [INCOMPLETE][49] ([i915#198])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-skl2/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][50] -> [FAIL][51] ([i915#2122]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#2672]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-iclb: NOTRUN -> [SKIP][53] ([i915#2587])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt:
- shard-iclb: NOTRUN -> [SKIP][54] ([fdo#109280]) +6 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#533])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl4/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-kbl: [PASS][56] -> [DMESG-WARN][57] ([i915#180]) +8 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][58] ([fdo#108145] / [i915#265]) +3 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][59] -> [FAIL][60] ([fdo#108145] / [i915#265])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-c-tiling-x:
- shard-iclb: NOTRUN -> [SKIP][61] ([i915#3536])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@kms_plane_lowres@pipe-c-tiling-x.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#658]) +3 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
- shard-iclb: NOTRUN -> [SKIP][63] ([i915#658])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-skl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#658])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-skl1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
- shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#658]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: NOTRUN -> [SKIP][66] ([fdo#109441]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][67] ([IGT#2])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl1/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-d-query-forked-hang:
- shard-snb: NOTRUN -> [SKIP][68] ([fdo#109271]) +291 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-snb5/igt@kms_vblank@pipe-d-query-forked-hang.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271]) +267 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl1/igt@kms_vblank@pipe-d-ts-continuation-idle.html
* igt@kms_writeback@writeback-check-output:
- shard-kbl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#2437])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl4/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#2437])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl7/igt@kms_writeback@writeback-fb-id.html
- shard-iclb: NOTRUN -> [SKIP][72] ([i915#2437])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@kms_writeback@writeback-fb-id.html
* igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame:
- shard-iclb: NOTRUN -> [SKIP][73] ([i915#2530])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-iclb8/igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame.html
* igt@perf@polling-parameterized:
- shard-glk: [PASS][74] -> [FAIL][75] ([i915#1542])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-glk5/igt@perf@polling-parameterized.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-glk6/igt@perf@polling-parameterized.html
* igt@sysfs_clients@busy:
- shard-kbl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#2994])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl4/igt@sysfs_clients@busy.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2994]) +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl8/igt@sysfs_clients@fair-1.html
* igt@vgem_basic@unload:
- shard-kbl: NOTRUN -> [INCOMPLETE][78] ([i915#3744])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl2/igt@vgem_basic@unload.html
- shard-apl: NOTRUN -> [INCOMPLETE][79] ([i915#3744])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl1/igt@vgem_basic@unload.html
- shard-snb: NOTRUN -> [INCOMPLETE][80] ([i915#3744])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-snb7/igt@vgem_basic@unload.html
#### Possible fixes ####
* igt@fbdev@nullptr:
- {shard-rkl}: [SKIP][81] ([i915#2582]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-2/igt@fbdev@nullptr.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@fbdev@nullptr.html
* igt@gem_create@create-clear:
- shard-glk: [FAIL][83] ([i915#3160]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-glk6/igt@gem_create@create-clear.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-glk3/igt@gem_create@create-clear.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [DMESG-WARN][85] ([i915#180]) -> [PASS][86] +3 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl2/igt@gem_ctx_isolation@preservation-s3@bcs0.html
- shard-apl: [DMESG-WARN][87] ([i915#180]) -> [PASS][88] +2 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-apl8/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-apl: [SKIP][89] ([fdo#109271]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-apl8/igt@gem_exec_fair@basic-none-share@rcs0.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [SKIP][91] ([fdo#109271]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs0.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@i915_pm_rpm@drm-resources-equal:
- {shard-rkl}: [SKIP][93] ([fdo#109308]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-2/igt@i915_pm_rpm@drm-resources-equal.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@i915_pm_rpm@drm-resources-equal.html
* igt@i915_pm_rpm@modeset-lpsp:
- {shard-rkl}: [SKIP][95] ([i915#1397]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-180:
- {shard-rkl}: [SKIP][97] ([i915#3638]) -> [PASS][98] +2 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-2/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- {shard-rkl}: [SKIP][99] ([i915#3721]) -> [PASS][100] +4 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- {shard-rkl}: [FAIL][101] ([i915#3678]) -> [PASS][102] +5 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-2/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_color@pipe-c-ctm-max:
- {shard-rkl}: [SKIP][103] ([i915#1149] / [i915#1849]) -> [PASS][104] +4 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-1/igt@kms_color@pipe-c-ctm-max.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@kms_color@pipe-c-ctm-max.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen:
- {shard-rkl}: [SKIP][105] ([fdo#112022]) -> [PASS][106] +12 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-2/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-128x128-onscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic:
- {shard-rkl}: [SKIP][107] ([fdo#111825]) -> [PASS][108] +4 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-2/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
* igt@kms_dp_aux_dev:
- {shard-rkl}: [SKIP][109] ([i915#1257]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-1/igt@kms_dp_aux_dev.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@kms_dp_aux_dev.html
* igt@kms_draw_crc@draw-method-rgb565-blt-untiled:
- {shard-rkl}: [SKIP][111] ([fdo#111314]) -> [PASS][112] +3 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-2/igt@kms_draw_crc@draw-method-rgb565-blt-untiled.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@kms_draw_crc@draw-method-rgb565-blt-untiled.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][113] ([i915#79]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@b-edp1:
- shard-skl: [FAIL][115] ([i915#2122]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-skl1/igt@kms_flip@flip-vs-absolute-wf_vblank@b-edp1.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-skl3/igt@kms_flip@flip-vs-absolute-wf_vblank@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@a-dp1:
- shard-kbl: [FAIL][117] ([i915#79]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-kbl6/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- {shard-rkl}: [SKIP][119] ([i915#1849]) -> [PASS][120] +41 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-2/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
* igt@kms_plane@plane-position-hole@pipe-b-planes:
- {shard-rkl}: [SKIP][121] ([i915#3558]) -> [PASS][122] +3 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-2/igt@kms_plane@plane-position-hole@pipe-b-planes.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@kms_plane@plane-position-hole@pipe-b-planes.html
* igt@kms_psr@sprite_mmap_cpu:
- {shard-rkl}: [SKIP][123] ([i915#1072]) -> [PASS][124] +1 similar issue
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-2/igt@kms_psr@sprite_mmap_cpu.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@kms_psr@sprite_mmap_cpu.html
* igt@kms_vblank@pipe-c-wait-busy:
- {shard-rkl}: [SKIP][125] ([i915#1845]) -> [PASS][126] +22 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-rkl-2/igt@kms_vblank@pipe-c-wait-busy.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-rkl-6/igt@kms_vblank@pipe-c-wait-busy.html
#### Warnings ####
* igt@core_hotunplug@unbind-rebind:
- shard-apl: [DMESG-WARN][127] ([i915#2283]) -> [DMESG-WARN][128] ([i915#1982] / [i915#2283])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-apl1/igt@core_hotunplug@unbind-rebind.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-apl7/igt@core_hotunplug@unbind-rebind.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2283] / [i915#2505] / [i915#3002] / [i915#3363]) -> ([FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2283] / [i915#2292] / [i915#2505] / [i915#2722] / [i915#3002] / [i915#3363] / [i915#602])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-kbl1/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-kbl6/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-kbl1/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-kbl2/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-kbl6/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-kbl4/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-kbl3/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10309/shard-kbl2/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl1/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl6/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl6/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl7/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl1/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl6/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl4/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl6/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl4/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl6/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl2/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl7/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl7/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/shard-kbl1/igt@runner@aborted.html
- shard-iclb: ([FAIL][151], [
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20545/index.html
[-- Attachment #1.2: Type: text/html, Size: 33906 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 6/8] drm/i915/fbc: Align FBC segments to 512B on glk+
2021-07-02 20:46 ` [Intel-gfx] [PATCH 6/8] drm/i915/fbc: Align FBC segments to 512B on glk+ Ville Syrjala
@ 2021-08-19 10:50 ` Juha-Pekka Heikkila
0 siblings, 0 replies; 22+ messages in thread
From: Juha-Pekka Heikkila @ 2021-08-19 10:50 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Look ok to me.
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
On 2.7.2021 23.46, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Apply the same 512 byte FBC segment alignment to glk+ as we use
> on skl+. The only real difference is that we now have a dedicated
> register for the FBC override stride. Not 100% sure which
> platforms really need the 512B alignment, but it's easieest
> to just do it on everything.
>
> Also the hardware no longer seems to misclaculate the CFB stride
> for linear, so we can omit the use of the override stride for
> linear unless the stride is misaligned.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 14 +++++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> 2 files changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 2baf58af016c..2da5295092e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -93,7 +93,7 @@ static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915,
> * be 512 byte aligned. Aligning each line to 512 bytes guarantees
> * that regardless of the compression limit we choose later.
> */
> - if (DISPLAY_VER(i915) == 9)
> + if (DISPLAY_VER(i915) >= 9)
> return ALIGN(stride, 512);
> else
> return stride;
> @@ -334,10 +334,18 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
> const struct intel_fbc_reg_params *params = &fbc->params;
> u32 dpfc_ctl;
>
> - /* Display WA #0529: skl, kbl, bxt. */
> - if (DISPLAY_VER(dev_priv) == 9) {
> + if (DISPLAY_VER(dev_priv) >= 10) {
> u32 val = 0;
>
> + if (params->override_cfb_stride)
> + val |= FBC_STRIDE_OVERRIDE |
> + FBC_STRIDE(params->override_cfb_stride / fbc->limit);
> +
> + intel_de_write(dev_priv, GLK_FBC_STRIDE, val);
> + } else if (DISPLAY_VER(dev_priv) == 9) {
> + u32 val = 0;
> +
> + /* Display WA #0529: skl, kbl, bxt. */
> if (params->override_cfb_stride)
> val |= CHICKEN_FBC_STRIDE_OVERRIDE |
> CHICKEN_FBC_STRIDE(params->override_cfb_stride / fbc->limit);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ab2bd4837efd..7cf318d84d81 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3334,6 +3334,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define ILK_DPFC_DISABLE_DUMMY0 (1 << 8)
> #define ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL (1 << 14)
> #define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23)
> +#define GLK_FBC_STRIDE _MMIO(0x43228)
> +#define FBC_STRIDE_OVERRIDE REG_BIT(15)
> +#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
> +#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
> #define ILK_FBC_RT_BASE _MMIO(0x2128)
> #define ILK_FBC_RT_VALID (1 << 0)
> #define SNB_FBC_FRONT_BUFFER (1 << 1)
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 7/8] drm/i915/fbc: Implement Wa_16011863758 for icl+
2021-07-02 20:46 ` [Intel-gfx] [PATCH 7/8] drm/i915/fbc: Implement Wa_16011863758 for icl+ Ville Syrjala
@ 2021-08-19 10:52 ` Juha-Pekka Heikkila
0 siblings, 0 replies; 22+ messages in thread
From: Juha-Pekka Heikkila @ 2021-08-19 10:52 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Maybe that TODO comment could be moved into the code instead of leaving
it just into commit message?
Either way, patch look ok to me.
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
On 2.7.2021 23.46, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> There's some kind of weird corner cases in FBC which requires
> FBC segments to be separated by at least one extra cacheline.
> Make sure that is present.
>
> TODO: the formula laid out in the spec seem to be semi-nonsense
> so this is mostly my interpretation on what it is actually trying
> to say. Need to wait for clarification from the hw folks to know
> for sure.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 2da5295092e7..daf2191dd3f6 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -88,6 +88,16 @@ static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915,
> {
> unsigned int stride = _intel_fbc_cfb_stride(cache);
>
> + /*
> + * Wa_16011863758: icl+
> + * CFB segment stride needs at least one extra cacheline.
> + * We make sure each line has an extra cacheline so that
> + * the 4 line segment will have one regarless of the
> + * compression limit we choose later.
> + */
> + if (DISPLAY_VER(i915) >= 11)
> + stride = max(stride, cache->plane.src_w * 4 + 64u);
> +
> /*
> * At least some of the platforms require each 4 line segment to
> * be 512 byte aligned. Aligning each line to 512 bytes guarantees
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 8/8] drm/i915/fbc: Allow higher compression limits on FBC1
2021-07-02 20:46 ` [Intel-gfx] [PATCH 8/8] drm/i915/fbc: Allow higher compression limits on FBC1 Ville Syrjala
@ 2021-08-23 17:52 ` Juha-Pekka Heikkilä
0 siblings, 0 replies; 22+ messages in thread
From: Juha-Pekka Heikkilä @ 2021-08-23 17:52 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Look ok to me.
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
On 2.7.2021 23.46, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On FBC1 we can specify an arbitrary cfb stride. The hw will
> simply throw away any compressed line that would exceed the
> specified limit and keep using the uncompressed data instead.
> Thus we can allow arbitrary compression limits.
>
> The one thing we have to keep in mind though is that the cfb
> stride is specified in units of 32B (gen2) or 64B (gen3+).
> Fortunately X-tile is already 128B (gen2) or 512B (gen3+) wide
> so as long as we limit outselves to the same 4x compression
> limit that FBC2 has we are guaranteed to have a sufficiently
> aligned cfb stride.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 20 +++++++-------------
> 1 file changed, 7 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index daf2191dd3f6..d46ee7b49d68 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -144,15 +144,13 @@ static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
>
> static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
> {
> - struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> + struct intel_fbc *fbc = &dev_priv->fbc;
> + const struct intel_fbc_reg_params *params = &fbc->params;
> int cfb_pitch;
> int i;
> u32 fbc_ctl;
>
> - /* Note: fbc.limit == 1 for i8xx */
> - cfb_pitch = params->cfb_size / FBC_LL_SIZE;
> - if (params->fb.stride < cfb_pitch)
> - cfb_pitch = params->fb.stride;
> + cfb_pitch = params->cfb_stride / fbc->limit;
>
> /* FBC_CTL wants 32B or 64B units */
> if (DISPLAY_VER(dev_priv) == 2)
> @@ -498,18 +496,14 @@ static int intel_fbc_min_limit(int fb_cpp)
>
> static int intel_fbc_max_limit(struct drm_i915_private *dev_priv)
> {
> - /*
> - * FIXME: FBC1 can have arbitrary cfb stride,
> - * so we could support different compression ratios.
> - */
> - if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
> - return 1;
> -
> /* WaFbcOnly1to1Ratio:ctg */
> if (IS_G4X(dev_priv))
> return 1;
>
> - /* FBC2 can only do 1:1, 1:2, 1:4 */
> + /*
> + * FBC2 can only do 1:1, 1:2, 1:4, we limit
> + * FBC1 to the same out of convenience.
> + */
> return 4;
> }
>
>
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* Re: [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb stride/size calculations
2021-07-02 20:46 ` [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb stride/size calculations Ville Syrjala
@ 2021-09-06 5:23 ` Shankar, Uma
2021-09-21 14:56 ` Ville Syrjälä
0 siblings, 1 reply; 22+ messages in thread
From: Shankar, Uma @ 2021-09-06 5:23 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Saturday, July 3, 2021 2:16 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb stride/size calculations
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The code to calculate the cfb stride/size is a bit of mess.
> The cfb size is getting calculated based purely on the plane stride and plane height.
> That doesn't account for extra alignment we want for the cfb stride. The gen9
> override stride OTOH is just calculated based on the plane width, and it does try to
> make things more aligned but any extra alignment added there is not considered in
> the cfb size calculations.
> So not at all convinced this is working as intended. Additionally the compression limit
> handling is split between the cfb allocation code and g4x_dpfc_ctl_limit() (for the
> 16bpp case), which is just confusing.
>
> Let's streamline the whole thing:
> - Start with the plane stride, convert that into cfb stride (cfb is
> always 4 bytes per pixel). All the calculations will assume 1:1
> compression limit since that will give us the max values, and we
> don't yet know how much stolen memory we will be able to allocate
> - Align the cfb stride to 512 bytes on modern platforms. This guarantees
> the 4 line segment will be 512 byte aligned regardles of the final
> compression limit we choose later. The 512 byte alignment for the
> segment is required by at least some of the platforms, and just doing
> it always seems like the easiest option
> - Figure out if we need to use the override stride or not. For X-tiled
> it's never needed since the plane stride is already 512 byte aligned,
> for Y-tiled it will be needed if the plane stride is not a multiple
> of 512 bytes, and for linear it's apparently always needed because the
> hardware miscalculates the cfb stride as PLANE_STRIDE*512 instead of
> the PLANE_STRIDE*64 that it use with linear.
> - The cfb size will be calculated based on the aligned cfb stride to
> guarantee we actually reserved enough stolen memory and the FBC hw
> won't end up scribbling over whatever else is allocated in stolen
> - The compression limit handling we just do fully in the cfb allocation
> code to make things less confusing
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 141 ++++++++++++++---------
> drivers/gpu/drm/i915/i915_drv.h | 4 +-
> 2 files changed, 90 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index f5cbbc53837c..2baf58af016c 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -62,19 +62,54 @@ static void intel_fbc_get_plane_source_size(const struct
> intel_fbc_state_cache *
> *height = cache->plane.src_h;
> }
>
> -static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
> - const struct intel_fbc_state_cache *cache)
> +/* plane stride in pixels */
> +static unsigned int intel_fbc_plane_stride(const struct
> +intel_plane_state *plane_state)
> {
> - int lines;
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + unsigned int stride;
> +
> + stride = plane_state->view.color_plane[0].stride;
> + if (!drm_rotation_90_or_270(plane_state->hw.rotation))
> + stride /= fb->format->cpp[0];
> +
> + return stride;
> +}
> +
> +/* plane stride based cfb stride in bytes, assuming 1:1 compression
> +limit */ static unsigned int _intel_fbc_cfb_stride(const struct
> +intel_fbc_state_cache *cache) {
> + /* FBC always 4 bytes per pixel internally */
> + return cache->fb.stride * 4;
> +}
> +
> +/* properly aligned cfb stride in bytes, assuming 1:1 compression limit
> +*/ static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915,
> + const struct intel_fbc_state_cache *cache)
> {
> + unsigned int stride = _intel_fbc_cfb_stride(cache);
> +
> + /*
> + * At least some of the platforms require each 4 line segment to
> + * be 512 byte aligned. Aligning each line to 512 bytes guarantees
> + * that regardless of the compression limit we choose later.
> + */
> + if (DISPLAY_VER(i915) == 9)
> + return ALIGN(stride, 512);
> + else
> + return stride;
> +}
> +
> +static unsigned int intel_fbc_cfb_size(struct drm_i915_private *dev_priv,
> + const struct intel_fbc_state_cache *cache) {
> + int lines = cache->plane.src_h;
>
> - intel_fbc_get_plane_source_size(cache, NULL, &lines);
> if (DISPLAY_VER(dev_priv) == 7)
> lines = min(lines, 2048);
> else if (DISPLAY_VER(dev_priv) >= 8)
> lines = min(lines, 2560);
>
> - /* Hardware needs the full buffer stride, not just the active area. */
> - return lines * cache->fb.stride;
> + return lines * intel_fbc_cfb_stride(dev_priv, cache);
> }
>
> static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) @@ -150,15
> +185,9 @@ static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
>
> static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915) {
> - const struct intel_fbc_reg_params *params = &i915->fbc.params;
> - int limit = i915->fbc.limit;
> -
> - if (params->fb.format->cpp[0] == 2)
> - limit <<= 1;
> -
> - switch (limit) {
> + switch (i915->fbc.limit) {
> default:
> - MISSING_CASE(limit);
> + MISSING_CASE(i915->fbc.limit);
> fallthrough;
> case 1:
> return DPFC_CTL_LIMIT_1X;
> @@ -301,7 +330,8 @@ static bool ilk_fbc_is_active(struct drm_i915_private
> *dev_priv)
>
> static void gen7_fbc_activate(struct drm_i915_private *dev_priv) {
> - struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> + struct intel_fbc *fbc = &dev_priv->fbc;
> + const struct intel_fbc_reg_params *params = &fbc->params;
> u32 dpfc_ctl;
>
> /* Display WA #0529: skl, kbl, bxt. */ @@ -310,7 +340,7 @@ static void
> gen7_fbc_activate(struct drm_i915_private *dev_priv)
>
> if (params->override_cfb_stride)
> val |= CHICKEN_FBC_STRIDE_OVERRIDE |
> - CHICKEN_FBC_STRIDE(params-
> >override_cfb_stride);
> + CHICKEN_FBC_STRIDE(params-
> >override_cfb_stride / fbc->limit);
>
> intel_de_rmw(dev_priv, CHICKEN_MISC_4,
> CHICKEN_FBC_STRIDE_OVERRIDE |
> @@ -443,7 +473,12 @@ static u64 intel_fbc_stolen_end(struct drm_i915_private
> *dev_priv)
> return min(end, intel_fbc_cfb_base_max(dev_priv));
> }
>
> -static int intel_fbc_max_limit(struct drm_i915_private *dev_priv, int fb_cpp)
> +static int intel_fbc_min_limit(int fb_cpp) {
> + return fb_cpp == 2 ? 2 : 1;
> +}
> +
> +static int intel_fbc_max_limit(struct drm_i915_private *dev_priv)
> {
> /*
> * FIXME: FBC1 can have arbitrary cfb stride, @@ -457,7 +492,7 @@ static
> int intel_fbc_max_limit(struct drm_i915_private *dev_priv, int fb_cpp)
> return 1;
>
> /* FBC2 can only do 1:1, 1:2, 1:4 */
> - return fb_cpp == 2 ? 2 : 4;
> + return 4;
> }
>
> static int find_compression_limit(struct drm_i915_private *dev_priv, @@ -466,7
> +501,9 @@ static int find_compression_limit(struct drm_i915_private *dev_priv, {
> struct intel_fbc *fbc = &dev_priv->fbc;
> u64 end = intel_fbc_stolen_end(dev_priv);
> - int ret, limit = 1;
> + int ret, limit = intel_fbc_min_limit(fb_cpp);
> +
> + size /= limit;
>
> /* Try to over-allocate to reduce reallocations and fragmentation. */
> ret = i915_gem_stolen_insert_node_in_range(dev_priv, &fbc-
> >compressed_fb, @@ -474,7 +511,7 @@ static int find_compression_limit(struct
> drm_i915_private *dev_priv,
> if (ret == 0)
> return limit;
>
> - for (; limit <= intel_fbc_max_limit(dev_priv, fb_cpp); limit <<= 1) {
> + for (; limit <= intel_fbc_max_limit(dev_priv); limit <<= 1) {
> ret = i915_gem_stolen_insert_node_in_range(dev_priv, &fbc-
> >compressed_fb,
> size >>= 1, 4096, 0, end);
> if (ret == 0)
> @@ -505,10 +542,9 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private
> *dev_priv,
> ret = find_compression_limit(dev_priv, size, fb_cpp);
> if (!ret)
> goto err_llb;
> - else if (ret > 1) {
> + else if (ret > intel_fbc_min_limit(fb_cpp))
> drm_info_once(&dev_priv->drm,
> "Reducing the compressed framebuffer size. This may
> lead to less power savings than a non-reduced-size. Try to increase stolen memory
> size if available in BIOS.\n");
> - }
>
> fbc->limit = ret;
>
> @@ -719,11 +755,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc
> *crtc,
>
> cache->fb.format = fb->format;
> cache->fb.modifier = fb->modifier;
> -
> - /* FIXME is this correct? */
> - cache->fb.stride = plane_state->view.color_plane[0].stride;
> - if (drm_rotation_90_or_270(plane_state->hw.rotation))
> - cache->fb.stride *= fb->format->cpp[0];
> + cache->fb.stride = intel_fbc_plane_stride(plane_state);
>
> /* FBC1 compression interval: arbitrary choice of 1 second */
> cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
> @@ -746,27 +778,29 @@ static bool intel_fbc_cfb_size_changed(struct
> drm_i915_private *dev_priv) {
> struct intel_fbc *fbc = &dev_priv->fbc;
>
> - return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
> + return intel_fbc_cfb_size(dev_priv, &fbc->state_cache) >
> fbc->compressed_fb.size * fbc->limit; }
>
> -static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv)
> +static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv,
> + const struct intel_fbc_state_cache *cache)
> {
> - struct intel_fbc *fbc = &dev_priv->fbc;
> - struct intel_fbc_state_cache *cache = &fbc->state_cache;
> + unsigned int stride = _intel_fbc_cfb_stride(cache);
> + unsigned int stride_aligned = intel_fbc_cfb_stride(dev_priv, cache);
>
> - if ((DISPLAY_VER(dev_priv) == 9) &&
> - cache->fb.modifier != I915_FORMAT_MOD_X_TILED)
> - return DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->limit) * 8;
> - else
> - return 0;
> -}
> + /*
> + * Override stride in 64 byte units per 4 line segment.
> + *
> + * Gen9 hw miscalculates cfb stride for linear as
> + * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so
> + * we always need to use the override there.
> + */
> + if (stride != stride_aligned ||
> + (DISPLAY_VER(dev_priv) == 9 &&
> + cache->fb.modifier == DRM_FORMAT_MOD_LINEAR))
> + return stride_aligned * 4 / 64;
As per bspec WA: 0529
"Corruption in some cases when FBC is enabled and the plane surface format is in linear, tile Y legacy, or tile Yf
WA: Display register 4208Ch bit 13 must be set to 1b and bits 12:0 must be programmed with the compressed
buffer stride value. The compressed buffer stride must be calculated using the following equation:
Compressed buffer stride = ceiling [(at least plane width in pixels) / (32 * compression limit factor)] * 8"
We need to use override stride even for TileY/Yf as well along with linear. Does the 512 alignment takes care of that.
And also whether the calculation for linear aligns with bspec WA. Just wanted to highlight, so that we don't miss.
Will go with your discretion.
>
> -static bool intel_fbc_override_cfb_stride_changed(struct drm_i915_private
> *dev_priv) -{
> - struct intel_fbc *fbc = &dev_priv->fbc;
> -
> - return fbc->params.override_cfb_stride !=
> intel_fbc_override_cfb_stride(dev_priv);
> + return 0;
> }
>
> static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) @@ -861,7
> +895,8 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> return false;
> }
>
> - if (!stride_is_valid(dev_priv, cache->fb.modifier, cache->fb.stride)) {
> + if (!stride_is_valid(dev_priv, cache->fb.modifier,
> + cache->fb.stride * cache->fb.format->cpp[0])) {
> fbc->no_fbc_reason = "framebuffer stride not supported";
> return false;
> }
> @@ -949,9 +984,9 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
> params->fb.modifier = cache->fb.modifier;
> params->fb.stride = cache->fb.stride;
>
> - params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
> -
> - params->override_cfb_stride = cache->override_cfb_stride;
> + params->cfb_stride = intel_fbc_cfb_stride(dev_priv, cache);
> + params->cfb_size = intel_fbc_cfb_size(dev_priv, cache);
> + params->override_cfb_stride = intel_fbc_override_cfb_stride(dev_priv,
> +cache);
>
> params->plane_visible = cache->plane.visible; } @@ -982,10 +1017,13 @@
> static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
> if (params->fb.stride != cache->fb.stride)
> return false;
>
> - if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
> + if (params->cfb_stride != intel_fbc_cfb_stride(dev_priv, cache))
> return false;
>
> - if (params->override_cfb_stride != cache->override_cfb_stride)
> + if (params->cfb_size != intel_fbc_cfb_size(dev_priv, cache))
> + return false;
> +
> + if (params->override_cfb_stride !=
> +intel_fbc_override_cfb_stride(dev_priv, cache))
> return false;
>
> return true;
> @@ -1266,8 +1304,7 @@ static void intel_fbc_enable(struct intel_atomic_state
> *state,
>
> if (fbc->crtc) {
> if (fbc->crtc != crtc ||
> - (!intel_fbc_cfb_size_changed(dev_priv) &&
> - !intel_fbc_override_cfb_stride_changed(dev_priv)))
> + !intel_fbc_cfb_size_changed(dev_priv))
> goto out;
>
> __intel_fbc_disable(dev_priv);
> @@ -1282,15 +1319,13 @@ static void intel_fbc_enable(struct intel_atomic_state
> *state,
> goto out;
>
> if (intel_fbc_alloc_cfb(dev_priv,
> - intel_fbc_calculate_cfb_size(dev_priv, cache),
> + intel_fbc_cfb_size(dev_priv, cache),
> plane_state->hw.fb->format->cpp[0])) {
> cache->plane.visible = false;
> fbc->no_fbc_reason = "not enough stolen memory";
> goto out;
> }
>
> - cache->override_cfb_stride = intel_fbc_override_cfb_stride(dev_priv);
> -
> drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n",
> pipe_name(crtc->pipe));
> fbc->no_fbc_reason = "FBC enabled but not active yet\n"; diff --git
> a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index
> 91a2d2425fd3..d124306c0a08 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -401,7 +401,6 @@ struct intel_fbc {
> } fb;
>
> unsigned int fence_y_offset;
> - u16 override_cfb_stride;
> u16 interval;
> s8 fence_id;
> bool psr2_active;
> @@ -426,7 +425,8 @@ struct intel_fbc {
> u64 modifier;
> } fb;
>
> - int cfb_size;
> + unsigned int cfb_stride;
> + unsigned int cfb_size;
> unsigned int fence_y_offset;
> u16 override_cfb_stride;
> u16 interval;
> --
> 2.31.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb stride/size calculations
2021-09-06 5:23 ` Shankar, Uma
@ 2021-09-21 14:56 ` Ville Syrjälä
2021-09-22 18:09 ` Shankar, Uma
0 siblings, 1 reply; 22+ messages in thread
From: Ville Syrjälä @ 2021-09-21 14:56 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-gfx
On Mon, Sep 06, 2021 at 05:23:42AM +0000, Shankar, Uma wrote:
>
>
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> > Sent: Saturday, July 3, 2021 2:16 AM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb stride/size calculations
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The code to calculate the cfb stride/size is a bit of mess.
> > The cfb size is getting calculated based purely on the plane stride and plane height.
> > That doesn't account for extra alignment we want for the cfb stride. The gen9
> > override stride OTOH is just calculated based on the plane width, and it does try to
> > make things more aligned but any extra alignment added there is not considered in
> > the cfb size calculations.
> > So not at all convinced this is working as intended. Additionally the compression limit
> > handling is split between the cfb allocation code and g4x_dpfc_ctl_limit() (for the
> > 16bpp case), which is just confusing.
> >
> > Let's streamline the whole thing:
> > - Start with the plane stride, convert that into cfb stride (cfb is
> > always 4 bytes per pixel). All the calculations will assume 1:1
> > compression limit since that will give us the max values, and we
> > don't yet know how much stolen memory we will be able to allocate
> > - Align the cfb stride to 512 bytes on modern platforms. This guarantees
> > the 4 line segment will be 512 byte aligned regardles of the final
> > compression limit we choose later. The 512 byte alignment for the
> > segment is required by at least some of the platforms, and just doing
> > it always seems like the easiest option
> > - Figure out if we need to use the override stride or not. For X-tiled
> > it's never needed since the plane stride is already 512 byte aligned,
> > for Y-tiled it will be needed if the plane stride is not a multiple
> > of 512 bytes, and for linear it's apparently always needed because the
> > hardware miscalculates the cfb stride as PLANE_STRIDE*512 instead of
> > the PLANE_STRIDE*64 that it use with linear.
> > - The cfb size will be calculated based on the aligned cfb stride to
> > guarantee we actually reserved enough stolen memory and the FBC hw
> > won't end up scribbling over whatever else is allocated in stolen
> > - The compression limit handling we just do fully in the cfb allocation
> > code to make things less confusing
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_fbc.c | 141 ++++++++++++++---------
> > drivers/gpu/drm/i915/i915_drv.h | 4 +-
> > 2 files changed, 90 insertions(+), 55 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index f5cbbc53837c..2baf58af016c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -62,19 +62,54 @@ static void intel_fbc_get_plane_source_size(const struct
> > intel_fbc_state_cache *
> > *height = cache->plane.src_h;
> > }
> >
> > -static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
> > - const struct intel_fbc_state_cache *cache)
> > +/* plane stride in pixels */
> > +static unsigned int intel_fbc_plane_stride(const struct
> > +intel_plane_state *plane_state)
> > {
> > - int lines;
> > + const struct drm_framebuffer *fb = plane_state->hw.fb;
> > + unsigned int stride;
> > +
> > + stride = plane_state->view.color_plane[0].stride;
> > + if (!drm_rotation_90_or_270(plane_state->hw.rotation))
> > + stride /= fb->format->cpp[0];
> > +
> > + return stride;
> > +}
> > +
> > +/* plane stride based cfb stride in bytes, assuming 1:1 compression
> > +limit */ static unsigned int _intel_fbc_cfb_stride(const struct
> > +intel_fbc_state_cache *cache) {
> > + /* FBC always 4 bytes per pixel internally */
> > + return cache->fb.stride * 4;
> > +}
> > +
> > +/* properly aligned cfb stride in bytes, assuming 1:1 compression limit
> > +*/ static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915,
> > + const struct intel_fbc_state_cache *cache)
> > {
> > + unsigned int stride = _intel_fbc_cfb_stride(cache);
> > +
> > + /*
> > + * At least some of the platforms require each 4 line segment to
> > + * be 512 byte aligned. Aligning each line to 512 bytes guarantees
> > + * that regardless of the compression limit we choose later.
> > + */
> > + if (DISPLAY_VER(i915) == 9)
> > + return ALIGN(stride, 512);
> > + else
> > + return stride;
> > +}
> > +
> > +static unsigned int intel_fbc_cfb_size(struct drm_i915_private *dev_priv,
> > + const struct intel_fbc_state_cache *cache) {
> > + int lines = cache->plane.src_h;
> >
> > - intel_fbc_get_plane_source_size(cache, NULL, &lines);
> > if (DISPLAY_VER(dev_priv) == 7)
> > lines = min(lines, 2048);
> > else if (DISPLAY_VER(dev_priv) >= 8)
> > lines = min(lines, 2560);
> >
> > - /* Hardware needs the full buffer stride, not just the active area. */
> > - return lines * cache->fb.stride;
> > + return lines * intel_fbc_cfb_stride(dev_priv, cache);
> > }
> >
> > static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) @@ -150,15
> > +185,9 @@ static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
> >
> > static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915) {
> > - const struct intel_fbc_reg_params *params = &i915->fbc.params;
> > - int limit = i915->fbc.limit;
> > -
> > - if (params->fb.format->cpp[0] == 2)
> > - limit <<= 1;
> > -
> > - switch (limit) {
> > + switch (i915->fbc.limit) {
> > default:
> > - MISSING_CASE(limit);
> > + MISSING_CASE(i915->fbc.limit);
> > fallthrough;
> > case 1:
> > return DPFC_CTL_LIMIT_1X;
> > @@ -301,7 +330,8 @@ static bool ilk_fbc_is_active(struct drm_i915_private
> > *dev_priv)
> >
> > static void gen7_fbc_activate(struct drm_i915_private *dev_priv) {
> > - struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> > + struct intel_fbc *fbc = &dev_priv->fbc;
> > + const struct intel_fbc_reg_params *params = &fbc->params;
> > u32 dpfc_ctl;
> >
> > /* Display WA #0529: skl, kbl, bxt. */ @@ -310,7 +340,7 @@ static void
> > gen7_fbc_activate(struct drm_i915_private *dev_priv)
> >
> > if (params->override_cfb_stride)
> > val |= CHICKEN_FBC_STRIDE_OVERRIDE |
> > - CHICKEN_FBC_STRIDE(params-
> > >override_cfb_stride);
> > + CHICKEN_FBC_STRIDE(params-
> > >override_cfb_stride / fbc->limit);
> >
> > intel_de_rmw(dev_priv, CHICKEN_MISC_4,
> > CHICKEN_FBC_STRIDE_OVERRIDE |
> > @@ -443,7 +473,12 @@ static u64 intel_fbc_stolen_end(struct drm_i915_private
> > *dev_priv)
> > return min(end, intel_fbc_cfb_base_max(dev_priv));
> > }
> >
> > -static int intel_fbc_max_limit(struct drm_i915_private *dev_priv, int fb_cpp)
> > +static int intel_fbc_min_limit(int fb_cpp) {
> > + return fb_cpp == 2 ? 2 : 1;
> > +}
> > +
> > +static int intel_fbc_max_limit(struct drm_i915_private *dev_priv)
> > {
> > /*
> > * FIXME: FBC1 can have arbitrary cfb stride, @@ -457,7 +492,7 @@ static
> > int intel_fbc_max_limit(struct drm_i915_private *dev_priv, int fb_cpp)
> > return 1;
> >
> > /* FBC2 can only do 1:1, 1:2, 1:4 */
> > - return fb_cpp == 2 ? 2 : 4;
> > + return 4;
> > }
> >
> > static int find_compression_limit(struct drm_i915_private *dev_priv, @@ -466,7
> > +501,9 @@ static int find_compression_limit(struct drm_i915_private *dev_priv, {
> > struct intel_fbc *fbc = &dev_priv->fbc;
> > u64 end = intel_fbc_stolen_end(dev_priv);
> > - int ret, limit = 1;
> > + int ret, limit = intel_fbc_min_limit(fb_cpp);
> > +
> > + size /= limit;
> >
> > /* Try to over-allocate to reduce reallocations and fragmentation. */
> > ret = i915_gem_stolen_insert_node_in_range(dev_priv, &fbc-
> > >compressed_fb, @@ -474,7 +511,7 @@ static int find_compression_limit(struct
> > drm_i915_private *dev_priv,
> > if (ret == 0)
> > return limit;
> >
> > - for (; limit <= intel_fbc_max_limit(dev_priv, fb_cpp); limit <<= 1) {
> > + for (; limit <= intel_fbc_max_limit(dev_priv); limit <<= 1) {
> > ret = i915_gem_stolen_insert_node_in_range(dev_priv, &fbc-
> > >compressed_fb,
> > size >>= 1, 4096, 0, end);
> > if (ret == 0)
> > @@ -505,10 +542,9 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private
> > *dev_priv,
> > ret = find_compression_limit(dev_priv, size, fb_cpp);
> > if (!ret)
> > goto err_llb;
> > - else if (ret > 1) {
> > + else if (ret > intel_fbc_min_limit(fb_cpp))
> > drm_info_once(&dev_priv->drm,
> > "Reducing the compressed framebuffer size. This may
> > lead to less power savings than a non-reduced-size. Try to increase stolen memory
> > size if available in BIOS.\n");
> > - }
> >
> > fbc->limit = ret;
> >
> > @@ -719,11 +755,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc
> > *crtc,
> >
> > cache->fb.format = fb->format;
> > cache->fb.modifier = fb->modifier;
> > -
> > - /* FIXME is this correct? */
> > - cache->fb.stride = plane_state->view.color_plane[0].stride;
> > - if (drm_rotation_90_or_270(plane_state->hw.rotation))
> > - cache->fb.stride *= fb->format->cpp[0];
> > + cache->fb.stride = intel_fbc_plane_stride(plane_state);
> >
> > /* FBC1 compression interval: arbitrary choice of 1 second */
> > cache->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
> > @@ -746,27 +778,29 @@ static bool intel_fbc_cfb_size_changed(struct
> > drm_i915_private *dev_priv) {
> > struct intel_fbc *fbc = &dev_priv->fbc;
> >
> > - return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
> > + return intel_fbc_cfb_size(dev_priv, &fbc->state_cache) >
> > fbc->compressed_fb.size * fbc->limit; }
> >
> > -static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv)
> > +static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv,
> > + const struct intel_fbc_state_cache *cache)
> > {
> > - struct intel_fbc *fbc = &dev_priv->fbc;
> > - struct intel_fbc_state_cache *cache = &fbc->state_cache;
> > + unsigned int stride = _intel_fbc_cfb_stride(cache);
> > + unsigned int stride_aligned = intel_fbc_cfb_stride(dev_priv, cache);
> >
> > - if ((DISPLAY_VER(dev_priv) == 9) &&
> > - cache->fb.modifier != I915_FORMAT_MOD_X_TILED)
> > - return DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->limit) * 8;
> > - else
> > - return 0;
> > -}
> > + /*
> > + * Override stride in 64 byte units per 4 line segment.
> > + *
> > + * Gen9 hw miscalculates cfb stride for linear as
> > + * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so
> > + * we always need to use the override there.
> > + */
> > + if (stride != stride_aligned ||
> > + (DISPLAY_VER(dev_priv) == 9 &&
> > + cache->fb.modifier == DRM_FORMAT_MOD_LINEAR))
> > + return stride_aligned * 4 / 64;
>
> As per bspec WA: 0529
> "Corruption in some cases when FBC is enabled and the plane surface format is in linear, tile Y legacy, or tile Yf
> WA: Display register 4208Ch bit 13 must be set to 1b and bits 12:0 must be programmed with the compressed
> buffer stride value. The compressed buffer stride must be calculated using the following equation:
>
> Compressed buffer stride = ceiling [(at least plane width in pixels) / (32 * compression limit factor)] * 8"
>
> We need to use override stride even for TileY/Yf as well along with linear. Does the 512 alignment takes care of that.
TileY is actually fine without the w/a if the plane stride is
suitably aligned. It only goes bad when the stride is misaligned.
Not quite sure about Yf since I've not tested it, but we don't
even allow FBC with Yf at the moment so doesn't really matter.
> And also whether the calculation for linear aligns with bspec WA. Just wanted to highlight, so that we don't miss.
The bspec calculations are written in a bit convoluted way. I'll
respin these patches a bit to write the calcualtions out in a way
that actually makes it clear what we're doing...
> Will go with your discretion.
>
> >
> > -static bool intel_fbc_override_cfb_stride_changed(struct drm_i915_private
> > *dev_priv) -{
> > - struct intel_fbc *fbc = &dev_priv->fbc;
> > -
> > - return fbc->params.override_cfb_stride !=
> > intel_fbc_override_cfb_stride(dev_priv);
> > + return 0;
> > }
> >
> > static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) @@ -861,7
> > +895,8 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> > return false;
> > }
> >
> > - if (!stride_is_valid(dev_priv, cache->fb.modifier, cache->fb.stride)) {
> > + if (!stride_is_valid(dev_priv, cache->fb.modifier,
> > + cache->fb.stride * cache->fb.format->cpp[0])) {
> > fbc->no_fbc_reason = "framebuffer stride not supported";
> > return false;
> > }
> > @@ -949,9 +984,9 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
> > params->fb.modifier = cache->fb.modifier;
> > params->fb.stride = cache->fb.stride;
> >
> > - params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
> > -
> > - params->override_cfb_stride = cache->override_cfb_stride;
> > + params->cfb_stride = intel_fbc_cfb_stride(dev_priv, cache);
> > + params->cfb_size = intel_fbc_cfb_size(dev_priv, cache);
> > + params->override_cfb_stride = intel_fbc_override_cfb_stride(dev_priv,
> > +cache);
> >
> > params->plane_visible = cache->plane.visible; } @@ -982,10 +1017,13 @@
> > static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
> > if (params->fb.stride != cache->fb.stride)
> > return false;
> >
> > - if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
> > + if (params->cfb_stride != intel_fbc_cfb_stride(dev_priv, cache))
> > return false;
> >
> > - if (params->override_cfb_stride != cache->override_cfb_stride)
> > + if (params->cfb_size != intel_fbc_cfb_size(dev_priv, cache))
> > + return false;
> > +
> > + if (params->override_cfb_stride !=
> > +intel_fbc_override_cfb_stride(dev_priv, cache))
> > return false;
> >
> > return true;
> > @@ -1266,8 +1304,7 @@ static void intel_fbc_enable(struct intel_atomic_state
> > *state,
> >
> > if (fbc->crtc) {
> > if (fbc->crtc != crtc ||
> > - (!intel_fbc_cfb_size_changed(dev_priv) &&
> > - !intel_fbc_override_cfb_stride_changed(dev_priv)))
> > + !intel_fbc_cfb_size_changed(dev_priv))
> > goto out;
> >
> > __intel_fbc_disable(dev_priv);
> > @@ -1282,15 +1319,13 @@ static void intel_fbc_enable(struct intel_atomic_state
> > *state,
> > goto out;
> >
> > if (intel_fbc_alloc_cfb(dev_priv,
> > - intel_fbc_calculate_cfb_size(dev_priv, cache),
> > + intel_fbc_cfb_size(dev_priv, cache),
> > plane_state->hw.fb->format->cpp[0])) {
> > cache->plane.visible = false;
> > fbc->no_fbc_reason = "not enough stolen memory";
> > goto out;
> > }
> >
> > - cache->override_cfb_stride = intel_fbc_override_cfb_stride(dev_priv);
> > -
> > drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n",
> > pipe_name(crtc->pipe));
> > fbc->no_fbc_reason = "FBC enabled but not active yet\n"; diff --git
> > a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index
> > 91a2d2425fd3..d124306c0a08 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -401,7 +401,6 @@ struct intel_fbc {
> > } fb;
> >
> > unsigned int fence_y_offset;
> > - u16 override_cfb_stride;
> > u16 interval;
> > s8 fence_id;
> > bool psr2_active;
> > @@ -426,7 +425,8 @@ struct intel_fbc {
> > u64 modifier;
> > } fb;
> >
> > - int cfb_size;
> > + unsigned int cfb_stride;
> > + unsigned int cfb_size;
> > unsigned int fence_y_offset;
> > u16 override_cfb_stride;
> > u16 interval;
> > --
> > 2.31.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb stride/size calculations
2021-09-21 14:56 ` Ville Syrjälä
@ 2021-09-22 18:09 ` Shankar, Uma
0 siblings, 0 replies; 22+ messages in thread
From: Shankar, Uma @ 2021-09-22 18:09 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, September 21, 2021 8:27 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb stride/size
> calculations
>
> On Mon, Sep 06, 2021 at 05:23:42AM +0000, Shankar, Uma wrote:
> >
> >
> > > -----Original Message-----
> > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> > > Of Ville Syrjala
> > > Sent: Saturday, July 3, 2021 2:16 AM
> > > To: intel-gfx@lists.freedesktop.org
> > > Subject: [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb
> > > stride/size calculations
> > >
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > The code to calculate the cfb stride/size is a bit of mess.
> > > The cfb size is getting calculated based purely on the plane stride and plane
> height.
> > > That doesn't account for extra alignment we want for the cfb stride.
> > > The gen9 override stride OTOH is just calculated based on the plane
> > > width, and it does try to make things more aligned but any extra
> > > alignment added there is not considered in the cfb size calculations.
> > > So not at all convinced this is working as intended. Additionally
> > > the compression limit handling is split between the cfb allocation
> > > code and g4x_dpfc_ctl_limit() (for the 16bpp case), which is just confusing.
> > >
> > > Let's streamline the whole thing:
> > > - Start with the plane stride, convert that into cfb stride (cfb is
> > > always 4 bytes per pixel). All the calculations will assume 1:1
> > > compression limit since that will give us the max values, and we
> > > don't yet know how much stolen memory we will be able to allocate
> > > - Align the cfb stride to 512 bytes on modern platforms. This guarantees
> > > the 4 line segment will be 512 byte aligned regardles of the final
> > > compression limit we choose later. The 512 byte alignment for the
> > > segment is required by at least some of the platforms, and just doing
> > > it always seems like the easiest option
> > > - Figure out if we need to use the override stride or not. For X-tiled
> > > it's never needed since the plane stride is already 512 byte aligned,
> > > for Y-tiled it will be needed if the plane stride is not a multiple
> > > of 512 bytes, and for linear it's apparently always needed because the
> > > hardware miscalculates the cfb stride as PLANE_STRIDE*512 instead of
> > > the PLANE_STRIDE*64 that it use with linear.
> > > - The cfb size will be calculated based on the aligned cfb stride to
> > > guarantee we actually reserved enough stolen memory and the FBC hw
> > > won't end up scribbling over whatever else is allocated in stolen
> > > - The compression limit handling we just do fully in the cfb allocation
> > > code to make things less confusing
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_fbc.c | 141 ++++++++++++++---------
> > > drivers/gpu/drm/i915/i915_drv.h | 4 +-
> > > 2 files changed, 90 insertions(+), 55 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index f5cbbc53837c..2baf58af016c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -62,19 +62,54 @@ static void
> > > intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache *
> > > *height = cache->plane.src_h;
> > > }
> > >
> > > -static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
> > > - const struct intel_fbc_state_cache *cache)
> > > +/* plane stride in pixels */
> > > +static unsigned int intel_fbc_plane_stride(const struct
> > > +intel_plane_state *plane_state)
> > > {
> > > - int lines;
> > > + const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > + unsigned int stride;
> > > +
> > > + stride = plane_state->view.color_plane[0].stride;
> > > + if (!drm_rotation_90_or_270(plane_state->hw.rotation))
> > > + stride /= fb->format->cpp[0];
> > > +
> > > + return stride;
> > > +}
> > > +
> > > +/* plane stride based cfb stride in bytes, assuming 1:1 compression
> > > +limit */ static unsigned int _intel_fbc_cfb_stride(const struct
> > > +intel_fbc_state_cache *cache) {
> > > + /* FBC always 4 bytes per pixel internally */
> > > + return cache->fb.stride * 4;
> > > +}
> > > +
> > > +/* properly aligned cfb stride in bytes, assuming 1:1 compression
> > > +limit */ static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915,
> > > + const struct intel_fbc_state_cache *cache)
> > > {
> > > + unsigned int stride = _intel_fbc_cfb_stride(cache);
> > > +
> > > + /*
> > > + * At least some of the platforms require each 4 line segment to
> > > + * be 512 byte aligned. Aligning each line to 512 bytes guarantees
> > > + * that regardless of the compression limit we choose later.
> > > + */
> > > + if (DISPLAY_VER(i915) == 9)
> > > + return ALIGN(stride, 512);
> > > + else
> > > + return stride;
> > > +}
> > > +
> > > +static unsigned int intel_fbc_cfb_size(struct drm_i915_private *dev_priv,
> > > + const struct intel_fbc_state_cache *cache) {
> > > + int lines = cache->plane.src_h;
> > >
> > > - intel_fbc_get_plane_source_size(cache, NULL, &lines);
> > > if (DISPLAY_VER(dev_priv) == 7)
> > > lines = min(lines, 2048);
> > > else if (DISPLAY_VER(dev_priv) >= 8)
> > > lines = min(lines, 2560);
> > >
> > > - /* Hardware needs the full buffer stride, not just the active area. */
> > > - return lines * cache->fb.stride;
> > > + return lines * intel_fbc_cfb_stride(dev_priv, cache);
> > > }
> > >
> > > static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
> > > @@ -150,15
> > > +185,9 @@ static bool i8xx_fbc_is_active(struct drm_i915_private
> > > +*dev_priv)
> > >
> > > static u32 g4x_dpfc_ctl_limit(struct drm_i915_private *i915) {
> > > - const struct intel_fbc_reg_params *params = &i915->fbc.params;
> > > - int limit = i915->fbc.limit;
> > > -
> > > - if (params->fb.format->cpp[0] == 2)
> > > - limit <<= 1;
> > > -
> > > - switch (limit) {
> > > + switch (i915->fbc.limit) {
> > > default:
> > > - MISSING_CASE(limit);
> > > + MISSING_CASE(i915->fbc.limit);
> > > fallthrough;
> > > case 1:
> > > return DPFC_CTL_LIMIT_1X;
> > > @@ -301,7 +330,8 @@ static bool ilk_fbc_is_active(struct
> > > drm_i915_private
> > > *dev_priv)
> > >
> > > static void gen7_fbc_activate(struct drm_i915_private *dev_priv) {
> > > - struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> > > + struct intel_fbc *fbc = &dev_priv->fbc;
> > > + const struct intel_fbc_reg_params *params = &fbc->params;
> > > u32 dpfc_ctl;
> > >
> > > /* Display WA #0529: skl, kbl, bxt. */ @@ -310,7 +340,7 @@ static
> > > void gen7_fbc_activate(struct drm_i915_private *dev_priv)
> > >
> > > if (params->override_cfb_stride)
> > > val |= CHICKEN_FBC_STRIDE_OVERRIDE |
> > > - CHICKEN_FBC_STRIDE(params-
> > > >override_cfb_stride);
> > > + CHICKEN_FBC_STRIDE(params-
> > > >override_cfb_stride / fbc->limit);
> > >
> > > intel_de_rmw(dev_priv, CHICKEN_MISC_4,
> > > CHICKEN_FBC_STRIDE_OVERRIDE | @@ -443,7 +473,12
> @@ static
> > > u64 intel_fbc_stolen_end(struct drm_i915_private
> > > *dev_priv)
> > > return min(end, intel_fbc_cfb_base_max(dev_priv));
> > > }
> > >
> > > -static int intel_fbc_max_limit(struct drm_i915_private *dev_priv,
> > > int fb_cpp)
> > > +static int intel_fbc_min_limit(int fb_cpp) {
> > > + return fb_cpp == 2 ? 2 : 1;
> > > +}
> > > +
> > > +static int intel_fbc_max_limit(struct drm_i915_private *dev_priv)
> > > {
> > > /*
> > > * FIXME: FBC1 can have arbitrary cfb stride, @@ -457,7 +492,7 @@
> > > static int intel_fbc_max_limit(struct drm_i915_private *dev_priv, int fb_cpp)
> > > return 1;
> > >
> > > /* FBC2 can only do 1:1, 1:2, 1:4 */
> > > - return fb_cpp == 2 ? 2 : 4;
> > > + return 4;
> > > }
> > >
> > > static int find_compression_limit(struct drm_i915_private
> > > *dev_priv, @@ -466,7
> > > +501,9 @@ static int find_compression_limit(struct drm_i915_private
> > > +*dev_priv, {
> > > struct intel_fbc *fbc = &dev_priv->fbc;
> > > u64 end = intel_fbc_stolen_end(dev_priv);
> > > - int ret, limit = 1;
> > > + int ret, limit = intel_fbc_min_limit(fb_cpp);
> > > +
> > > + size /= limit;
> > >
> > > /* Try to over-allocate to reduce reallocations and fragmentation. */
> > > ret = i915_gem_stolen_insert_node_in_range(dev_priv, &fbc-
> > > >compressed_fb, @@ -474,7 +511,7 @@ static int
> > > >find_compression_limit(struct
> > > drm_i915_private *dev_priv,
> > > if (ret == 0)
> > > return limit;
> > >
> > > - for (; limit <= intel_fbc_max_limit(dev_priv, fb_cpp); limit <<= 1) {
> > > + for (; limit <= intel_fbc_max_limit(dev_priv); limit <<= 1) {
> > > ret = i915_gem_stolen_insert_node_in_range(dev_priv, &fbc-
> > > >compressed_fb,
> > > size >>= 1, 4096, 0, end);
> > > if (ret == 0)
> > > @@ -505,10 +542,9 @@ static int intel_fbc_alloc_cfb(struct
> > > drm_i915_private *dev_priv,
> > > ret = find_compression_limit(dev_priv, size, fb_cpp);
> > > if (!ret)
> > > goto err_llb;
> > > - else if (ret > 1) {
> > > + else if (ret > intel_fbc_min_limit(fb_cpp))
> > > drm_info_once(&dev_priv->drm,
> > > "Reducing the compressed framebuffer size. This may
> lead
> > > to less power savings than a non-reduced-size. Try to increase
> > > stolen memory size if available in BIOS.\n");
> > > - }
> > >
> > > fbc->limit = ret;
> > >
> > > @@ -719,11 +755,7 @@ static void intel_fbc_update_state_cache(struct
> > > intel_crtc *crtc,
> > >
> > > cache->fb.format = fb->format;
> > > cache->fb.modifier = fb->modifier;
> > > -
> > > - /* FIXME is this correct? */
> > > - cache->fb.stride = plane_state->view.color_plane[0].stride;
> > > - if (drm_rotation_90_or_270(plane_state->hw.rotation))
> > > - cache->fb.stride *= fb->format->cpp[0];
> > > + cache->fb.stride = intel_fbc_plane_stride(plane_state);
> > >
> > > /* FBC1 compression interval: arbitrary choice of 1 second */
> > > cache->interval =
> > > drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
> > > @@ -746,27 +778,29 @@ static bool intel_fbc_cfb_size_changed(struct
> > > drm_i915_private *dev_priv) {
> > > struct intel_fbc *fbc = &dev_priv->fbc;
> > >
> > > - return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
> > > + return intel_fbc_cfb_size(dev_priv, &fbc->state_cache) >
> > > fbc->compressed_fb.size * fbc->limit; }
> > >
> > > -static u16 intel_fbc_override_cfb_stride(struct drm_i915_private
> > > *dev_priv)
> > > +static u16 intel_fbc_override_cfb_stride(struct drm_i915_private *dev_priv,
> > > + const struct intel_fbc_state_cache *cache)
> > > {
> > > - struct intel_fbc *fbc = &dev_priv->fbc;
> > > - struct intel_fbc_state_cache *cache = &fbc->state_cache;
> > > + unsigned int stride = _intel_fbc_cfb_stride(cache);
> > > + unsigned int stride_aligned = intel_fbc_cfb_stride(dev_priv,
> > > +cache);
> > >
> > > - if ((DISPLAY_VER(dev_priv) == 9) &&
> > > - cache->fb.modifier != I915_FORMAT_MOD_X_TILED)
> > > - return DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->limit) * 8;
> > > - else
> > > - return 0;
> > > -}
> > > + /*
> > > + * Override stride in 64 byte units per 4 line segment.
> > > + *
> > > + * Gen9 hw miscalculates cfb stride for linear as
> > > + * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so
> > > + * we always need to use the override there.
> > > + */
> > > + if (stride != stride_aligned ||
> > > + (DISPLAY_VER(dev_priv) == 9 &&
> > > + cache->fb.modifier == DRM_FORMAT_MOD_LINEAR))
> > > + return stride_aligned * 4 / 64;
> >
> > As per bspec WA: 0529
> > "Corruption in some cases when FBC is enabled and the plane surface
> > format is in linear, tile Y legacy, or tile Yf
> > WA: Display register 4208Ch bit 13 must be set to 1b and bits 12:0
> > must be programmed with the compressed buffer stride value. The compressed
> buffer stride must be calculated using the following equation:
> >
> > Compressed buffer stride = ceiling [(at least plane width in pixels) / (32 *
> compression limit factor)] * 8"
> >
> > We need to use override stride even for TileY/Yf as well along with linear. Does the
> 512 alignment takes care of that.
>
> TileY is actually fine without the w/a if the plane stride is suitably aligned. It only
> goes bad when the stride is misaligned.
>
Ok, so we should be covered here due to the alignment.
> Not quite sure about Yf since I've not tested it, but we don't even allow FBC with Yf
> at the moment so doesn't really matter.
Yeah ok, make sense.
> > And also whether the calculation for linear aligns with bspec WA. Just wanted to
> highlight, so that we don't miss.
>
> The bspec calculations are written in a bit convoluted way. I'll respin these patches a
> bit to write the calcualtions out in a way that actually makes it clear what we're
> doing...
Ok sure Ville. Will check and ack that.
Regards,
Uma Shankar
> > Will go with your discretion.
> >
> > >
> > > -static bool intel_fbc_override_cfb_stride_changed(struct
> > > drm_i915_private
> > > *dev_priv) -{
> > > - struct intel_fbc *fbc = &dev_priv->fbc;
> > > -
> > > - return fbc->params.override_cfb_stride !=
> > > intel_fbc_override_cfb_stride(dev_priv);
> > > + return 0;
> > > }
> > >
> > > static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
> > > @@ -861,7
> > > +895,8 @@ static bool intel_fbc_can_activate(struct intel_crtc
> > > +*crtc)
> > > return false;
> > > }
> > >
> > > - if (!stride_is_valid(dev_priv, cache->fb.modifier, cache->fb.stride)) {
> > > + if (!stride_is_valid(dev_priv, cache->fb.modifier,
> > > + cache->fb.stride * cache->fb.format->cpp[0])) {
> > > fbc->no_fbc_reason = "framebuffer stride not supported";
> > > return false;
> > > }
> > > @@ -949,9 +984,9 @@ static void intel_fbc_get_reg_params(struct intel_crtc
> *crtc,
> > > params->fb.modifier = cache->fb.modifier;
> > > params->fb.stride = cache->fb.stride;
> > >
> > > - params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
> > > -
> > > - params->override_cfb_stride = cache->override_cfb_stride;
> > > + params->cfb_stride = intel_fbc_cfb_stride(dev_priv, cache);
> > > + params->cfb_size = intel_fbc_cfb_size(dev_priv, cache);
> > > + params->override_cfb_stride =
> > > +intel_fbc_override_cfb_stride(dev_priv,
> > > +cache);
> > >
> > > params->plane_visible = cache->plane.visible; } @@ -982,10
> > > +1017,13 @@ static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state
> *crtc_state)
> > > if (params->fb.stride != cache->fb.stride)
> > > return false;
> > >
> > > - if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
> > > + if (params->cfb_stride != intel_fbc_cfb_stride(dev_priv, cache))
> > > return false;
> > >
> > > - if (params->override_cfb_stride != cache->override_cfb_stride)
> > > + if (params->cfb_size != intel_fbc_cfb_size(dev_priv, cache))
> > > + return false;
> > > +
> > > + if (params->override_cfb_stride !=
> > > +intel_fbc_override_cfb_stride(dev_priv, cache))
> > > return false;
> > >
> > > return true;
> > > @@ -1266,8 +1304,7 @@ static void intel_fbc_enable(struct
> > > intel_atomic_state *state,
> > >
> > > if (fbc->crtc) {
> > > if (fbc->crtc != crtc ||
> > > - (!intel_fbc_cfb_size_changed(dev_priv) &&
> > > - !intel_fbc_override_cfb_stride_changed(dev_priv)))
> > > + !intel_fbc_cfb_size_changed(dev_priv))
> > > goto out;
> > >
> > > __intel_fbc_disable(dev_priv);
> > > @@ -1282,15 +1319,13 @@ static void intel_fbc_enable(struct
> > > intel_atomic_state *state,
> > > goto out;
> > >
> > > if (intel_fbc_alloc_cfb(dev_priv,
> > > - intel_fbc_calculate_cfb_size(dev_priv, cache),
> > > + intel_fbc_cfb_size(dev_priv, cache),
> > > plane_state->hw.fb->format->cpp[0])) {
> > > cache->plane.visible = false;
> > > fbc->no_fbc_reason = "not enough stolen memory";
> > > goto out;
> > > }
> > >
> > > - cache->override_cfb_stride = intel_fbc_override_cfb_stride(dev_priv);
> > > -
> > > drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n",
> > > pipe_name(crtc->pipe));
> > > fbc->no_fbc_reason = "FBC enabled but not active yet\n"; diff
> > > --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h index
> > > 91a2d2425fd3..d124306c0a08 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -401,7 +401,6 @@ struct intel_fbc {
> > > } fb;
> > >
> > > unsigned int fence_y_offset;
> > > - u16 override_cfb_stride;
> > > u16 interval;
> > > s8 fence_id;
> > > bool psr2_active;
> > > @@ -426,7 +425,8 @@ struct intel_fbc {
> > > u64 modifier;
> > > } fb;
> > >
> > > - int cfb_size;
> > > + unsigned int cfb_stride;
> > > + unsigned int cfb_size;
> > > unsigned int fence_y_offset;
> > > u16 override_cfb_stride;
> > > u16 interval;
> > > --
> > > 2.31.1
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2021-09-22 18:09 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-02 20:45 [Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations Ville Syrjala
2021-07-02 20:45 ` [Intel-gfx] [PATCH 1/8] drm/i915/fbc: Rewrite the FBC tiling check a bit Ville Syrjala
2021-07-02 20:45 ` [Intel-gfx] [PATCH 2/8] drm/i915/fbc: Extract intel_fbc_update() Ville Syrjala
2021-07-02 20:45 ` [Intel-gfx] [PATCH 3/8] drm/i915/fbc: Move the "recompress on activate" to a central place Ville Syrjala
2021-07-02 20:45 ` [Intel-gfx] [PATCH 4/8] drm/i915/fbc: Polish the skl+ FBC stride override handling Ville Syrjala
2021-07-05 8:02 ` Jani Nikula
2021-07-02 20:46 ` [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb stride/size calculations Ville Syrjala
2021-09-06 5:23 ` Shankar, Uma
2021-09-21 14:56 ` Ville Syrjälä
2021-09-22 18:09 ` Shankar, Uma
2021-07-02 20:46 ` [Intel-gfx] [PATCH 6/8] drm/i915/fbc: Align FBC segments to 512B on glk+ Ville Syrjala
2021-08-19 10:50 ` Juha-Pekka Heikkila
2021-07-02 20:46 ` [Intel-gfx] [PATCH 7/8] drm/i915/fbc: Implement Wa_16011863758 for icl+ Ville Syrjala
2021-08-19 10:52 ` Juha-Pekka Heikkila
2021-07-02 20:46 ` [Intel-gfx] [PATCH 8/8] drm/i915/fbc: Allow higher compression limits on FBC1 Ville Syrjala
2021-08-23 17:52 ` Juha-Pekka Heikkilä
2021-07-02 22:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations Patchwork
2021-07-02 22:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-03 1:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-07-07 15:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations (rev2) Patchwork
2021-07-07 15:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-07 20:05 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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